intel-lpss.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Intel Sunrisepoint LPSS core support.
  4. *
  5. * Copyright (C) 2015, Intel Corporation
  6. *
  7. * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
  8. * Mika Westerberg <mika.westerberg@linux.intel.com>
  9. * Heikki Krogerus <heikki.krogerus@linux.intel.com>
  10. * Jarkko Nikula <jarkko.nikula@linux.intel.com>
  11. */
  12. #include <linux/clk.h>
  13. #include <linux/clkdev.h>
  14. #include <linux/clk-provider.h>
  15. #include <linux/debugfs.h>
  16. #include <linux/idr.h>
  17. #include <linux/io.h>
  18. #include <linux/ioport.h>
  19. #include <linux/kernel.h>
  20. #include <linux/module.h>
  21. #include <linux/mfd/core.h>
  22. #include <linux/pm_qos.h>
  23. #include <linux/pm_runtime.h>
  24. #include <linux/property.h>
  25. #include <linux/seq_file.h>
  26. #include <linux/io-64-nonatomic-lo-hi.h>
  27. #include <linux/dma/idma64.h>
  28. #include "intel-lpss.h"
  29. #define LPSS_DEV_OFFSET 0x000
  30. #define LPSS_DEV_SIZE 0x200
  31. #define LPSS_PRIV_OFFSET 0x200
  32. #define LPSS_PRIV_SIZE 0x100
  33. #define LPSS_PRIV_REG_COUNT (LPSS_PRIV_SIZE / 4)
  34. #define LPSS_IDMA64_OFFSET 0x800
  35. #define LPSS_IDMA64_SIZE 0x800
  36. /* Offsets from lpss->priv */
  37. #define LPSS_PRIV_RESETS 0x04
  38. #define LPSS_PRIV_RESETS_IDMA BIT(2)
  39. #define LPSS_PRIV_RESETS_FUNC 0x3
  40. #define LPSS_PRIV_ACTIVELTR 0x10
  41. #define LPSS_PRIV_IDLELTR 0x14
  42. #define LPSS_PRIV_LTR_REQ BIT(15)
  43. #define LPSS_PRIV_LTR_SCALE_MASK GENMASK(11, 10)
  44. #define LPSS_PRIV_LTR_SCALE_1US (2 << 10)
  45. #define LPSS_PRIV_LTR_SCALE_32US (3 << 10)
  46. #define LPSS_PRIV_LTR_VALUE_MASK GENMASK(9, 0)
  47. #define LPSS_PRIV_SSP_REG 0x20
  48. #define LPSS_PRIV_SSP_REG_DIS_DMA_FIN BIT(0)
  49. #define LPSS_PRIV_REMAP_ADDR 0x40
  50. #define LPSS_PRIV_CAPS 0xfc
  51. #define LPSS_PRIV_CAPS_NO_IDMA BIT(8)
  52. #define LPSS_PRIV_CAPS_TYPE_MASK GENMASK(7, 4)
  53. #define LPSS_PRIV_CAPS_TYPE_SHIFT 4
  54. /* This matches the type field in CAPS register */
  55. enum intel_lpss_dev_type {
  56. LPSS_DEV_I2C = 0,
  57. LPSS_DEV_UART,
  58. LPSS_DEV_SPI,
  59. };
  60. struct intel_lpss {
  61. const struct intel_lpss_platform_info *info;
  62. enum intel_lpss_dev_type type;
  63. struct clk *clk;
  64. struct clk_lookup *clock;
  65. struct mfd_cell *cell;
  66. struct device *dev;
  67. void __iomem *priv;
  68. u32 priv_ctx[LPSS_PRIV_REG_COUNT];
  69. int devid;
  70. u32 caps;
  71. u32 active_ltr;
  72. u32 idle_ltr;
  73. struct dentry *debugfs;
  74. };
  75. static const struct resource intel_lpss_dev_resources[] = {
  76. DEFINE_RES_MEM_NAMED(LPSS_DEV_OFFSET, LPSS_DEV_SIZE, "lpss_dev"),
  77. DEFINE_RES_MEM_NAMED(LPSS_PRIV_OFFSET, LPSS_PRIV_SIZE, "lpss_priv"),
  78. DEFINE_RES_IRQ(0),
  79. };
  80. static const struct resource intel_lpss_idma64_resources[] = {
  81. DEFINE_RES_MEM(LPSS_IDMA64_OFFSET, LPSS_IDMA64_SIZE),
  82. DEFINE_RES_IRQ(0),
  83. };
  84. /*
  85. * Cells needs to be ordered so that the iDMA is created first. This is
  86. * because we need to be sure the DMA is available when the host controller
  87. * driver is probed.
  88. */
  89. static const struct mfd_cell intel_lpss_idma64_cell = {
  90. .name = LPSS_IDMA64_DRIVER_NAME,
  91. .num_resources = ARRAY_SIZE(intel_lpss_idma64_resources),
  92. .resources = intel_lpss_idma64_resources,
  93. };
  94. static const struct mfd_cell intel_lpss_i2c_cell = {
  95. .name = "i2c_designware",
  96. .num_resources = ARRAY_SIZE(intel_lpss_dev_resources),
  97. .resources = intel_lpss_dev_resources,
  98. };
  99. static const struct mfd_cell intel_lpss_uart_cell = {
  100. .name = "dw-apb-uart",
  101. .num_resources = ARRAY_SIZE(intel_lpss_dev_resources),
  102. .resources = intel_lpss_dev_resources,
  103. };
  104. static const struct mfd_cell intel_lpss_spi_cell = {
  105. .name = "pxa2xx-spi",
  106. .num_resources = ARRAY_SIZE(intel_lpss_dev_resources),
  107. .resources = intel_lpss_dev_resources,
  108. };
  109. static DEFINE_IDA(intel_lpss_devid_ida);
  110. static struct dentry *intel_lpss_debugfs;
  111. static void intel_lpss_cache_ltr(struct intel_lpss *lpss)
  112. {
  113. lpss->active_ltr = readl(lpss->priv + LPSS_PRIV_ACTIVELTR);
  114. lpss->idle_ltr = readl(lpss->priv + LPSS_PRIV_IDLELTR);
  115. }
  116. static int intel_lpss_debugfs_add(struct intel_lpss *lpss)
  117. {
  118. struct dentry *dir;
  119. dir = debugfs_create_dir(dev_name(lpss->dev), intel_lpss_debugfs);
  120. if (IS_ERR(dir))
  121. return PTR_ERR(dir);
  122. /* Cache the values into lpss structure */
  123. intel_lpss_cache_ltr(lpss);
  124. debugfs_create_x32("capabilities", S_IRUGO, dir, &lpss->caps);
  125. debugfs_create_x32("active_ltr", S_IRUGO, dir, &lpss->active_ltr);
  126. debugfs_create_x32("idle_ltr", S_IRUGO, dir, &lpss->idle_ltr);
  127. lpss->debugfs = dir;
  128. return 0;
  129. }
  130. static void intel_lpss_debugfs_remove(struct intel_lpss *lpss)
  131. {
  132. debugfs_remove_recursive(lpss->debugfs);
  133. }
  134. static void intel_lpss_ltr_set(struct device *dev, s32 val)
  135. {
  136. struct intel_lpss *lpss = dev_get_drvdata(dev);
  137. u32 ltr;
  138. /*
  139. * Program latency tolerance (LTR) accordingly what has been asked
  140. * by the PM QoS layer or disable it in case we were passed
  141. * negative value or PM_QOS_LATENCY_ANY.
  142. */
  143. ltr = readl(lpss->priv + LPSS_PRIV_ACTIVELTR);
  144. if (val == PM_QOS_LATENCY_ANY || val < 0) {
  145. ltr &= ~LPSS_PRIV_LTR_REQ;
  146. } else {
  147. ltr |= LPSS_PRIV_LTR_REQ;
  148. ltr &= ~LPSS_PRIV_LTR_SCALE_MASK;
  149. ltr &= ~LPSS_PRIV_LTR_VALUE_MASK;
  150. if (val > LPSS_PRIV_LTR_VALUE_MASK)
  151. ltr |= LPSS_PRIV_LTR_SCALE_32US | val >> 5;
  152. else
  153. ltr |= LPSS_PRIV_LTR_SCALE_1US | val;
  154. }
  155. if (ltr == lpss->active_ltr)
  156. return;
  157. writel(ltr, lpss->priv + LPSS_PRIV_ACTIVELTR);
  158. writel(ltr, lpss->priv + LPSS_PRIV_IDLELTR);
  159. /* Cache the values into lpss structure */
  160. intel_lpss_cache_ltr(lpss);
  161. }
  162. static void intel_lpss_ltr_expose(struct intel_lpss *lpss)
  163. {
  164. lpss->dev->power.set_latency_tolerance = intel_lpss_ltr_set;
  165. dev_pm_qos_expose_latency_tolerance(lpss->dev);
  166. }
  167. static void intel_lpss_ltr_hide(struct intel_lpss *lpss)
  168. {
  169. dev_pm_qos_hide_latency_tolerance(lpss->dev);
  170. lpss->dev->power.set_latency_tolerance = NULL;
  171. }
  172. static int intel_lpss_assign_devs(struct intel_lpss *lpss)
  173. {
  174. const struct mfd_cell *cell;
  175. unsigned int type;
  176. type = lpss->caps & LPSS_PRIV_CAPS_TYPE_MASK;
  177. type >>= LPSS_PRIV_CAPS_TYPE_SHIFT;
  178. switch (type) {
  179. case LPSS_DEV_I2C:
  180. cell = &intel_lpss_i2c_cell;
  181. break;
  182. case LPSS_DEV_UART:
  183. cell = &intel_lpss_uart_cell;
  184. break;
  185. case LPSS_DEV_SPI:
  186. cell = &intel_lpss_spi_cell;
  187. break;
  188. default:
  189. return -ENODEV;
  190. }
  191. lpss->cell = devm_kmemdup(lpss->dev, cell, sizeof(*cell), GFP_KERNEL);
  192. if (!lpss->cell)
  193. return -ENOMEM;
  194. lpss->type = type;
  195. return 0;
  196. }
  197. static bool intel_lpss_has_idma(const struct intel_lpss *lpss)
  198. {
  199. return (lpss->caps & LPSS_PRIV_CAPS_NO_IDMA) == 0;
  200. }
  201. static void intel_lpss_set_remap_addr(const struct intel_lpss *lpss)
  202. {
  203. resource_size_t addr = lpss->info->mem->start;
  204. lo_hi_writeq(addr, lpss->priv + LPSS_PRIV_REMAP_ADDR);
  205. }
  206. static void intel_lpss_deassert_reset(const struct intel_lpss *lpss)
  207. {
  208. u32 value = LPSS_PRIV_RESETS_FUNC | LPSS_PRIV_RESETS_IDMA;
  209. /* Bring out the device from reset */
  210. writel(value, lpss->priv + LPSS_PRIV_RESETS);
  211. }
  212. static void intel_lpss_init_dev(const struct intel_lpss *lpss)
  213. {
  214. u32 value = LPSS_PRIV_SSP_REG_DIS_DMA_FIN;
  215. /* Set the device in reset state */
  216. writel(0, lpss->priv + LPSS_PRIV_RESETS);
  217. intel_lpss_deassert_reset(lpss);
  218. intel_lpss_set_remap_addr(lpss);
  219. if (!intel_lpss_has_idma(lpss))
  220. return;
  221. /* Make sure that SPI multiblock DMA transfers are re-enabled */
  222. if (lpss->type == LPSS_DEV_SPI)
  223. writel(value, lpss->priv + LPSS_PRIV_SSP_REG);
  224. }
  225. static void intel_lpss_unregister_clock_tree(struct clk *clk)
  226. {
  227. struct clk *parent;
  228. while (clk) {
  229. parent = clk_get_parent(clk);
  230. clk_unregister(clk);
  231. clk = parent;
  232. }
  233. }
  234. static int intel_lpss_register_clock_divider(struct intel_lpss *lpss,
  235. const char *devname,
  236. struct clk **clk)
  237. {
  238. char name[32];
  239. struct clk *tmp = *clk;
  240. snprintf(name, sizeof(name), "%s-enable", devname);
  241. tmp = clk_register_gate(NULL, name, __clk_get_name(tmp), 0,
  242. lpss->priv, 0, 0, NULL);
  243. if (IS_ERR(tmp))
  244. return PTR_ERR(tmp);
  245. snprintf(name, sizeof(name), "%s-div", devname);
  246. tmp = clk_register_fractional_divider(NULL, name, __clk_get_name(tmp),
  247. 0, lpss->priv, 1, 15, 16, 15, 0,
  248. NULL);
  249. if (IS_ERR(tmp))
  250. return PTR_ERR(tmp);
  251. *clk = tmp;
  252. snprintf(name, sizeof(name), "%s-update", devname);
  253. tmp = clk_register_gate(NULL, name, __clk_get_name(tmp),
  254. CLK_SET_RATE_PARENT, lpss->priv, 31, 0, NULL);
  255. if (IS_ERR(tmp))
  256. return PTR_ERR(tmp);
  257. *clk = tmp;
  258. return 0;
  259. }
  260. static int intel_lpss_register_clock(struct intel_lpss *lpss)
  261. {
  262. const struct mfd_cell *cell = lpss->cell;
  263. struct clk *clk;
  264. char devname[24];
  265. int ret;
  266. if (!lpss->info->clk_rate)
  267. return 0;
  268. /* Root clock */
  269. clk = clk_register_fixed_rate(NULL, dev_name(lpss->dev), NULL, 0,
  270. lpss->info->clk_rate);
  271. if (IS_ERR(clk))
  272. return PTR_ERR(clk);
  273. snprintf(devname, sizeof(devname), "%s.%d", cell->name, lpss->devid);
  274. /*
  275. * Support for clock divider only if it has some preset value.
  276. * Otherwise we assume that the divider is not used.
  277. */
  278. if (lpss->type != LPSS_DEV_I2C) {
  279. ret = intel_lpss_register_clock_divider(lpss, devname, &clk);
  280. if (ret)
  281. goto err_clk_register;
  282. }
  283. ret = -ENOMEM;
  284. /* Clock for the host controller */
  285. lpss->clock = clkdev_create(clk, lpss->info->clk_con_id, "%s", devname);
  286. if (!lpss->clock)
  287. goto err_clk_register;
  288. lpss->clk = clk;
  289. return 0;
  290. err_clk_register:
  291. intel_lpss_unregister_clock_tree(clk);
  292. return ret;
  293. }
  294. static void intel_lpss_unregister_clock(struct intel_lpss *lpss)
  295. {
  296. if (IS_ERR_OR_NULL(lpss->clk))
  297. return;
  298. clkdev_drop(lpss->clock);
  299. intel_lpss_unregister_clock_tree(lpss->clk);
  300. }
  301. int intel_lpss_probe(struct device *dev,
  302. const struct intel_lpss_platform_info *info)
  303. {
  304. struct intel_lpss *lpss;
  305. int ret;
  306. if (!info || !info->mem || info->irq <= 0)
  307. return -EINVAL;
  308. lpss = devm_kzalloc(dev, sizeof(*lpss), GFP_KERNEL);
  309. if (!lpss)
  310. return -ENOMEM;
  311. lpss->priv = devm_ioremap_uc(dev, info->mem->start + LPSS_PRIV_OFFSET,
  312. LPSS_PRIV_SIZE);
  313. if (!lpss->priv)
  314. return -ENOMEM;
  315. lpss->info = info;
  316. lpss->dev = dev;
  317. lpss->caps = readl(lpss->priv + LPSS_PRIV_CAPS);
  318. dev_set_drvdata(dev, lpss);
  319. ret = intel_lpss_assign_devs(lpss);
  320. if (ret)
  321. return ret;
  322. lpss->cell->properties = info->properties;
  323. intel_lpss_init_dev(lpss);
  324. lpss->devid = ida_simple_get(&intel_lpss_devid_ida, 0, 0, GFP_KERNEL);
  325. if (lpss->devid < 0)
  326. return lpss->devid;
  327. ret = intel_lpss_register_clock(lpss);
  328. if (ret)
  329. goto err_clk_register;
  330. intel_lpss_ltr_expose(lpss);
  331. ret = intel_lpss_debugfs_add(lpss);
  332. if (ret)
  333. dev_warn(dev, "Failed to create debugfs entries\n");
  334. if (intel_lpss_has_idma(lpss)) {
  335. ret = mfd_add_devices(dev, lpss->devid, &intel_lpss_idma64_cell,
  336. 1, info->mem, info->irq, NULL);
  337. if (ret)
  338. dev_warn(dev, "Failed to add %s, fallback to PIO\n",
  339. LPSS_IDMA64_DRIVER_NAME);
  340. }
  341. ret = mfd_add_devices(dev, lpss->devid, lpss->cell,
  342. 1, info->mem, info->irq, NULL);
  343. if (ret)
  344. goto err_remove_ltr;
  345. dev_pm_set_driver_flags(dev, DPM_FLAG_SMART_SUSPEND);
  346. return 0;
  347. err_remove_ltr:
  348. intel_lpss_debugfs_remove(lpss);
  349. intel_lpss_ltr_hide(lpss);
  350. intel_lpss_unregister_clock(lpss);
  351. err_clk_register:
  352. ida_simple_remove(&intel_lpss_devid_ida, lpss->devid);
  353. return ret;
  354. }
  355. EXPORT_SYMBOL_GPL(intel_lpss_probe);
  356. void intel_lpss_remove(struct device *dev)
  357. {
  358. struct intel_lpss *lpss = dev_get_drvdata(dev);
  359. mfd_remove_devices(dev);
  360. intel_lpss_debugfs_remove(lpss);
  361. intel_lpss_ltr_hide(lpss);
  362. intel_lpss_unregister_clock(lpss);
  363. ida_simple_remove(&intel_lpss_devid_ida, lpss->devid);
  364. }
  365. EXPORT_SYMBOL_GPL(intel_lpss_remove);
  366. static int resume_lpss_device(struct device *dev, void *data)
  367. {
  368. if (!dev_pm_test_driver_flags(dev, DPM_FLAG_SMART_SUSPEND))
  369. pm_runtime_resume(dev);
  370. return 0;
  371. }
  372. int intel_lpss_prepare(struct device *dev)
  373. {
  374. /*
  375. * Resume both child devices before entering system sleep. This
  376. * ensures that they are in proper state before they get suspended.
  377. */
  378. device_for_each_child_reverse(dev, NULL, resume_lpss_device);
  379. return 0;
  380. }
  381. EXPORT_SYMBOL_GPL(intel_lpss_prepare);
  382. int intel_lpss_suspend(struct device *dev)
  383. {
  384. struct intel_lpss *lpss = dev_get_drvdata(dev);
  385. unsigned int i;
  386. /* Save device context */
  387. for (i = 0; i < LPSS_PRIV_REG_COUNT; i++)
  388. lpss->priv_ctx[i] = readl(lpss->priv + i * 4);
  389. /*
  390. * If the device type is not UART, then put the controller into
  391. * reset. UART cannot be put into reset since S3/S0ix fail when
  392. * no_console_suspend flag is enabled.
  393. */
  394. if (lpss->type != LPSS_DEV_UART)
  395. writel(0, lpss->priv + LPSS_PRIV_RESETS);
  396. return 0;
  397. }
  398. EXPORT_SYMBOL_GPL(intel_lpss_suspend);
  399. int intel_lpss_resume(struct device *dev)
  400. {
  401. struct intel_lpss *lpss = dev_get_drvdata(dev);
  402. unsigned int i;
  403. intel_lpss_deassert_reset(lpss);
  404. /* Restore device context */
  405. for (i = 0; i < LPSS_PRIV_REG_COUNT; i++)
  406. writel(lpss->priv_ctx[i], lpss->priv + i * 4);
  407. return 0;
  408. }
  409. EXPORT_SYMBOL_GPL(intel_lpss_resume);
  410. static int __init intel_lpss_init(void)
  411. {
  412. intel_lpss_debugfs = debugfs_create_dir("intel_lpss", NULL);
  413. return 0;
  414. }
  415. module_init(intel_lpss_init);
  416. static void __exit intel_lpss_exit(void)
  417. {
  418. ida_destroy(&intel_lpss_devid_ida);
  419. debugfs_remove(intel_lpss_debugfs);
  420. }
  421. module_exit(intel_lpss_exit);
  422. MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
  423. MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
  424. MODULE_AUTHOR("Heikki Krogerus <heikki.krogerus@linux.intel.com>");
  425. MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@linux.intel.com>");
  426. MODULE_DESCRIPTION("Intel LPSS core driver");
  427. MODULE_LICENSE("GPL v2");
  428. /*
  429. * Ensure the DMA driver is loaded before the host controller device appears,
  430. * so that the host controller driver can request its DMA channels as early
  431. * as possible.
  432. *
  433. * If the DMA module is not there that's OK as well.
  434. */
  435. MODULE_SOFTDEP("pre: platform:" LPSS_IDMA64_DRIVER_NAME);