dbx500-prcmu-regs.h 8.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (C) STMicroelectronics 2009
  4. * Copyright (C) ST-Ericsson SA 2010
  5. *
  6. * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
  7. * Author: Sundar Iyer <sundar.iyer@stericsson.com>
  8. *
  9. * PRCM Unit registers
  10. */
  11. #ifndef __DB8500_PRCMU_REGS_H
  12. #define __DB8500_PRCMU_REGS_H
  13. #define BITS(_start, _end) ((BIT(_end) - BIT(_start)) + BIT(_end))
  14. #define PRCM_ACLK_MGT (0x004)
  15. #define PRCM_SVAMMCSPCLK_MGT (0x008)
  16. #define PRCM_SIAMMDSPCLK_MGT (0x00C)
  17. #define PRCM_SGACLK_MGT (0x014)
  18. #define PRCM_UARTCLK_MGT (0x018)
  19. #define PRCM_MSP02CLK_MGT (0x01C)
  20. #define PRCM_I2CCLK_MGT (0x020)
  21. #define PRCM_SDMMCCLK_MGT (0x024)
  22. #define PRCM_SLIMCLK_MGT (0x028)
  23. #define PRCM_PER1CLK_MGT (0x02C)
  24. #define PRCM_PER2CLK_MGT (0x030)
  25. #define PRCM_PER3CLK_MGT (0x034)
  26. #define PRCM_PER5CLK_MGT (0x038)
  27. #define PRCM_PER6CLK_MGT (0x03C)
  28. #define PRCM_PER7CLK_MGT (0x040)
  29. #define PRCM_LCDCLK_MGT (0x044)
  30. #define PRCM_BMLCLK_MGT (0x04C)
  31. #define PRCM_HSITXCLK_MGT (0x050)
  32. #define PRCM_HSIRXCLK_MGT (0x054)
  33. #define PRCM_HDMICLK_MGT (0x058)
  34. #define PRCM_APEATCLK_MGT (0x05C)
  35. #define PRCM_APETRACECLK_MGT (0x060)
  36. #define PRCM_MCDECLK_MGT (0x064)
  37. #define PRCM_IPI2CCLK_MGT (0x068)
  38. #define PRCM_DSIALTCLK_MGT (0x06C)
  39. #define PRCM_DMACLK_MGT (0x074)
  40. #define PRCM_B2R2CLK_MGT (0x078)
  41. #define PRCM_TVCLK_MGT (0x07C)
  42. #define PRCM_UNIPROCLK_MGT (0x278)
  43. #define PRCM_SSPCLK_MGT (0x280)
  44. #define PRCM_RNGCLK_MGT (0x284)
  45. #define PRCM_UICCCLK_MGT (0x27C)
  46. #define PRCM_MSP1CLK_MGT (0x288)
  47. #define PRCM_ARM_PLLDIVPS (prcmu_base + 0x118)
  48. #define PRCM_ARM_PLLDIVPS_ARM_BRM_RATE 0x3f
  49. #define PRCM_ARM_PLLDIVPS_MAX_MASK 0xf
  50. #define PRCM_PLLARM_LOCKP (prcmu_base + 0x0a8)
  51. #define PRCM_PLLARM_LOCKP_PRCM_PLLARM_LOCKP3 0x2
  52. #define PRCM_ARM_CHGCLKREQ (prcmu_base + 0x114)
  53. #define PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ BIT(0)
  54. #define PRCM_ARM_CHGCLKREQ_PRCM_ARM_DIVSEL BIT(16)
  55. #define PRCM_PLLARM_ENABLE (prcmu_base + 0x98)
  56. #define PRCM_PLLARM_ENABLE_PRCM_PLLARM_ENABLE 0x1
  57. #define PRCM_PLLARM_ENABLE_PRCM_PLLARM_COUNTON 0x100
  58. #define PRCM_ARMCLKFIX_MGT (prcmu_base + 0x0)
  59. #define PRCM_A9PL_FORCE_CLKEN (prcmu_base + 0x19C)
  60. #define PRCM_A9_RESETN_CLR (prcmu_base + 0x1f4)
  61. #define PRCM_A9_RESETN_SET (prcmu_base + 0x1f0)
  62. #define PRCM_ARM_LS_CLAMP (prcmu_base + 0x30c)
  63. #define PRCM_SRAM_A9 (prcmu_base + 0x308)
  64. #define PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN BIT(0)
  65. #define PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN BIT(1)
  66. /* CPU mailbox registers */
  67. #define PRCM_MBOX_CPU_VAL (prcmu_base + 0x0fc)
  68. #define PRCM_MBOX_CPU_SET (prcmu_base + 0x100)
  69. #define PRCM_MBOX_CPU_CLR (prcmu_base + 0x104)
  70. #define PRCM_HOSTACCESS_REQ (prcmu_base + 0x334)
  71. #define PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ 0x1
  72. #define PRCM_HOSTACCESS_REQ_WAKE_REQ BIT(16)
  73. #define ARM_WAKEUP_MODEM 0x1
  74. #define PRCM_ARM_IT1_CLR (prcmu_base + 0x48C)
  75. #define PRCM_ARM_IT1_VAL (prcmu_base + 0x494)
  76. #define PRCM_HOLD_EVT (prcmu_base + 0x174)
  77. #define PRCM_MOD_AWAKE_STATUS (prcmu_base + 0x4A0)
  78. #define PRCM_MOD_AWAKE_STATUS_PRCM_MOD_COREPD_AWAKE BIT(0)
  79. #define PRCM_MOD_AWAKE_STATUS_PRCM_MOD_AAPD_AWAKE BIT(1)
  80. #define PRCM_MOD_AWAKE_STATUS_PRCM_MOD_VMODEM_OFF_ISO BIT(2)
  81. #define PRCM_ITSTATUS0 (prcmu_base + 0x148)
  82. #define PRCM_ITSTATUS1 (prcmu_base + 0x150)
  83. #define PRCM_ITSTATUS2 (prcmu_base + 0x158)
  84. #define PRCM_ITSTATUS3 (prcmu_base + 0x160)
  85. #define PRCM_ITSTATUS4 (prcmu_base + 0x168)
  86. #define PRCM_ITSTATUS5 (prcmu_base + 0x484)
  87. #define PRCM_ITCLEAR5 (prcmu_base + 0x488)
  88. #define PRCM_ARMIT_MASKXP70_IT (prcmu_base + 0x1018)
  89. /* System reset register */
  90. #define PRCM_APE_SOFTRST (prcmu_base + 0x228)
  91. /* Level shifter and clamp control registers */
  92. #define PRCM_MMIP_LS_CLAMP_SET (prcmu_base + 0x420)
  93. #define PRCM_MMIP_LS_CLAMP_CLR (prcmu_base + 0x424)
  94. #define PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP BIT(11)
  95. #define PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI BIT(22)
  96. /* PRCMU clock/PLL/reset registers */
  97. #define PRCM_PLLSOC0_FREQ (prcmu_base + 0x080)
  98. #define PRCM_PLLSOC1_FREQ (prcmu_base + 0x084)
  99. #define PRCM_PLLARM_FREQ (prcmu_base + 0x088)
  100. #define PRCM_PLLDDR_FREQ (prcmu_base + 0x08C)
  101. #define PRCM_PLL_FREQ_D_SHIFT 0
  102. #define PRCM_PLL_FREQ_D_MASK BITS(0, 7)
  103. #define PRCM_PLL_FREQ_N_SHIFT 8
  104. #define PRCM_PLL_FREQ_N_MASK BITS(8, 13)
  105. #define PRCM_PLL_FREQ_R_SHIFT 16
  106. #define PRCM_PLL_FREQ_R_MASK BITS(16, 18)
  107. #define PRCM_PLL_FREQ_SELDIV2 BIT(24)
  108. #define PRCM_PLL_FREQ_DIV2EN BIT(25)
  109. #define PRCM_PLLDSI_FREQ (prcmu_base + 0x500)
  110. #define PRCM_PLLDSI_ENABLE (prcmu_base + 0x504)
  111. #define PRCM_PLLDSI_LOCKP (prcmu_base + 0x508)
  112. #define PRCM_DSI_PLLOUT_SEL (prcmu_base + 0x530)
  113. #define PRCM_DSITVCLK_DIV (prcmu_base + 0x52C)
  114. #define PRCM_PLLDSI_LOCKP (prcmu_base + 0x508)
  115. #define PRCM_APE_RESETN_SET (prcmu_base + 0x1E4)
  116. #define PRCM_APE_RESETN_CLR (prcmu_base + 0x1E8)
  117. #define PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE BIT(0)
  118. #define PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 BIT(0)
  119. #define PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3 BIT(1)
  120. #define PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_SHIFT 0
  121. #define PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_MASK BITS(0, 2)
  122. #define PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_SHIFT 8
  123. #define PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_MASK BITS(8, 10)
  124. #define PRCM_DSI_PLLOUT_SEL_OFF 0
  125. #define PRCM_DSI_PLLOUT_SEL_PHI 1
  126. #define PRCM_DSI_PLLOUT_SEL_PHI_2 2
  127. #define PRCM_DSI_PLLOUT_SEL_PHI_4 3
  128. #define PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_SHIFT 0
  129. #define PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_MASK BITS(0, 7)
  130. #define PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_SHIFT 8
  131. #define PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_MASK BITS(8, 15)
  132. #define PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_SHIFT 16
  133. #define PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_MASK BITS(16, 23)
  134. #define PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_EN BIT(24)
  135. #define PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_EN BIT(25)
  136. #define PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_EN BIT(26)
  137. #define PRCM_APE_RESETN_DSIPLL_RESETN BIT(14)
  138. #define PRCM_CLKOCR (prcmu_base + 0x1CC)
  139. #define PRCM_CLKOCR_CLKOUT0_REF_CLK (1 << 0)
  140. #define PRCM_CLKOCR_CLKOUT0_MASK BITS(0, 13)
  141. #define PRCM_CLKOCR_CLKOUT1_REF_CLK (1 << 16)
  142. #define PRCM_CLKOCR_CLKOUT1_MASK BITS(16, 29)
  143. /* ePOD and memory power signal control registers */
  144. #define PRCM_EPOD_C_SET (prcmu_base + 0x410)
  145. #define PRCM_SRAM_LS_SLEEP (prcmu_base + 0x304)
  146. /* Debug power control unit registers */
  147. #define PRCM_POWER_STATE_SET (prcmu_base + 0x254)
  148. /* Miscellaneous unit registers */
  149. #define PRCM_DSI_SW_RESET (prcmu_base + 0x324)
  150. #define PRCM_GPIOCR (prcmu_base + 0x138)
  151. #define PRCM_GPIOCR_DBG_STM_MOD_CMD1 0x800
  152. #define PRCM_GPIOCR_DBG_UARTMOD_CMD0 0x1
  153. /* PRCMU HW semaphore */
  154. #define PRCM_SEM (prcmu_base + 0x400)
  155. #define PRCM_SEM_PRCM_SEM BIT(0)
  156. #define PRCM_TCR (prcmu_base + 0x1C8)
  157. #define PRCM_TCR_TENSEL_MASK BITS(0, 7)
  158. #define PRCM_TCR_STOP_TIMERS BIT(16)
  159. #define PRCM_TCR_DOZE_MODE BIT(17)
  160. #define PRCM_CLKOCR_CLKODIV0_SHIFT 0
  161. #define PRCM_CLKOCR_CLKODIV0_MASK BITS(0, 5)
  162. #define PRCM_CLKOCR_CLKOSEL0_SHIFT 6
  163. #define PRCM_CLKOCR_CLKOSEL0_MASK BITS(6, 8)
  164. #define PRCM_CLKOCR_CLKODIV1_SHIFT 16
  165. #define PRCM_CLKOCR_CLKODIV1_MASK BITS(16, 21)
  166. #define PRCM_CLKOCR_CLKOSEL1_SHIFT 22
  167. #define PRCM_CLKOCR_CLKOSEL1_MASK BITS(22, 24)
  168. #define PRCM_CLKOCR_CLK1TYPE BIT(28)
  169. #define PRCM_CLK_MGT_CLKPLLDIV_MASK BITS(0, 4)
  170. #define PRCM_CLK_MGT_CLKPLLSW_SOC0 BIT(5)
  171. #define PRCM_CLK_MGT_CLKPLLSW_SOC1 BIT(6)
  172. #define PRCM_CLK_MGT_CLKPLLSW_DDR BIT(7)
  173. #define PRCM_CLK_MGT_CLKPLLSW_MASK BITS(5, 7)
  174. #define PRCM_CLK_MGT_CLKEN BIT(8)
  175. #define PRCM_CLK_MGT_CLK38 BIT(9)
  176. #define PRCM_CLK_MGT_CLK38DIV BIT(11)
  177. #define PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN BIT(12)
  178. /* GPIOCR register */
  179. #define PRCM_GPIOCR_SPI2_SELECT BIT(23)
  180. #define PRCM_DDR_SUBSYS_APE_MINBW (prcmu_base + 0x438)
  181. #define PRCM_CGATING_BYPASS (prcmu_base + 0x134)
  182. #define PRCM_CGATING_BYPASS_ICN2 BIT(6)
  183. /* Miscellaneous unit registers */
  184. #define PRCM_RESOUTN_SET (prcmu_base + 0x214)
  185. #define PRCM_RESOUTN_CLR (prcmu_base + 0x218)
  186. /* System reset register */
  187. #define PRCM_APE_SOFTRST (prcmu_base + 0x228)
  188. #endif /* __DB8500_PRCMU_REGS_H */