da9062-core.c 23 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Core, IRQ and I2C device driver for DA9061 and DA9062 PMICs
  4. * Copyright (C) 2015-2017 Dialog Semiconductor
  5. */
  6. #include <linux/kernel.h>
  7. #include <linux/module.h>
  8. #include <linux/init.h>
  9. #include <linux/device.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/regmap.h>
  12. #include <linux/irq.h>
  13. #include <linux/mfd/core.h>
  14. #include <linux/i2c.h>
  15. #include <linux/mfd/da9062/core.h>
  16. #include <linux/mfd/da9062/registers.h>
  17. #include <linux/regulator/of_regulator.h>
  18. #define DA9062_REG_EVENT_A_OFFSET 0
  19. #define DA9062_REG_EVENT_B_OFFSET 1
  20. #define DA9062_REG_EVENT_C_OFFSET 2
  21. #define DA9062_IRQ_LOW 0
  22. #define DA9062_IRQ_HIGH 1
  23. static struct regmap_irq da9061_irqs[] = {
  24. /* EVENT A */
  25. [DA9061_IRQ_ONKEY] = {
  26. .reg_offset = DA9062_REG_EVENT_A_OFFSET,
  27. .mask = DA9062AA_M_NONKEY_MASK,
  28. },
  29. [DA9061_IRQ_WDG_WARN] = {
  30. .reg_offset = DA9062_REG_EVENT_A_OFFSET,
  31. .mask = DA9062AA_M_WDG_WARN_MASK,
  32. },
  33. [DA9061_IRQ_SEQ_RDY] = {
  34. .reg_offset = DA9062_REG_EVENT_A_OFFSET,
  35. .mask = DA9062AA_M_SEQ_RDY_MASK,
  36. },
  37. /* EVENT B */
  38. [DA9061_IRQ_TEMP] = {
  39. .reg_offset = DA9062_REG_EVENT_B_OFFSET,
  40. .mask = DA9062AA_M_TEMP_MASK,
  41. },
  42. [DA9061_IRQ_LDO_LIM] = {
  43. .reg_offset = DA9062_REG_EVENT_B_OFFSET,
  44. .mask = DA9062AA_M_LDO_LIM_MASK,
  45. },
  46. [DA9061_IRQ_DVC_RDY] = {
  47. .reg_offset = DA9062_REG_EVENT_B_OFFSET,
  48. .mask = DA9062AA_M_DVC_RDY_MASK,
  49. },
  50. [DA9061_IRQ_VDD_WARN] = {
  51. .reg_offset = DA9062_REG_EVENT_B_OFFSET,
  52. .mask = DA9062AA_M_VDD_WARN_MASK,
  53. },
  54. /* EVENT C */
  55. [DA9061_IRQ_GPI0] = {
  56. .reg_offset = DA9062_REG_EVENT_C_OFFSET,
  57. .mask = DA9062AA_M_GPI0_MASK,
  58. },
  59. [DA9061_IRQ_GPI1] = {
  60. .reg_offset = DA9062_REG_EVENT_C_OFFSET,
  61. .mask = DA9062AA_M_GPI1_MASK,
  62. },
  63. [DA9061_IRQ_GPI2] = {
  64. .reg_offset = DA9062_REG_EVENT_C_OFFSET,
  65. .mask = DA9062AA_M_GPI2_MASK,
  66. },
  67. [DA9061_IRQ_GPI3] = {
  68. .reg_offset = DA9062_REG_EVENT_C_OFFSET,
  69. .mask = DA9062AA_M_GPI3_MASK,
  70. },
  71. [DA9061_IRQ_GPI4] = {
  72. .reg_offset = DA9062_REG_EVENT_C_OFFSET,
  73. .mask = DA9062AA_M_GPI4_MASK,
  74. },
  75. };
  76. static struct regmap_irq_chip da9061_irq_chip = {
  77. .name = "da9061-irq",
  78. .irqs = da9061_irqs,
  79. .num_irqs = DA9061_NUM_IRQ,
  80. .num_regs = 3,
  81. .status_base = DA9062AA_EVENT_A,
  82. .mask_base = DA9062AA_IRQ_MASK_A,
  83. .ack_base = DA9062AA_EVENT_A,
  84. };
  85. static struct regmap_irq da9062_irqs[] = {
  86. /* EVENT A */
  87. [DA9062_IRQ_ONKEY] = {
  88. .reg_offset = DA9062_REG_EVENT_A_OFFSET,
  89. .mask = DA9062AA_M_NONKEY_MASK,
  90. },
  91. [DA9062_IRQ_ALARM] = {
  92. .reg_offset = DA9062_REG_EVENT_A_OFFSET,
  93. .mask = DA9062AA_M_ALARM_MASK,
  94. },
  95. [DA9062_IRQ_TICK] = {
  96. .reg_offset = DA9062_REG_EVENT_A_OFFSET,
  97. .mask = DA9062AA_M_TICK_MASK,
  98. },
  99. [DA9062_IRQ_WDG_WARN] = {
  100. .reg_offset = DA9062_REG_EVENT_A_OFFSET,
  101. .mask = DA9062AA_M_WDG_WARN_MASK,
  102. },
  103. [DA9062_IRQ_SEQ_RDY] = {
  104. .reg_offset = DA9062_REG_EVENT_A_OFFSET,
  105. .mask = DA9062AA_M_SEQ_RDY_MASK,
  106. },
  107. /* EVENT B */
  108. [DA9062_IRQ_TEMP] = {
  109. .reg_offset = DA9062_REG_EVENT_B_OFFSET,
  110. .mask = DA9062AA_M_TEMP_MASK,
  111. },
  112. [DA9062_IRQ_LDO_LIM] = {
  113. .reg_offset = DA9062_REG_EVENT_B_OFFSET,
  114. .mask = DA9062AA_M_LDO_LIM_MASK,
  115. },
  116. [DA9062_IRQ_DVC_RDY] = {
  117. .reg_offset = DA9062_REG_EVENT_B_OFFSET,
  118. .mask = DA9062AA_M_DVC_RDY_MASK,
  119. },
  120. [DA9062_IRQ_VDD_WARN] = {
  121. .reg_offset = DA9062_REG_EVENT_B_OFFSET,
  122. .mask = DA9062AA_M_VDD_WARN_MASK,
  123. },
  124. /* EVENT C */
  125. [DA9062_IRQ_GPI0] = {
  126. .reg_offset = DA9062_REG_EVENT_C_OFFSET,
  127. .mask = DA9062AA_M_GPI0_MASK,
  128. },
  129. [DA9062_IRQ_GPI1] = {
  130. .reg_offset = DA9062_REG_EVENT_C_OFFSET,
  131. .mask = DA9062AA_M_GPI1_MASK,
  132. },
  133. [DA9062_IRQ_GPI2] = {
  134. .reg_offset = DA9062_REG_EVENT_C_OFFSET,
  135. .mask = DA9062AA_M_GPI2_MASK,
  136. },
  137. [DA9062_IRQ_GPI3] = {
  138. .reg_offset = DA9062_REG_EVENT_C_OFFSET,
  139. .mask = DA9062AA_M_GPI3_MASK,
  140. },
  141. [DA9062_IRQ_GPI4] = {
  142. .reg_offset = DA9062_REG_EVENT_C_OFFSET,
  143. .mask = DA9062AA_M_GPI4_MASK,
  144. },
  145. };
  146. static struct regmap_irq_chip da9062_irq_chip = {
  147. .name = "da9062-irq",
  148. .irqs = da9062_irqs,
  149. .num_irqs = DA9062_NUM_IRQ,
  150. .num_regs = 3,
  151. .status_base = DA9062AA_EVENT_A,
  152. .mask_base = DA9062AA_IRQ_MASK_A,
  153. .ack_base = DA9062AA_EVENT_A,
  154. };
  155. static struct resource da9061_core_resources[] = {
  156. DEFINE_RES_IRQ_NAMED(DA9061_IRQ_VDD_WARN, "VDD_WARN"),
  157. };
  158. static struct resource da9061_regulators_resources[] = {
  159. DEFINE_RES_IRQ_NAMED(DA9061_IRQ_LDO_LIM, "LDO_LIM"),
  160. };
  161. static struct resource da9061_thermal_resources[] = {
  162. DEFINE_RES_IRQ_NAMED(DA9061_IRQ_TEMP, "THERMAL"),
  163. };
  164. static struct resource da9061_wdt_resources[] = {
  165. DEFINE_RES_IRQ_NAMED(DA9061_IRQ_WDG_WARN, "WD_WARN"),
  166. };
  167. static struct resource da9061_onkey_resources[] = {
  168. DEFINE_RES_IRQ_NAMED(DA9061_IRQ_ONKEY, "ONKEY"),
  169. };
  170. static const struct mfd_cell da9061_devs[] = {
  171. {
  172. .name = "da9061-core",
  173. .num_resources = ARRAY_SIZE(da9061_core_resources),
  174. .resources = da9061_core_resources,
  175. },
  176. {
  177. .name = "da9062-regulators",
  178. .num_resources = ARRAY_SIZE(da9061_regulators_resources),
  179. .resources = da9061_regulators_resources,
  180. },
  181. {
  182. .name = "da9061-watchdog",
  183. .num_resources = ARRAY_SIZE(da9061_wdt_resources),
  184. .resources = da9061_wdt_resources,
  185. .of_compatible = "dlg,da9061-watchdog",
  186. },
  187. {
  188. .name = "da9061-thermal",
  189. .num_resources = ARRAY_SIZE(da9061_thermal_resources),
  190. .resources = da9061_thermal_resources,
  191. .of_compatible = "dlg,da9061-thermal",
  192. },
  193. {
  194. .name = "da9061-onkey",
  195. .num_resources = ARRAY_SIZE(da9061_onkey_resources),
  196. .resources = da9061_onkey_resources,
  197. .of_compatible = "dlg,da9061-onkey",
  198. },
  199. };
  200. static struct resource da9062_core_resources[] = {
  201. DEFINE_RES_NAMED(DA9062_IRQ_VDD_WARN, 1, "VDD_WARN", IORESOURCE_IRQ),
  202. };
  203. static struct resource da9062_regulators_resources[] = {
  204. DEFINE_RES_NAMED(DA9062_IRQ_LDO_LIM, 1, "LDO_LIM", IORESOURCE_IRQ),
  205. };
  206. static struct resource da9062_thermal_resources[] = {
  207. DEFINE_RES_NAMED(DA9062_IRQ_TEMP, 1, "THERMAL", IORESOURCE_IRQ),
  208. };
  209. static struct resource da9062_wdt_resources[] = {
  210. DEFINE_RES_NAMED(DA9062_IRQ_WDG_WARN, 1, "WD_WARN", IORESOURCE_IRQ),
  211. };
  212. static struct resource da9062_rtc_resources[] = {
  213. DEFINE_RES_NAMED(DA9062_IRQ_ALARM, 1, "ALARM", IORESOURCE_IRQ),
  214. DEFINE_RES_NAMED(DA9062_IRQ_TICK, 1, "TICK", IORESOURCE_IRQ),
  215. };
  216. static struct resource da9062_onkey_resources[] = {
  217. DEFINE_RES_NAMED(DA9062_IRQ_ONKEY, 1, "ONKEY", IORESOURCE_IRQ),
  218. };
  219. static struct resource da9062_gpio_resources[] = {
  220. DEFINE_RES_NAMED(DA9062_IRQ_GPI0, 1, "GPI0", IORESOURCE_IRQ),
  221. DEFINE_RES_NAMED(DA9062_IRQ_GPI1, 1, "GPI1", IORESOURCE_IRQ),
  222. DEFINE_RES_NAMED(DA9062_IRQ_GPI2, 1, "GPI2", IORESOURCE_IRQ),
  223. DEFINE_RES_NAMED(DA9062_IRQ_GPI3, 1, "GPI3", IORESOURCE_IRQ),
  224. DEFINE_RES_NAMED(DA9062_IRQ_GPI4, 1, "GPI4", IORESOURCE_IRQ),
  225. };
  226. static const struct mfd_cell da9062_devs[] = {
  227. {
  228. .name = "da9062-core",
  229. .num_resources = ARRAY_SIZE(da9062_core_resources),
  230. .resources = da9062_core_resources,
  231. },
  232. {
  233. .name = "da9062-regulators",
  234. .num_resources = ARRAY_SIZE(da9062_regulators_resources),
  235. .resources = da9062_regulators_resources,
  236. },
  237. {
  238. .name = "da9062-watchdog",
  239. .num_resources = ARRAY_SIZE(da9062_wdt_resources),
  240. .resources = da9062_wdt_resources,
  241. .of_compatible = "dlg,da9062-watchdog",
  242. },
  243. {
  244. .name = "da9062-thermal",
  245. .num_resources = ARRAY_SIZE(da9062_thermal_resources),
  246. .resources = da9062_thermal_resources,
  247. .of_compatible = "dlg,da9062-thermal",
  248. },
  249. {
  250. .name = "da9062-rtc",
  251. .num_resources = ARRAY_SIZE(da9062_rtc_resources),
  252. .resources = da9062_rtc_resources,
  253. .of_compatible = "dlg,da9062-rtc",
  254. },
  255. {
  256. .name = "da9062-onkey",
  257. .num_resources = ARRAY_SIZE(da9062_onkey_resources),
  258. .resources = da9062_onkey_resources,
  259. .of_compatible = "dlg,da9062-onkey",
  260. },
  261. {
  262. .name = "da9062-gpio",
  263. .num_resources = ARRAY_SIZE(da9062_gpio_resources),
  264. .resources = da9062_gpio_resources,
  265. .of_compatible = "dlg,da9062-gpio",
  266. },
  267. };
  268. static int da9062_clear_fault_log(struct da9062 *chip)
  269. {
  270. int ret;
  271. int fault_log;
  272. ret = regmap_read(chip->regmap, DA9062AA_FAULT_LOG, &fault_log);
  273. if (ret < 0)
  274. return ret;
  275. if (fault_log) {
  276. if (fault_log & DA9062AA_TWD_ERROR_MASK)
  277. dev_dbg(chip->dev, "Fault log entry detected: TWD_ERROR\n");
  278. if (fault_log & DA9062AA_POR_MASK)
  279. dev_dbg(chip->dev, "Fault log entry detected: POR\n");
  280. if (fault_log & DA9062AA_VDD_FAULT_MASK)
  281. dev_dbg(chip->dev, "Fault log entry detected: VDD_FAULT\n");
  282. if (fault_log & DA9062AA_VDD_START_MASK)
  283. dev_dbg(chip->dev, "Fault log entry detected: VDD_START\n");
  284. if (fault_log & DA9062AA_TEMP_CRIT_MASK)
  285. dev_dbg(chip->dev, "Fault log entry detected: TEMP_CRIT\n");
  286. if (fault_log & DA9062AA_KEY_RESET_MASK)
  287. dev_dbg(chip->dev, "Fault log entry detected: KEY_RESET\n");
  288. if (fault_log & DA9062AA_NSHUTDOWN_MASK)
  289. dev_dbg(chip->dev, "Fault log entry detected: NSHUTDOWN\n");
  290. if (fault_log & DA9062AA_WAIT_SHUT_MASK)
  291. dev_dbg(chip->dev, "Fault log entry detected: WAIT_SHUT\n");
  292. ret = regmap_write(chip->regmap, DA9062AA_FAULT_LOG,
  293. fault_log);
  294. }
  295. return ret;
  296. }
  297. static int da9062_get_device_type(struct da9062 *chip)
  298. {
  299. int device_id, variant_id, variant_mrc, variant_vrc;
  300. char *type;
  301. int ret;
  302. ret = regmap_read(chip->regmap, DA9062AA_DEVICE_ID, &device_id);
  303. if (ret < 0) {
  304. dev_err(chip->dev, "Cannot read chip ID.\n");
  305. return -EIO;
  306. }
  307. if (device_id != DA9062_PMIC_DEVICE_ID) {
  308. dev_err(chip->dev, "Invalid device ID: 0x%02x\n", device_id);
  309. return -ENODEV;
  310. }
  311. ret = regmap_read(chip->regmap, DA9062AA_VARIANT_ID, &variant_id);
  312. if (ret < 0) {
  313. dev_err(chip->dev, "Cannot read chip variant id.\n");
  314. return -EIO;
  315. }
  316. variant_vrc = (variant_id & DA9062AA_VRC_MASK) >> DA9062AA_VRC_SHIFT;
  317. switch (variant_vrc) {
  318. case DA9062_PMIC_VARIANT_VRC_DA9061:
  319. type = "DA9061";
  320. break;
  321. case DA9062_PMIC_VARIANT_VRC_DA9062:
  322. type = "DA9062";
  323. break;
  324. default:
  325. type = "Unknown";
  326. break;
  327. }
  328. dev_info(chip->dev,
  329. "Device detected (device-ID: 0x%02X, var-ID: 0x%02X, %s)\n",
  330. device_id, variant_id, type);
  331. variant_mrc = (variant_id & DA9062AA_MRC_MASK) >> DA9062AA_MRC_SHIFT;
  332. if (variant_mrc < DA9062_PMIC_VARIANT_MRC_AA) {
  333. dev_err(chip->dev,
  334. "Cannot support variant MRC: 0x%02X\n", variant_mrc);
  335. return -ENODEV;
  336. }
  337. return ret;
  338. }
  339. static u32 da9062_configure_irq_type(struct da9062 *chip, int irq, u32 *trigger)
  340. {
  341. u32 irq_type = 0;
  342. struct irq_data *irq_data = irq_get_irq_data(irq);
  343. if (!irq_data) {
  344. dev_err(chip->dev, "Invalid IRQ: %d\n", irq);
  345. return -EINVAL;
  346. }
  347. *trigger = irqd_get_trigger_type(irq_data);
  348. switch (*trigger) {
  349. case IRQ_TYPE_LEVEL_HIGH:
  350. irq_type = DA9062_IRQ_HIGH;
  351. break;
  352. case IRQ_TYPE_LEVEL_LOW:
  353. irq_type = DA9062_IRQ_LOW;
  354. break;
  355. default:
  356. dev_warn(chip->dev, "Unsupported IRQ type: %d\n", *trigger);
  357. return -EINVAL;
  358. }
  359. return regmap_update_bits(chip->regmap, DA9062AA_CONFIG_A,
  360. DA9062AA_IRQ_TYPE_MASK,
  361. irq_type << DA9062AA_IRQ_TYPE_SHIFT);
  362. }
  363. static const struct regmap_range da9061_aa_readable_ranges[] = {
  364. regmap_reg_range(DA9062AA_PAGE_CON, DA9062AA_STATUS_B),
  365. regmap_reg_range(DA9062AA_STATUS_D, DA9062AA_EVENT_C),
  366. regmap_reg_range(DA9062AA_IRQ_MASK_A, DA9062AA_IRQ_MASK_C),
  367. regmap_reg_range(DA9062AA_CONTROL_A, DA9062AA_GPIO_4),
  368. regmap_reg_range(DA9062AA_GPIO_WKUP_MODE, DA9062AA_GPIO_OUT3_4),
  369. regmap_reg_range(DA9062AA_BUCK1_CONT, DA9062AA_BUCK4_CONT),
  370. regmap_reg_range(DA9062AA_BUCK3_CONT, DA9062AA_BUCK3_CONT),
  371. regmap_reg_range(DA9062AA_LDO1_CONT, DA9062AA_LDO4_CONT),
  372. regmap_reg_range(DA9062AA_DVC_1, DA9062AA_DVC_1),
  373. regmap_reg_range(DA9062AA_SEQ, DA9062AA_ID_4_3),
  374. regmap_reg_range(DA9062AA_ID_12_11, DA9062AA_ID_16_15),
  375. regmap_reg_range(DA9062AA_ID_22_21, DA9062AA_ID_32_31),
  376. regmap_reg_range(DA9062AA_SEQ_A, DA9062AA_WAIT),
  377. regmap_reg_range(DA9062AA_RESET, DA9062AA_BUCK_ILIM_C),
  378. regmap_reg_range(DA9062AA_BUCK1_CFG, DA9062AA_BUCK3_CFG),
  379. regmap_reg_range(DA9062AA_VBUCK1_A, DA9062AA_VBUCK4_A),
  380. regmap_reg_range(DA9062AA_VBUCK3_A, DA9062AA_VBUCK3_A),
  381. regmap_reg_range(DA9062AA_VLDO1_A, DA9062AA_VLDO4_A),
  382. regmap_reg_range(DA9062AA_CONFIG_A, DA9062AA_CONFIG_A),
  383. regmap_reg_range(DA9062AA_VBUCK1_B, DA9062AA_VBUCK4_B),
  384. regmap_reg_range(DA9062AA_VBUCK3_B, DA9062AA_VBUCK3_B),
  385. regmap_reg_range(DA9062AA_VLDO1_B, DA9062AA_VLDO4_B),
  386. regmap_reg_range(DA9062AA_INTERFACE, DA9062AA_CONFIG_E),
  387. regmap_reg_range(DA9062AA_CONFIG_G, DA9062AA_CONFIG_K),
  388. regmap_reg_range(DA9062AA_CONFIG_M, DA9062AA_CONFIG_M),
  389. regmap_reg_range(DA9062AA_GP_ID_0, DA9062AA_GP_ID_19),
  390. regmap_reg_range(DA9062AA_DEVICE_ID, DA9062AA_CONFIG_ID),
  391. };
  392. static const struct regmap_range da9061_aa_writeable_ranges[] = {
  393. regmap_reg_range(DA9062AA_PAGE_CON, DA9062AA_PAGE_CON),
  394. regmap_reg_range(DA9062AA_FAULT_LOG, DA9062AA_EVENT_C),
  395. regmap_reg_range(DA9062AA_IRQ_MASK_A, DA9062AA_IRQ_MASK_C),
  396. regmap_reg_range(DA9062AA_CONTROL_A, DA9062AA_GPIO_4),
  397. regmap_reg_range(DA9062AA_GPIO_WKUP_MODE, DA9062AA_GPIO_OUT3_4),
  398. regmap_reg_range(DA9062AA_BUCK1_CONT, DA9062AA_BUCK4_CONT),
  399. regmap_reg_range(DA9062AA_BUCK3_CONT, DA9062AA_BUCK3_CONT),
  400. regmap_reg_range(DA9062AA_LDO1_CONT, DA9062AA_LDO4_CONT),
  401. regmap_reg_range(DA9062AA_DVC_1, DA9062AA_DVC_1),
  402. regmap_reg_range(DA9062AA_SEQ, DA9062AA_ID_4_3),
  403. regmap_reg_range(DA9062AA_ID_12_11, DA9062AA_ID_16_15),
  404. regmap_reg_range(DA9062AA_ID_22_21, DA9062AA_ID_32_31),
  405. regmap_reg_range(DA9062AA_SEQ_A, DA9062AA_WAIT),
  406. regmap_reg_range(DA9062AA_RESET, DA9062AA_BUCK_ILIM_C),
  407. regmap_reg_range(DA9062AA_BUCK1_CFG, DA9062AA_BUCK3_CFG),
  408. regmap_reg_range(DA9062AA_VBUCK1_A, DA9062AA_VBUCK4_A),
  409. regmap_reg_range(DA9062AA_VBUCK3_A, DA9062AA_VBUCK3_A),
  410. regmap_reg_range(DA9062AA_VLDO1_A, DA9062AA_VLDO4_A),
  411. regmap_reg_range(DA9062AA_CONFIG_A, DA9062AA_CONFIG_A),
  412. regmap_reg_range(DA9062AA_VBUCK1_B, DA9062AA_VBUCK4_B),
  413. regmap_reg_range(DA9062AA_VBUCK3_B, DA9062AA_VBUCK3_B),
  414. regmap_reg_range(DA9062AA_VLDO1_B, DA9062AA_VLDO4_B),
  415. regmap_reg_range(DA9062AA_GP_ID_0, DA9062AA_GP_ID_19),
  416. };
  417. static const struct regmap_range da9061_aa_volatile_ranges[] = {
  418. regmap_reg_range(DA9062AA_PAGE_CON, DA9062AA_STATUS_B),
  419. regmap_reg_range(DA9062AA_STATUS_D, DA9062AA_EVENT_C),
  420. regmap_reg_range(DA9062AA_CONTROL_A, DA9062AA_CONTROL_B),
  421. regmap_reg_range(DA9062AA_CONTROL_E, DA9062AA_CONTROL_F),
  422. regmap_reg_range(DA9062AA_BUCK1_CONT, DA9062AA_BUCK4_CONT),
  423. regmap_reg_range(DA9062AA_BUCK3_CONT, DA9062AA_BUCK3_CONT),
  424. regmap_reg_range(DA9062AA_LDO1_CONT, DA9062AA_LDO4_CONT),
  425. regmap_reg_range(DA9062AA_DVC_1, DA9062AA_DVC_1),
  426. regmap_reg_range(DA9062AA_SEQ, DA9062AA_SEQ),
  427. };
  428. static const struct regmap_access_table da9061_aa_readable_table = {
  429. .yes_ranges = da9061_aa_readable_ranges,
  430. .n_yes_ranges = ARRAY_SIZE(da9061_aa_readable_ranges),
  431. };
  432. static const struct regmap_access_table da9061_aa_writeable_table = {
  433. .yes_ranges = da9061_aa_writeable_ranges,
  434. .n_yes_ranges = ARRAY_SIZE(da9061_aa_writeable_ranges),
  435. };
  436. static const struct regmap_access_table da9061_aa_volatile_table = {
  437. .yes_ranges = da9061_aa_volatile_ranges,
  438. .n_yes_ranges = ARRAY_SIZE(da9061_aa_volatile_ranges),
  439. };
  440. static const struct regmap_range_cfg da9061_range_cfg[] = {
  441. {
  442. .range_min = DA9062AA_PAGE_CON,
  443. .range_max = DA9062AA_CONFIG_ID,
  444. .selector_reg = DA9062AA_PAGE_CON,
  445. .selector_mask = 1 << DA9062_I2C_PAGE_SEL_SHIFT,
  446. .selector_shift = DA9062_I2C_PAGE_SEL_SHIFT,
  447. .window_start = 0,
  448. .window_len = 256,
  449. }
  450. };
  451. static struct regmap_config da9061_regmap_config = {
  452. .reg_bits = 8,
  453. .val_bits = 8,
  454. .ranges = da9061_range_cfg,
  455. .num_ranges = ARRAY_SIZE(da9061_range_cfg),
  456. .max_register = DA9062AA_CONFIG_ID,
  457. .cache_type = REGCACHE_RBTREE,
  458. .rd_table = &da9061_aa_readable_table,
  459. .wr_table = &da9061_aa_writeable_table,
  460. .volatile_table = &da9061_aa_volatile_table,
  461. };
  462. static const struct regmap_range da9062_aa_readable_ranges[] = {
  463. regmap_reg_range(DA9062AA_PAGE_CON, DA9062AA_STATUS_B),
  464. regmap_reg_range(DA9062AA_STATUS_D, DA9062AA_EVENT_C),
  465. regmap_reg_range(DA9062AA_IRQ_MASK_A, DA9062AA_IRQ_MASK_C),
  466. regmap_reg_range(DA9062AA_CONTROL_A, DA9062AA_GPIO_4),
  467. regmap_reg_range(DA9062AA_GPIO_WKUP_MODE, DA9062AA_BUCK4_CONT),
  468. regmap_reg_range(DA9062AA_BUCK3_CONT, DA9062AA_BUCK3_CONT),
  469. regmap_reg_range(DA9062AA_LDO1_CONT, DA9062AA_LDO4_CONT),
  470. regmap_reg_range(DA9062AA_DVC_1, DA9062AA_DVC_1),
  471. regmap_reg_range(DA9062AA_COUNT_S, DA9062AA_SECOND_D),
  472. regmap_reg_range(DA9062AA_SEQ, DA9062AA_ID_4_3),
  473. regmap_reg_range(DA9062AA_ID_12_11, DA9062AA_ID_16_15),
  474. regmap_reg_range(DA9062AA_ID_22_21, DA9062AA_ID_32_31),
  475. regmap_reg_range(DA9062AA_SEQ_A, DA9062AA_BUCK3_CFG),
  476. regmap_reg_range(DA9062AA_VBUCK2_A, DA9062AA_VBUCK4_A),
  477. regmap_reg_range(DA9062AA_VBUCK3_A, DA9062AA_VBUCK3_A),
  478. regmap_reg_range(DA9062AA_VLDO1_A, DA9062AA_VLDO4_A),
  479. regmap_reg_range(DA9062AA_VBUCK2_B, DA9062AA_VBUCK4_B),
  480. regmap_reg_range(DA9062AA_VBUCK3_B, DA9062AA_VBUCK3_B),
  481. regmap_reg_range(DA9062AA_VLDO1_B, DA9062AA_VLDO4_B),
  482. regmap_reg_range(DA9062AA_BBAT_CONT, DA9062AA_BBAT_CONT),
  483. regmap_reg_range(DA9062AA_INTERFACE, DA9062AA_CONFIG_E),
  484. regmap_reg_range(DA9062AA_CONFIG_G, DA9062AA_CONFIG_K),
  485. regmap_reg_range(DA9062AA_CONFIG_M, DA9062AA_CONFIG_M),
  486. regmap_reg_range(DA9062AA_TRIM_CLDR, DA9062AA_GP_ID_19),
  487. regmap_reg_range(DA9062AA_DEVICE_ID, DA9062AA_CONFIG_ID),
  488. };
  489. static const struct regmap_range da9062_aa_writeable_ranges[] = {
  490. regmap_reg_range(DA9062AA_PAGE_CON, DA9062AA_PAGE_CON),
  491. regmap_reg_range(DA9062AA_FAULT_LOG, DA9062AA_EVENT_C),
  492. regmap_reg_range(DA9062AA_IRQ_MASK_A, DA9062AA_IRQ_MASK_C),
  493. regmap_reg_range(DA9062AA_CONTROL_A, DA9062AA_GPIO_4),
  494. regmap_reg_range(DA9062AA_GPIO_WKUP_MODE, DA9062AA_BUCK4_CONT),
  495. regmap_reg_range(DA9062AA_BUCK3_CONT, DA9062AA_BUCK3_CONT),
  496. regmap_reg_range(DA9062AA_LDO1_CONT, DA9062AA_LDO4_CONT),
  497. regmap_reg_range(DA9062AA_DVC_1, DA9062AA_DVC_1),
  498. regmap_reg_range(DA9062AA_COUNT_S, DA9062AA_ALARM_Y),
  499. regmap_reg_range(DA9062AA_SEQ, DA9062AA_ID_4_3),
  500. regmap_reg_range(DA9062AA_ID_12_11, DA9062AA_ID_16_15),
  501. regmap_reg_range(DA9062AA_ID_22_21, DA9062AA_ID_32_31),
  502. regmap_reg_range(DA9062AA_SEQ_A, DA9062AA_BUCK3_CFG),
  503. regmap_reg_range(DA9062AA_VBUCK2_A, DA9062AA_VBUCK4_A),
  504. regmap_reg_range(DA9062AA_VBUCK3_A, DA9062AA_VBUCK3_A),
  505. regmap_reg_range(DA9062AA_VLDO1_A, DA9062AA_VLDO4_A),
  506. regmap_reg_range(DA9062AA_VBUCK2_B, DA9062AA_VBUCK4_B),
  507. regmap_reg_range(DA9062AA_VBUCK3_B, DA9062AA_VBUCK3_B),
  508. regmap_reg_range(DA9062AA_VLDO1_B, DA9062AA_VLDO4_B),
  509. regmap_reg_range(DA9062AA_BBAT_CONT, DA9062AA_BBAT_CONT),
  510. regmap_reg_range(DA9062AA_GP_ID_0, DA9062AA_GP_ID_19),
  511. };
  512. static const struct regmap_range da9062_aa_volatile_ranges[] = {
  513. regmap_reg_range(DA9062AA_PAGE_CON, DA9062AA_STATUS_B),
  514. regmap_reg_range(DA9062AA_STATUS_D, DA9062AA_EVENT_C),
  515. regmap_reg_range(DA9062AA_CONTROL_A, DA9062AA_CONTROL_B),
  516. regmap_reg_range(DA9062AA_CONTROL_E, DA9062AA_CONTROL_F),
  517. regmap_reg_range(DA9062AA_BUCK2_CONT, DA9062AA_BUCK4_CONT),
  518. regmap_reg_range(DA9062AA_BUCK3_CONT, DA9062AA_BUCK3_CONT),
  519. regmap_reg_range(DA9062AA_LDO1_CONT, DA9062AA_LDO4_CONT),
  520. regmap_reg_range(DA9062AA_DVC_1, DA9062AA_DVC_1),
  521. regmap_reg_range(DA9062AA_COUNT_S, DA9062AA_SECOND_D),
  522. regmap_reg_range(DA9062AA_SEQ, DA9062AA_SEQ),
  523. regmap_reg_range(DA9062AA_EN_32K, DA9062AA_EN_32K),
  524. };
  525. static const struct regmap_access_table da9062_aa_readable_table = {
  526. .yes_ranges = da9062_aa_readable_ranges,
  527. .n_yes_ranges = ARRAY_SIZE(da9062_aa_readable_ranges),
  528. };
  529. static const struct regmap_access_table da9062_aa_writeable_table = {
  530. .yes_ranges = da9062_aa_writeable_ranges,
  531. .n_yes_ranges = ARRAY_SIZE(da9062_aa_writeable_ranges),
  532. };
  533. static const struct regmap_access_table da9062_aa_volatile_table = {
  534. .yes_ranges = da9062_aa_volatile_ranges,
  535. .n_yes_ranges = ARRAY_SIZE(da9062_aa_volatile_ranges),
  536. };
  537. static const struct regmap_range_cfg da9062_range_cfg[] = {
  538. {
  539. .range_min = DA9062AA_PAGE_CON,
  540. .range_max = DA9062AA_CONFIG_ID,
  541. .selector_reg = DA9062AA_PAGE_CON,
  542. .selector_mask = 1 << DA9062_I2C_PAGE_SEL_SHIFT,
  543. .selector_shift = DA9062_I2C_PAGE_SEL_SHIFT,
  544. .window_start = 0,
  545. .window_len = 256,
  546. }
  547. };
  548. static struct regmap_config da9062_regmap_config = {
  549. .reg_bits = 8,
  550. .val_bits = 8,
  551. .ranges = da9062_range_cfg,
  552. .num_ranges = ARRAY_SIZE(da9062_range_cfg),
  553. .max_register = DA9062AA_CONFIG_ID,
  554. .cache_type = REGCACHE_RBTREE,
  555. .rd_table = &da9062_aa_readable_table,
  556. .wr_table = &da9062_aa_writeable_table,
  557. .volatile_table = &da9062_aa_volatile_table,
  558. };
  559. static const struct of_device_id da9062_dt_ids[] = {
  560. { .compatible = "dlg,da9061", .data = (void *)COMPAT_TYPE_DA9061, },
  561. { .compatible = "dlg,da9062", .data = (void *)COMPAT_TYPE_DA9062, },
  562. { }
  563. };
  564. MODULE_DEVICE_TABLE(of, da9062_dt_ids);
  565. static int da9062_i2c_probe(struct i2c_client *i2c,
  566. const struct i2c_device_id *id)
  567. {
  568. struct da9062 *chip;
  569. const struct of_device_id *match;
  570. unsigned int irq_base;
  571. const struct mfd_cell *cell;
  572. const struct regmap_irq_chip *irq_chip;
  573. const struct regmap_config *config;
  574. int cell_num;
  575. u32 trigger_type = 0;
  576. int ret;
  577. chip = devm_kzalloc(&i2c->dev, sizeof(*chip), GFP_KERNEL);
  578. if (!chip)
  579. return -ENOMEM;
  580. if (i2c->dev.of_node) {
  581. match = of_match_node(da9062_dt_ids, i2c->dev.of_node);
  582. if (!match)
  583. return -EINVAL;
  584. chip->chip_type = (uintptr_t)match->data;
  585. } else {
  586. chip->chip_type = id->driver_data;
  587. }
  588. i2c_set_clientdata(i2c, chip);
  589. chip->dev = &i2c->dev;
  590. if (!i2c->irq) {
  591. dev_err(chip->dev, "No IRQ configured\n");
  592. return -EINVAL;
  593. }
  594. switch (chip->chip_type) {
  595. case COMPAT_TYPE_DA9061:
  596. cell = da9061_devs;
  597. cell_num = ARRAY_SIZE(da9061_devs);
  598. irq_chip = &da9061_irq_chip;
  599. config = &da9061_regmap_config;
  600. break;
  601. case COMPAT_TYPE_DA9062:
  602. cell = da9062_devs;
  603. cell_num = ARRAY_SIZE(da9062_devs);
  604. irq_chip = &da9062_irq_chip;
  605. config = &da9062_regmap_config;
  606. break;
  607. default:
  608. dev_err(chip->dev, "Unrecognised chip type\n");
  609. return -ENODEV;
  610. }
  611. chip->regmap = devm_regmap_init_i2c(i2c, config);
  612. if (IS_ERR(chip->regmap)) {
  613. ret = PTR_ERR(chip->regmap);
  614. dev_err(chip->dev, "Failed to allocate register map: %d\n",
  615. ret);
  616. return ret;
  617. }
  618. ret = da9062_clear_fault_log(chip);
  619. if (ret < 0)
  620. dev_warn(chip->dev, "Cannot clear fault log\n");
  621. ret = da9062_get_device_type(chip);
  622. if (ret)
  623. return ret;
  624. ret = da9062_configure_irq_type(chip, i2c->irq, &trigger_type);
  625. if (ret < 0) {
  626. dev_err(chip->dev, "Failed to configure IRQ type\n");
  627. return ret;
  628. }
  629. ret = regmap_add_irq_chip(chip->regmap, i2c->irq,
  630. trigger_type | IRQF_SHARED | IRQF_ONESHOT,
  631. -1, irq_chip, &chip->regmap_irq);
  632. if (ret) {
  633. dev_err(chip->dev, "Failed to request IRQ %d: %d\n",
  634. i2c->irq, ret);
  635. return ret;
  636. }
  637. irq_base = regmap_irq_chip_get_base(chip->regmap_irq);
  638. ret = mfd_add_devices(chip->dev, PLATFORM_DEVID_NONE, cell,
  639. cell_num, NULL, irq_base,
  640. NULL);
  641. if (ret) {
  642. dev_err(chip->dev, "Cannot register child devices\n");
  643. regmap_del_irq_chip(i2c->irq, chip->regmap_irq);
  644. return ret;
  645. }
  646. return ret;
  647. }
  648. static int da9062_i2c_remove(struct i2c_client *i2c)
  649. {
  650. struct da9062 *chip = i2c_get_clientdata(i2c);
  651. mfd_remove_devices(chip->dev);
  652. regmap_del_irq_chip(i2c->irq, chip->regmap_irq);
  653. return 0;
  654. }
  655. static const struct i2c_device_id da9062_i2c_id[] = {
  656. { "da9061", COMPAT_TYPE_DA9061 },
  657. { "da9062", COMPAT_TYPE_DA9062 },
  658. { },
  659. };
  660. MODULE_DEVICE_TABLE(i2c, da9062_i2c_id);
  661. static struct i2c_driver da9062_i2c_driver = {
  662. .driver = {
  663. .name = "da9062",
  664. .of_match_table = of_match_ptr(da9062_dt_ids),
  665. },
  666. .probe = da9062_i2c_probe,
  667. .remove = da9062_i2c_remove,
  668. .id_table = da9062_i2c_id,
  669. };
  670. module_i2c_driver(da9062_i2c_driver);
  671. MODULE_DESCRIPTION("Core device driver for Dialog DA9061 and DA9062");
  672. MODULE_AUTHOR("Steve Twiss <stwiss.opensource@diasemi.com>");
  673. MODULE_LICENSE("GPL");