da9052-irq.c 5.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * DA9052 interrupt support
  4. *
  5. * Author: Fabio Estevam <fabio.estevam@freescale.com>
  6. * Based on arizona-irq.c, which is:
  7. *
  8. * Copyright 2012 Wolfson Microelectronics plc
  9. *
  10. * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  11. */
  12. #include <linux/device.h>
  13. #include <linux/delay.h>
  14. #include <linux/input.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/irq.h>
  17. #include <linux/irqdomain.h>
  18. #include <linux/slab.h>
  19. #include <linux/module.h>
  20. #include <linux/mfd/da9052/da9052.h>
  21. #include <linux/mfd/da9052/reg.h>
  22. #define DA9052_NUM_IRQ_REGS 4
  23. #define DA9052_IRQ_MASK_POS_1 0x01
  24. #define DA9052_IRQ_MASK_POS_2 0x02
  25. #define DA9052_IRQ_MASK_POS_3 0x04
  26. #define DA9052_IRQ_MASK_POS_4 0x08
  27. #define DA9052_IRQ_MASK_POS_5 0x10
  28. #define DA9052_IRQ_MASK_POS_6 0x20
  29. #define DA9052_IRQ_MASK_POS_7 0x40
  30. #define DA9052_IRQ_MASK_POS_8 0x80
  31. static const struct regmap_irq da9052_irqs[] = {
  32. [DA9052_IRQ_DCIN] = {
  33. .reg_offset = 0,
  34. .mask = DA9052_IRQ_MASK_POS_1,
  35. },
  36. [DA9052_IRQ_VBUS] = {
  37. .reg_offset = 0,
  38. .mask = DA9052_IRQ_MASK_POS_2,
  39. },
  40. [DA9052_IRQ_DCINREM] = {
  41. .reg_offset = 0,
  42. .mask = DA9052_IRQ_MASK_POS_3,
  43. },
  44. [DA9052_IRQ_VBUSREM] = {
  45. .reg_offset = 0,
  46. .mask = DA9052_IRQ_MASK_POS_4,
  47. },
  48. [DA9052_IRQ_VDDLOW] = {
  49. .reg_offset = 0,
  50. .mask = DA9052_IRQ_MASK_POS_5,
  51. },
  52. [DA9052_IRQ_ALARM] = {
  53. .reg_offset = 0,
  54. .mask = DA9052_IRQ_MASK_POS_6,
  55. },
  56. [DA9052_IRQ_SEQRDY] = {
  57. .reg_offset = 0,
  58. .mask = DA9052_IRQ_MASK_POS_7,
  59. },
  60. [DA9052_IRQ_COMP1V2] = {
  61. .reg_offset = 0,
  62. .mask = DA9052_IRQ_MASK_POS_8,
  63. },
  64. [DA9052_IRQ_NONKEY] = {
  65. .reg_offset = 1,
  66. .mask = DA9052_IRQ_MASK_POS_1,
  67. },
  68. [DA9052_IRQ_IDFLOAT] = {
  69. .reg_offset = 1,
  70. .mask = DA9052_IRQ_MASK_POS_2,
  71. },
  72. [DA9052_IRQ_IDGND] = {
  73. .reg_offset = 1,
  74. .mask = DA9052_IRQ_MASK_POS_3,
  75. },
  76. [DA9052_IRQ_CHGEND] = {
  77. .reg_offset = 1,
  78. .mask = DA9052_IRQ_MASK_POS_4,
  79. },
  80. [DA9052_IRQ_TBAT] = {
  81. .reg_offset = 1,
  82. .mask = DA9052_IRQ_MASK_POS_5,
  83. },
  84. [DA9052_IRQ_ADC_EOM] = {
  85. .reg_offset = 1,
  86. .mask = DA9052_IRQ_MASK_POS_6,
  87. },
  88. [DA9052_IRQ_PENDOWN] = {
  89. .reg_offset = 1,
  90. .mask = DA9052_IRQ_MASK_POS_7,
  91. },
  92. [DA9052_IRQ_TSIREADY] = {
  93. .reg_offset = 1,
  94. .mask = DA9052_IRQ_MASK_POS_8,
  95. },
  96. [DA9052_IRQ_GPI0] = {
  97. .reg_offset = 2,
  98. .mask = DA9052_IRQ_MASK_POS_1,
  99. },
  100. [DA9052_IRQ_GPI1] = {
  101. .reg_offset = 2,
  102. .mask = DA9052_IRQ_MASK_POS_2,
  103. },
  104. [DA9052_IRQ_GPI2] = {
  105. .reg_offset = 2,
  106. .mask = DA9052_IRQ_MASK_POS_3,
  107. },
  108. [DA9052_IRQ_GPI3] = {
  109. .reg_offset = 2,
  110. .mask = DA9052_IRQ_MASK_POS_4,
  111. },
  112. [DA9052_IRQ_GPI4] = {
  113. .reg_offset = 2,
  114. .mask = DA9052_IRQ_MASK_POS_5,
  115. },
  116. [DA9052_IRQ_GPI5] = {
  117. .reg_offset = 2,
  118. .mask = DA9052_IRQ_MASK_POS_6,
  119. },
  120. [DA9052_IRQ_GPI6] = {
  121. .reg_offset = 2,
  122. .mask = DA9052_IRQ_MASK_POS_7,
  123. },
  124. [DA9052_IRQ_GPI7] = {
  125. .reg_offset = 2,
  126. .mask = DA9052_IRQ_MASK_POS_8,
  127. },
  128. [DA9052_IRQ_GPI8] = {
  129. .reg_offset = 3,
  130. .mask = DA9052_IRQ_MASK_POS_1,
  131. },
  132. [DA9052_IRQ_GPI9] = {
  133. .reg_offset = 3,
  134. .mask = DA9052_IRQ_MASK_POS_2,
  135. },
  136. [DA9052_IRQ_GPI10] = {
  137. .reg_offset = 3,
  138. .mask = DA9052_IRQ_MASK_POS_3,
  139. },
  140. [DA9052_IRQ_GPI11] = {
  141. .reg_offset = 3,
  142. .mask = DA9052_IRQ_MASK_POS_4,
  143. },
  144. [DA9052_IRQ_GPI12] = {
  145. .reg_offset = 3,
  146. .mask = DA9052_IRQ_MASK_POS_5,
  147. },
  148. [DA9052_IRQ_GPI13] = {
  149. .reg_offset = 3,
  150. .mask = DA9052_IRQ_MASK_POS_6,
  151. },
  152. [DA9052_IRQ_GPI14] = {
  153. .reg_offset = 3,
  154. .mask = DA9052_IRQ_MASK_POS_7,
  155. },
  156. [DA9052_IRQ_GPI15] = {
  157. .reg_offset = 3,
  158. .mask = DA9052_IRQ_MASK_POS_8,
  159. },
  160. };
  161. static const struct regmap_irq_chip da9052_regmap_irq_chip = {
  162. .name = "da9052_irq",
  163. .status_base = DA9052_EVENT_A_REG,
  164. .mask_base = DA9052_IRQ_MASK_A_REG,
  165. .ack_base = DA9052_EVENT_A_REG,
  166. .num_regs = DA9052_NUM_IRQ_REGS,
  167. .irqs = da9052_irqs,
  168. .num_irqs = ARRAY_SIZE(da9052_irqs),
  169. };
  170. static int da9052_map_irq(struct da9052 *da9052, int irq)
  171. {
  172. return regmap_irq_get_virq(da9052->irq_data, irq);
  173. }
  174. int da9052_enable_irq(struct da9052 *da9052, int irq)
  175. {
  176. irq = da9052_map_irq(da9052, irq);
  177. if (irq < 0)
  178. return irq;
  179. enable_irq(irq);
  180. return 0;
  181. }
  182. EXPORT_SYMBOL_GPL(da9052_enable_irq);
  183. int da9052_disable_irq(struct da9052 *da9052, int irq)
  184. {
  185. irq = da9052_map_irq(da9052, irq);
  186. if (irq < 0)
  187. return irq;
  188. disable_irq(irq);
  189. return 0;
  190. }
  191. EXPORT_SYMBOL_GPL(da9052_disable_irq);
  192. int da9052_disable_irq_nosync(struct da9052 *da9052, int irq)
  193. {
  194. irq = da9052_map_irq(da9052, irq);
  195. if (irq < 0)
  196. return irq;
  197. disable_irq_nosync(irq);
  198. return 0;
  199. }
  200. EXPORT_SYMBOL_GPL(da9052_disable_irq_nosync);
  201. int da9052_request_irq(struct da9052 *da9052, int irq, char *name,
  202. irq_handler_t handler, void *data)
  203. {
  204. irq = da9052_map_irq(da9052, irq);
  205. if (irq < 0)
  206. return irq;
  207. return request_threaded_irq(irq, NULL, handler,
  208. IRQF_TRIGGER_LOW | IRQF_ONESHOT,
  209. name, data);
  210. }
  211. EXPORT_SYMBOL_GPL(da9052_request_irq);
  212. void da9052_free_irq(struct da9052 *da9052, int irq, void *data)
  213. {
  214. irq = da9052_map_irq(da9052, irq);
  215. if (irq < 0)
  216. return;
  217. free_irq(irq, data);
  218. }
  219. EXPORT_SYMBOL_GPL(da9052_free_irq);
  220. static irqreturn_t da9052_auxadc_irq(int irq, void *irq_data)
  221. {
  222. struct da9052 *da9052 = irq_data;
  223. complete(&da9052->done);
  224. return IRQ_HANDLED;
  225. }
  226. int da9052_irq_init(struct da9052 *da9052)
  227. {
  228. int ret;
  229. ret = regmap_add_irq_chip(da9052->regmap, da9052->chip_irq,
  230. IRQF_TRIGGER_LOW | IRQF_ONESHOT,
  231. -1, &da9052_regmap_irq_chip,
  232. &da9052->irq_data);
  233. if (ret < 0) {
  234. dev_err(da9052->dev, "regmap_add_irq_chip failed: %d\n", ret);
  235. goto regmap_err;
  236. }
  237. enable_irq_wake(da9052->chip_irq);
  238. ret = da9052_request_irq(da9052, DA9052_IRQ_ADC_EOM, "adc-irq",
  239. da9052_auxadc_irq, da9052);
  240. if (ret != 0) {
  241. dev_err(da9052->dev, "DA9052_IRQ_ADC_EOM failed: %d\n", ret);
  242. goto request_irq_err;
  243. }
  244. return 0;
  245. request_irq_err:
  246. regmap_del_irq_chip(da9052->chip_irq, da9052->irq_data);
  247. regmap_err:
  248. return ret;
  249. }
  250. int da9052_irq_exit(struct da9052 *da9052)
  251. {
  252. da9052_free_irq(da9052, DA9052_IRQ_ADC_EOM, da9052);
  253. regmap_del_irq_chip(da9052->chip_irq, da9052->irq_data);
  254. return 0;
  255. }