mptbase.c 236 KB

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  1. /*
  2. * linux/drivers/message/fusion/mptbase.c
  3. * This is the Fusion MPT base driver which supports multiple
  4. * (SCSI + LAN) specialized protocol drivers.
  5. * For use with LSI PCI chip/adapter(s)
  6. * running LSI Fusion MPT (Message Passing Technology) firmware.
  7. *
  8. * Copyright (c) 1999-2008 LSI Corporation
  9. * (mailto:DL-MPTFusionLinux@lsi.com)
  10. *
  11. */
  12. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  13. /*
  14. This program is free software; you can redistribute it and/or modify
  15. it under the terms of the GNU General Public License as published by
  16. the Free Software Foundation; version 2 of the License.
  17. This program is distributed in the hope that it will be useful,
  18. but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. GNU General Public License for more details.
  21. NO WARRANTY
  22. THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
  23. CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
  24. LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
  25. MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
  26. solely responsible for determining the appropriateness of using and
  27. distributing the Program and assumes all risks associated with its
  28. exercise of rights under this Agreement, including but not limited to
  29. the risks and costs of program errors, damage to or loss of data,
  30. programs or equipment, and unavailability or interruption of operations.
  31. DISCLAIMER OF LIABILITY
  32. NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
  33. DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  34. DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
  35. ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
  36. TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  37. USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
  38. HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
  39. You should have received a copy of the GNU General Public License
  40. along with this program; if not, write to the Free Software
  41. Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  42. */
  43. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  44. #include <linux/kernel.h>
  45. #include <linux/module.h>
  46. #include <linux/errno.h>
  47. #include <linux/init.h>
  48. #include <linux/seq_file.h>
  49. #include <linux/slab.h>
  50. #include <linux/types.h>
  51. #include <linux/pci.h>
  52. #include <linux/kdev_t.h>
  53. #include <linux/blkdev.h>
  54. #include <linux/delay.h>
  55. #include <linux/interrupt.h> /* needed for in_interrupt() proto */
  56. #include <linux/dma-mapping.h>
  57. #include <linux/kthread.h>
  58. #include <scsi/scsi_host.h>
  59. #include "mptbase.h"
  60. #include "lsi/mpi_log_fc.h"
  61. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  62. #define my_NAME "Fusion MPT base driver"
  63. #define my_VERSION MPT_LINUX_VERSION_COMMON
  64. #define MYNAM "mptbase"
  65. MODULE_AUTHOR(MODULEAUTHOR);
  66. MODULE_DESCRIPTION(my_NAME);
  67. MODULE_LICENSE("GPL");
  68. MODULE_VERSION(my_VERSION);
  69. /*
  70. * cmd line parameters
  71. */
  72. static int mpt_msi_enable_spi;
  73. module_param(mpt_msi_enable_spi, int, 0);
  74. MODULE_PARM_DESC(mpt_msi_enable_spi,
  75. " Enable MSI Support for SPI controllers (default=0)");
  76. static int mpt_msi_enable_fc;
  77. module_param(mpt_msi_enable_fc, int, 0);
  78. MODULE_PARM_DESC(mpt_msi_enable_fc,
  79. " Enable MSI Support for FC controllers (default=0)");
  80. static int mpt_msi_enable_sas;
  81. module_param(mpt_msi_enable_sas, int, 0);
  82. MODULE_PARM_DESC(mpt_msi_enable_sas,
  83. " Enable MSI Support for SAS controllers (default=0)");
  84. static int mpt_channel_mapping;
  85. module_param(mpt_channel_mapping, int, 0);
  86. MODULE_PARM_DESC(mpt_channel_mapping, " Mapping id's to channels (default=0)");
  87. static int mpt_debug_level;
  88. static int mpt_set_debug_level(const char *val, const struct kernel_param *kp);
  89. module_param_call(mpt_debug_level, mpt_set_debug_level, param_get_int,
  90. &mpt_debug_level, 0600);
  91. MODULE_PARM_DESC(mpt_debug_level,
  92. " debug level - refer to mptdebug.h - (default=0)");
  93. int mpt_fwfault_debug;
  94. EXPORT_SYMBOL(mpt_fwfault_debug);
  95. module_param(mpt_fwfault_debug, int, 0600);
  96. MODULE_PARM_DESC(mpt_fwfault_debug,
  97. "Enable detection of Firmware fault and halt Firmware on fault - (default=0)");
  98. static char MptCallbacksName[MPT_MAX_PROTOCOL_DRIVERS]
  99. [MPT_MAX_CALLBACKNAME_LEN+1];
  100. #ifdef MFCNT
  101. static int mfcounter = 0;
  102. #define PRINT_MF_COUNT 20000
  103. #endif
  104. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  105. /*
  106. * Public data...
  107. */
  108. #define WHOINIT_UNKNOWN 0xAA
  109. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  110. /*
  111. * Private data...
  112. */
  113. /* Adapter link list */
  114. LIST_HEAD(ioc_list);
  115. /* Callback lookup table */
  116. static MPT_CALLBACK MptCallbacks[MPT_MAX_PROTOCOL_DRIVERS];
  117. /* Protocol driver class lookup table */
  118. static int MptDriverClass[MPT_MAX_PROTOCOL_DRIVERS];
  119. /* Event handler lookup table */
  120. static MPT_EVHANDLER MptEvHandlers[MPT_MAX_PROTOCOL_DRIVERS];
  121. /* Reset handler lookup table */
  122. static MPT_RESETHANDLER MptResetHandlers[MPT_MAX_PROTOCOL_DRIVERS];
  123. static struct mpt_pci_driver *MptDeviceDriverHandlers[MPT_MAX_PROTOCOL_DRIVERS];
  124. #ifdef CONFIG_PROC_FS
  125. static struct proc_dir_entry *mpt_proc_root_dir;
  126. #endif
  127. /*
  128. * Driver Callback Index's
  129. */
  130. static u8 mpt_base_index = MPT_MAX_PROTOCOL_DRIVERS;
  131. static u8 last_drv_idx;
  132. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  133. /*
  134. * Forward protos...
  135. */
  136. static irqreturn_t mpt_interrupt(int irq, void *bus_id);
  137. static int mptbase_reply(MPT_ADAPTER *ioc, MPT_FRAME_HDR *req,
  138. MPT_FRAME_HDR *reply);
  139. static int mpt_handshake_req_reply_wait(MPT_ADAPTER *ioc, int reqBytes,
  140. u32 *req, int replyBytes, u16 *u16reply, int maxwait,
  141. int sleepFlag);
  142. static int mpt_do_ioc_recovery(MPT_ADAPTER *ioc, u32 reason, int sleepFlag);
  143. static void mpt_detect_bound_ports(MPT_ADAPTER *ioc, struct pci_dev *pdev);
  144. static void mpt_adapter_disable(MPT_ADAPTER *ioc);
  145. static void mpt_adapter_dispose(MPT_ADAPTER *ioc);
  146. static void MptDisplayIocCapabilities(MPT_ADAPTER *ioc);
  147. static int MakeIocReady(MPT_ADAPTER *ioc, int force, int sleepFlag);
  148. static int GetIocFacts(MPT_ADAPTER *ioc, int sleepFlag, int reason);
  149. static int GetPortFacts(MPT_ADAPTER *ioc, int portnum, int sleepFlag);
  150. static int SendIocInit(MPT_ADAPTER *ioc, int sleepFlag);
  151. static int SendPortEnable(MPT_ADAPTER *ioc, int portnum, int sleepFlag);
  152. static int mpt_do_upload(MPT_ADAPTER *ioc, int sleepFlag);
  153. static int mpt_downloadboot(MPT_ADAPTER *ioc, MpiFwHeader_t *pFwHeader, int sleepFlag);
  154. static int mpt_diag_reset(MPT_ADAPTER *ioc, int ignore, int sleepFlag);
  155. static int KickStart(MPT_ADAPTER *ioc, int ignore, int sleepFlag);
  156. static int SendIocReset(MPT_ADAPTER *ioc, u8 reset_type, int sleepFlag);
  157. static int PrimeIocFifos(MPT_ADAPTER *ioc);
  158. static int WaitForDoorbellAck(MPT_ADAPTER *ioc, int howlong, int sleepFlag);
  159. static int WaitForDoorbellInt(MPT_ADAPTER *ioc, int howlong, int sleepFlag);
  160. static int WaitForDoorbellReply(MPT_ADAPTER *ioc, int howlong, int sleepFlag);
  161. static int GetLanConfigPages(MPT_ADAPTER *ioc);
  162. static int GetIoUnitPage2(MPT_ADAPTER *ioc);
  163. int mptbase_sas_persist_operation(MPT_ADAPTER *ioc, u8 persist_opcode);
  164. static int mpt_GetScsiPortSettings(MPT_ADAPTER *ioc, int portnum);
  165. static int mpt_readScsiDevicePageHeaders(MPT_ADAPTER *ioc, int portnum);
  166. static void mpt_read_ioc_pg_1(MPT_ADAPTER *ioc);
  167. static void mpt_read_ioc_pg_4(MPT_ADAPTER *ioc);
  168. static void mpt_get_manufacturing_pg_0(MPT_ADAPTER *ioc);
  169. static int SendEventNotification(MPT_ADAPTER *ioc, u8 EvSwitch,
  170. int sleepFlag);
  171. static int SendEventAck(MPT_ADAPTER *ioc, EventNotificationReply_t *evnp);
  172. static int mpt_host_page_access_control(MPT_ADAPTER *ioc, u8 access_control_value, int sleepFlag);
  173. static int mpt_host_page_alloc(MPT_ADAPTER *ioc, pIOCInit_t ioc_init);
  174. #ifdef CONFIG_PROC_FS
  175. static int mpt_summary_proc_show(struct seq_file *m, void *v);
  176. static int mpt_version_proc_show(struct seq_file *m, void *v);
  177. static int mpt_iocinfo_proc_show(struct seq_file *m, void *v);
  178. #endif
  179. static void mpt_get_fw_exp_ver(char *buf, MPT_ADAPTER *ioc);
  180. static int ProcessEventNotification(MPT_ADAPTER *ioc,
  181. EventNotificationReply_t *evReply, int *evHandlers);
  182. static void mpt_iocstatus_info(MPT_ADAPTER *ioc, u32 ioc_status, MPT_FRAME_HDR *mf);
  183. static void mpt_fc_log_info(MPT_ADAPTER *ioc, u32 log_info);
  184. static void mpt_spi_log_info(MPT_ADAPTER *ioc, u32 log_info);
  185. static void mpt_sas_log_info(MPT_ADAPTER *ioc, u32 log_info , u8 cb_idx);
  186. static int mpt_read_ioc_pg_3(MPT_ADAPTER *ioc);
  187. static void mpt_inactive_raid_list_free(MPT_ADAPTER *ioc);
  188. /* module entry point */
  189. static int __init fusion_init (void);
  190. static void __exit fusion_exit (void);
  191. #define CHIPREG_READ32(addr) readl_relaxed(addr)
  192. #define CHIPREG_READ32_dmasync(addr) readl(addr)
  193. #define CHIPREG_WRITE32(addr,val) writel(val, addr)
  194. #define CHIPREG_PIO_WRITE32(addr,val) outl(val, (unsigned long)addr)
  195. #define CHIPREG_PIO_READ32(addr) inl((unsigned long)addr)
  196. static void
  197. pci_disable_io_access(struct pci_dev *pdev)
  198. {
  199. u16 command_reg;
  200. pci_read_config_word(pdev, PCI_COMMAND, &command_reg);
  201. command_reg &= ~1;
  202. pci_write_config_word(pdev, PCI_COMMAND, command_reg);
  203. }
  204. static void
  205. pci_enable_io_access(struct pci_dev *pdev)
  206. {
  207. u16 command_reg;
  208. pci_read_config_word(pdev, PCI_COMMAND, &command_reg);
  209. command_reg |= 1;
  210. pci_write_config_word(pdev, PCI_COMMAND, command_reg);
  211. }
  212. static int mpt_set_debug_level(const char *val, const struct kernel_param *kp)
  213. {
  214. int ret = param_set_int(val, kp);
  215. MPT_ADAPTER *ioc;
  216. if (ret)
  217. return ret;
  218. list_for_each_entry(ioc, &ioc_list, list)
  219. ioc->debug_level = mpt_debug_level;
  220. return 0;
  221. }
  222. /**
  223. * mpt_get_cb_idx - obtain cb_idx for registered driver
  224. * @dclass: class driver enum
  225. *
  226. * Returns cb_idx, or zero means it wasn't found
  227. **/
  228. static u8
  229. mpt_get_cb_idx(MPT_DRIVER_CLASS dclass)
  230. {
  231. u8 cb_idx;
  232. for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--)
  233. if (MptDriverClass[cb_idx] == dclass)
  234. return cb_idx;
  235. return 0;
  236. }
  237. /**
  238. * mpt_is_discovery_complete - determine if discovery has completed
  239. * @ioc: per adatper instance
  240. *
  241. * Returns 1 when discovery completed, else zero.
  242. */
  243. static int
  244. mpt_is_discovery_complete(MPT_ADAPTER *ioc)
  245. {
  246. ConfigExtendedPageHeader_t hdr;
  247. CONFIGPARMS cfg;
  248. SasIOUnitPage0_t *buffer;
  249. dma_addr_t dma_handle;
  250. int rc = 0;
  251. memset(&hdr, 0, sizeof(ConfigExtendedPageHeader_t));
  252. memset(&cfg, 0, sizeof(CONFIGPARMS));
  253. hdr.PageVersion = MPI_SASIOUNITPAGE0_PAGEVERSION;
  254. hdr.PageType = MPI_CONFIG_PAGETYPE_EXTENDED;
  255. hdr.ExtPageType = MPI_CONFIG_EXTPAGETYPE_SAS_IO_UNIT;
  256. cfg.cfghdr.ehdr = &hdr;
  257. cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
  258. if ((mpt_config(ioc, &cfg)))
  259. goto out;
  260. if (!hdr.ExtPageLength)
  261. goto out;
  262. buffer = pci_alloc_consistent(ioc->pcidev, hdr.ExtPageLength * 4,
  263. &dma_handle);
  264. if (!buffer)
  265. goto out;
  266. cfg.physAddr = dma_handle;
  267. cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
  268. if ((mpt_config(ioc, &cfg)))
  269. goto out_free_consistent;
  270. if (!(buffer->PhyData[0].PortFlags &
  271. MPI_SAS_IOUNIT0_PORT_FLAGS_DISCOVERY_IN_PROGRESS))
  272. rc = 1;
  273. out_free_consistent:
  274. pci_free_consistent(ioc->pcidev, hdr.ExtPageLength * 4,
  275. buffer, dma_handle);
  276. out:
  277. return rc;
  278. }
  279. /**
  280. * mpt_remove_dead_ioc_func - kthread context to remove dead ioc
  281. * @arg: input argument, used to derive ioc
  282. *
  283. * Return 0 if controller is removed from pci subsystem.
  284. * Return -1 for other case.
  285. */
  286. static int mpt_remove_dead_ioc_func(void *arg)
  287. {
  288. MPT_ADAPTER *ioc = (MPT_ADAPTER *)arg;
  289. struct pci_dev *pdev;
  290. if (!ioc)
  291. return -1;
  292. pdev = ioc->pcidev;
  293. if (!pdev)
  294. return -1;
  295. pci_stop_and_remove_bus_device_locked(pdev);
  296. return 0;
  297. }
  298. /**
  299. * mpt_fault_reset_work - work performed on workq after ioc fault
  300. * @work: input argument, used to derive ioc
  301. *
  302. **/
  303. static void
  304. mpt_fault_reset_work(struct work_struct *work)
  305. {
  306. MPT_ADAPTER *ioc =
  307. container_of(work, MPT_ADAPTER, fault_reset_work.work);
  308. u32 ioc_raw_state;
  309. int rc;
  310. unsigned long flags;
  311. MPT_SCSI_HOST *hd;
  312. struct task_struct *p;
  313. if (ioc->ioc_reset_in_progress || !ioc->active)
  314. goto out;
  315. ioc_raw_state = mpt_GetIocState(ioc, 0);
  316. if ((ioc_raw_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_MASK) {
  317. printk(MYIOC_s_INFO_FMT "%s: IOC is non-operational !!!!\n",
  318. ioc->name, __func__);
  319. /*
  320. * Call mptscsih_flush_pending_cmds callback so that we
  321. * flush all pending commands back to OS.
  322. * This call is required to aovid deadlock at block layer.
  323. * Dead IOC will fail to do diag reset,and this call is safe
  324. * since dead ioc will never return any command back from HW.
  325. */
  326. hd = shost_priv(ioc->sh);
  327. ioc->schedule_dead_ioc_flush_running_cmds(hd);
  328. /*Remove the Dead Host */
  329. p = kthread_run(mpt_remove_dead_ioc_func, ioc,
  330. "mpt_dead_ioc_%d", ioc->id);
  331. if (IS_ERR(p)) {
  332. printk(MYIOC_s_ERR_FMT
  333. "%s: Running mpt_dead_ioc thread failed !\n",
  334. ioc->name, __func__);
  335. } else {
  336. printk(MYIOC_s_WARN_FMT
  337. "%s: Running mpt_dead_ioc thread success !\n",
  338. ioc->name, __func__);
  339. }
  340. return; /* don't rearm timer */
  341. }
  342. if ((ioc_raw_state & MPI_IOC_STATE_MASK)
  343. == MPI_IOC_STATE_FAULT) {
  344. printk(MYIOC_s_WARN_FMT "IOC is in FAULT state (%04xh)!!!\n",
  345. ioc->name, ioc_raw_state & MPI_DOORBELL_DATA_MASK);
  346. printk(MYIOC_s_WARN_FMT "Issuing HardReset from %s!!\n",
  347. ioc->name, __func__);
  348. rc = mpt_HardResetHandler(ioc, CAN_SLEEP);
  349. printk(MYIOC_s_WARN_FMT "%s: HardReset: %s\n", ioc->name,
  350. __func__, (rc == 0) ? "success" : "failed");
  351. ioc_raw_state = mpt_GetIocState(ioc, 0);
  352. if ((ioc_raw_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_FAULT)
  353. printk(MYIOC_s_WARN_FMT "IOC is in FAULT state after "
  354. "reset (%04xh)\n", ioc->name, ioc_raw_state &
  355. MPI_DOORBELL_DATA_MASK);
  356. } else if (ioc->bus_type == SAS && ioc->sas_discovery_quiesce_io) {
  357. if ((mpt_is_discovery_complete(ioc))) {
  358. devtprintk(ioc, printk(MYIOC_s_DEBUG_FMT "clearing "
  359. "discovery_quiesce_io flag\n", ioc->name));
  360. ioc->sas_discovery_quiesce_io = 0;
  361. }
  362. }
  363. out:
  364. /*
  365. * Take turns polling alternate controller
  366. */
  367. if (ioc->alt_ioc)
  368. ioc = ioc->alt_ioc;
  369. /* rearm the timer */
  370. spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
  371. if (ioc->reset_work_q)
  372. queue_delayed_work(ioc->reset_work_q, &ioc->fault_reset_work,
  373. msecs_to_jiffies(MPT_POLLING_INTERVAL));
  374. spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
  375. }
  376. /*
  377. * Process turbo (context) reply...
  378. */
  379. static void
  380. mpt_turbo_reply(MPT_ADAPTER *ioc, u32 pa)
  381. {
  382. MPT_FRAME_HDR *mf = NULL;
  383. MPT_FRAME_HDR *mr = NULL;
  384. u16 req_idx = 0;
  385. u8 cb_idx;
  386. dmfprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Got TURBO reply req_idx=%08x\n",
  387. ioc->name, pa));
  388. switch (pa >> MPI_CONTEXT_REPLY_TYPE_SHIFT) {
  389. case MPI_CONTEXT_REPLY_TYPE_SCSI_INIT:
  390. req_idx = pa & 0x0000FFFF;
  391. cb_idx = (pa & 0x00FF0000) >> 16;
  392. mf = MPT_INDEX_2_MFPTR(ioc, req_idx);
  393. break;
  394. case MPI_CONTEXT_REPLY_TYPE_LAN:
  395. cb_idx = mpt_get_cb_idx(MPTLAN_DRIVER);
  396. /*
  397. * Blind set of mf to NULL here was fatal
  398. * after lan_reply says "freeme"
  399. * Fix sort of combined with an optimization here;
  400. * added explicit check for case where lan_reply
  401. * was just returning 1 and doing nothing else.
  402. * For this case skip the callback, but set up
  403. * proper mf value first here:-)
  404. */
  405. if ((pa & 0x58000000) == 0x58000000) {
  406. req_idx = pa & 0x0000FFFF;
  407. mf = MPT_INDEX_2_MFPTR(ioc, req_idx);
  408. mpt_free_msg_frame(ioc, mf);
  409. mb();
  410. return;
  411. break;
  412. }
  413. mr = (MPT_FRAME_HDR *) CAST_U32_TO_PTR(pa);
  414. break;
  415. case MPI_CONTEXT_REPLY_TYPE_SCSI_TARGET:
  416. cb_idx = mpt_get_cb_idx(MPTSTM_DRIVER);
  417. mr = (MPT_FRAME_HDR *) CAST_U32_TO_PTR(pa);
  418. break;
  419. default:
  420. cb_idx = 0;
  421. BUG();
  422. }
  423. /* Check for (valid) IO callback! */
  424. if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS ||
  425. MptCallbacks[cb_idx] == NULL) {
  426. printk(MYIOC_s_WARN_FMT "%s: Invalid cb_idx (%d)!\n",
  427. __func__, ioc->name, cb_idx);
  428. goto out;
  429. }
  430. if (MptCallbacks[cb_idx](ioc, mf, mr))
  431. mpt_free_msg_frame(ioc, mf);
  432. out:
  433. mb();
  434. }
  435. static void
  436. mpt_reply(MPT_ADAPTER *ioc, u32 pa)
  437. {
  438. MPT_FRAME_HDR *mf;
  439. MPT_FRAME_HDR *mr;
  440. u16 req_idx;
  441. u8 cb_idx;
  442. int freeme;
  443. u32 reply_dma_low;
  444. u16 ioc_stat;
  445. /* non-TURBO reply! Hmmm, something may be up...
  446. * Newest turbo reply mechanism; get address
  447. * via left shift 1 (get rid of MPI_ADDRESS_REPLY_A_BIT)!
  448. */
  449. /* Map DMA address of reply header to cpu address.
  450. * pa is 32 bits - but the dma address may be 32 or 64 bits
  451. * get offset based only only the low addresses
  452. */
  453. reply_dma_low = (pa <<= 1);
  454. mr = (MPT_FRAME_HDR *)((u8 *)ioc->reply_frames +
  455. (reply_dma_low - ioc->reply_frames_low_dma));
  456. req_idx = le16_to_cpu(mr->u.frame.hwhdr.msgctxu.fld.req_idx);
  457. cb_idx = mr->u.frame.hwhdr.msgctxu.fld.cb_idx;
  458. mf = MPT_INDEX_2_MFPTR(ioc, req_idx);
  459. dmfprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Got non-TURBO reply=%p req_idx=%x cb_idx=%x Function=%x\n",
  460. ioc->name, mr, req_idx, cb_idx, mr->u.hdr.Function));
  461. DBG_DUMP_REPLY_FRAME(ioc, (u32 *)mr);
  462. /* Check/log IOC log info
  463. */
  464. ioc_stat = le16_to_cpu(mr->u.reply.IOCStatus);
  465. if (ioc_stat & MPI_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
  466. u32 log_info = le32_to_cpu(mr->u.reply.IOCLogInfo);
  467. if (ioc->bus_type == FC)
  468. mpt_fc_log_info(ioc, log_info);
  469. else if (ioc->bus_type == SPI)
  470. mpt_spi_log_info(ioc, log_info);
  471. else if (ioc->bus_type == SAS)
  472. mpt_sas_log_info(ioc, log_info, cb_idx);
  473. }
  474. if (ioc_stat & MPI_IOCSTATUS_MASK)
  475. mpt_iocstatus_info(ioc, (u32)ioc_stat, mf);
  476. /* Check for (valid) IO callback! */
  477. if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS ||
  478. MptCallbacks[cb_idx] == NULL) {
  479. printk(MYIOC_s_WARN_FMT "%s: Invalid cb_idx (%d)!\n",
  480. __func__, ioc->name, cb_idx);
  481. freeme = 0;
  482. goto out;
  483. }
  484. freeme = MptCallbacks[cb_idx](ioc, mf, mr);
  485. out:
  486. /* Flush (non-TURBO) reply with a WRITE! */
  487. CHIPREG_WRITE32(&ioc->chip->ReplyFifo, pa);
  488. if (freeme)
  489. mpt_free_msg_frame(ioc, mf);
  490. mb();
  491. }
  492. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  493. /**
  494. * mpt_interrupt - MPT adapter (IOC) specific interrupt handler.
  495. * @irq: irq number (not used)
  496. * @bus_id: bus identifier cookie == pointer to MPT_ADAPTER structure
  497. *
  498. * This routine is registered via the request_irq() kernel API call,
  499. * and handles all interrupts generated from a specific MPT adapter
  500. * (also referred to as a IO Controller or IOC).
  501. * This routine must clear the interrupt from the adapter and does
  502. * so by reading the reply FIFO. Multiple replies may be processed
  503. * per single call to this routine.
  504. *
  505. * This routine handles register-level access of the adapter but
  506. * dispatches (calls) a protocol-specific callback routine to handle
  507. * the protocol-specific details of the MPT request completion.
  508. */
  509. static irqreturn_t
  510. mpt_interrupt(int irq, void *bus_id)
  511. {
  512. MPT_ADAPTER *ioc = bus_id;
  513. u32 pa = CHIPREG_READ32_dmasync(&ioc->chip->ReplyFifo);
  514. if (pa == 0xFFFFFFFF)
  515. return IRQ_NONE;
  516. /*
  517. * Drain the reply FIFO!
  518. */
  519. do {
  520. if (pa & MPI_ADDRESS_REPLY_A_BIT)
  521. mpt_reply(ioc, pa);
  522. else
  523. mpt_turbo_reply(ioc, pa);
  524. pa = CHIPREG_READ32_dmasync(&ioc->chip->ReplyFifo);
  525. } while (pa != 0xFFFFFFFF);
  526. return IRQ_HANDLED;
  527. }
  528. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  529. /**
  530. * mptbase_reply - MPT base driver's callback routine
  531. * @ioc: Pointer to MPT_ADAPTER structure
  532. * @req: Pointer to original MPT request frame
  533. * @reply: Pointer to MPT reply frame (NULL if TurboReply)
  534. *
  535. * MPT base driver's callback routine; all base driver
  536. * "internal" request/reply processing is routed here.
  537. * Currently used for EventNotification and EventAck handling.
  538. *
  539. * Returns 1 indicating original alloc'd request frame ptr
  540. * should be freed, or 0 if it shouldn't.
  541. */
  542. static int
  543. mptbase_reply(MPT_ADAPTER *ioc, MPT_FRAME_HDR *req, MPT_FRAME_HDR *reply)
  544. {
  545. EventNotificationReply_t *pEventReply;
  546. u8 event;
  547. int evHandlers;
  548. int freereq = 1;
  549. switch (reply->u.hdr.Function) {
  550. case MPI_FUNCTION_EVENT_NOTIFICATION:
  551. pEventReply = (EventNotificationReply_t *)reply;
  552. evHandlers = 0;
  553. ProcessEventNotification(ioc, pEventReply, &evHandlers);
  554. event = le32_to_cpu(pEventReply->Event) & 0xFF;
  555. if (pEventReply->MsgFlags & MPI_MSGFLAGS_CONTINUATION_REPLY)
  556. freereq = 0;
  557. if (event != MPI_EVENT_EVENT_CHANGE)
  558. break;
  559. fallthrough;
  560. case MPI_FUNCTION_CONFIG:
  561. case MPI_FUNCTION_SAS_IO_UNIT_CONTROL:
  562. ioc->mptbase_cmds.status |= MPT_MGMT_STATUS_COMMAND_GOOD;
  563. ioc->mptbase_cmds.status |= MPT_MGMT_STATUS_RF_VALID;
  564. memcpy(ioc->mptbase_cmds.reply, reply,
  565. min(MPT_DEFAULT_FRAME_SIZE,
  566. 4 * reply->u.reply.MsgLength));
  567. if (ioc->mptbase_cmds.status & MPT_MGMT_STATUS_PENDING) {
  568. ioc->mptbase_cmds.status &= ~MPT_MGMT_STATUS_PENDING;
  569. complete(&ioc->mptbase_cmds.done);
  570. } else
  571. freereq = 0;
  572. if (ioc->mptbase_cmds.status & MPT_MGMT_STATUS_FREE_MF)
  573. freereq = 1;
  574. break;
  575. case MPI_FUNCTION_EVENT_ACK:
  576. devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  577. "EventAck reply received\n", ioc->name));
  578. break;
  579. default:
  580. printk(MYIOC_s_ERR_FMT
  581. "Unexpected msg function (=%02Xh) reply received!\n",
  582. ioc->name, reply->u.hdr.Function);
  583. break;
  584. }
  585. /*
  586. * Conditionally tell caller to free the original
  587. * EventNotification/EventAck/unexpected request frame!
  588. */
  589. return freereq;
  590. }
  591. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  592. /**
  593. * mpt_register - Register protocol-specific main callback handler.
  594. * @cbfunc: callback function pointer
  595. * @dclass: Protocol driver's class (%MPT_DRIVER_CLASS enum value)
  596. * @func_name: call function's name
  597. *
  598. * This routine is called by a protocol-specific driver (SCSI host,
  599. * LAN, SCSI target) to register its reply callback routine. Each
  600. * protocol-specific driver must do this before it will be able to
  601. * use any IOC resources, such as obtaining request frames.
  602. *
  603. * NOTES: The SCSI protocol driver currently calls this routine thrice
  604. * in order to register separate callbacks; one for "normal" SCSI IO;
  605. * one for MptScsiTaskMgmt requests; one for Scan/DV requests.
  606. *
  607. * Returns u8 valued "handle" in the range (and S.O.D. order)
  608. * {N,...,7,6,5,...,1} if successful.
  609. * A return value of MPT_MAX_PROTOCOL_DRIVERS (including zero!) should be
  610. * considered an error by the caller.
  611. */
  612. u8
  613. mpt_register(MPT_CALLBACK cbfunc, MPT_DRIVER_CLASS dclass, char *func_name)
  614. {
  615. u8 cb_idx;
  616. last_drv_idx = MPT_MAX_PROTOCOL_DRIVERS;
  617. /*
  618. * Search for empty callback slot in this order: {N,...,7,6,5,...,1}
  619. * (slot/handle 0 is reserved!)
  620. */
  621. for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
  622. if (MptCallbacks[cb_idx] == NULL) {
  623. MptCallbacks[cb_idx] = cbfunc;
  624. MptDriverClass[cb_idx] = dclass;
  625. MptEvHandlers[cb_idx] = NULL;
  626. last_drv_idx = cb_idx;
  627. strlcpy(MptCallbacksName[cb_idx], func_name,
  628. MPT_MAX_CALLBACKNAME_LEN+1);
  629. break;
  630. }
  631. }
  632. return last_drv_idx;
  633. }
  634. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  635. /**
  636. * mpt_deregister - Deregister a protocol drivers resources.
  637. * @cb_idx: previously registered callback handle
  638. *
  639. * Each protocol-specific driver should call this routine when its
  640. * module is unloaded.
  641. */
  642. void
  643. mpt_deregister(u8 cb_idx)
  644. {
  645. if (cb_idx && (cb_idx < MPT_MAX_PROTOCOL_DRIVERS)) {
  646. MptCallbacks[cb_idx] = NULL;
  647. MptDriverClass[cb_idx] = MPTUNKNOWN_DRIVER;
  648. MptEvHandlers[cb_idx] = NULL;
  649. last_drv_idx++;
  650. }
  651. }
  652. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  653. /**
  654. * mpt_event_register - Register protocol-specific event callback handler.
  655. * @cb_idx: previously registered (via mpt_register) callback handle
  656. * @ev_cbfunc: callback function
  657. *
  658. * This routine can be called by one or more protocol-specific drivers
  659. * if/when they choose to be notified of MPT events.
  660. *
  661. * Returns 0 for success.
  662. */
  663. int
  664. mpt_event_register(u8 cb_idx, MPT_EVHANDLER ev_cbfunc)
  665. {
  666. if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS)
  667. return -1;
  668. MptEvHandlers[cb_idx] = ev_cbfunc;
  669. return 0;
  670. }
  671. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  672. /**
  673. * mpt_event_deregister - Deregister protocol-specific event callback handler
  674. * @cb_idx: previously registered callback handle
  675. *
  676. * Each protocol-specific driver should call this routine
  677. * when it does not (or can no longer) handle events,
  678. * or when its module is unloaded.
  679. */
  680. void
  681. mpt_event_deregister(u8 cb_idx)
  682. {
  683. if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS)
  684. return;
  685. MptEvHandlers[cb_idx] = NULL;
  686. }
  687. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  688. /**
  689. * mpt_reset_register - Register protocol-specific IOC reset handler.
  690. * @cb_idx: previously registered (via mpt_register) callback handle
  691. * @reset_func: reset function
  692. *
  693. * This routine can be called by one or more protocol-specific drivers
  694. * if/when they choose to be notified of IOC resets.
  695. *
  696. * Returns 0 for success.
  697. */
  698. int
  699. mpt_reset_register(u8 cb_idx, MPT_RESETHANDLER reset_func)
  700. {
  701. if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS)
  702. return -1;
  703. MptResetHandlers[cb_idx] = reset_func;
  704. return 0;
  705. }
  706. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  707. /**
  708. * mpt_reset_deregister - Deregister protocol-specific IOC reset handler.
  709. * @cb_idx: previously registered callback handle
  710. *
  711. * Each protocol-specific driver should call this routine
  712. * when it does not (or can no longer) handle IOC reset handling,
  713. * or when its module is unloaded.
  714. */
  715. void
  716. mpt_reset_deregister(u8 cb_idx)
  717. {
  718. if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS)
  719. return;
  720. MptResetHandlers[cb_idx] = NULL;
  721. }
  722. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  723. /**
  724. * mpt_device_driver_register - Register device driver hooks
  725. * @dd_cbfunc: driver callbacks struct
  726. * @cb_idx: MPT protocol driver index
  727. */
  728. int
  729. mpt_device_driver_register(struct mpt_pci_driver * dd_cbfunc, u8 cb_idx)
  730. {
  731. MPT_ADAPTER *ioc;
  732. const struct pci_device_id *id;
  733. if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS)
  734. return -EINVAL;
  735. MptDeviceDriverHandlers[cb_idx] = dd_cbfunc;
  736. /* call per pci device probe entry point */
  737. list_for_each_entry(ioc, &ioc_list, list) {
  738. id = ioc->pcidev->driver ?
  739. ioc->pcidev->driver->id_table : NULL;
  740. if (dd_cbfunc->probe)
  741. dd_cbfunc->probe(ioc->pcidev, id);
  742. }
  743. return 0;
  744. }
  745. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  746. /**
  747. * mpt_device_driver_deregister - DeRegister device driver hooks
  748. * @cb_idx: MPT protocol driver index
  749. */
  750. void
  751. mpt_device_driver_deregister(u8 cb_idx)
  752. {
  753. struct mpt_pci_driver *dd_cbfunc;
  754. MPT_ADAPTER *ioc;
  755. if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS)
  756. return;
  757. dd_cbfunc = MptDeviceDriverHandlers[cb_idx];
  758. list_for_each_entry(ioc, &ioc_list, list) {
  759. if (dd_cbfunc->remove)
  760. dd_cbfunc->remove(ioc->pcidev);
  761. }
  762. MptDeviceDriverHandlers[cb_idx] = NULL;
  763. }
  764. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  765. /**
  766. * mpt_get_msg_frame - Obtain an MPT request frame from the pool
  767. * @cb_idx: Handle of registered MPT protocol driver
  768. * @ioc: Pointer to MPT adapter structure
  769. *
  770. * Obtain an MPT request frame from the pool (of 1024) that are
  771. * allocated per MPT adapter.
  772. *
  773. * Returns pointer to a MPT request frame or %NULL if none are available
  774. * or IOC is not active.
  775. */
  776. MPT_FRAME_HDR*
  777. mpt_get_msg_frame(u8 cb_idx, MPT_ADAPTER *ioc)
  778. {
  779. MPT_FRAME_HDR *mf;
  780. unsigned long flags;
  781. u16 req_idx; /* Request index */
  782. /* validate handle and ioc identifier */
  783. #ifdef MFCNT
  784. if (!ioc->active)
  785. printk(MYIOC_s_WARN_FMT "IOC Not Active! mpt_get_msg_frame "
  786. "returning NULL!\n", ioc->name);
  787. #endif
  788. /* If interrupts are not attached, do not return a request frame */
  789. if (!ioc->active)
  790. return NULL;
  791. spin_lock_irqsave(&ioc->FreeQlock, flags);
  792. if (!list_empty(&ioc->FreeQ)) {
  793. int req_offset;
  794. mf = list_entry(ioc->FreeQ.next, MPT_FRAME_HDR,
  795. u.frame.linkage.list);
  796. list_del(&mf->u.frame.linkage.list);
  797. mf->u.frame.linkage.arg1 = 0;
  798. mf->u.frame.hwhdr.msgctxu.fld.cb_idx = cb_idx; /* byte */
  799. req_offset = (u8 *)mf - (u8 *)ioc->req_frames;
  800. /* u16! */
  801. req_idx = req_offset / ioc->req_sz;
  802. mf->u.frame.hwhdr.msgctxu.fld.req_idx = cpu_to_le16(req_idx);
  803. mf->u.frame.hwhdr.msgctxu.fld.rsvd = 0;
  804. /* Default, will be changed if necessary in SG generation */
  805. ioc->RequestNB[req_idx] = ioc->NB_for_64_byte_frame;
  806. #ifdef MFCNT
  807. ioc->mfcnt++;
  808. #endif
  809. }
  810. else
  811. mf = NULL;
  812. spin_unlock_irqrestore(&ioc->FreeQlock, flags);
  813. #ifdef MFCNT
  814. if (mf == NULL)
  815. printk(MYIOC_s_WARN_FMT "IOC Active. No free Msg Frames! "
  816. "Count 0x%x Max 0x%x\n", ioc->name, ioc->mfcnt,
  817. ioc->req_depth);
  818. mfcounter++;
  819. if (mfcounter == PRINT_MF_COUNT)
  820. printk(MYIOC_s_INFO_FMT "MF Count 0x%x Max 0x%x \n", ioc->name,
  821. ioc->mfcnt, ioc->req_depth);
  822. #endif
  823. dmfprintk(ioc, printk(MYIOC_s_DEBUG_FMT "mpt_get_msg_frame(%d,%d), got mf=%p\n",
  824. ioc->name, cb_idx, ioc->id, mf));
  825. return mf;
  826. }
  827. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  828. /**
  829. * mpt_put_msg_frame - Send a protocol-specific MPT request frame to an IOC
  830. * @cb_idx: Handle of registered MPT protocol driver
  831. * @ioc: Pointer to MPT adapter structure
  832. * @mf: Pointer to MPT request frame
  833. *
  834. * This routine posts an MPT request frame to the request post FIFO of a
  835. * specific MPT adapter.
  836. */
  837. void
  838. mpt_put_msg_frame(u8 cb_idx, MPT_ADAPTER *ioc, MPT_FRAME_HDR *mf)
  839. {
  840. u32 mf_dma_addr;
  841. int req_offset;
  842. u16 req_idx; /* Request index */
  843. /* ensure values are reset properly! */
  844. mf->u.frame.hwhdr.msgctxu.fld.cb_idx = cb_idx; /* byte */
  845. req_offset = (u8 *)mf - (u8 *)ioc->req_frames;
  846. /* u16! */
  847. req_idx = req_offset / ioc->req_sz;
  848. mf->u.frame.hwhdr.msgctxu.fld.req_idx = cpu_to_le16(req_idx);
  849. mf->u.frame.hwhdr.msgctxu.fld.rsvd = 0;
  850. DBG_DUMP_PUT_MSG_FRAME(ioc, (u32 *)mf);
  851. mf_dma_addr = (ioc->req_frames_low_dma + req_offset) | ioc->RequestNB[req_idx];
  852. dsgprintk(ioc, printk(MYIOC_s_DEBUG_FMT "mf_dma_addr=%x req_idx=%d "
  853. "RequestNB=%x\n", ioc->name, mf_dma_addr, req_idx,
  854. ioc->RequestNB[req_idx]));
  855. CHIPREG_WRITE32(&ioc->chip->RequestFifo, mf_dma_addr);
  856. }
  857. /**
  858. * mpt_put_msg_frame_hi_pri - Send a hi-pri protocol-specific MPT request frame
  859. * @cb_idx: Handle of registered MPT protocol driver
  860. * @ioc: Pointer to MPT adapter structure
  861. * @mf: Pointer to MPT request frame
  862. *
  863. * Send a protocol-specific MPT request frame to an IOC using
  864. * hi-priority request queue.
  865. *
  866. * This routine posts an MPT request frame to the request post FIFO of a
  867. * specific MPT adapter.
  868. **/
  869. void
  870. mpt_put_msg_frame_hi_pri(u8 cb_idx, MPT_ADAPTER *ioc, MPT_FRAME_HDR *mf)
  871. {
  872. u32 mf_dma_addr;
  873. int req_offset;
  874. u16 req_idx; /* Request index */
  875. /* ensure values are reset properly! */
  876. mf->u.frame.hwhdr.msgctxu.fld.cb_idx = cb_idx;
  877. req_offset = (u8 *)mf - (u8 *)ioc->req_frames;
  878. req_idx = req_offset / ioc->req_sz;
  879. mf->u.frame.hwhdr.msgctxu.fld.req_idx = cpu_to_le16(req_idx);
  880. mf->u.frame.hwhdr.msgctxu.fld.rsvd = 0;
  881. DBG_DUMP_PUT_MSG_FRAME(ioc, (u32 *)mf);
  882. mf_dma_addr = (ioc->req_frames_low_dma + req_offset);
  883. dsgprintk(ioc, printk(MYIOC_s_DEBUG_FMT "mf_dma_addr=%x req_idx=%d\n",
  884. ioc->name, mf_dma_addr, req_idx));
  885. CHIPREG_WRITE32(&ioc->chip->RequestHiPriFifo, mf_dma_addr);
  886. }
  887. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  888. /**
  889. * mpt_free_msg_frame - Place MPT request frame back on FreeQ.
  890. * @ioc: Pointer to MPT adapter structure
  891. * @mf: Pointer to MPT request frame
  892. *
  893. * This routine places a MPT request frame back on the MPT adapter's
  894. * FreeQ.
  895. */
  896. void
  897. mpt_free_msg_frame(MPT_ADAPTER *ioc, MPT_FRAME_HDR *mf)
  898. {
  899. unsigned long flags;
  900. /* Put Request back on FreeQ! */
  901. spin_lock_irqsave(&ioc->FreeQlock, flags);
  902. if (cpu_to_le32(mf->u.frame.linkage.arg1) == 0xdeadbeaf)
  903. goto out;
  904. /* signature to know if this mf is freed */
  905. mf->u.frame.linkage.arg1 = cpu_to_le32(0xdeadbeaf);
  906. list_add(&mf->u.frame.linkage.list, &ioc->FreeQ);
  907. #ifdef MFCNT
  908. ioc->mfcnt--;
  909. #endif
  910. out:
  911. spin_unlock_irqrestore(&ioc->FreeQlock, flags);
  912. }
  913. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  914. /**
  915. * mpt_add_sge - Place a simple 32 bit SGE at address pAddr.
  916. * @pAddr: virtual address for SGE
  917. * @flagslength: SGE flags and data transfer length
  918. * @dma_addr: Physical address
  919. *
  920. * This routine places a MPT request frame back on the MPT adapter's
  921. * FreeQ.
  922. */
  923. static void
  924. mpt_add_sge(void *pAddr, u32 flagslength, dma_addr_t dma_addr)
  925. {
  926. SGESimple32_t *pSge = (SGESimple32_t *) pAddr;
  927. pSge->FlagsLength = cpu_to_le32(flagslength);
  928. pSge->Address = cpu_to_le32(dma_addr);
  929. }
  930. /**
  931. * mpt_add_sge_64bit - Place a simple 64 bit SGE at address pAddr.
  932. * @pAddr: virtual address for SGE
  933. * @flagslength: SGE flags and data transfer length
  934. * @dma_addr: Physical address
  935. *
  936. * This routine places a MPT request frame back on the MPT adapter's
  937. * FreeQ.
  938. **/
  939. static void
  940. mpt_add_sge_64bit(void *pAddr, u32 flagslength, dma_addr_t dma_addr)
  941. {
  942. SGESimple64_t *pSge = (SGESimple64_t *) pAddr;
  943. pSge->Address.Low = cpu_to_le32
  944. (lower_32_bits(dma_addr));
  945. pSge->Address.High = cpu_to_le32
  946. (upper_32_bits(dma_addr));
  947. pSge->FlagsLength = cpu_to_le32
  948. ((flagslength | MPT_SGE_FLAGS_64_BIT_ADDRESSING));
  949. }
  950. /**
  951. * mpt_add_sge_64bit_1078 - Place a simple 64 bit SGE at address pAddr (1078 workaround).
  952. * @pAddr: virtual address for SGE
  953. * @flagslength: SGE flags and data transfer length
  954. * @dma_addr: Physical address
  955. *
  956. * This routine places a MPT request frame back on the MPT adapter's
  957. * FreeQ.
  958. **/
  959. static void
  960. mpt_add_sge_64bit_1078(void *pAddr, u32 flagslength, dma_addr_t dma_addr)
  961. {
  962. SGESimple64_t *pSge = (SGESimple64_t *) pAddr;
  963. u32 tmp;
  964. pSge->Address.Low = cpu_to_le32
  965. (lower_32_bits(dma_addr));
  966. tmp = (u32)(upper_32_bits(dma_addr));
  967. /*
  968. * 1078 errata workaround for the 36GB limitation
  969. */
  970. if ((((u64)dma_addr + MPI_SGE_LENGTH(flagslength)) >> 32) == 9) {
  971. flagslength |=
  972. MPI_SGE_SET_FLAGS(MPI_SGE_FLAGS_LOCAL_ADDRESS);
  973. tmp |= (1<<31);
  974. if (mpt_debug_level & MPT_DEBUG_36GB_MEM)
  975. printk(KERN_DEBUG "1078 P0M2 addressing for "
  976. "addr = 0x%llx len = %d\n",
  977. (unsigned long long)dma_addr,
  978. MPI_SGE_LENGTH(flagslength));
  979. }
  980. pSge->Address.High = cpu_to_le32(tmp);
  981. pSge->FlagsLength = cpu_to_le32(
  982. (flagslength | MPT_SGE_FLAGS_64_BIT_ADDRESSING));
  983. }
  984. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  985. /**
  986. * mpt_add_chain - Place a 32 bit chain SGE at address pAddr.
  987. * @pAddr: virtual address for SGE
  988. * @next: nextChainOffset value (u32's)
  989. * @length: length of next SGL segment
  990. * @dma_addr: Physical address
  991. *
  992. */
  993. static void
  994. mpt_add_chain(void *pAddr, u8 next, u16 length, dma_addr_t dma_addr)
  995. {
  996. SGEChain32_t *pChain = (SGEChain32_t *) pAddr;
  997. pChain->Length = cpu_to_le16(length);
  998. pChain->Flags = MPI_SGE_FLAGS_CHAIN_ELEMENT;
  999. pChain->NextChainOffset = next;
  1000. pChain->Address = cpu_to_le32(dma_addr);
  1001. }
  1002. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  1003. /**
  1004. * mpt_add_chain_64bit - Place a 64 bit chain SGE at address pAddr.
  1005. * @pAddr: virtual address for SGE
  1006. * @next: nextChainOffset value (u32's)
  1007. * @length: length of next SGL segment
  1008. * @dma_addr: Physical address
  1009. *
  1010. */
  1011. static void
  1012. mpt_add_chain_64bit(void *pAddr, u8 next, u16 length, dma_addr_t dma_addr)
  1013. {
  1014. SGEChain64_t *pChain = (SGEChain64_t *) pAddr;
  1015. u32 tmp = dma_addr & 0xFFFFFFFF;
  1016. pChain->Length = cpu_to_le16(length);
  1017. pChain->Flags = (MPI_SGE_FLAGS_CHAIN_ELEMENT |
  1018. MPI_SGE_FLAGS_64_BIT_ADDRESSING);
  1019. pChain->NextChainOffset = next;
  1020. pChain->Address.Low = cpu_to_le32(tmp);
  1021. tmp = (u32)(upper_32_bits(dma_addr));
  1022. pChain->Address.High = cpu_to_le32(tmp);
  1023. }
  1024. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  1025. /**
  1026. * mpt_send_handshake_request - Send MPT request via doorbell handshake method.
  1027. * @cb_idx: Handle of registered MPT protocol driver
  1028. * @ioc: Pointer to MPT adapter structure
  1029. * @reqBytes: Size of the request in bytes
  1030. * @req: Pointer to MPT request frame
  1031. * @sleepFlag: Use schedule if CAN_SLEEP else use udelay.
  1032. *
  1033. * This routine is used exclusively to send MptScsiTaskMgmt
  1034. * requests since they are required to be sent via doorbell handshake.
  1035. *
  1036. * NOTE: It is the callers responsibility to byte-swap fields in the
  1037. * request which are greater than 1 byte in size.
  1038. *
  1039. * Returns 0 for success, non-zero for failure.
  1040. */
  1041. int
  1042. mpt_send_handshake_request(u8 cb_idx, MPT_ADAPTER *ioc, int reqBytes, u32 *req, int sleepFlag)
  1043. {
  1044. int r = 0;
  1045. u8 *req_as_bytes;
  1046. int ii;
  1047. /* State is known to be good upon entering
  1048. * this function so issue the bus reset
  1049. * request.
  1050. */
  1051. /*
  1052. * Emulate what mpt_put_msg_frame() does /wrt to sanity
  1053. * setting cb_idx/req_idx. But ONLY if this request
  1054. * is in proper (pre-alloc'd) request buffer range...
  1055. */
  1056. ii = MFPTR_2_MPT_INDEX(ioc,(MPT_FRAME_HDR*)req);
  1057. if (reqBytes >= 12 && ii >= 0 && ii < ioc->req_depth) {
  1058. MPT_FRAME_HDR *mf = (MPT_FRAME_HDR*)req;
  1059. mf->u.frame.hwhdr.msgctxu.fld.req_idx = cpu_to_le16(ii);
  1060. mf->u.frame.hwhdr.msgctxu.fld.cb_idx = cb_idx;
  1061. }
  1062. /* Make sure there are no doorbells */
  1063. CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
  1064. CHIPREG_WRITE32(&ioc->chip->Doorbell,
  1065. ((MPI_FUNCTION_HANDSHAKE<<MPI_DOORBELL_FUNCTION_SHIFT) |
  1066. ((reqBytes/4)<<MPI_DOORBELL_ADD_DWORDS_SHIFT)));
  1067. /* Wait for IOC doorbell int */
  1068. if ((ii = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0) {
  1069. return ii;
  1070. }
  1071. /* Read doorbell and check for active bit */
  1072. if (!(CHIPREG_READ32(&ioc->chip->Doorbell) & MPI_DOORBELL_ACTIVE))
  1073. return -5;
  1074. dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "mpt_send_handshake_request start, WaitCnt=%d\n",
  1075. ioc->name, ii));
  1076. CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
  1077. if ((r = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0) {
  1078. return -2;
  1079. }
  1080. /* Send request via doorbell handshake */
  1081. req_as_bytes = (u8 *) req;
  1082. for (ii = 0; ii < reqBytes/4; ii++) {
  1083. u32 word;
  1084. word = ((req_as_bytes[(ii*4) + 0] << 0) |
  1085. (req_as_bytes[(ii*4) + 1] << 8) |
  1086. (req_as_bytes[(ii*4) + 2] << 16) |
  1087. (req_as_bytes[(ii*4) + 3] << 24));
  1088. CHIPREG_WRITE32(&ioc->chip->Doorbell, word);
  1089. if ((r = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0) {
  1090. r = -3;
  1091. break;
  1092. }
  1093. }
  1094. if (r >= 0 && WaitForDoorbellInt(ioc, 10, sleepFlag) >= 0)
  1095. r = 0;
  1096. else
  1097. r = -4;
  1098. /* Make sure there are no doorbells */
  1099. CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
  1100. return r;
  1101. }
  1102. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  1103. /**
  1104. * mpt_host_page_access_control - control the IOC's Host Page Buffer access
  1105. * @ioc: Pointer to MPT adapter structure
  1106. * @access_control_value: define bits below
  1107. * @sleepFlag: Specifies whether the process can sleep
  1108. *
  1109. * Provides mechanism for the host driver to control the IOC's
  1110. * Host Page Buffer access.
  1111. *
  1112. * Access Control Value - bits[15:12]
  1113. * 0h Reserved
  1114. * 1h Enable Access { MPI_DB_HPBAC_ENABLE_ACCESS }
  1115. * 2h Disable Access { MPI_DB_HPBAC_DISABLE_ACCESS }
  1116. * 3h Free Buffer { MPI_DB_HPBAC_FREE_BUFFER }
  1117. *
  1118. * Returns 0 for success, non-zero for failure.
  1119. */
  1120. static int
  1121. mpt_host_page_access_control(MPT_ADAPTER *ioc, u8 access_control_value, int sleepFlag)
  1122. {
  1123. int r = 0;
  1124. /* return if in use */
  1125. if (CHIPREG_READ32(&ioc->chip->Doorbell)
  1126. & MPI_DOORBELL_ACTIVE)
  1127. return -1;
  1128. CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
  1129. CHIPREG_WRITE32(&ioc->chip->Doorbell,
  1130. ((MPI_FUNCTION_HOST_PAGEBUF_ACCESS_CONTROL
  1131. <<MPI_DOORBELL_FUNCTION_SHIFT) |
  1132. (access_control_value<<12)));
  1133. /* Wait for IOC to clear Doorbell Status bit */
  1134. if ((r = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0) {
  1135. return -2;
  1136. }else
  1137. return 0;
  1138. }
  1139. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  1140. /**
  1141. * mpt_host_page_alloc - allocate system memory for the fw
  1142. * @ioc: Pointer to pointer to IOC adapter
  1143. * @ioc_init: Pointer to ioc init config page
  1144. *
  1145. * If we already allocated memory in past, then resend the same pointer.
  1146. * Returns 0 for success, non-zero for failure.
  1147. */
  1148. static int
  1149. mpt_host_page_alloc(MPT_ADAPTER *ioc, pIOCInit_t ioc_init)
  1150. {
  1151. char *psge;
  1152. int flags_length;
  1153. u32 host_page_buffer_sz=0;
  1154. if(!ioc->HostPageBuffer) {
  1155. host_page_buffer_sz =
  1156. le32_to_cpu(ioc->facts.HostPageBufferSGE.FlagsLength) & 0xFFFFFF;
  1157. if(!host_page_buffer_sz)
  1158. return 0; /* fw doesn't need any host buffers */
  1159. /* spin till we get enough memory */
  1160. while (host_page_buffer_sz > 0) {
  1161. ioc->HostPageBuffer =
  1162. dma_alloc_coherent(&ioc->pcidev->dev,
  1163. host_page_buffer_sz,
  1164. &ioc->HostPageBuffer_dma,
  1165. GFP_KERNEL);
  1166. if (ioc->HostPageBuffer) {
  1167. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  1168. "host_page_buffer @ %p, dma @ %x, sz=%d bytes\n",
  1169. ioc->name, ioc->HostPageBuffer,
  1170. (u32)ioc->HostPageBuffer_dma,
  1171. host_page_buffer_sz));
  1172. ioc->alloc_total += host_page_buffer_sz;
  1173. ioc->HostPageBuffer_sz = host_page_buffer_sz;
  1174. break;
  1175. }
  1176. host_page_buffer_sz -= (4*1024);
  1177. }
  1178. }
  1179. if(!ioc->HostPageBuffer) {
  1180. printk(MYIOC_s_ERR_FMT
  1181. "Failed to alloc memory for host_page_buffer!\n",
  1182. ioc->name);
  1183. return -999;
  1184. }
  1185. psge = (char *)&ioc_init->HostPageBufferSGE;
  1186. flags_length = MPI_SGE_FLAGS_SIMPLE_ELEMENT |
  1187. MPI_SGE_FLAGS_SYSTEM_ADDRESS |
  1188. MPI_SGE_FLAGS_HOST_TO_IOC |
  1189. MPI_SGE_FLAGS_END_OF_BUFFER;
  1190. flags_length = flags_length << MPI_SGE_FLAGS_SHIFT;
  1191. flags_length |= ioc->HostPageBuffer_sz;
  1192. ioc->add_sge(psge, flags_length, ioc->HostPageBuffer_dma);
  1193. ioc->facts.HostPageBufferSGE = ioc_init->HostPageBufferSGE;
  1194. return 0;
  1195. }
  1196. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  1197. /**
  1198. * mpt_verify_adapter - Given IOC identifier, set pointer to its adapter structure.
  1199. * @iocid: IOC unique identifier (integer)
  1200. * @iocpp: Pointer to pointer to IOC adapter
  1201. *
  1202. * Given a unique IOC identifier, set pointer to the associated MPT
  1203. * adapter structure.
  1204. *
  1205. * Returns iocid and sets iocpp if iocid is found.
  1206. * Returns -1 if iocid is not found.
  1207. */
  1208. int
  1209. mpt_verify_adapter(int iocid, MPT_ADAPTER **iocpp)
  1210. {
  1211. MPT_ADAPTER *ioc;
  1212. list_for_each_entry(ioc,&ioc_list,list) {
  1213. if (ioc->id == iocid) {
  1214. *iocpp =ioc;
  1215. return iocid;
  1216. }
  1217. }
  1218. *iocpp = NULL;
  1219. return -1;
  1220. }
  1221. /**
  1222. * mpt_get_product_name - returns product string
  1223. * @vendor: pci vendor id
  1224. * @device: pci device id
  1225. * @revision: pci revision id
  1226. *
  1227. * Returns product string displayed when driver loads,
  1228. * in /proc/mpt/summary and /sysfs/class/scsi_host/host<X>/version_product
  1229. *
  1230. **/
  1231. static const char*
  1232. mpt_get_product_name(u16 vendor, u16 device, u8 revision)
  1233. {
  1234. char *product_str = NULL;
  1235. if (vendor == PCI_VENDOR_ID_BROCADE) {
  1236. switch (device)
  1237. {
  1238. case MPI_MANUFACTPAGE_DEVICEID_FC949E:
  1239. switch (revision)
  1240. {
  1241. case 0x00:
  1242. product_str = "BRE040 A0";
  1243. break;
  1244. case 0x01:
  1245. product_str = "BRE040 A1";
  1246. break;
  1247. default:
  1248. product_str = "BRE040";
  1249. break;
  1250. }
  1251. break;
  1252. }
  1253. goto out;
  1254. }
  1255. switch (device)
  1256. {
  1257. case MPI_MANUFACTPAGE_DEVICEID_FC909:
  1258. product_str = "LSIFC909 B1";
  1259. break;
  1260. case MPI_MANUFACTPAGE_DEVICEID_FC919:
  1261. product_str = "LSIFC919 B0";
  1262. break;
  1263. case MPI_MANUFACTPAGE_DEVICEID_FC929:
  1264. product_str = "LSIFC929 B0";
  1265. break;
  1266. case MPI_MANUFACTPAGE_DEVICEID_FC919X:
  1267. if (revision < 0x80)
  1268. product_str = "LSIFC919X A0";
  1269. else
  1270. product_str = "LSIFC919XL A1";
  1271. break;
  1272. case MPI_MANUFACTPAGE_DEVICEID_FC929X:
  1273. if (revision < 0x80)
  1274. product_str = "LSIFC929X A0";
  1275. else
  1276. product_str = "LSIFC929XL A1";
  1277. break;
  1278. case MPI_MANUFACTPAGE_DEVICEID_FC939X:
  1279. product_str = "LSIFC939X A1";
  1280. break;
  1281. case MPI_MANUFACTPAGE_DEVICEID_FC949X:
  1282. product_str = "LSIFC949X A1";
  1283. break;
  1284. case MPI_MANUFACTPAGE_DEVICEID_FC949E:
  1285. switch (revision)
  1286. {
  1287. case 0x00:
  1288. product_str = "LSIFC949E A0";
  1289. break;
  1290. case 0x01:
  1291. product_str = "LSIFC949E A1";
  1292. break;
  1293. default:
  1294. product_str = "LSIFC949E";
  1295. break;
  1296. }
  1297. break;
  1298. case MPI_MANUFACTPAGE_DEVID_53C1030:
  1299. switch (revision)
  1300. {
  1301. case 0x00:
  1302. product_str = "LSI53C1030 A0";
  1303. break;
  1304. case 0x01:
  1305. product_str = "LSI53C1030 B0";
  1306. break;
  1307. case 0x03:
  1308. product_str = "LSI53C1030 B1";
  1309. break;
  1310. case 0x07:
  1311. product_str = "LSI53C1030 B2";
  1312. break;
  1313. case 0x08:
  1314. product_str = "LSI53C1030 C0";
  1315. break;
  1316. case 0x80:
  1317. product_str = "LSI53C1030T A0";
  1318. break;
  1319. case 0x83:
  1320. product_str = "LSI53C1030T A2";
  1321. break;
  1322. case 0x87:
  1323. product_str = "LSI53C1030T A3";
  1324. break;
  1325. case 0xc1:
  1326. product_str = "LSI53C1020A A1";
  1327. break;
  1328. default:
  1329. product_str = "LSI53C1030";
  1330. break;
  1331. }
  1332. break;
  1333. case MPI_MANUFACTPAGE_DEVID_1030_53C1035:
  1334. switch (revision)
  1335. {
  1336. case 0x03:
  1337. product_str = "LSI53C1035 A2";
  1338. break;
  1339. case 0x04:
  1340. product_str = "LSI53C1035 B0";
  1341. break;
  1342. default:
  1343. product_str = "LSI53C1035";
  1344. break;
  1345. }
  1346. break;
  1347. case MPI_MANUFACTPAGE_DEVID_SAS1064:
  1348. switch (revision)
  1349. {
  1350. case 0x00:
  1351. product_str = "LSISAS1064 A1";
  1352. break;
  1353. case 0x01:
  1354. product_str = "LSISAS1064 A2";
  1355. break;
  1356. case 0x02:
  1357. product_str = "LSISAS1064 A3";
  1358. break;
  1359. case 0x03:
  1360. product_str = "LSISAS1064 A4";
  1361. break;
  1362. default:
  1363. product_str = "LSISAS1064";
  1364. break;
  1365. }
  1366. break;
  1367. case MPI_MANUFACTPAGE_DEVID_SAS1064E:
  1368. switch (revision)
  1369. {
  1370. case 0x00:
  1371. product_str = "LSISAS1064E A0";
  1372. break;
  1373. case 0x01:
  1374. product_str = "LSISAS1064E B0";
  1375. break;
  1376. case 0x02:
  1377. product_str = "LSISAS1064E B1";
  1378. break;
  1379. case 0x04:
  1380. product_str = "LSISAS1064E B2";
  1381. break;
  1382. case 0x08:
  1383. product_str = "LSISAS1064E B3";
  1384. break;
  1385. default:
  1386. product_str = "LSISAS1064E";
  1387. break;
  1388. }
  1389. break;
  1390. case MPI_MANUFACTPAGE_DEVID_SAS1068:
  1391. switch (revision)
  1392. {
  1393. case 0x00:
  1394. product_str = "LSISAS1068 A0";
  1395. break;
  1396. case 0x01:
  1397. product_str = "LSISAS1068 B0";
  1398. break;
  1399. case 0x02:
  1400. product_str = "LSISAS1068 B1";
  1401. break;
  1402. default:
  1403. product_str = "LSISAS1068";
  1404. break;
  1405. }
  1406. break;
  1407. case MPI_MANUFACTPAGE_DEVID_SAS1068E:
  1408. switch (revision)
  1409. {
  1410. case 0x00:
  1411. product_str = "LSISAS1068E A0";
  1412. break;
  1413. case 0x01:
  1414. product_str = "LSISAS1068E B0";
  1415. break;
  1416. case 0x02:
  1417. product_str = "LSISAS1068E B1";
  1418. break;
  1419. case 0x04:
  1420. product_str = "LSISAS1068E B2";
  1421. break;
  1422. case 0x08:
  1423. product_str = "LSISAS1068E B3";
  1424. break;
  1425. default:
  1426. product_str = "LSISAS1068E";
  1427. break;
  1428. }
  1429. break;
  1430. case MPI_MANUFACTPAGE_DEVID_SAS1078:
  1431. switch (revision)
  1432. {
  1433. case 0x00:
  1434. product_str = "LSISAS1078 A0";
  1435. break;
  1436. case 0x01:
  1437. product_str = "LSISAS1078 B0";
  1438. break;
  1439. case 0x02:
  1440. product_str = "LSISAS1078 C0";
  1441. break;
  1442. case 0x03:
  1443. product_str = "LSISAS1078 C1";
  1444. break;
  1445. case 0x04:
  1446. product_str = "LSISAS1078 C2";
  1447. break;
  1448. default:
  1449. product_str = "LSISAS1078";
  1450. break;
  1451. }
  1452. break;
  1453. }
  1454. out:
  1455. return product_str;
  1456. }
  1457. /**
  1458. * mpt_mapresources - map in memory mapped io
  1459. * @ioc: Pointer to pointer to IOC adapter
  1460. *
  1461. **/
  1462. static int
  1463. mpt_mapresources(MPT_ADAPTER *ioc)
  1464. {
  1465. u8 __iomem *mem;
  1466. int ii;
  1467. resource_size_t mem_phys;
  1468. unsigned long port;
  1469. u32 msize;
  1470. u32 psize;
  1471. int r = -ENODEV;
  1472. struct pci_dev *pdev;
  1473. pdev = ioc->pcidev;
  1474. ioc->bars = pci_select_bars(pdev, IORESOURCE_MEM);
  1475. if (pci_enable_device_mem(pdev)) {
  1476. printk(MYIOC_s_ERR_FMT "pci_enable_device_mem() "
  1477. "failed\n", ioc->name);
  1478. return r;
  1479. }
  1480. if (pci_request_selected_regions(pdev, ioc->bars, "mpt")) {
  1481. printk(MYIOC_s_ERR_FMT "pci_request_selected_regions() with "
  1482. "MEM failed\n", ioc->name);
  1483. goto out_pci_disable_device;
  1484. }
  1485. if (sizeof(dma_addr_t) > 4) {
  1486. const uint64_t required_mask = dma_get_required_mask
  1487. (&pdev->dev);
  1488. if (required_mask > DMA_BIT_MASK(32)
  1489. && !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
  1490. && !pci_set_consistent_dma_mask(pdev,
  1491. DMA_BIT_MASK(64))) {
  1492. ioc->dma_mask = DMA_BIT_MASK(64);
  1493. dinitprintk(ioc, printk(MYIOC_s_INFO_FMT
  1494. ": 64 BIT PCI BUS DMA ADDRESSING SUPPORTED\n",
  1495. ioc->name));
  1496. } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))
  1497. && !pci_set_consistent_dma_mask(pdev,
  1498. DMA_BIT_MASK(32))) {
  1499. ioc->dma_mask = DMA_BIT_MASK(32);
  1500. dinitprintk(ioc, printk(MYIOC_s_INFO_FMT
  1501. ": 32 BIT PCI BUS DMA ADDRESSING SUPPORTED\n",
  1502. ioc->name));
  1503. } else {
  1504. printk(MYIOC_s_WARN_FMT "no suitable DMA mask for %s\n",
  1505. ioc->name, pci_name(pdev));
  1506. goto out_pci_release_region;
  1507. }
  1508. } else {
  1509. if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))
  1510. && !pci_set_consistent_dma_mask(pdev,
  1511. DMA_BIT_MASK(32))) {
  1512. ioc->dma_mask = DMA_BIT_MASK(32);
  1513. dinitprintk(ioc, printk(MYIOC_s_INFO_FMT
  1514. ": 32 BIT PCI BUS DMA ADDRESSING SUPPORTED\n",
  1515. ioc->name));
  1516. } else {
  1517. printk(MYIOC_s_WARN_FMT "no suitable DMA mask for %s\n",
  1518. ioc->name, pci_name(pdev));
  1519. goto out_pci_release_region;
  1520. }
  1521. }
  1522. mem_phys = msize = 0;
  1523. port = psize = 0;
  1524. for (ii = 0; ii < DEVICE_COUNT_RESOURCE; ii++) {
  1525. if (pci_resource_flags(pdev, ii) & PCI_BASE_ADDRESS_SPACE_IO) {
  1526. if (psize)
  1527. continue;
  1528. /* Get I/O space! */
  1529. port = pci_resource_start(pdev, ii);
  1530. psize = pci_resource_len(pdev, ii);
  1531. } else {
  1532. if (msize)
  1533. continue;
  1534. /* Get memmap */
  1535. mem_phys = pci_resource_start(pdev, ii);
  1536. msize = pci_resource_len(pdev, ii);
  1537. }
  1538. }
  1539. ioc->mem_size = msize;
  1540. mem = NULL;
  1541. /* Get logical ptr for PciMem0 space */
  1542. /*mem = ioremap(mem_phys, msize);*/
  1543. mem = ioremap(mem_phys, msize);
  1544. if (mem == NULL) {
  1545. printk(MYIOC_s_ERR_FMT ": ERROR - Unable to map adapter"
  1546. " memory!\n", ioc->name);
  1547. r = -EINVAL;
  1548. goto out_pci_release_region;
  1549. }
  1550. ioc->memmap = mem;
  1551. dinitprintk(ioc, printk(MYIOC_s_INFO_FMT "mem = %p, mem_phys = %llx\n",
  1552. ioc->name, mem, (unsigned long long)mem_phys));
  1553. ioc->mem_phys = mem_phys;
  1554. ioc->chip = (SYSIF_REGS __iomem *)mem;
  1555. /* Save Port IO values in case we need to do downloadboot */
  1556. ioc->pio_mem_phys = port;
  1557. ioc->pio_chip = (SYSIF_REGS __iomem *)port;
  1558. return 0;
  1559. out_pci_release_region:
  1560. pci_release_selected_regions(pdev, ioc->bars);
  1561. out_pci_disable_device:
  1562. pci_disable_device(pdev);
  1563. return r;
  1564. }
  1565. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  1566. /**
  1567. * mpt_attach - Install a PCI intelligent MPT adapter.
  1568. * @pdev: Pointer to pci_dev structure
  1569. * @id: PCI device ID information
  1570. *
  1571. * This routine performs all the steps necessary to bring the IOC of
  1572. * a MPT adapter to a OPERATIONAL state. This includes registering
  1573. * memory regions, registering the interrupt, and allocating request
  1574. * and reply memory pools.
  1575. *
  1576. * This routine also pre-fetches the LAN MAC address of a Fibre Channel
  1577. * MPT adapter.
  1578. *
  1579. * Returns 0 for success, non-zero for failure.
  1580. *
  1581. * TODO: Add support for polled controllers
  1582. */
  1583. int
  1584. mpt_attach(struct pci_dev *pdev, const struct pci_device_id *id)
  1585. {
  1586. MPT_ADAPTER *ioc;
  1587. u8 cb_idx;
  1588. int r = -ENODEV;
  1589. u8 pcixcmd;
  1590. static int mpt_ids = 0;
  1591. #ifdef CONFIG_PROC_FS
  1592. struct proc_dir_entry *dent;
  1593. #endif
  1594. ioc = kzalloc(sizeof(MPT_ADAPTER), GFP_KERNEL);
  1595. if (ioc == NULL) {
  1596. printk(KERN_ERR MYNAM ": ERROR - Insufficient memory to add adapter!\n");
  1597. return -ENOMEM;
  1598. }
  1599. ioc->id = mpt_ids++;
  1600. sprintf(ioc->name, "ioc%d", ioc->id);
  1601. dinitprintk(ioc, printk(KERN_WARNING MYNAM ": mpt_adapter_install\n"));
  1602. /*
  1603. * set initial debug level
  1604. * (refer to mptdebug.h)
  1605. *
  1606. */
  1607. ioc->debug_level = mpt_debug_level;
  1608. if (mpt_debug_level)
  1609. printk(KERN_INFO "mpt_debug_level=%xh\n", mpt_debug_level);
  1610. dinitprintk(ioc, printk(MYIOC_s_INFO_FMT ": mpt_adapter_install\n", ioc->name));
  1611. ioc->pcidev = pdev;
  1612. if (mpt_mapresources(ioc)) {
  1613. goto out_free_ioc;
  1614. }
  1615. /*
  1616. * Setting up proper handlers for scatter gather handling
  1617. */
  1618. if (ioc->dma_mask == DMA_BIT_MASK(64)) {
  1619. if (pdev->device == MPI_MANUFACTPAGE_DEVID_SAS1078)
  1620. ioc->add_sge = &mpt_add_sge_64bit_1078;
  1621. else
  1622. ioc->add_sge = &mpt_add_sge_64bit;
  1623. ioc->add_chain = &mpt_add_chain_64bit;
  1624. ioc->sg_addr_size = 8;
  1625. } else {
  1626. ioc->add_sge = &mpt_add_sge;
  1627. ioc->add_chain = &mpt_add_chain;
  1628. ioc->sg_addr_size = 4;
  1629. }
  1630. ioc->SGE_size = sizeof(u32) + ioc->sg_addr_size;
  1631. ioc->alloc_total = sizeof(MPT_ADAPTER);
  1632. ioc->req_sz = MPT_DEFAULT_FRAME_SIZE; /* avoid div by zero! */
  1633. ioc->reply_sz = MPT_REPLY_FRAME_SIZE;
  1634. spin_lock_init(&ioc->taskmgmt_lock);
  1635. mutex_init(&ioc->internal_cmds.mutex);
  1636. init_completion(&ioc->internal_cmds.done);
  1637. mutex_init(&ioc->mptbase_cmds.mutex);
  1638. init_completion(&ioc->mptbase_cmds.done);
  1639. mutex_init(&ioc->taskmgmt_cmds.mutex);
  1640. init_completion(&ioc->taskmgmt_cmds.done);
  1641. /* Initialize the event logging.
  1642. */
  1643. ioc->eventTypes = 0; /* None */
  1644. ioc->eventContext = 0;
  1645. ioc->eventLogSize = 0;
  1646. ioc->events = NULL;
  1647. #ifdef MFCNT
  1648. ioc->mfcnt = 0;
  1649. #endif
  1650. ioc->sh = NULL;
  1651. ioc->cached_fw = NULL;
  1652. /* Initialize SCSI Config Data structure
  1653. */
  1654. memset(&ioc->spi_data, 0, sizeof(SpiCfgData));
  1655. /* Initialize the fc rport list head.
  1656. */
  1657. INIT_LIST_HEAD(&ioc->fc_rports);
  1658. /* Find lookup slot. */
  1659. INIT_LIST_HEAD(&ioc->list);
  1660. /* Initialize workqueue */
  1661. INIT_DELAYED_WORK(&ioc->fault_reset_work, mpt_fault_reset_work);
  1662. snprintf(ioc->reset_work_q_name, MPT_KOBJ_NAME_LEN,
  1663. "mpt_poll_%d", ioc->id);
  1664. ioc->reset_work_q = alloc_workqueue(ioc->reset_work_q_name,
  1665. WQ_MEM_RECLAIM, 0);
  1666. if (!ioc->reset_work_q) {
  1667. printk(MYIOC_s_ERR_FMT "Insufficient memory to add adapter!\n",
  1668. ioc->name);
  1669. r = -ENOMEM;
  1670. goto out_unmap_resources;
  1671. }
  1672. dinitprintk(ioc, printk(MYIOC_s_INFO_FMT "facts @ %p, pfacts[0] @ %p\n",
  1673. ioc->name, &ioc->facts, &ioc->pfacts[0]));
  1674. ioc->prod_name = mpt_get_product_name(pdev->vendor, pdev->device,
  1675. pdev->revision);
  1676. switch (pdev->device)
  1677. {
  1678. case MPI_MANUFACTPAGE_DEVICEID_FC939X:
  1679. case MPI_MANUFACTPAGE_DEVICEID_FC949X:
  1680. ioc->errata_flag_1064 = 1;
  1681. fallthrough;
  1682. case MPI_MANUFACTPAGE_DEVICEID_FC909:
  1683. case MPI_MANUFACTPAGE_DEVICEID_FC929:
  1684. case MPI_MANUFACTPAGE_DEVICEID_FC919:
  1685. case MPI_MANUFACTPAGE_DEVICEID_FC949E:
  1686. ioc->bus_type = FC;
  1687. break;
  1688. case MPI_MANUFACTPAGE_DEVICEID_FC929X:
  1689. if (pdev->revision < XL_929) {
  1690. /* 929X Chip Fix. Set Split transactions level
  1691. * for PCIX. Set MOST bits to zero.
  1692. */
  1693. pci_read_config_byte(pdev, 0x6a, &pcixcmd);
  1694. pcixcmd &= 0x8F;
  1695. pci_write_config_byte(pdev, 0x6a, pcixcmd);
  1696. } else {
  1697. /* 929XL Chip Fix. Set MMRBC to 0x08.
  1698. */
  1699. pci_read_config_byte(pdev, 0x6a, &pcixcmd);
  1700. pcixcmd |= 0x08;
  1701. pci_write_config_byte(pdev, 0x6a, pcixcmd);
  1702. }
  1703. ioc->bus_type = FC;
  1704. break;
  1705. case MPI_MANUFACTPAGE_DEVICEID_FC919X:
  1706. /* 919X Chip Fix. Set Split transactions level
  1707. * for PCIX. Set MOST bits to zero.
  1708. */
  1709. pci_read_config_byte(pdev, 0x6a, &pcixcmd);
  1710. pcixcmd &= 0x8F;
  1711. pci_write_config_byte(pdev, 0x6a, pcixcmd);
  1712. ioc->bus_type = FC;
  1713. break;
  1714. case MPI_MANUFACTPAGE_DEVID_53C1030:
  1715. /* 1030 Chip Fix. Disable Split transactions
  1716. * for PCIX. Set MOST bits to zero if Rev < C0( = 8).
  1717. */
  1718. if (pdev->revision < C0_1030) {
  1719. pci_read_config_byte(pdev, 0x6a, &pcixcmd);
  1720. pcixcmd &= 0x8F;
  1721. pci_write_config_byte(pdev, 0x6a, pcixcmd);
  1722. }
  1723. fallthrough;
  1724. case MPI_MANUFACTPAGE_DEVID_1030_53C1035:
  1725. ioc->bus_type = SPI;
  1726. break;
  1727. case MPI_MANUFACTPAGE_DEVID_SAS1064:
  1728. case MPI_MANUFACTPAGE_DEVID_SAS1068:
  1729. ioc->errata_flag_1064 = 1;
  1730. ioc->bus_type = SAS;
  1731. break;
  1732. case MPI_MANUFACTPAGE_DEVID_SAS1064E:
  1733. case MPI_MANUFACTPAGE_DEVID_SAS1068E:
  1734. case MPI_MANUFACTPAGE_DEVID_SAS1078:
  1735. ioc->bus_type = SAS;
  1736. break;
  1737. }
  1738. switch (ioc->bus_type) {
  1739. case SAS:
  1740. ioc->msi_enable = mpt_msi_enable_sas;
  1741. break;
  1742. case SPI:
  1743. ioc->msi_enable = mpt_msi_enable_spi;
  1744. break;
  1745. case FC:
  1746. ioc->msi_enable = mpt_msi_enable_fc;
  1747. break;
  1748. default:
  1749. ioc->msi_enable = 0;
  1750. break;
  1751. }
  1752. ioc->fw_events_off = 1;
  1753. if (ioc->errata_flag_1064)
  1754. pci_disable_io_access(pdev);
  1755. spin_lock_init(&ioc->FreeQlock);
  1756. /* Disable all! */
  1757. CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF);
  1758. ioc->active = 0;
  1759. CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
  1760. /* Set IOC ptr in the pcidev's driver data. */
  1761. pci_set_drvdata(ioc->pcidev, ioc);
  1762. /* Set lookup ptr. */
  1763. list_add_tail(&ioc->list, &ioc_list);
  1764. /* Check for "bound ports" (929, 929X, 1030, 1035) to reduce redundant resets.
  1765. */
  1766. mpt_detect_bound_ports(ioc, pdev);
  1767. INIT_LIST_HEAD(&ioc->fw_event_list);
  1768. spin_lock_init(&ioc->fw_event_lock);
  1769. snprintf(ioc->fw_event_q_name, MPT_KOBJ_NAME_LEN, "mpt/%d", ioc->id);
  1770. ioc->fw_event_q = alloc_workqueue(ioc->fw_event_q_name,
  1771. WQ_MEM_RECLAIM, 0);
  1772. if (!ioc->fw_event_q) {
  1773. printk(MYIOC_s_ERR_FMT "Insufficient memory to add adapter!\n",
  1774. ioc->name);
  1775. r = -ENOMEM;
  1776. goto out_remove_ioc;
  1777. }
  1778. if ((r = mpt_do_ioc_recovery(ioc, MPT_HOSTEVENT_IOC_BRINGUP,
  1779. CAN_SLEEP)) != 0){
  1780. printk(MYIOC_s_ERR_FMT "didn't initialize properly! (%d)\n",
  1781. ioc->name, r);
  1782. destroy_workqueue(ioc->fw_event_q);
  1783. ioc->fw_event_q = NULL;
  1784. list_del(&ioc->list);
  1785. if (ioc->alt_ioc)
  1786. ioc->alt_ioc->alt_ioc = NULL;
  1787. iounmap(ioc->memmap);
  1788. if (pci_is_enabled(pdev))
  1789. pci_disable_device(pdev);
  1790. if (r != -5)
  1791. pci_release_selected_regions(pdev, ioc->bars);
  1792. destroy_workqueue(ioc->reset_work_q);
  1793. ioc->reset_work_q = NULL;
  1794. kfree(ioc);
  1795. return r;
  1796. }
  1797. /* call per device driver probe entry point */
  1798. for(cb_idx = 0; cb_idx < MPT_MAX_PROTOCOL_DRIVERS; cb_idx++) {
  1799. if(MptDeviceDriverHandlers[cb_idx] &&
  1800. MptDeviceDriverHandlers[cb_idx]->probe) {
  1801. MptDeviceDriverHandlers[cb_idx]->probe(pdev,id);
  1802. }
  1803. }
  1804. #ifdef CONFIG_PROC_FS
  1805. /*
  1806. * Create "/proc/mpt/iocN" subdirectory entry for each MPT adapter.
  1807. */
  1808. dent = proc_mkdir(ioc->name, mpt_proc_root_dir);
  1809. if (dent) {
  1810. proc_create_single_data("info", S_IRUGO, dent,
  1811. mpt_iocinfo_proc_show, ioc);
  1812. proc_create_single_data("summary", S_IRUGO, dent,
  1813. mpt_summary_proc_show, ioc);
  1814. }
  1815. #endif
  1816. if (!ioc->alt_ioc)
  1817. queue_delayed_work(ioc->reset_work_q, &ioc->fault_reset_work,
  1818. msecs_to_jiffies(MPT_POLLING_INTERVAL));
  1819. return 0;
  1820. out_remove_ioc:
  1821. list_del(&ioc->list);
  1822. if (ioc->alt_ioc)
  1823. ioc->alt_ioc->alt_ioc = NULL;
  1824. destroy_workqueue(ioc->reset_work_q);
  1825. ioc->reset_work_q = NULL;
  1826. out_unmap_resources:
  1827. iounmap(ioc->memmap);
  1828. pci_disable_device(pdev);
  1829. pci_release_selected_regions(pdev, ioc->bars);
  1830. out_free_ioc:
  1831. kfree(ioc);
  1832. return r;
  1833. }
  1834. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  1835. /**
  1836. * mpt_detach - Remove a PCI intelligent MPT adapter.
  1837. * @pdev: Pointer to pci_dev structure
  1838. */
  1839. void
  1840. mpt_detach(struct pci_dev *pdev)
  1841. {
  1842. MPT_ADAPTER *ioc = pci_get_drvdata(pdev);
  1843. char pname[64];
  1844. u8 cb_idx;
  1845. unsigned long flags;
  1846. struct workqueue_struct *wq;
  1847. /*
  1848. * Stop polling ioc for fault condition
  1849. */
  1850. spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
  1851. wq = ioc->reset_work_q;
  1852. ioc->reset_work_q = NULL;
  1853. spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
  1854. cancel_delayed_work(&ioc->fault_reset_work);
  1855. destroy_workqueue(wq);
  1856. spin_lock_irqsave(&ioc->fw_event_lock, flags);
  1857. wq = ioc->fw_event_q;
  1858. ioc->fw_event_q = NULL;
  1859. spin_unlock_irqrestore(&ioc->fw_event_lock, flags);
  1860. destroy_workqueue(wq);
  1861. snprintf(pname, sizeof(pname), MPT_PROCFS_MPTBASEDIR "/%s/summary", ioc->name);
  1862. remove_proc_entry(pname, NULL);
  1863. snprintf(pname, sizeof(pname), MPT_PROCFS_MPTBASEDIR "/%s/info", ioc->name);
  1864. remove_proc_entry(pname, NULL);
  1865. snprintf(pname, sizeof(pname), MPT_PROCFS_MPTBASEDIR "/%s", ioc->name);
  1866. remove_proc_entry(pname, NULL);
  1867. /* call per device driver remove entry point */
  1868. for(cb_idx = 0; cb_idx < MPT_MAX_PROTOCOL_DRIVERS; cb_idx++) {
  1869. if(MptDeviceDriverHandlers[cb_idx] &&
  1870. MptDeviceDriverHandlers[cb_idx]->remove) {
  1871. MptDeviceDriverHandlers[cb_idx]->remove(pdev);
  1872. }
  1873. }
  1874. /* Disable interrupts! */
  1875. CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF);
  1876. ioc->active = 0;
  1877. synchronize_irq(pdev->irq);
  1878. /* Clear any lingering interrupt */
  1879. CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
  1880. CHIPREG_READ32(&ioc->chip->IntStatus);
  1881. mpt_adapter_dispose(ioc);
  1882. }
  1883. /**************************************************************************
  1884. * Power Management
  1885. */
  1886. #ifdef CONFIG_PM
  1887. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  1888. /**
  1889. * mpt_suspend - Fusion MPT base driver suspend routine.
  1890. * @pdev: Pointer to pci_dev structure
  1891. * @state: new state to enter
  1892. */
  1893. int
  1894. mpt_suspend(struct pci_dev *pdev, pm_message_t state)
  1895. {
  1896. u32 device_state;
  1897. MPT_ADAPTER *ioc = pci_get_drvdata(pdev);
  1898. device_state = pci_choose_state(pdev, state);
  1899. printk(MYIOC_s_INFO_FMT "pci-suspend: pdev=0x%p, slot=%s, Entering "
  1900. "operating state [D%d]\n", ioc->name, pdev, pci_name(pdev),
  1901. device_state);
  1902. /* put ioc into READY_STATE */
  1903. if (SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, CAN_SLEEP)) {
  1904. printk(MYIOC_s_ERR_FMT
  1905. "pci-suspend: IOC msg unit reset failed!\n", ioc->name);
  1906. }
  1907. /* disable interrupts */
  1908. CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF);
  1909. ioc->active = 0;
  1910. /* Clear any lingering interrupt */
  1911. CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
  1912. free_irq(ioc->pci_irq, ioc);
  1913. if (ioc->msi_enable)
  1914. pci_disable_msi(ioc->pcidev);
  1915. ioc->pci_irq = -1;
  1916. pci_save_state(pdev);
  1917. pci_disable_device(pdev);
  1918. pci_release_selected_regions(pdev, ioc->bars);
  1919. pci_set_power_state(pdev, device_state);
  1920. return 0;
  1921. }
  1922. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  1923. /**
  1924. * mpt_resume - Fusion MPT base driver resume routine.
  1925. * @pdev: Pointer to pci_dev structure
  1926. */
  1927. int
  1928. mpt_resume(struct pci_dev *pdev)
  1929. {
  1930. MPT_ADAPTER *ioc = pci_get_drvdata(pdev);
  1931. u32 device_state = pdev->current_state;
  1932. int recovery_state;
  1933. int err;
  1934. printk(MYIOC_s_INFO_FMT "pci-resume: pdev=0x%p, slot=%s, Previous "
  1935. "operating state [D%d]\n", ioc->name, pdev, pci_name(pdev),
  1936. device_state);
  1937. pci_set_power_state(pdev, PCI_D0);
  1938. pci_enable_wake(pdev, PCI_D0, 0);
  1939. pci_restore_state(pdev);
  1940. ioc->pcidev = pdev;
  1941. err = mpt_mapresources(ioc);
  1942. if (err)
  1943. return err;
  1944. if (ioc->dma_mask == DMA_BIT_MASK(64)) {
  1945. if (pdev->device == MPI_MANUFACTPAGE_DEVID_SAS1078)
  1946. ioc->add_sge = &mpt_add_sge_64bit_1078;
  1947. else
  1948. ioc->add_sge = &mpt_add_sge_64bit;
  1949. ioc->add_chain = &mpt_add_chain_64bit;
  1950. ioc->sg_addr_size = 8;
  1951. } else {
  1952. ioc->add_sge = &mpt_add_sge;
  1953. ioc->add_chain = &mpt_add_chain;
  1954. ioc->sg_addr_size = 4;
  1955. }
  1956. ioc->SGE_size = sizeof(u32) + ioc->sg_addr_size;
  1957. printk(MYIOC_s_INFO_FMT "pci-resume: ioc-state=0x%x,doorbell=0x%x\n",
  1958. ioc->name, (mpt_GetIocState(ioc, 1) >> MPI_IOC_STATE_SHIFT),
  1959. CHIPREG_READ32(&ioc->chip->Doorbell));
  1960. /*
  1961. * Errata workaround for SAS pci express:
  1962. * Upon returning to the D0 state, the contents of the doorbell will be
  1963. * stale data, and this will incorrectly signal to the host driver that
  1964. * the firmware is ready to process mpt commands. The workaround is
  1965. * to issue a diagnostic reset.
  1966. */
  1967. if (ioc->bus_type == SAS && (pdev->device ==
  1968. MPI_MANUFACTPAGE_DEVID_SAS1068E || pdev->device ==
  1969. MPI_MANUFACTPAGE_DEVID_SAS1064E)) {
  1970. if (KickStart(ioc, 1, CAN_SLEEP) < 0) {
  1971. printk(MYIOC_s_WARN_FMT "pci-resume: Cannot recover\n",
  1972. ioc->name);
  1973. goto out;
  1974. }
  1975. }
  1976. /* bring ioc to operational state */
  1977. printk(MYIOC_s_INFO_FMT "Sending mpt_do_ioc_recovery\n", ioc->name);
  1978. recovery_state = mpt_do_ioc_recovery(ioc, MPT_HOSTEVENT_IOC_BRINGUP,
  1979. CAN_SLEEP);
  1980. if (recovery_state != 0)
  1981. printk(MYIOC_s_WARN_FMT "pci-resume: Cannot recover, "
  1982. "error:[%x]\n", ioc->name, recovery_state);
  1983. else
  1984. printk(MYIOC_s_INFO_FMT
  1985. "pci-resume: success\n", ioc->name);
  1986. out:
  1987. return 0;
  1988. }
  1989. #endif
  1990. static int
  1991. mpt_signal_reset(u8 index, MPT_ADAPTER *ioc, int reset_phase)
  1992. {
  1993. if ((MptDriverClass[index] == MPTSPI_DRIVER &&
  1994. ioc->bus_type != SPI) ||
  1995. (MptDriverClass[index] == MPTFC_DRIVER &&
  1996. ioc->bus_type != FC) ||
  1997. (MptDriverClass[index] == MPTSAS_DRIVER &&
  1998. ioc->bus_type != SAS))
  1999. /* make sure we only call the relevant reset handler
  2000. * for the bus */
  2001. return 0;
  2002. return (MptResetHandlers[index])(ioc, reset_phase);
  2003. }
  2004. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  2005. /**
  2006. * mpt_do_ioc_recovery - Initialize or recover MPT adapter.
  2007. * @ioc: Pointer to MPT adapter structure
  2008. * @reason: Event word / reason
  2009. * @sleepFlag: Use schedule if CAN_SLEEP else use udelay.
  2010. *
  2011. * This routine performs all the steps necessary to bring the IOC
  2012. * to a OPERATIONAL state.
  2013. *
  2014. * This routine also pre-fetches the LAN MAC address of a Fibre Channel
  2015. * MPT adapter.
  2016. *
  2017. * Returns:
  2018. * 0 for success
  2019. * -1 if failed to get board READY
  2020. * -2 if READY but IOCFacts Failed
  2021. * -3 if READY but PrimeIOCFifos Failed
  2022. * -4 if READY but IOCInit Failed
  2023. * -5 if failed to enable_device and/or request_selected_regions
  2024. * -6 if failed to upload firmware
  2025. */
  2026. static int
  2027. mpt_do_ioc_recovery(MPT_ADAPTER *ioc, u32 reason, int sleepFlag)
  2028. {
  2029. int hard_reset_done = 0;
  2030. int alt_ioc_ready = 0;
  2031. int hard;
  2032. int rc=0;
  2033. int ii;
  2034. int ret = 0;
  2035. int reset_alt_ioc_active = 0;
  2036. int irq_allocated = 0;
  2037. u8 *a;
  2038. printk(MYIOC_s_INFO_FMT "Initiating %s\n", ioc->name,
  2039. reason == MPT_HOSTEVENT_IOC_BRINGUP ? "bringup" : "recovery");
  2040. /* Disable reply interrupts (also blocks FreeQ) */
  2041. CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF);
  2042. ioc->active = 0;
  2043. if (ioc->alt_ioc) {
  2044. if (ioc->alt_ioc->active ||
  2045. reason == MPT_HOSTEVENT_IOC_RECOVER) {
  2046. reset_alt_ioc_active = 1;
  2047. /* Disable alt-IOC's reply interrupts
  2048. * (and FreeQ) for a bit
  2049. **/
  2050. CHIPREG_WRITE32(&ioc->alt_ioc->chip->IntMask,
  2051. 0xFFFFFFFF);
  2052. ioc->alt_ioc->active = 0;
  2053. }
  2054. }
  2055. hard = 1;
  2056. if (reason == MPT_HOSTEVENT_IOC_BRINGUP)
  2057. hard = 0;
  2058. if ((hard_reset_done = MakeIocReady(ioc, hard, sleepFlag)) < 0) {
  2059. if (hard_reset_done == -4) {
  2060. printk(MYIOC_s_WARN_FMT "Owned by PEER..skipping!\n",
  2061. ioc->name);
  2062. if (reset_alt_ioc_active && ioc->alt_ioc) {
  2063. /* (re)Enable alt-IOC! (reply interrupt, FreeQ) */
  2064. dprintk(ioc, printk(MYIOC_s_INFO_FMT
  2065. "alt_ioc reply irq re-enabled\n", ioc->alt_ioc->name));
  2066. CHIPREG_WRITE32(&ioc->alt_ioc->chip->IntMask, MPI_HIM_DIM);
  2067. ioc->alt_ioc->active = 1;
  2068. }
  2069. } else {
  2070. printk(MYIOC_s_WARN_FMT
  2071. "NOT READY WARNING!\n", ioc->name);
  2072. }
  2073. ret = -1;
  2074. goto out;
  2075. }
  2076. /* hard_reset_done = 0 if a soft reset was performed
  2077. * and 1 if a hard reset was performed.
  2078. */
  2079. if (hard_reset_done && reset_alt_ioc_active && ioc->alt_ioc) {
  2080. if ((rc = MakeIocReady(ioc->alt_ioc, 0, sleepFlag)) == 0)
  2081. alt_ioc_ready = 1;
  2082. else
  2083. printk(MYIOC_s_WARN_FMT
  2084. ": alt-ioc Not ready WARNING!\n",
  2085. ioc->alt_ioc->name);
  2086. }
  2087. for (ii=0; ii<5; ii++) {
  2088. /* Get IOC facts! Allow 5 retries */
  2089. if ((rc = GetIocFacts(ioc, sleepFlag, reason)) == 0)
  2090. break;
  2091. }
  2092. if (ii == 5) {
  2093. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  2094. "Retry IocFacts failed rc=%x\n", ioc->name, rc));
  2095. ret = -2;
  2096. } else if (reason == MPT_HOSTEVENT_IOC_BRINGUP) {
  2097. MptDisplayIocCapabilities(ioc);
  2098. }
  2099. if (alt_ioc_ready) {
  2100. if ((rc = GetIocFacts(ioc->alt_ioc, sleepFlag, reason)) != 0) {
  2101. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  2102. "Initial Alt IocFacts failed rc=%x\n",
  2103. ioc->name, rc));
  2104. /* Retry - alt IOC was initialized once
  2105. */
  2106. rc = GetIocFacts(ioc->alt_ioc, sleepFlag, reason);
  2107. }
  2108. if (rc) {
  2109. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  2110. "Retry Alt IocFacts failed rc=%x\n", ioc->name, rc));
  2111. alt_ioc_ready = 0;
  2112. reset_alt_ioc_active = 0;
  2113. } else if (reason == MPT_HOSTEVENT_IOC_BRINGUP) {
  2114. MptDisplayIocCapabilities(ioc->alt_ioc);
  2115. }
  2116. }
  2117. if ((ret == 0) && (reason == MPT_HOSTEVENT_IOC_BRINGUP) &&
  2118. (ioc->facts.Flags & MPI_IOCFACTS_FLAGS_FW_DOWNLOAD_BOOT)) {
  2119. pci_release_selected_regions(ioc->pcidev, ioc->bars);
  2120. ioc->bars = pci_select_bars(ioc->pcidev, IORESOURCE_MEM |
  2121. IORESOURCE_IO);
  2122. if (pci_enable_device(ioc->pcidev))
  2123. return -5;
  2124. if (pci_request_selected_regions(ioc->pcidev, ioc->bars,
  2125. "mpt"))
  2126. return -5;
  2127. }
  2128. /*
  2129. * Device is reset now. It must have de-asserted the interrupt line
  2130. * (if it was asserted) and it should be safe to register for the
  2131. * interrupt now.
  2132. */
  2133. if ((ret == 0) && (reason == MPT_HOSTEVENT_IOC_BRINGUP)) {
  2134. ioc->pci_irq = -1;
  2135. if (ioc->pcidev->irq) {
  2136. if (ioc->msi_enable && !pci_enable_msi(ioc->pcidev))
  2137. printk(MYIOC_s_INFO_FMT "PCI-MSI enabled\n",
  2138. ioc->name);
  2139. else
  2140. ioc->msi_enable = 0;
  2141. rc = request_irq(ioc->pcidev->irq, mpt_interrupt,
  2142. IRQF_SHARED, ioc->name, ioc);
  2143. if (rc < 0) {
  2144. printk(MYIOC_s_ERR_FMT "Unable to allocate "
  2145. "interrupt %d!\n",
  2146. ioc->name, ioc->pcidev->irq);
  2147. if (ioc->msi_enable)
  2148. pci_disable_msi(ioc->pcidev);
  2149. ret = -EBUSY;
  2150. goto out;
  2151. }
  2152. irq_allocated = 1;
  2153. ioc->pci_irq = ioc->pcidev->irq;
  2154. pci_set_master(ioc->pcidev); /* ?? */
  2155. pci_set_drvdata(ioc->pcidev, ioc);
  2156. dinitprintk(ioc, printk(MYIOC_s_INFO_FMT
  2157. "installed at interrupt %d\n", ioc->name,
  2158. ioc->pcidev->irq));
  2159. }
  2160. }
  2161. /* Prime reply & request queues!
  2162. * (mucho alloc's) Must be done prior to
  2163. * init as upper addresses are needed for init.
  2164. * If fails, continue with alt-ioc processing
  2165. */
  2166. dinitprintk(ioc, printk(MYIOC_s_INFO_FMT "PrimeIocFifos\n",
  2167. ioc->name));
  2168. if ((ret == 0) && ((rc = PrimeIocFifos(ioc)) != 0))
  2169. ret = -3;
  2170. /* May need to check/upload firmware & data here!
  2171. * If fails, continue with alt-ioc processing
  2172. */
  2173. dinitprintk(ioc, printk(MYIOC_s_INFO_FMT "SendIocInit\n",
  2174. ioc->name));
  2175. if ((ret == 0) && ((rc = SendIocInit(ioc, sleepFlag)) != 0))
  2176. ret = -4;
  2177. // NEW!
  2178. if (alt_ioc_ready && ((rc = PrimeIocFifos(ioc->alt_ioc)) != 0)) {
  2179. printk(MYIOC_s_WARN_FMT
  2180. ": alt-ioc (%d) FIFO mgmt alloc WARNING!\n",
  2181. ioc->alt_ioc->name, rc);
  2182. alt_ioc_ready = 0;
  2183. reset_alt_ioc_active = 0;
  2184. }
  2185. if (alt_ioc_ready) {
  2186. if ((rc = SendIocInit(ioc->alt_ioc, sleepFlag)) != 0) {
  2187. alt_ioc_ready = 0;
  2188. reset_alt_ioc_active = 0;
  2189. printk(MYIOC_s_WARN_FMT
  2190. ": alt-ioc: (%d) init failure WARNING!\n",
  2191. ioc->alt_ioc->name, rc);
  2192. }
  2193. }
  2194. if (reason == MPT_HOSTEVENT_IOC_BRINGUP){
  2195. if (ioc->upload_fw) {
  2196. ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  2197. "firmware upload required!\n", ioc->name));
  2198. /* Controller is not operational, cannot do upload
  2199. */
  2200. if (ret == 0) {
  2201. rc = mpt_do_upload(ioc, sleepFlag);
  2202. if (rc == 0) {
  2203. if (ioc->alt_ioc && ioc->alt_ioc->cached_fw) {
  2204. /*
  2205. * Maintain only one pointer to FW memory
  2206. * so there will not be two attempt to
  2207. * downloadboot onboard dual function
  2208. * chips (mpt_adapter_disable,
  2209. * mpt_diag_reset)
  2210. */
  2211. ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  2212. "mpt_upload: alt_%s has cached_fw=%p \n",
  2213. ioc->name, ioc->alt_ioc->name, ioc->alt_ioc->cached_fw));
  2214. ioc->cached_fw = NULL;
  2215. }
  2216. } else {
  2217. printk(MYIOC_s_WARN_FMT
  2218. "firmware upload failure!\n", ioc->name);
  2219. ret = -6;
  2220. }
  2221. }
  2222. }
  2223. }
  2224. /* Enable MPT base driver management of EventNotification
  2225. * and EventAck handling.
  2226. */
  2227. if ((ret == 0) && (!ioc->facts.EventState)) {
  2228. dinitprintk(ioc, printk(MYIOC_s_INFO_FMT
  2229. "SendEventNotification\n",
  2230. ioc->name));
  2231. ret = SendEventNotification(ioc, 1, sleepFlag); /* 1=Enable */
  2232. }
  2233. if (ioc->alt_ioc && alt_ioc_ready && !ioc->alt_ioc->facts.EventState)
  2234. rc = SendEventNotification(ioc->alt_ioc, 1, sleepFlag);
  2235. if (ret == 0) {
  2236. /* Enable! (reply interrupt) */
  2237. CHIPREG_WRITE32(&ioc->chip->IntMask, MPI_HIM_DIM);
  2238. ioc->active = 1;
  2239. }
  2240. if (rc == 0) { /* alt ioc */
  2241. if (reset_alt_ioc_active && ioc->alt_ioc) {
  2242. /* (re)Enable alt-IOC! (reply interrupt) */
  2243. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "alt-ioc"
  2244. "reply irq re-enabled\n",
  2245. ioc->alt_ioc->name));
  2246. CHIPREG_WRITE32(&ioc->alt_ioc->chip->IntMask,
  2247. MPI_HIM_DIM);
  2248. ioc->alt_ioc->active = 1;
  2249. }
  2250. }
  2251. /* Add additional "reason" check before call to GetLanConfigPages
  2252. * (combined with GetIoUnitPage2 call). This prevents a somewhat
  2253. * recursive scenario; GetLanConfigPages times out, timer expired
  2254. * routine calls HardResetHandler, which calls into here again,
  2255. * and we try GetLanConfigPages again...
  2256. */
  2257. if ((ret == 0) && (reason == MPT_HOSTEVENT_IOC_BRINGUP)) {
  2258. /*
  2259. * Initialize link list for inactive raid volumes.
  2260. */
  2261. mutex_init(&ioc->raid_data.inactive_list_mutex);
  2262. INIT_LIST_HEAD(&ioc->raid_data.inactive_list);
  2263. switch (ioc->bus_type) {
  2264. case SAS:
  2265. /* clear persistency table */
  2266. if(ioc->facts.IOCExceptions &
  2267. MPI_IOCFACTS_EXCEPT_PERSISTENT_TABLE_FULL) {
  2268. ret = mptbase_sas_persist_operation(ioc,
  2269. MPI_SAS_OP_CLEAR_NOT_PRESENT);
  2270. if(ret != 0)
  2271. goto out;
  2272. }
  2273. /* Find IM volumes
  2274. */
  2275. mpt_findImVolumes(ioc);
  2276. /* Check, and possibly reset, the coalescing value
  2277. */
  2278. mpt_read_ioc_pg_1(ioc);
  2279. break;
  2280. case FC:
  2281. if ((ioc->pfacts[0].ProtocolFlags &
  2282. MPI_PORTFACTS_PROTOCOL_LAN) &&
  2283. (ioc->lan_cnfg_page0.Header.PageLength == 0)) {
  2284. /*
  2285. * Pre-fetch the ports LAN MAC address!
  2286. * (LANPage1_t stuff)
  2287. */
  2288. (void) GetLanConfigPages(ioc);
  2289. a = (u8*)&ioc->lan_cnfg_page1.HardwareAddressLow;
  2290. dprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  2291. "LanAddr = %pMR\n", ioc->name, a));
  2292. }
  2293. break;
  2294. case SPI:
  2295. /* Get NVRAM and adapter maximums from SPP 0 and 2
  2296. */
  2297. mpt_GetScsiPortSettings(ioc, 0);
  2298. /* Get version and length of SDP 1
  2299. */
  2300. mpt_readScsiDevicePageHeaders(ioc, 0);
  2301. /* Find IM volumes
  2302. */
  2303. if (ioc->facts.MsgVersion >= MPI_VERSION_01_02)
  2304. mpt_findImVolumes(ioc);
  2305. /* Check, and possibly reset, the coalescing value
  2306. */
  2307. mpt_read_ioc_pg_1(ioc);
  2308. mpt_read_ioc_pg_4(ioc);
  2309. break;
  2310. }
  2311. GetIoUnitPage2(ioc);
  2312. mpt_get_manufacturing_pg_0(ioc);
  2313. }
  2314. out:
  2315. if ((ret != 0) && irq_allocated) {
  2316. free_irq(ioc->pci_irq, ioc);
  2317. if (ioc->msi_enable)
  2318. pci_disable_msi(ioc->pcidev);
  2319. }
  2320. return ret;
  2321. }
  2322. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  2323. /**
  2324. * mpt_detect_bound_ports - Search for matching PCI bus/dev_function
  2325. * @ioc: Pointer to MPT adapter structure
  2326. * @pdev: Pointer to (struct pci_dev) structure
  2327. *
  2328. * Search for PCI bus/dev_function which matches
  2329. * PCI bus/dev_function (+/-1) for newly discovered 929,
  2330. * 929X, 1030 or 1035.
  2331. *
  2332. * If match on PCI dev_function +/-1 is found, bind the two MPT adapters
  2333. * using alt_ioc pointer fields in their %MPT_ADAPTER structures.
  2334. */
  2335. static void
  2336. mpt_detect_bound_ports(MPT_ADAPTER *ioc, struct pci_dev *pdev)
  2337. {
  2338. struct pci_dev *peer=NULL;
  2339. unsigned int slot = PCI_SLOT(pdev->devfn);
  2340. unsigned int func = PCI_FUNC(pdev->devfn);
  2341. MPT_ADAPTER *ioc_srch;
  2342. dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "PCI device %s devfn=%x/%x,"
  2343. " searching for devfn match on %x or %x\n",
  2344. ioc->name, pci_name(pdev), pdev->bus->number,
  2345. pdev->devfn, func-1, func+1));
  2346. peer = pci_get_slot(pdev->bus, PCI_DEVFN(slot,func-1));
  2347. if (!peer) {
  2348. peer = pci_get_slot(pdev->bus, PCI_DEVFN(slot,func+1));
  2349. if (!peer)
  2350. return;
  2351. }
  2352. list_for_each_entry(ioc_srch, &ioc_list, list) {
  2353. struct pci_dev *_pcidev = ioc_srch->pcidev;
  2354. if (_pcidev == peer) {
  2355. /* Paranoia checks */
  2356. if (ioc->alt_ioc != NULL) {
  2357. printk(MYIOC_s_WARN_FMT
  2358. "Oops, already bound (%s <==> %s)!\n",
  2359. ioc->name, ioc->name, ioc->alt_ioc->name);
  2360. break;
  2361. } else if (ioc_srch->alt_ioc != NULL) {
  2362. printk(MYIOC_s_WARN_FMT
  2363. "Oops, already bound (%s <==> %s)!\n",
  2364. ioc_srch->name, ioc_srch->name,
  2365. ioc_srch->alt_ioc->name);
  2366. break;
  2367. }
  2368. dprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  2369. "FOUND! binding %s <==> %s\n",
  2370. ioc->name, ioc->name, ioc_srch->name));
  2371. ioc_srch->alt_ioc = ioc;
  2372. ioc->alt_ioc = ioc_srch;
  2373. }
  2374. }
  2375. pci_dev_put(peer);
  2376. }
  2377. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  2378. /**
  2379. * mpt_adapter_disable - Disable misbehaving MPT adapter.
  2380. * @ioc: Pointer to MPT adapter structure
  2381. */
  2382. static void
  2383. mpt_adapter_disable(MPT_ADAPTER *ioc)
  2384. {
  2385. int sz;
  2386. int ret;
  2387. if (ioc->cached_fw != NULL) {
  2388. ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  2389. "%s: Pushing FW onto adapter\n", __func__, ioc->name));
  2390. if ((ret = mpt_downloadboot(ioc, (MpiFwHeader_t *)
  2391. ioc->cached_fw, CAN_SLEEP)) < 0) {
  2392. printk(MYIOC_s_WARN_FMT
  2393. ": firmware downloadboot failure (%d)!\n",
  2394. ioc->name, ret);
  2395. }
  2396. }
  2397. /*
  2398. * Put the controller into ready state (if its not already)
  2399. */
  2400. if (mpt_GetIocState(ioc, 1) != MPI_IOC_STATE_READY) {
  2401. if (!SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET,
  2402. CAN_SLEEP)) {
  2403. if (mpt_GetIocState(ioc, 1) != MPI_IOC_STATE_READY)
  2404. printk(MYIOC_s_ERR_FMT "%s: IOC msg unit "
  2405. "reset failed to put ioc in ready state!\n",
  2406. ioc->name, __func__);
  2407. } else
  2408. printk(MYIOC_s_ERR_FMT "%s: IOC msg unit reset "
  2409. "failed!\n", ioc->name, __func__);
  2410. }
  2411. /* Disable adapter interrupts! */
  2412. synchronize_irq(ioc->pcidev->irq);
  2413. CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF);
  2414. ioc->active = 0;
  2415. /* Clear any lingering interrupt */
  2416. CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
  2417. CHIPREG_READ32(&ioc->chip->IntStatus);
  2418. if (ioc->alloc != NULL) {
  2419. sz = ioc->alloc_sz;
  2420. dexitprintk(ioc, printk(MYIOC_s_INFO_FMT "free @ %p, sz=%d bytes\n",
  2421. ioc->name, ioc->alloc, ioc->alloc_sz));
  2422. dma_free_coherent(&ioc->pcidev->dev, sz, ioc->alloc,
  2423. ioc->alloc_dma);
  2424. ioc->reply_frames = NULL;
  2425. ioc->req_frames = NULL;
  2426. ioc->alloc = NULL;
  2427. ioc->alloc_total -= sz;
  2428. }
  2429. if (ioc->sense_buf_pool != NULL) {
  2430. sz = (ioc->req_depth * MPT_SENSE_BUFFER_ALLOC);
  2431. dma_free_coherent(&ioc->pcidev->dev, sz, ioc->sense_buf_pool,
  2432. ioc->sense_buf_pool_dma);
  2433. ioc->sense_buf_pool = NULL;
  2434. ioc->alloc_total -= sz;
  2435. }
  2436. if (ioc->events != NULL){
  2437. sz = MPTCTL_EVENT_LOG_SIZE * sizeof(MPT_IOCTL_EVENTS);
  2438. kfree(ioc->events);
  2439. ioc->events = NULL;
  2440. ioc->alloc_total -= sz;
  2441. }
  2442. mpt_free_fw_memory(ioc);
  2443. kfree(ioc->spi_data.nvram);
  2444. mpt_inactive_raid_list_free(ioc);
  2445. kfree(ioc->raid_data.pIocPg2);
  2446. kfree(ioc->raid_data.pIocPg3);
  2447. ioc->spi_data.nvram = NULL;
  2448. ioc->raid_data.pIocPg3 = NULL;
  2449. if (ioc->spi_data.pIocPg4 != NULL) {
  2450. sz = ioc->spi_data.IocPg4Sz;
  2451. pci_free_consistent(ioc->pcidev, sz,
  2452. ioc->spi_data.pIocPg4,
  2453. ioc->spi_data.IocPg4_dma);
  2454. ioc->spi_data.pIocPg4 = NULL;
  2455. ioc->alloc_total -= sz;
  2456. }
  2457. if (ioc->ReqToChain != NULL) {
  2458. kfree(ioc->ReqToChain);
  2459. kfree(ioc->RequestNB);
  2460. ioc->ReqToChain = NULL;
  2461. }
  2462. kfree(ioc->ChainToChain);
  2463. ioc->ChainToChain = NULL;
  2464. if (ioc->HostPageBuffer != NULL) {
  2465. if((ret = mpt_host_page_access_control(ioc,
  2466. MPI_DB_HPBAC_FREE_BUFFER, NO_SLEEP)) != 0) {
  2467. printk(MYIOC_s_ERR_FMT
  2468. ": %s: host page buffers free failed (%d)!\n",
  2469. ioc->name, __func__, ret);
  2470. }
  2471. dexitprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  2472. "HostPageBuffer free @ %p, sz=%d bytes\n",
  2473. ioc->name, ioc->HostPageBuffer,
  2474. ioc->HostPageBuffer_sz));
  2475. dma_free_coherent(&ioc->pcidev->dev, ioc->HostPageBuffer_sz,
  2476. ioc->HostPageBuffer, ioc->HostPageBuffer_dma);
  2477. ioc->HostPageBuffer = NULL;
  2478. ioc->HostPageBuffer_sz = 0;
  2479. ioc->alloc_total -= ioc->HostPageBuffer_sz;
  2480. }
  2481. pci_set_drvdata(ioc->pcidev, NULL);
  2482. }
  2483. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  2484. /**
  2485. * mpt_adapter_dispose - Free all resources associated with an MPT adapter
  2486. * @ioc: Pointer to MPT adapter structure
  2487. *
  2488. * This routine unregisters h/w resources and frees all alloc'd memory
  2489. * associated with a MPT adapter structure.
  2490. */
  2491. static void
  2492. mpt_adapter_dispose(MPT_ADAPTER *ioc)
  2493. {
  2494. int sz_first, sz_last;
  2495. if (ioc == NULL)
  2496. return;
  2497. sz_first = ioc->alloc_total;
  2498. mpt_adapter_disable(ioc);
  2499. if (ioc->pci_irq != -1) {
  2500. free_irq(ioc->pci_irq, ioc);
  2501. if (ioc->msi_enable)
  2502. pci_disable_msi(ioc->pcidev);
  2503. ioc->pci_irq = -1;
  2504. }
  2505. if (ioc->memmap != NULL) {
  2506. iounmap(ioc->memmap);
  2507. ioc->memmap = NULL;
  2508. }
  2509. pci_disable_device(ioc->pcidev);
  2510. pci_release_selected_regions(ioc->pcidev, ioc->bars);
  2511. /* Zap the adapter lookup ptr! */
  2512. list_del(&ioc->list);
  2513. sz_last = ioc->alloc_total;
  2514. dprintk(ioc, printk(MYIOC_s_INFO_FMT "free'd %d of %d bytes\n",
  2515. ioc->name, sz_first-sz_last+(int)sizeof(*ioc), sz_first));
  2516. if (ioc->alt_ioc)
  2517. ioc->alt_ioc->alt_ioc = NULL;
  2518. kfree(ioc);
  2519. }
  2520. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  2521. /**
  2522. * MptDisplayIocCapabilities - Disply IOC's capabilities.
  2523. * @ioc: Pointer to MPT adapter structure
  2524. */
  2525. static void
  2526. MptDisplayIocCapabilities(MPT_ADAPTER *ioc)
  2527. {
  2528. int i = 0;
  2529. printk(KERN_INFO "%s: ", ioc->name);
  2530. if (ioc->prod_name)
  2531. pr_cont("%s: ", ioc->prod_name);
  2532. pr_cont("Capabilities={");
  2533. if (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_INITIATOR) {
  2534. pr_cont("Initiator");
  2535. i++;
  2536. }
  2537. if (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_TARGET) {
  2538. pr_cont("%sTarget", i ? "," : "");
  2539. i++;
  2540. }
  2541. if (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_LAN) {
  2542. pr_cont("%sLAN", i ? "," : "");
  2543. i++;
  2544. }
  2545. #if 0
  2546. /*
  2547. * This would probably evoke more questions than it's worth
  2548. */
  2549. if (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_TARGET) {
  2550. pr_cont("%sLogBusAddr", i ? "," : "");
  2551. i++;
  2552. }
  2553. #endif
  2554. pr_cont("}\n");
  2555. }
  2556. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  2557. /**
  2558. * MakeIocReady - Get IOC to a READY state, using KickStart if needed.
  2559. * @ioc: Pointer to MPT_ADAPTER structure
  2560. * @force: Force hard KickStart of IOC
  2561. * @sleepFlag: Specifies whether the process can sleep
  2562. *
  2563. * Returns:
  2564. * 1 - DIAG reset and READY
  2565. * 0 - READY initially OR soft reset and READY
  2566. * -1 - Any failure on KickStart
  2567. * -2 - Msg Unit Reset Failed
  2568. * -3 - IO Unit Reset Failed
  2569. * -4 - IOC owned by a PEER
  2570. */
  2571. static int
  2572. MakeIocReady(MPT_ADAPTER *ioc, int force, int sleepFlag)
  2573. {
  2574. u32 ioc_state;
  2575. int statefault = 0;
  2576. int cntdn;
  2577. int hard_reset_done = 0;
  2578. int r;
  2579. int ii;
  2580. int whoinit;
  2581. /* Get current [raw] IOC state */
  2582. ioc_state = mpt_GetIocState(ioc, 0);
  2583. dhsprintk(ioc, printk(MYIOC_s_INFO_FMT "MakeIocReady [raw] state=%08x\n", ioc->name, ioc_state));
  2584. /*
  2585. * Check to see if IOC got left/stuck in doorbell handshake
  2586. * grip of death. If so, hard reset the IOC.
  2587. */
  2588. if (ioc_state & MPI_DOORBELL_ACTIVE) {
  2589. statefault = 1;
  2590. printk(MYIOC_s_WARN_FMT "Unexpected doorbell active!\n",
  2591. ioc->name);
  2592. }
  2593. /* Is it already READY? */
  2594. if (!statefault &&
  2595. ((ioc_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_READY)) {
  2596. dinitprintk(ioc, printk(MYIOC_s_INFO_FMT
  2597. "IOC is in READY state\n", ioc->name));
  2598. return 0;
  2599. }
  2600. /*
  2601. * Check to see if IOC is in FAULT state.
  2602. */
  2603. if ((ioc_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_FAULT) {
  2604. statefault = 2;
  2605. printk(MYIOC_s_WARN_FMT "IOC is in FAULT state!!!\n",
  2606. ioc->name);
  2607. printk(MYIOC_s_WARN_FMT " FAULT code = %04xh\n",
  2608. ioc->name, ioc_state & MPI_DOORBELL_DATA_MASK);
  2609. }
  2610. /*
  2611. * Hmmm... Did it get left operational?
  2612. */
  2613. if ((ioc_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_OPERATIONAL) {
  2614. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "IOC operational unexpected\n",
  2615. ioc->name));
  2616. /* Check WhoInit.
  2617. * If PCI Peer, exit.
  2618. * Else, if no fault conditions are present, issue a MessageUnitReset
  2619. * Else, fall through to KickStart case
  2620. */
  2621. whoinit = (ioc_state & MPI_DOORBELL_WHO_INIT_MASK) >> MPI_DOORBELL_WHO_INIT_SHIFT;
  2622. dinitprintk(ioc, printk(MYIOC_s_INFO_FMT
  2623. "whoinit 0x%x statefault %d force %d\n",
  2624. ioc->name, whoinit, statefault, force));
  2625. if (whoinit == MPI_WHOINIT_PCI_PEER)
  2626. return -4;
  2627. else {
  2628. if ((statefault == 0 ) && (force == 0)) {
  2629. if ((r = SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, sleepFlag)) == 0)
  2630. return 0;
  2631. }
  2632. statefault = 3;
  2633. }
  2634. }
  2635. hard_reset_done = KickStart(ioc, statefault||force, sleepFlag);
  2636. if (hard_reset_done < 0)
  2637. return -1;
  2638. /*
  2639. * Loop here waiting for IOC to come READY.
  2640. */
  2641. ii = 0;
  2642. cntdn = ((sleepFlag == CAN_SLEEP) ? HZ : 1000) * 5; /* 5 seconds */
  2643. while ((ioc_state = mpt_GetIocState(ioc, 1)) != MPI_IOC_STATE_READY) {
  2644. if (ioc_state == MPI_IOC_STATE_OPERATIONAL) {
  2645. /*
  2646. * BIOS or previous driver load left IOC in OP state.
  2647. * Reset messaging FIFOs.
  2648. */
  2649. if ((r = SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, sleepFlag)) != 0) {
  2650. printk(MYIOC_s_ERR_FMT "IOC msg unit reset failed!\n", ioc->name);
  2651. return -2;
  2652. }
  2653. } else if (ioc_state == MPI_IOC_STATE_RESET) {
  2654. /*
  2655. * Something is wrong. Try to get IOC back
  2656. * to a known state.
  2657. */
  2658. if ((r = SendIocReset(ioc, MPI_FUNCTION_IO_UNIT_RESET, sleepFlag)) != 0) {
  2659. printk(MYIOC_s_ERR_FMT "IO unit reset failed!\n", ioc->name);
  2660. return -3;
  2661. }
  2662. }
  2663. ii++; cntdn--;
  2664. if (!cntdn) {
  2665. printk(MYIOC_s_ERR_FMT
  2666. "Wait IOC_READY state (0x%x) timeout(%d)!\n",
  2667. ioc->name, ioc_state, (int)((ii+5)/HZ));
  2668. return -ETIME;
  2669. }
  2670. if (sleepFlag == CAN_SLEEP) {
  2671. msleep(1);
  2672. } else {
  2673. mdelay (1); /* 1 msec delay */
  2674. }
  2675. }
  2676. if (statefault < 3) {
  2677. printk(MYIOC_s_INFO_FMT "Recovered from %s\n", ioc->name,
  2678. statefault == 1 ? "stuck handshake" : "IOC FAULT");
  2679. }
  2680. return hard_reset_done;
  2681. }
  2682. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  2683. /**
  2684. * mpt_GetIocState - Get the current state of a MPT adapter.
  2685. * @ioc: Pointer to MPT_ADAPTER structure
  2686. * @cooked: Request raw or cooked IOC state
  2687. *
  2688. * Returns all IOC Doorbell register bits if cooked==0, else just the
  2689. * Doorbell bits in MPI_IOC_STATE_MASK.
  2690. */
  2691. u32
  2692. mpt_GetIocState(MPT_ADAPTER *ioc, int cooked)
  2693. {
  2694. u32 s, sc;
  2695. /* Get! */
  2696. s = CHIPREG_READ32(&ioc->chip->Doorbell);
  2697. sc = s & MPI_IOC_STATE_MASK;
  2698. /* Save! */
  2699. ioc->last_state = sc;
  2700. return cooked ? sc : s;
  2701. }
  2702. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  2703. /**
  2704. * GetIocFacts - Send IOCFacts request to MPT adapter.
  2705. * @ioc: Pointer to MPT_ADAPTER structure
  2706. * @sleepFlag: Specifies whether the process can sleep
  2707. * @reason: If recovery, only update facts.
  2708. *
  2709. * Returns 0 for success, non-zero for failure.
  2710. */
  2711. static int
  2712. GetIocFacts(MPT_ADAPTER *ioc, int sleepFlag, int reason)
  2713. {
  2714. IOCFacts_t get_facts;
  2715. IOCFactsReply_t *facts;
  2716. int r;
  2717. int req_sz;
  2718. int reply_sz;
  2719. int sz;
  2720. u32 status, vv;
  2721. u8 shiftFactor=1;
  2722. /* IOC *must* NOT be in RESET state! */
  2723. if (ioc->last_state == MPI_IOC_STATE_RESET) {
  2724. printk(KERN_ERR MYNAM
  2725. ": ERROR - Can't get IOCFacts, %s NOT READY! (%08x)\n",
  2726. ioc->name, ioc->last_state);
  2727. return -44;
  2728. }
  2729. facts = &ioc->facts;
  2730. /* Destination (reply area)... */
  2731. reply_sz = sizeof(*facts);
  2732. memset(facts, 0, reply_sz);
  2733. /* Request area (get_facts on the stack right now!) */
  2734. req_sz = sizeof(get_facts);
  2735. memset(&get_facts, 0, req_sz);
  2736. get_facts.Function = MPI_FUNCTION_IOC_FACTS;
  2737. /* Assert: All other get_facts fields are zero! */
  2738. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  2739. "Sending get IocFacts request req_sz=%d reply_sz=%d\n",
  2740. ioc->name, req_sz, reply_sz));
  2741. /* No non-zero fields in the get_facts request are greater than
  2742. * 1 byte in size, so we can just fire it off as is.
  2743. */
  2744. r = mpt_handshake_req_reply_wait(ioc, req_sz, (u32*)&get_facts,
  2745. reply_sz, (u16*)facts, 5 /*seconds*/, sleepFlag);
  2746. if (r != 0)
  2747. return r;
  2748. /*
  2749. * Now byte swap (GRRR) the necessary fields before any further
  2750. * inspection of reply contents.
  2751. *
  2752. * But need to do some sanity checks on MsgLength (byte) field
  2753. * to make sure we don't zero IOC's req_sz!
  2754. */
  2755. /* Did we get a valid reply? */
  2756. if (facts->MsgLength > offsetof(IOCFactsReply_t, RequestFrameSize)/sizeof(u32)) {
  2757. if (reason == MPT_HOSTEVENT_IOC_BRINGUP) {
  2758. /*
  2759. * If not been here, done that, save off first WhoInit value
  2760. */
  2761. if (ioc->FirstWhoInit == WHOINIT_UNKNOWN)
  2762. ioc->FirstWhoInit = facts->WhoInit;
  2763. }
  2764. facts->MsgVersion = le16_to_cpu(facts->MsgVersion);
  2765. facts->MsgContext = le32_to_cpu(facts->MsgContext);
  2766. facts->IOCExceptions = le16_to_cpu(facts->IOCExceptions);
  2767. facts->IOCStatus = le16_to_cpu(facts->IOCStatus);
  2768. facts->IOCLogInfo = le32_to_cpu(facts->IOCLogInfo);
  2769. status = le16_to_cpu(facts->IOCStatus) & MPI_IOCSTATUS_MASK;
  2770. /* CHECKME! IOCStatus, IOCLogInfo */
  2771. facts->ReplyQueueDepth = le16_to_cpu(facts->ReplyQueueDepth);
  2772. facts->RequestFrameSize = le16_to_cpu(facts->RequestFrameSize);
  2773. /*
  2774. * FC f/w version changed between 1.1 and 1.2
  2775. * Old: u16{Major(4),Minor(4),SubMinor(8)}
  2776. * New: u32{Major(8),Minor(8),Unit(8),Dev(8)}
  2777. */
  2778. if (facts->MsgVersion < MPI_VERSION_01_02) {
  2779. /*
  2780. * Handle old FC f/w style, convert to new...
  2781. */
  2782. u16 oldv = le16_to_cpu(facts->Reserved_0101_FWVersion);
  2783. facts->FWVersion.Word =
  2784. ((oldv<<12) & 0xFF000000) |
  2785. ((oldv<<8) & 0x000FFF00);
  2786. } else
  2787. facts->FWVersion.Word = le32_to_cpu(facts->FWVersion.Word);
  2788. facts->ProductID = le16_to_cpu(facts->ProductID);
  2789. if ((ioc->facts.ProductID & MPI_FW_HEADER_PID_PROD_MASK)
  2790. > MPI_FW_HEADER_PID_PROD_TARGET_SCSI)
  2791. ioc->ir_firmware = 1;
  2792. facts->CurrentHostMfaHighAddr =
  2793. le32_to_cpu(facts->CurrentHostMfaHighAddr);
  2794. facts->GlobalCredits = le16_to_cpu(facts->GlobalCredits);
  2795. facts->CurrentSenseBufferHighAddr =
  2796. le32_to_cpu(facts->CurrentSenseBufferHighAddr);
  2797. facts->CurReplyFrameSize =
  2798. le16_to_cpu(facts->CurReplyFrameSize);
  2799. facts->IOCCapabilities = le32_to_cpu(facts->IOCCapabilities);
  2800. /*
  2801. * Handle NEW (!) IOCFactsReply fields in MPI-1.01.xx
  2802. * Older MPI-1.00.xx struct had 13 dwords, and enlarged
  2803. * to 14 in MPI-1.01.0x.
  2804. */
  2805. if (facts->MsgLength >= (offsetof(IOCFactsReply_t,FWImageSize) + 7)/4 &&
  2806. facts->MsgVersion > MPI_VERSION_01_00) {
  2807. facts->FWImageSize = le32_to_cpu(facts->FWImageSize);
  2808. }
  2809. facts->FWImageSize = ALIGN(facts->FWImageSize, 4);
  2810. if (!facts->RequestFrameSize) {
  2811. /* Something is wrong! */
  2812. printk(MYIOC_s_ERR_FMT "IOC reported invalid 0 request size!\n",
  2813. ioc->name);
  2814. return -55;
  2815. }
  2816. r = sz = facts->BlockSize;
  2817. vv = ((63 / (sz * 4)) + 1) & 0x03;
  2818. ioc->NB_for_64_byte_frame = vv;
  2819. while ( sz )
  2820. {
  2821. shiftFactor++;
  2822. sz = sz >> 1;
  2823. }
  2824. ioc->NBShiftFactor = shiftFactor;
  2825. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  2826. "NB_for_64_byte_frame=%x NBShiftFactor=%x BlockSize=%x\n",
  2827. ioc->name, vv, shiftFactor, r));
  2828. if (reason == MPT_HOSTEVENT_IOC_BRINGUP) {
  2829. /*
  2830. * Set values for this IOC's request & reply frame sizes,
  2831. * and request & reply queue depths...
  2832. */
  2833. ioc->req_sz = min(MPT_DEFAULT_FRAME_SIZE, facts->RequestFrameSize * 4);
  2834. ioc->req_depth = min_t(int, MPT_MAX_REQ_DEPTH, facts->GlobalCredits);
  2835. ioc->reply_sz = MPT_REPLY_FRAME_SIZE;
  2836. ioc->reply_depth = min_t(int, MPT_DEFAULT_REPLY_DEPTH, facts->ReplyQueueDepth);
  2837. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "reply_sz=%3d, reply_depth=%4d\n",
  2838. ioc->name, ioc->reply_sz, ioc->reply_depth));
  2839. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "req_sz =%3d, req_depth =%4d\n",
  2840. ioc->name, ioc->req_sz, ioc->req_depth));
  2841. /* Get port facts! */
  2842. if ( (r = GetPortFacts(ioc, 0, sleepFlag)) != 0 )
  2843. return r;
  2844. }
  2845. } else {
  2846. printk(MYIOC_s_ERR_FMT
  2847. "Invalid IOC facts reply, msgLength=%d offsetof=%zd!\n",
  2848. ioc->name, facts->MsgLength, (offsetof(IOCFactsReply_t,
  2849. RequestFrameSize)/sizeof(u32)));
  2850. return -66;
  2851. }
  2852. return 0;
  2853. }
  2854. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  2855. /**
  2856. * GetPortFacts - Send PortFacts request to MPT adapter.
  2857. * @ioc: Pointer to MPT_ADAPTER structure
  2858. * @portnum: Port number
  2859. * @sleepFlag: Specifies whether the process can sleep
  2860. *
  2861. * Returns 0 for success, non-zero for failure.
  2862. */
  2863. static int
  2864. GetPortFacts(MPT_ADAPTER *ioc, int portnum, int sleepFlag)
  2865. {
  2866. PortFacts_t get_pfacts;
  2867. PortFactsReply_t *pfacts;
  2868. int ii;
  2869. int req_sz;
  2870. int reply_sz;
  2871. int max_id;
  2872. /* IOC *must* NOT be in RESET state! */
  2873. if (ioc->last_state == MPI_IOC_STATE_RESET) {
  2874. printk(MYIOC_s_ERR_FMT "Can't get PortFacts NOT READY! (%08x)\n",
  2875. ioc->name, ioc->last_state );
  2876. return -4;
  2877. }
  2878. pfacts = &ioc->pfacts[portnum];
  2879. /* Destination (reply area)... */
  2880. reply_sz = sizeof(*pfacts);
  2881. memset(pfacts, 0, reply_sz);
  2882. /* Request area (get_pfacts on the stack right now!) */
  2883. req_sz = sizeof(get_pfacts);
  2884. memset(&get_pfacts, 0, req_sz);
  2885. get_pfacts.Function = MPI_FUNCTION_PORT_FACTS;
  2886. get_pfacts.PortNumber = portnum;
  2887. /* Assert: All other get_pfacts fields are zero! */
  2888. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending get PortFacts(%d) request\n",
  2889. ioc->name, portnum));
  2890. /* No non-zero fields in the get_pfacts request are greater than
  2891. * 1 byte in size, so we can just fire it off as is.
  2892. */
  2893. ii = mpt_handshake_req_reply_wait(ioc, req_sz, (u32*)&get_pfacts,
  2894. reply_sz, (u16*)pfacts, 5 /*seconds*/, sleepFlag);
  2895. if (ii != 0)
  2896. return ii;
  2897. /* Did we get a valid reply? */
  2898. /* Now byte swap the necessary fields in the response. */
  2899. pfacts->MsgContext = le32_to_cpu(pfacts->MsgContext);
  2900. pfacts->IOCStatus = le16_to_cpu(pfacts->IOCStatus);
  2901. pfacts->IOCLogInfo = le32_to_cpu(pfacts->IOCLogInfo);
  2902. pfacts->MaxDevices = le16_to_cpu(pfacts->MaxDevices);
  2903. pfacts->PortSCSIID = le16_to_cpu(pfacts->PortSCSIID);
  2904. pfacts->ProtocolFlags = le16_to_cpu(pfacts->ProtocolFlags);
  2905. pfacts->MaxPostedCmdBuffers = le16_to_cpu(pfacts->MaxPostedCmdBuffers);
  2906. pfacts->MaxPersistentIDs = le16_to_cpu(pfacts->MaxPersistentIDs);
  2907. pfacts->MaxLanBuckets = le16_to_cpu(pfacts->MaxLanBuckets);
  2908. max_id = (ioc->bus_type == SAS) ? pfacts->PortSCSIID :
  2909. pfacts->MaxDevices;
  2910. ioc->devices_per_bus = (max_id > 255) ? 256 : max_id;
  2911. ioc->number_of_buses = (ioc->devices_per_bus < 256) ? 1 : max_id/256;
  2912. /*
  2913. * Place all the devices on channels
  2914. *
  2915. * (for debuging)
  2916. */
  2917. if (mpt_channel_mapping) {
  2918. ioc->devices_per_bus = 1;
  2919. ioc->number_of_buses = (max_id > 255) ? 255 : max_id;
  2920. }
  2921. return 0;
  2922. }
  2923. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  2924. /**
  2925. * SendIocInit - Send IOCInit request to MPT adapter.
  2926. * @ioc: Pointer to MPT_ADAPTER structure
  2927. * @sleepFlag: Specifies whether the process can sleep
  2928. *
  2929. * Send IOCInit followed by PortEnable to bring IOC to OPERATIONAL state.
  2930. *
  2931. * Returns 0 for success, non-zero for failure.
  2932. */
  2933. static int
  2934. SendIocInit(MPT_ADAPTER *ioc, int sleepFlag)
  2935. {
  2936. IOCInit_t ioc_init;
  2937. MPIDefaultReply_t init_reply;
  2938. u32 state;
  2939. int r;
  2940. int count;
  2941. int cntdn;
  2942. memset(&ioc_init, 0, sizeof(ioc_init));
  2943. memset(&init_reply, 0, sizeof(init_reply));
  2944. ioc_init.WhoInit = MPI_WHOINIT_HOST_DRIVER;
  2945. ioc_init.Function = MPI_FUNCTION_IOC_INIT;
  2946. /* If we are in a recovery mode and we uploaded the FW image,
  2947. * then this pointer is not NULL. Skip the upload a second time.
  2948. * Set this flag if cached_fw set for either IOC.
  2949. */
  2950. if (ioc->facts.Flags & MPI_IOCFACTS_FLAGS_FW_DOWNLOAD_BOOT)
  2951. ioc->upload_fw = 1;
  2952. else
  2953. ioc->upload_fw = 0;
  2954. ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "upload_fw %d facts.Flags=%x\n",
  2955. ioc->name, ioc->upload_fw, ioc->facts.Flags));
  2956. ioc_init.MaxDevices = (U8)ioc->devices_per_bus;
  2957. ioc_init.MaxBuses = (U8)ioc->number_of_buses;
  2958. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "facts.MsgVersion=%x\n",
  2959. ioc->name, ioc->facts.MsgVersion));
  2960. if (ioc->facts.MsgVersion >= MPI_VERSION_01_05) {
  2961. // set MsgVersion and HeaderVersion host driver was built with
  2962. ioc_init.MsgVersion = cpu_to_le16(MPI_VERSION);
  2963. ioc_init.HeaderVersion = cpu_to_le16(MPI_HEADER_VERSION);
  2964. if (ioc->facts.Flags & MPI_IOCFACTS_FLAGS_HOST_PAGE_BUFFER_PERSISTENT) {
  2965. ioc_init.HostPageBufferSGE = ioc->facts.HostPageBufferSGE;
  2966. } else if(mpt_host_page_alloc(ioc, &ioc_init))
  2967. return -99;
  2968. }
  2969. ioc_init.ReplyFrameSize = cpu_to_le16(ioc->reply_sz); /* in BYTES */
  2970. if (ioc->sg_addr_size == sizeof(u64)) {
  2971. /* Save the upper 32-bits of the request
  2972. * (reply) and sense buffers.
  2973. */
  2974. ioc_init.HostMfaHighAddr = cpu_to_le32((u32)((u64)ioc->alloc_dma >> 32));
  2975. ioc_init.SenseBufferHighAddr = cpu_to_le32((u32)((u64)ioc->sense_buf_pool_dma >> 32));
  2976. } else {
  2977. /* Force 32-bit addressing */
  2978. ioc_init.HostMfaHighAddr = cpu_to_le32(0);
  2979. ioc_init.SenseBufferHighAddr = cpu_to_le32(0);
  2980. }
  2981. ioc->facts.CurrentHostMfaHighAddr = ioc_init.HostMfaHighAddr;
  2982. ioc->facts.CurrentSenseBufferHighAddr = ioc_init.SenseBufferHighAddr;
  2983. ioc->facts.MaxDevices = ioc_init.MaxDevices;
  2984. ioc->facts.MaxBuses = ioc_init.MaxBuses;
  2985. dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending IOCInit (req @ %p)\n",
  2986. ioc->name, &ioc_init));
  2987. r = mpt_handshake_req_reply_wait(ioc, sizeof(IOCInit_t), (u32*)&ioc_init,
  2988. sizeof(MPIDefaultReply_t), (u16*)&init_reply, 10 /*seconds*/, sleepFlag);
  2989. if (r != 0) {
  2990. printk(MYIOC_s_ERR_FMT "Sending IOCInit failed(%d)!\n",ioc->name, r);
  2991. return r;
  2992. }
  2993. /* No need to byte swap the multibyte fields in the reply
  2994. * since we don't even look at its contents.
  2995. */
  2996. dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending PortEnable (req @ %p)\n",
  2997. ioc->name, &ioc_init));
  2998. if ((r = SendPortEnable(ioc, 0, sleepFlag)) != 0) {
  2999. printk(MYIOC_s_ERR_FMT "Sending PortEnable failed(%d)!\n",ioc->name, r);
  3000. return r;
  3001. }
  3002. /* YIKES! SUPER IMPORTANT!!!
  3003. * Poll IocState until _OPERATIONAL while IOC is doing
  3004. * LoopInit and TargetDiscovery!
  3005. */
  3006. count = 0;
  3007. cntdn = ((sleepFlag == CAN_SLEEP) ? HZ : 1000) * 60; /* 60 seconds */
  3008. state = mpt_GetIocState(ioc, 1);
  3009. while (state != MPI_IOC_STATE_OPERATIONAL && --cntdn) {
  3010. if (sleepFlag == CAN_SLEEP) {
  3011. msleep(1);
  3012. } else {
  3013. mdelay(1);
  3014. }
  3015. if (!cntdn) {
  3016. printk(MYIOC_s_ERR_FMT "Wait IOC_OP state timeout(%d)!\n",
  3017. ioc->name, (int)((count+5)/HZ));
  3018. return -9;
  3019. }
  3020. state = mpt_GetIocState(ioc, 1);
  3021. count++;
  3022. }
  3023. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Wait IOC_OPERATIONAL state (cnt=%d)\n",
  3024. ioc->name, count));
  3025. ioc->aen_event_read_flag=0;
  3026. return r;
  3027. }
  3028. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  3029. /**
  3030. * SendPortEnable - Send PortEnable request to MPT adapter port.
  3031. * @ioc: Pointer to MPT_ADAPTER structure
  3032. * @portnum: Port number to enable
  3033. * @sleepFlag: Specifies whether the process can sleep
  3034. *
  3035. * Send PortEnable to bring IOC to OPERATIONAL state.
  3036. *
  3037. * Returns 0 for success, non-zero for failure.
  3038. */
  3039. static int
  3040. SendPortEnable(MPT_ADAPTER *ioc, int portnum, int sleepFlag)
  3041. {
  3042. PortEnable_t port_enable;
  3043. MPIDefaultReply_t reply_buf;
  3044. int rc;
  3045. int req_sz;
  3046. int reply_sz;
  3047. /* Destination... */
  3048. reply_sz = sizeof(MPIDefaultReply_t);
  3049. memset(&reply_buf, 0, reply_sz);
  3050. req_sz = sizeof(PortEnable_t);
  3051. memset(&port_enable, 0, req_sz);
  3052. port_enable.Function = MPI_FUNCTION_PORT_ENABLE;
  3053. port_enable.PortNumber = portnum;
  3054. /* port_enable.ChainOffset = 0; */
  3055. /* port_enable.MsgFlags = 0; */
  3056. /* port_enable.MsgContext = 0; */
  3057. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending Port(%d)Enable (req @ %p)\n",
  3058. ioc->name, portnum, &port_enable));
  3059. /* RAID FW may take a long time to enable
  3060. */
  3061. if (ioc->ir_firmware || ioc->bus_type == SAS) {
  3062. rc = mpt_handshake_req_reply_wait(ioc, req_sz,
  3063. (u32*)&port_enable, reply_sz, (u16*)&reply_buf,
  3064. 300 /*seconds*/, sleepFlag);
  3065. } else {
  3066. rc = mpt_handshake_req_reply_wait(ioc, req_sz,
  3067. (u32*)&port_enable, reply_sz, (u16*)&reply_buf,
  3068. 30 /*seconds*/, sleepFlag);
  3069. }
  3070. return rc;
  3071. }
  3072. /**
  3073. * mpt_alloc_fw_memory - allocate firmware memory
  3074. * @ioc: Pointer to MPT_ADAPTER structure
  3075. * @size: total FW bytes
  3076. *
  3077. * If memory has already been allocated, the same (cached) value
  3078. * is returned.
  3079. *
  3080. * Return 0 if successful, or non-zero for failure
  3081. **/
  3082. int
  3083. mpt_alloc_fw_memory(MPT_ADAPTER *ioc, int size)
  3084. {
  3085. int rc;
  3086. if (ioc->cached_fw) {
  3087. rc = 0; /* use already allocated memory */
  3088. goto out;
  3089. }
  3090. else if (ioc->alt_ioc && ioc->alt_ioc->cached_fw) {
  3091. ioc->cached_fw = ioc->alt_ioc->cached_fw; /* use alt_ioc's memory */
  3092. ioc->cached_fw_dma = ioc->alt_ioc->cached_fw_dma;
  3093. rc = 0;
  3094. goto out;
  3095. }
  3096. ioc->cached_fw = pci_alloc_consistent(ioc->pcidev, size, &ioc->cached_fw_dma);
  3097. if (!ioc->cached_fw) {
  3098. printk(MYIOC_s_ERR_FMT "Unable to allocate memory for the cached firmware image!\n",
  3099. ioc->name);
  3100. rc = -1;
  3101. } else {
  3102. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "FW Image @ %p[%p], sz=%d[%x] bytes\n",
  3103. ioc->name, ioc->cached_fw, (void *)(ulong)ioc->cached_fw_dma, size, size));
  3104. ioc->alloc_total += size;
  3105. rc = 0;
  3106. }
  3107. out:
  3108. return rc;
  3109. }
  3110. /**
  3111. * mpt_free_fw_memory - free firmware memory
  3112. * @ioc: Pointer to MPT_ADAPTER structure
  3113. *
  3114. * If alt_img is NULL, delete from ioc structure.
  3115. * Else, delete a secondary image in same format.
  3116. **/
  3117. void
  3118. mpt_free_fw_memory(MPT_ADAPTER *ioc)
  3119. {
  3120. int sz;
  3121. if (!ioc->cached_fw)
  3122. return;
  3123. sz = ioc->facts.FWImageSize;
  3124. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "free_fw_memory: FW Image @ %p[%p], sz=%d[%x] bytes\n",
  3125. ioc->name, ioc->cached_fw, (void *)(ulong)ioc->cached_fw_dma, sz, sz));
  3126. pci_free_consistent(ioc->pcidev, sz, ioc->cached_fw, ioc->cached_fw_dma);
  3127. ioc->alloc_total -= sz;
  3128. ioc->cached_fw = NULL;
  3129. }
  3130. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  3131. /**
  3132. * mpt_do_upload - Construct and Send FWUpload request to MPT adapter port.
  3133. * @ioc: Pointer to MPT_ADAPTER structure
  3134. * @sleepFlag: Specifies whether the process can sleep
  3135. *
  3136. * Returns 0 for success, >0 for handshake failure
  3137. * <0 for fw upload failure.
  3138. *
  3139. * Remark: If bound IOC and a successful FWUpload was performed
  3140. * on the bound IOC, the second image is discarded
  3141. * and memory is free'd. Both channels must upload to prevent
  3142. * IOC from running in degraded mode.
  3143. */
  3144. static int
  3145. mpt_do_upload(MPT_ADAPTER *ioc, int sleepFlag)
  3146. {
  3147. u8 reply[sizeof(FWUploadReply_t)];
  3148. FWUpload_t *prequest;
  3149. FWUploadReply_t *preply;
  3150. FWUploadTCSGE_t *ptcsge;
  3151. u32 flagsLength;
  3152. int ii, sz, reply_sz;
  3153. int cmdStatus;
  3154. int request_size;
  3155. /* If the image size is 0, we are done.
  3156. */
  3157. if ((sz = ioc->facts.FWImageSize) == 0)
  3158. return 0;
  3159. if (mpt_alloc_fw_memory(ioc, ioc->facts.FWImageSize) != 0)
  3160. return -ENOMEM;
  3161. dinitprintk(ioc, printk(MYIOC_s_INFO_FMT ": FW Image @ %p[%p], sz=%d[%x] bytes\n",
  3162. ioc->name, ioc->cached_fw, (void *)(ulong)ioc->cached_fw_dma, sz, sz));
  3163. prequest = (sleepFlag == NO_SLEEP) ? kzalloc(ioc->req_sz, GFP_ATOMIC) :
  3164. kzalloc(ioc->req_sz, GFP_KERNEL);
  3165. if (!prequest) {
  3166. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "fw upload failed "
  3167. "while allocating memory \n", ioc->name));
  3168. mpt_free_fw_memory(ioc);
  3169. return -ENOMEM;
  3170. }
  3171. preply = (FWUploadReply_t *)&reply;
  3172. reply_sz = sizeof(reply);
  3173. memset(preply, 0, reply_sz);
  3174. prequest->ImageType = MPI_FW_UPLOAD_ITYPE_FW_IOC_MEM;
  3175. prequest->Function = MPI_FUNCTION_FW_UPLOAD;
  3176. ptcsge = (FWUploadTCSGE_t *) &prequest->SGL;
  3177. ptcsge->DetailsLength = 12;
  3178. ptcsge->Flags = MPI_SGE_FLAGS_TRANSACTION_ELEMENT;
  3179. ptcsge->ImageSize = cpu_to_le32(sz);
  3180. ptcsge++;
  3181. flagsLength = MPT_SGE_FLAGS_SSIMPLE_READ | sz;
  3182. ioc->add_sge((char *)ptcsge, flagsLength, ioc->cached_fw_dma);
  3183. request_size = offsetof(FWUpload_t, SGL) + sizeof(FWUploadTCSGE_t) +
  3184. ioc->SGE_size;
  3185. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending FW Upload "
  3186. " (req @ %p) fw_size=%d mf_request_size=%d\n", ioc->name, prequest,
  3187. ioc->facts.FWImageSize, request_size));
  3188. DBG_DUMP_FW_REQUEST_FRAME(ioc, (u32 *)prequest);
  3189. ii = mpt_handshake_req_reply_wait(ioc, request_size, (u32 *)prequest,
  3190. reply_sz, (u16 *)preply, 65 /*seconds*/, sleepFlag);
  3191. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "FW Upload completed "
  3192. "rc=%x \n", ioc->name, ii));
  3193. cmdStatus = -EFAULT;
  3194. if (ii == 0) {
  3195. /* Handshake transfer was complete and successful.
  3196. * Check the Reply Frame.
  3197. */
  3198. int status;
  3199. status = le16_to_cpu(preply->IOCStatus) &
  3200. MPI_IOCSTATUS_MASK;
  3201. if (status == MPI_IOCSTATUS_SUCCESS &&
  3202. ioc->facts.FWImageSize ==
  3203. le32_to_cpu(preply->ActualImageSize))
  3204. cmdStatus = 0;
  3205. }
  3206. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT ": do_upload cmdStatus=%d \n",
  3207. ioc->name, cmdStatus));
  3208. if (cmdStatus) {
  3209. ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "fw upload failed, "
  3210. "freeing image \n", ioc->name));
  3211. mpt_free_fw_memory(ioc);
  3212. }
  3213. kfree(prequest);
  3214. return cmdStatus;
  3215. }
  3216. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  3217. /**
  3218. * mpt_downloadboot - DownloadBoot code
  3219. * @ioc: Pointer to MPT_ADAPTER structure
  3220. * @pFwHeader: Pointer to firmware header info
  3221. * @sleepFlag: Specifies whether the process can sleep
  3222. *
  3223. * FwDownloadBoot requires Programmed IO access.
  3224. *
  3225. * Returns 0 for success
  3226. * -1 FW Image size is 0
  3227. * -2 No valid cached_fw Pointer
  3228. * <0 for fw upload failure.
  3229. */
  3230. static int
  3231. mpt_downloadboot(MPT_ADAPTER *ioc, MpiFwHeader_t *pFwHeader, int sleepFlag)
  3232. {
  3233. MpiExtImageHeader_t *pExtImage;
  3234. u32 fwSize;
  3235. u32 diag0val;
  3236. int count;
  3237. u32 *ptrFw;
  3238. u32 diagRwData;
  3239. u32 nextImage;
  3240. u32 load_addr;
  3241. u32 ioc_state=0;
  3242. ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "downloadboot: fw size 0x%x (%d), FW Ptr %p\n",
  3243. ioc->name, pFwHeader->ImageSize, pFwHeader->ImageSize, pFwHeader));
  3244. CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF);
  3245. CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_1ST_KEY_VALUE);
  3246. CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_2ND_KEY_VALUE);
  3247. CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_3RD_KEY_VALUE);
  3248. CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_4TH_KEY_VALUE);
  3249. CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_5TH_KEY_VALUE);
  3250. CHIPREG_WRITE32(&ioc->chip->Diagnostic, (MPI_DIAG_PREVENT_IOC_BOOT | MPI_DIAG_DISABLE_ARM));
  3251. /* wait 1 msec */
  3252. if (sleepFlag == CAN_SLEEP) {
  3253. msleep(1);
  3254. } else {
  3255. mdelay (1);
  3256. }
  3257. diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
  3258. CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val | MPI_DIAG_RESET_ADAPTER);
  3259. for (count = 0; count < 30; count ++) {
  3260. diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
  3261. if (!(diag0val & MPI_DIAG_RESET_ADAPTER)) {
  3262. ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RESET_ADAPTER cleared, count=%d\n",
  3263. ioc->name, count));
  3264. break;
  3265. }
  3266. /* wait .1 sec */
  3267. if (sleepFlag == CAN_SLEEP) {
  3268. msleep (100);
  3269. } else {
  3270. mdelay (100);
  3271. }
  3272. }
  3273. if ( count == 30 ) {
  3274. ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "downloadboot failed! "
  3275. "Unable to get MPI_DIAG_DRWE mode, diag0val=%x\n",
  3276. ioc->name, diag0val));
  3277. return -3;
  3278. }
  3279. CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF);
  3280. CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_1ST_KEY_VALUE);
  3281. CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_2ND_KEY_VALUE);
  3282. CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_3RD_KEY_VALUE);
  3283. CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_4TH_KEY_VALUE);
  3284. CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_5TH_KEY_VALUE);
  3285. /* Set the DiagRwEn and Disable ARM bits */
  3286. CHIPREG_WRITE32(&ioc->chip->Diagnostic, (MPI_DIAG_RW_ENABLE | MPI_DIAG_DISABLE_ARM));
  3287. fwSize = (pFwHeader->ImageSize + 3)/4;
  3288. ptrFw = (u32 *) pFwHeader;
  3289. /* Write the LoadStartAddress to the DiagRw Address Register
  3290. * using Programmed IO
  3291. */
  3292. if (ioc->errata_flag_1064)
  3293. pci_enable_io_access(ioc->pcidev);
  3294. CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, pFwHeader->LoadStartAddress);
  3295. ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "LoadStart addr written 0x%x \n",
  3296. ioc->name, pFwHeader->LoadStartAddress));
  3297. ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Write FW Image: 0x%x bytes @ %p\n",
  3298. ioc->name, fwSize*4, ptrFw));
  3299. while (fwSize--) {
  3300. CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, *ptrFw++);
  3301. }
  3302. nextImage = pFwHeader->NextImageHeaderOffset;
  3303. while (nextImage) {
  3304. pExtImage = (MpiExtImageHeader_t *) ((char *)pFwHeader + nextImage);
  3305. load_addr = pExtImage->LoadStartAddress;
  3306. fwSize = (pExtImage->ImageSize + 3) >> 2;
  3307. ptrFw = (u32 *)pExtImage;
  3308. ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Write Ext Image: 0x%x (%d) bytes @ %p load_addr=%x\n",
  3309. ioc->name, fwSize*4, fwSize*4, ptrFw, load_addr));
  3310. CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, load_addr);
  3311. while (fwSize--) {
  3312. CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, *ptrFw++);
  3313. }
  3314. nextImage = pExtImage->NextImageHeaderOffset;
  3315. }
  3316. /* Write the IopResetVectorRegAddr */
  3317. ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Write IopResetVector Addr=%x! \n", ioc->name, pFwHeader->IopResetRegAddr));
  3318. CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, pFwHeader->IopResetRegAddr);
  3319. /* Write the IopResetVectorValue */
  3320. ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Write IopResetVector Value=%x! \n", ioc->name, pFwHeader->IopResetVectorValue));
  3321. CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, pFwHeader->IopResetVectorValue);
  3322. /* Clear the internal flash bad bit - autoincrementing register,
  3323. * so must do two writes.
  3324. */
  3325. if (ioc->bus_type == SPI) {
  3326. /*
  3327. * 1030 and 1035 H/W errata, workaround to access
  3328. * the ClearFlashBadSignatureBit
  3329. */
  3330. CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, 0x3F000000);
  3331. diagRwData = CHIPREG_PIO_READ32(&ioc->pio_chip->DiagRwData);
  3332. diagRwData |= 0x40000000;
  3333. CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, 0x3F000000);
  3334. CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, diagRwData);
  3335. } else /* if((ioc->bus_type == SAS) || (ioc->bus_type == FC)) */ {
  3336. diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
  3337. CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val |
  3338. MPI_DIAG_CLEAR_FLASH_BAD_SIG);
  3339. /* wait 1 msec */
  3340. if (sleepFlag == CAN_SLEEP) {
  3341. msleep (1);
  3342. } else {
  3343. mdelay (1);
  3344. }
  3345. }
  3346. if (ioc->errata_flag_1064)
  3347. pci_disable_io_access(ioc->pcidev);
  3348. diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
  3349. ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "downloadboot diag0val=%x, "
  3350. "turning off PREVENT_IOC_BOOT, DISABLE_ARM, RW_ENABLE\n",
  3351. ioc->name, diag0val));
  3352. diag0val &= ~(MPI_DIAG_PREVENT_IOC_BOOT | MPI_DIAG_DISABLE_ARM | MPI_DIAG_RW_ENABLE);
  3353. ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "downloadboot now diag0val=%x\n",
  3354. ioc->name, diag0val));
  3355. CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val);
  3356. /* Write 0xFF to reset the sequencer */
  3357. CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF);
  3358. if (ioc->bus_type == SAS) {
  3359. ioc_state = mpt_GetIocState(ioc, 0);
  3360. if ( (GetIocFacts(ioc, sleepFlag,
  3361. MPT_HOSTEVENT_IOC_BRINGUP)) != 0 ) {
  3362. ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "GetIocFacts failed: IocState=%x\n",
  3363. ioc->name, ioc_state));
  3364. return -EFAULT;
  3365. }
  3366. }
  3367. for (count=0; count<HZ*20; count++) {
  3368. if ((ioc_state = mpt_GetIocState(ioc, 0)) & MPI_IOC_STATE_READY) {
  3369. ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  3370. "downloadboot successful! (count=%d) IocState=%x\n",
  3371. ioc->name, count, ioc_state));
  3372. if (ioc->bus_type == SAS) {
  3373. return 0;
  3374. }
  3375. if ((SendIocInit(ioc, sleepFlag)) != 0) {
  3376. ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  3377. "downloadboot: SendIocInit failed\n",
  3378. ioc->name));
  3379. return -EFAULT;
  3380. }
  3381. ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  3382. "downloadboot: SendIocInit successful\n",
  3383. ioc->name));
  3384. return 0;
  3385. }
  3386. if (sleepFlag == CAN_SLEEP) {
  3387. msleep (10);
  3388. } else {
  3389. mdelay (10);
  3390. }
  3391. }
  3392. ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  3393. "downloadboot failed! IocState=%x\n",ioc->name, ioc_state));
  3394. return -EFAULT;
  3395. }
  3396. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  3397. /**
  3398. * KickStart - Perform hard reset of MPT adapter.
  3399. * @ioc: Pointer to MPT_ADAPTER structure
  3400. * @force: Force hard reset
  3401. * @sleepFlag: Specifies whether the process can sleep
  3402. *
  3403. * This routine places MPT adapter in diagnostic mode via the
  3404. * WriteSequence register, and then performs a hard reset of adapter
  3405. * via the Diagnostic register.
  3406. *
  3407. * Inputs: sleepflag - CAN_SLEEP (non-interrupt thread)
  3408. * or NO_SLEEP (interrupt thread, use mdelay)
  3409. * force - 1 if doorbell active, board fault state
  3410. * board operational, IOC_RECOVERY or
  3411. * IOC_BRINGUP and there is an alt_ioc.
  3412. * 0 else
  3413. *
  3414. * Returns:
  3415. * 1 - hard reset, READY
  3416. * 0 - no reset due to History bit, READY
  3417. * -1 - no reset due to History bit but not READY
  3418. * OR reset but failed to come READY
  3419. * -2 - no reset, could not enter DIAG mode
  3420. * -3 - reset but bad FW bit
  3421. */
  3422. static int
  3423. KickStart(MPT_ADAPTER *ioc, int force, int sleepFlag)
  3424. {
  3425. int hard_reset_done = 0;
  3426. u32 ioc_state=0;
  3427. int cnt,cntdn;
  3428. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "KickStarting!\n", ioc->name));
  3429. if (ioc->bus_type == SPI) {
  3430. /* Always issue a Msg Unit Reset first. This will clear some
  3431. * SCSI bus hang conditions.
  3432. */
  3433. SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, sleepFlag);
  3434. if (sleepFlag == CAN_SLEEP) {
  3435. msleep (1000);
  3436. } else {
  3437. mdelay (1000);
  3438. }
  3439. }
  3440. hard_reset_done = mpt_diag_reset(ioc, force, sleepFlag);
  3441. if (hard_reset_done < 0)
  3442. return hard_reset_done;
  3443. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Diagnostic reset successful!\n",
  3444. ioc->name));
  3445. cntdn = ((sleepFlag == CAN_SLEEP) ? HZ : 1000) * 2; /* 2 seconds */
  3446. for (cnt=0; cnt<cntdn; cnt++) {
  3447. ioc_state = mpt_GetIocState(ioc, 1);
  3448. if ((ioc_state == MPI_IOC_STATE_READY) || (ioc_state == MPI_IOC_STATE_OPERATIONAL)) {
  3449. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "KickStart successful! (cnt=%d)\n",
  3450. ioc->name, cnt));
  3451. return hard_reset_done;
  3452. }
  3453. if (sleepFlag == CAN_SLEEP) {
  3454. msleep (10);
  3455. } else {
  3456. mdelay (10);
  3457. }
  3458. }
  3459. dinitprintk(ioc, printk(MYIOC_s_ERR_FMT "Failed to come READY after reset! IocState=%x\n",
  3460. ioc->name, mpt_GetIocState(ioc, 0)));
  3461. return -1;
  3462. }
  3463. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  3464. /**
  3465. * mpt_diag_reset - Perform hard reset of the adapter.
  3466. * @ioc: Pointer to MPT_ADAPTER structure
  3467. * @ignore: Set if to honor and clear to ignore
  3468. * the reset history bit
  3469. * @sleepFlag: CAN_SLEEP if called in a non-interrupt thread,
  3470. * else set to NO_SLEEP (use mdelay instead)
  3471. *
  3472. * This routine places the adapter in diagnostic mode via the
  3473. * WriteSequence register and then performs a hard reset of adapter
  3474. * via the Diagnostic register. Adapter should be in ready state
  3475. * upon successful completion.
  3476. *
  3477. * Returns: 1 hard reset successful
  3478. * 0 no reset performed because reset history bit set
  3479. * -2 enabling diagnostic mode failed
  3480. * -3 diagnostic reset failed
  3481. */
  3482. static int
  3483. mpt_diag_reset(MPT_ADAPTER *ioc, int ignore, int sleepFlag)
  3484. {
  3485. u32 diag0val;
  3486. u32 doorbell;
  3487. int hard_reset_done = 0;
  3488. int count = 0;
  3489. u32 diag1val = 0;
  3490. MpiFwHeader_t *cached_fw; /* Pointer to FW */
  3491. u8 cb_idx;
  3492. /* Clear any existing interrupts */
  3493. CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
  3494. if (ioc->pcidev->device == MPI_MANUFACTPAGE_DEVID_SAS1078) {
  3495. if (!ignore)
  3496. return 0;
  3497. drsprintk(ioc, printk(MYIOC_s_WARN_FMT "%s: Doorbell=%p; 1078 reset "
  3498. "address=%p\n", ioc->name, __func__,
  3499. &ioc->chip->Doorbell, &ioc->chip->Reset_1078));
  3500. CHIPREG_WRITE32(&ioc->chip->Reset_1078, 0x07);
  3501. if (sleepFlag == CAN_SLEEP)
  3502. msleep(1);
  3503. else
  3504. mdelay(1);
  3505. /*
  3506. * Call each currently registered protocol IOC reset handler
  3507. * with pre-reset indication.
  3508. * NOTE: If we're doing _IOC_BRINGUP, there can be no
  3509. * MptResetHandlers[] registered yet.
  3510. */
  3511. for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
  3512. if (MptResetHandlers[cb_idx])
  3513. (*(MptResetHandlers[cb_idx]))(ioc,
  3514. MPT_IOC_PRE_RESET);
  3515. }
  3516. for (count = 0; count < 60; count ++) {
  3517. doorbell = CHIPREG_READ32(&ioc->chip->Doorbell);
  3518. doorbell &= MPI_IOC_STATE_MASK;
  3519. drsprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  3520. "looking for READY STATE: doorbell=%x"
  3521. " count=%d\n",
  3522. ioc->name, doorbell, count));
  3523. if (doorbell == MPI_IOC_STATE_READY) {
  3524. return 1;
  3525. }
  3526. /* wait 1 sec */
  3527. if (sleepFlag == CAN_SLEEP)
  3528. msleep(1000);
  3529. else
  3530. mdelay(1000);
  3531. }
  3532. return -1;
  3533. }
  3534. /* Use "Diagnostic reset" method! (only thing available!) */
  3535. diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
  3536. if (ioc->debug_level & MPT_DEBUG) {
  3537. if (ioc->alt_ioc)
  3538. diag1val = CHIPREG_READ32(&ioc->alt_ioc->chip->Diagnostic);
  3539. dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "DbG1: diag0=%08x, diag1=%08x\n",
  3540. ioc->name, diag0val, diag1val));
  3541. }
  3542. /* Do the reset if we are told to ignore the reset history
  3543. * or if the reset history is 0
  3544. */
  3545. if (ignore || !(diag0val & MPI_DIAG_RESET_HISTORY)) {
  3546. while ((diag0val & MPI_DIAG_DRWE) == 0) {
  3547. /* Write magic sequence to WriteSequence register
  3548. * Loop until in diagnostic mode
  3549. */
  3550. CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF);
  3551. CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_1ST_KEY_VALUE);
  3552. CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_2ND_KEY_VALUE);
  3553. CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_3RD_KEY_VALUE);
  3554. CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_4TH_KEY_VALUE);
  3555. CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_5TH_KEY_VALUE);
  3556. /* wait 100 msec */
  3557. if (sleepFlag == CAN_SLEEP) {
  3558. msleep (100);
  3559. } else {
  3560. mdelay (100);
  3561. }
  3562. count++;
  3563. if (count > 20) {
  3564. printk(MYIOC_s_ERR_FMT "Enable Diagnostic mode FAILED! (%02xh)\n",
  3565. ioc->name, diag0val);
  3566. return -2;
  3567. }
  3568. diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
  3569. dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Wrote magic DiagWriteEn sequence (%x)\n",
  3570. ioc->name, diag0val));
  3571. }
  3572. if (ioc->debug_level & MPT_DEBUG) {
  3573. if (ioc->alt_ioc)
  3574. diag1val = CHIPREG_READ32(&ioc->alt_ioc->chip->Diagnostic);
  3575. dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "DbG2: diag0=%08x, diag1=%08x\n",
  3576. ioc->name, diag0val, diag1val));
  3577. }
  3578. /*
  3579. * Disable the ARM (Bug fix)
  3580. *
  3581. */
  3582. CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val | MPI_DIAG_DISABLE_ARM);
  3583. mdelay(1);
  3584. /*
  3585. * Now hit the reset bit in the Diagnostic register
  3586. * (THE BIG HAMMER!) (Clears DRWE bit).
  3587. */
  3588. CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val | MPI_DIAG_RESET_ADAPTER);
  3589. hard_reset_done = 1;
  3590. dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Diagnostic reset performed\n",
  3591. ioc->name));
  3592. /*
  3593. * Call each currently registered protocol IOC reset handler
  3594. * with pre-reset indication.
  3595. * NOTE: If we're doing _IOC_BRINGUP, there can be no
  3596. * MptResetHandlers[] registered yet.
  3597. */
  3598. for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
  3599. if (MptResetHandlers[cb_idx]) {
  3600. mpt_signal_reset(cb_idx,
  3601. ioc, MPT_IOC_PRE_RESET);
  3602. if (ioc->alt_ioc) {
  3603. mpt_signal_reset(cb_idx,
  3604. ioc->alt_ioc, MPT_IOC_PRE_RESET);
  3605. }
  3606. }
  3607. }
  3608. if (ioc->cached_fw)
  3609. cached_fw = (MpiFwHeader_t *)ioc->cached_fw;
  3610. else if (ioc->alt_ioc && ioc->alt_ioc->cached_fw)
  3611. cached_fw = (MpiFwHeader_t *)ioc->alt_ioc->cached_fw;
  3612. else
  3613. cached_fw = NULL;
  3614. if (cached_fw) {
  3615. /* If the DownloadBoot operation fails, the
  3616. * IOC will be left unusable. This is a fatal error
  3617. * case. _diag_reset will return < 0
  3618. */
  3619. for (count = 0; count < 30; count ++) {
  3620. diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
  3621. if (!(diag0val & MPI_DIAG_RESET_ADAPTER)) {
  3622. break;
  3623. }
  3624. dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "cached_fw: diag0val=%x count=%d\n",
  3625. ioc->name, diag0val, count));
  3626. /* wait 1 sec */
  3627. if (sleepFlag == CAN_SLEEP) {
  3628. msleep (1000);
  3629. } else {
  3630. mdelay (1000);
  3631. }
  3632. }
  3633. if ((count = mpt_downloadboot(ioc, cached_fw, sleepFlag)) < 0) {
  3634. printk(MYIOC_s_WARN_FMT
  3635. "firmware downloadboot failure (%d)!\n", ioc->name, count);
  3636. }
  3637. } else {
  3638. /* Wait for FW to reload and for board
  3639. * to go to the READY state.
  3640. * Maximum wait is 60 seconds.
  3641. * If fail, no error will check again
  3642. * with calling program.
  3643. */
  3644. for (count = 0; count < 60; count ++) {
  3645. doorbell = CHIPREG_READ32(&ioc->chip->Doorbell);
  3646. doorbell &= MPI_IOC_STATE_MASK;
  3647. drsprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  3648. "looking for READY STATE: doorbell=%x"
  3649. " count=%d\n", ioc->name, doorbell, count));
  3650. if (doorbell == MPI_IOC_STATE_READY) {
  3651. break;
  3652. }
  3653. /* wait 1 sec */
  3654. if (sleepFlag == CAN_SLEEP) {
  3655. msleep (1000);
  3656. } else {
  3657. mdelay (1000);
  3658. }
  3659. }
  3660. if (doorbell != MPI_IOC_STATE_READY)
  3661. printk(MYIOC_s_ERR_FMT "Failed to come READY "
  3662. "after reset! IocState=%x", ioc->name,
  3663. doorbell);
  3664. }
  3665. }
  3666. diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
  3667. if (ioc->debug_level & MPT_DEBUG) {
  3668. if (ioc->alt_ioc)
  3669. diag1val = CHIPREG_READ32(&ioc->alt_ioc->chip->Diagnostic);
  3670. dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "DbG3: diag0=%08x, diag1=%08x\n",
  3671. ioc->name, diag0val, diag1val));
  3672. }
  3673. /* Clear RESET_HISTORY bit! Place board in the
  3674. * diagnostic mode to update the diag register.
  3675. */
  3676. diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
  3677. count = 0;
  3678. while ((diag0val & MPI_DIAG_DRWE) == 0) {
  3679. /* Write magic sequence to WriteSequence register
  3680. * Loop until in diagnostic mode
  3681. */
  3682. CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF);
  3683. CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_1ST_KEY_VALUE);
  3684. CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_2ND_KEY_VALUE);
  3685. CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_3RD_KEY_VALUE);
  3686. CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_4TH_KEY_VALUE);
  3687. CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_5TH_KEY_VALUE);
  3688. /* wait 100 msec */
  3689. if (sleepFlag == CAN_SLEEP) {
  3690. msleep (100);
  3691. } else {
  3692. mdelay (100);
  3693. }
  3694. count++;
  3695. if (count > 20) {
  3696. printk(MYIOC_s_ERR_FMT "Enable Diagnostic mode FAILED! (%02xh)\n",
  3697. ioc->name, diag0val);
  3698. break;
  3699. }
  3700. diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
  3701. }
  3702. diag0val &= ~MPI_DIAG_RESET_HISTORY;
  3703. CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val);
  3704. diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
  3705. if (diag0val & MPI_DIAG_RESET_HISTORY) {
  3706. printk(MYIOC_s_WARN_FMT "ResetHistory bit failed to clear!\n",
  3707. ioc->name);
  3708. }
  3709. /* Disable Diagnostic Mode
  3710. */
  3711. CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFFFFFFFF);
  3712. /* Check FW reload status flags.
  3713. */
  3714. diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
  3715. if (diag0val & (MPI_DIAG_FLASH_BAD_SIG | MPI_DIAG_RESET_ADAPTER | MPI_DIAG_DISABLE_ARM)) {
  3716. printk(MYIOC_s_ERR_FMT "Diagnostic reset FAILED! (%02xh)\n",
  3717. ioc->name, diag0val);
  3718. return -3;
  3719. }
  3720. if (ioc->debug_level & MPT_DEBUG) {
  3721. if (ioc->alt_ioc)
  3722. diag1val = CHIPREG_READ32(&ioc->alt_ioc->chip->Diagnostic);
  3723. dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "DbG4: diag0=%08x, diag1=%08x\n",
  3724. ioc->name, diag0val, diag1val));
  3725. }
  3726. /*
  3727. * Reset flag that says we've enabled event notification
  3728. */
  3729. ioc->facts.EventState = 0;
  3730. if (ioc->alt_ioc)
  3731. ioc->alt_ioc->facts.EventState = 0;
  3732. return hard_reset_done;
  3733. }
  3734. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  3735. /**
  3736. * SendIocReset - Send IOCReset request to MPT adapter.
  3737. * @ioc: Pointer to MPT_ADAPTER structure
  3738. * @reset_type: reset type, expected values are
  3739. * %MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET or %MPI_FUNCTION_IO_UNIT_RESET
  3740. * @sleepFlag: Specifies whether the process can sleep
  3741. *
  3742. * Send IOCReset request to the MPT adapter.
  3743. *
  3744. * Returns 0 for success, non-zero for failure.
  3745. */
  3746. static int
  3747. SendIocReset(MPT_ADAPTER *ioc, u8 reset_type, int sleepFlag)
  3748. {
  3749. int r;
  3750. u32 state;
  3751. int cntdn, count;
  3752. drsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending IOC reset(0x%02x)!\n",
  3753. ioc->name, reset_type));
  3754. CHIPREG_WRITE32(&ioc->chip->Doorbell, reset_type<<MPI_DOORBELL_FUNCTION_SHIFT);
  3755. if ((r = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0)
  3756. return r;
  3757. /* FW ACK'd request, wait for READY state
  3758. */
  3759. count = 0;
  3760. cntdn = ((sleepFlag == CAN_SLEEP) ? HZ : 1000) * 15; /* 15 seconds */
  3761. while ((state = mpt_GetIocState(ioc, 1)) != MPI_IOC_STATE_READY) {
  3762. cntdn--;
  3763. count++;
  3764. if (!cntdn) {
  3765. if (sleepFlag != CAN_SLEEP)
  3766. count *= 10;
  3767. printk(MYIOC_s_ERR_FMT
  3768. "Wait IOC_READY state (0x%x) timeout(%d)!\n",
  3769. ioc->name, state, (int)((count+5)/HZ));
  3770. return -ETIME;
  3771. }
  3772. if (sleepFlag == CAN_SLEEP) {
  3773. msleep(1);
  3774. } else {
  3775. mdelay (1); /* 1 msec delay */
  3776. }
  3777. }
  3778. /* TODO!
  3779. * Cleanup all event stuff for this IOC; re-issue EventNotification
  3780. * request if needed.
  3781. */
  3782. if (ioc->facts.Function)
  3783. ioc->facts.EventState = 0;
  3784. return 0;
  3785. }
  3786. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  3787. /**
  3788. * initChainBuffers - Allocate memory for and initialize chain buffers
  3789. * @ioc: Pointer to MPT_ADAPTER structure
  3790. *
  3791. * Allocates memory for and initializes chain buffers,
  3792. * chain buffer control arrays and spinlock.
  3793. */
  3794. static int
  3795. initChainBuffers(MPT_ADAPTER *ioc)
  3796. {
  3797. u8 *mem;
  3798. int sz, ii, num_chain;
  3799. int scale, num_sge, numSGE;
  3800. /* ReqToChain size must equal the req_depth
  3801. * index = req_idx
  3802. */
  3803. if (ioc->ReqToChain == NULL) {
  3804. sz = ioc->req_depth * sizeof(int);
  3805. mem = kmalloc(sz, GFP_ATOMIC);
  3806. if (mem == NULL)
  3807. return -1;
  3808. ioc->ReqToChain = (int *) mem;
  3809. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReqToChain alloc @ %p, sz=%d bytes\n",
  3810. ioc->name, mem, sz));
  3811. mem = kmalloc(sz, GFP_ATOMIC);
  3812. if (mem == NULL)
  3813. return -1;
  3814. ioc->RequestNB = (int *) mem;
  3815. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RequestNB alloc @ %p, sz=%d bytes\n",
  3816. ioc->name, mem, sz));
  3817. }
  3818. for (ii = 0; ii < ioc->req_depth; ii++) {
  3819. ioc->ReqToChain[ii] = MPT_HOST_NO_CHAIN;
  3820. }
  3821. /* ChainToChain size must equal the total number
  3822. * of chain buffers to be allocated.
  3823. * index = chain_idx
  3824. *
  3825. * Calculate the number of chain buffers needed(plus 1) per I/O
  3826. * then multiply the maximum number of simultaneous cmds
  3827. *
  3828. * num_sge = num sge in request frame + last chain buffer
  3829. * scale = num sge per chain buffer if no chain element
  3830. */
  3831. scale = ioc->req_sz / ioc->SGE_size;
  3832. if (ioc->sg_addr_size == sizeof(u64))
  3833. num_sge = scale + (ioc->req_sz - 60) / ioc->SGE_size;
  3834. else
  3835. num_sge = 1 + scale + (ioc->req_sz - 64) / ioc->SGE_size;
  3836. if (ioc->sg_addr_size == sizeof(u64)) {
  3837. numSGE = (scale - 1) * (ioc->facts.MaxChainDepth-1) + scale +
  3838. (ioc->req_sz - 60) / ioc->SGE_size;
  3839. } else {
  3840. numSGE = 1 + (scale - 1) * (ioc->facts.MaxChainDepth-1) +
  3841. scale + (ioc->req_sz - 64) / ioc->SGE_size;
  3842. }
  3843. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "num_sge=%d numSGE=%d\n",
  3844. ioc->name, num_sge, numSGE));
  3845. if (ioc->bus_type == FC) {
  3846. if (numSGE > MPT_SCSI_FC_SG_DEPTH)
  3847. numSGE = MPT_SCSI_FC_SG_DEPTH;
  3848. } else {
  3849. if (numSGE > MPT_SCSI_SG_DEPTH)
  3850. numSGE = MPT_SCSI_SG_DEPTH;
  3851. }
  3852. num_chain = 1;
  3853. while (numSGE - num_sge > 0) {
  3854. num_chain++;
  3855. num_sge += (scale - 1);
  3856. }
  3857. num_chain++;
  3858. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Now numSGE=%d num_sge=%d num_chain=%d\n",
  3859. ioc->name, numSGE, num_sge, num_chain));
  3860. if (ioc->bus_type == SPI)
  3861. num_chain *= MPT_SCSI_CAN_QUEUE;
  3862. else if (ioc->bus_type == SAS)
  3863. num_chain *= MPT_SAS_CAN_QUEUE;
  3864. else
  3865. num_chain *= MPT_FC_CAN_QUEUE;
  3866. ioc->num_chain = num_chain;
  3867. sz = num_chain * sizeof(int);
  3868. if (ioc->ChainToChain == NULL) {
  3869. mem = kmalloc(sz, GFP_ATOMIC);
  3870. if (mem == NULL)
  3871. return -1;
  3872. ioc->ChainToChain = (int *) mem;
  3873. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ChainToChain alloc @ %p, sz=%d bytes\n",
  3874. ioc->name, mem, sz));
  3875. } else {
  3876. mem = (u8 *) ioc->ChainToChain;
  3877. }
  3878. memset(mem, 0xFF, sz);
  3879. return num_chain;
  3880. }
  3881. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  3882. /**
  3883. * PrimeIocFifos - Initialize IOC request and reply FIFOs.
  3884. * @ioc: Pointer to MPT_ADAPTER structure
  3885. *
  3886. * This routine allocates memory for the MPT reply and request frame
  3887. * pools (if necessary), and primes the IOC reply FIFO with
  3888. * reply frames.
  3889. *
  3890. * Returns 0 for success, non-zero for failure.
  3891. */
  3892. static int
  3893. PrimeIocFifos(MPT_ADAPTER *ioc)
  3894. {
  3895. MPT_FRAME_HDR *mf;
  3896. unsigned long flags;
  3897. dma_addr_t alloc_dma;
  3898. u8 *mem;
  3899. int i, reply_sz, sz, total_size, num_chain;
  3900. u64 dma_mask;
  3901. dma_mask = 0;
  3902. /* Prime reply FIFO... */
  3903. if (ioc->reply_frames == NULL) {
  3904. if ( (num_chain = initChainBuffers(ioc)) < 0)
  3905. return -1;
  3906. /*
  3907. * 1078 errata workaround for the 36GB limitation
  3908. */
  3909. if (ioc->pcidev->device == MPI_MANUFACTPAGE_DEVID_SAS1078 &&
  3910. ioc->dma_mask > DMA_BIT_MASK(35)) {
  3911. if (!pci_set_dma_mask(ioc->pcidev, DMA_BIT_MASK(32))
  3912. && !pci_set_consistent_dma_mask(ioc->pcidev,
  3913. DMA_BIT_MASK(32))) {
  3914. dma_mask = DMA_BIT_MASK(35);
  3915. d36memprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  3916. "setting 35 bit addressing for "
  3917. "Request/Reply/Chain and Sense Buffers\n",
  3918. ioc->name));
  3919. } else {
  3920. /*Reseting DMA mask to 64 bit*/
  3921. pci_set_dma_mask(ioc->pcidev,
  3922. DMA_BIT_MASK(64));
  3923. pci_set_consistent_dma_mask(ioc->pcidev,
  3924. DMA_BIT_MASK(64));
  3925. printk(MYIOC_s_ERR_FMT
  3926. "failed setting 35 bit addressing for "
  3927. "Request/Reply/Chain and Sense Buffers\n",
  3928. ioc->name);
  3929. return -1;
  3930. }
  3931. }
  3932. total_size = reply_sz = (ioc->reply_sz * ioc->reply_depth);
  3933. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReplyBuffer sz=%d bytes, ReplyDepth=%d\n",
  3934. ioc->name, ioc->reply_sz, ioc->reply_depth));
  3935. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReplyBuffer sz=%d[%x] bytes\n",
  3936. ioc->name, reply_sz, reply_sz));
  3937. sz = (ioc->req_sz * ioc->req_depth);
  3938. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RequestBuffer sz=%d bytes, RequestDepth=%d\n",
  3939. ioc->name, ioc->req_sz, ioc->req_depth));
  3940. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RequestBuffer sz=%d[%x] bytes\n",
  3941. ioc->name, sz, sz));
  3942. total_size += sz;
  3943. sz = num_chain * ioc->req_sz; /* chain buffer pool size */
  3944. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ChainBuffer sz=%d bytes, ChainDepth=%d\n",
  3945. ioc->name, ioc->req_sz, num_chain));
  3946. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ChainBuffer sz=%d[%x] bytes num_chain=%d\n",
  3947. ioc->name, sz, sz, num_chain));
  3948. total_size += sz;
  3949. mem = dma_alloc_coherent(&ioc->pcidev->dev, total_size,
  3950. &alloc_dma, GFP_KERNEL);
  3951. if (mem == NULL) {
  3952. printk(MYIOC_s_ERR_FMT "Unable to allocate Reply, Request, Chain Buffers!\n",
  3953. ioc->name);
  3954. goto out_fail;
  3955. }
  3956. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Total alloc @ %p[%p], sz=%d[%x] bytes\n",
  3957. ioc->name, mem, (void *)(ulong)alloc_dma, total_size, total_size));
  3958. memset(mem, 0, total_size);
  3959. ioc->alloc_total += total_size;
  3960. ioc->alloc = mem;
  3961. ioc->alloc_dma = alloc_dma;
  3962. ioc->alloc_sz = total_size;
  3963. ioc->reply_frames = (MPT_FRAME_HDR *) mem;
  3964. ioc->reply_frames_low_dma = (u32) (alloc_dma & 0xFFFFFFFF);
  3965. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReplyBuffers @ %p[%p]\n",
  3966. ioc->name, ioc->reply_frames, (void *)(ulong)alloc_dma));
  3967. alloc_dma += reply_sz;
  3968. mem += reply_sz;
  3969. /* Request FIFO - WE manage this! */
  3970. ioc->req_frames = (MPT_FRAME_HDR *) mem;
  3971. ioc->req_frames_dma = alloc_dma;
  3972. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RequestBuffers @ %p[%p]\n",
  3973. ioc->name, mem, (void *)(ulong)alloc_dma));
  3974. ioc->req_frames_low_dma = (u32) (alloc_dma & 0xFFFFFFFF);
  3975. for (i = 0; i < ioc->req_depth; i++) {
  3976. alloc_dma += ioc->req_sz;
  3977. mem += ioc->req_sz;
  3978. }
  3979. ioc->ChainBuffer = mem;
  3980. ioc->ChainBufferDMA = alloc_dma;
  3981. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ChainBuffers @ %p(%p)\n",
  3982. ioc->name, ioc->ChainBuffer, (void *)(ulong)ioc->ChainBufferDMA));
  3983. /* Initialize the free chain Q.
  3984. */
  3985. INIT_LIST_HEAD(&ioc->FreeChainQ);
  3986. /* Post the chain buffers to the FreeChainQ.
  3987. */
  3988. mem = (u8 *)ioc->ChainBuffer;
  3989. for (i=0; i < num_chain; i++) {
  3990. mf = (MPT_FRAME_HDR *) mem;
  3991. list_add_tail(&mf->u.frame.linkage.list, &ioc->FreeChainQ);
  3992. mem += ioc->req_sz;
  3993. }
  3994. /* Initialize Request frames linked list
  3995. */
  3996. alloc_dma = ioc->req_frames_dma;
  3997. mem = (u8 *) ioc->req_frames;
  3998. spin_lock_irqsave(&ioc->FreeQlock, flags);
  3999. INIT_LIST_HEAD(&ioc->FreeQ);
  4000. for (i = 0; i < ioc->req_depth; i++) {
  4001. mf = (MPT_FRAME_HDR *) mem;
  4002. /* Queue REQUESTs *internally*! */
  4003. list_add_tail(&mf->u.frame.linkage.list, &ioc->FreeQ);
  4004. mem += ioc->req_sz;
  4005. }
  4006. spin_unlock_irqrestore(&ioc->FreeQlock, flags);
  4007. sz = (ioc->req_depth * MPT_SENSE_BUFFER_ALLOC);
  4008. ioc->sense_buf_pool = dma_alloc_coherent(&ioc->pcidev->dev, sz,
  4009. &ioc->sense_buf_pool_dma, GFP_KERNEL);
  4010. if (ioc->sense_buf_pool == NULL) {
  4011. printk(MYIOC_s_ERR_FMT "Unable to allocate Sense Buffers!\n",
  4012. ioc->name);
  4013. goto out_fail;
  4014. }
  4015. ioc->sense_buf_low_dma = (u32) (ioc->sense_buf_pool_dma & 0xFFFFFFFF);
  4016. ioc->alloc_total += sz;
  4017. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "SenseBuffers @ %p[%p]\n",
  4018. ioc->name, ioc->sense_buf_pool, (void *)(ulong)ioc->sense_buf_pool_dma));
  4019. }
  4020. /* Post Reply frames to FIFO
  4021. */
  4022. alloc_dma = ioc->alloc_dma;
  4023. dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReplyBuffers @ %p[%p]\n",
  4024. ioc->name, ioc->reply_frames, (void *)(ulong)alloc_dma));
  4025. for (i = 0; i < ioc->reply_depth; i++) {
  4026. /* Write each address to the IOC! */
  4027. CHIPREG_WRITE32(&ioc->chip->ReplyFifo, alloc_dma);
  4028. alloc_dma += ioc->reply_sz;
  4029. }
  4030. if (dma_mask == DMA_BIT_MASK(35) && !pci_set_dma_mask(ioc->pcidev,
  4031. ioc->dma_mask) && !pci_set_consistent_dma_mask(ioc->pcidev,
  4032. ioc->dma_mask))
  4033. d36memprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  4034. "restoring 64 bit addressing\n", ioc->name));
  4035. return 0;
  4036. out_fail:
  4037. if (ioc->alloc != NULL) {
  4038. sz = ioc->alloc_sz;
  4039. dma_free_coherent(&ioc->pcidev->dev, sz, ioc->alloc,
  4040. ioc->alloc_dma);
  4041. ioc->reply_frames = NULL;
  4042. ioc->req_frames = NULL;
  4043. ioc->alloc_total -= sz;
  4044. }
  4045. if (ioc->sense_buf_pool != NULL) {
  4046. sz = (ioc->req_depth * MPT_SENSE_BUFFER_ALLOC);
  4047. dma_free_coherent(&ioc->pcidev->dev, sz, ioc->sense_buf_pool,
  4048. ioc->sense_buf_pool_dma);
  4049. ioc->sense_buf_pool = NULL;
  4050. }
  4051. if (dma_mask == DMA_BIT_MASK(35) && !pci_set_dma_mask(ioc->pcidev,
  4052. DMA_BIT_MASK(64)) && !pci_set_consistent_dma_mask(ioc->pcidev,
  4053. DMA_BIT_MASK(64)))
  4054. d36memprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  4055. "restoring 64 bit addressing\n", ioc->name));
  4056. return -1;
  4057. }
  4058. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  4059. /**
  4060. * mpt_handshake_req_reply_wait - Send MPT request to and receive reply
  4061. * from IOC via doorbell handshake method.
  4062. * @ioc: Pointer to MPT_ADAPTER structure
  4063. * @reqBytes: Size of the request in bytes
  4064. * @req: Pointer to MPT request frame
  4065. * @replyBytes: Expected size of the reply in bytes
  4066. * @u16reply: Pointer to area where reply should be written
  4067. * @maxwait: Max wait time for a reply (in seconds)
  4068. * @sleepFlag: Specifies whether the process can sleep
  4069. *
  4070. * NOTES: It is the callers responsibility to byte-swap fields in the
  4071. * request which are greater than 1 byte in size. It is also the
  4072. * callers responsibility to byte-swap response fields which are
  4073. * greater than 1 byte in size.
  4074. *
  4075. * Returns 0 for success, non-zero for failure.
  4076. */
  4077. static int
  4078. mpt_handshake_req_reply_wait(MPT_ADAPTER *ioc, int reqBytes, u32 *req,
  4079. int replyBytes, u16 *u16reply, int maxwait, int sleepFlag)
  4080. {
  4081. MPIDefaultReply_t *mptReply;
  4082. int failcnt = 0;
  4083. int t;
  4084. /*
  4085. * Get ready to cache a handshake reply
  4086. */
  4087. ioc->hs_reply_idx = 0;
  4088. mptReply = (MPIDefaultReply_t *) ioc->hs_reply;
  4089. mptReply->MsgLength = 0;
  4090. /*
  4091. * Make sure there are no doorbells (WRITE 0 to IntStatus reg),
  4092. * then tell IOC that we want to handshake a request of N words.
  4093. * (WRITE u32val to Doorbell reg).
  4094. */
  4095. CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
  4096. CHIPREG_WRITE32(&ioc->chip->Doorbell,
  4097. ((MPI_FUNCTION_HANDSHAKE<<MPI_DOORBELL_FUNCTION_SHIFT) |
  4098. ((reqBytes/4)<<MPI_DOORBELL_ADD_DWORDS_SHIFT)));
  4099. /*
  4100. * Wait for IOC's doorbell handshake int
  4101. */
  4102. if ((t = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0)
  4103. failcnt++;
  4104. dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "HandShake request start reqBytes=%d, WaitCnt=%d%s\n",
  4105. ioc->name, reqBytes, t, failcnt ? " - MISSING DOORBELL HANDSHAKE!" : ""));
  4106. /* Read doorbell and check for active bit */
  4107. if (!(CHIPREG_READ32(&ioc->chip->Doorbell) & MPI_DOORBELL_ACTIVE))
  4108. return -1;
  4109. /*
  4110. * Clear doorbell int (WRITE 0 to IntStatus reg),
  4111. * then wait for IOC to ACKnowledge that it's ready for
  4112. * our handshake request.
  4113. */
  4114. CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
  4115. if (!failcnt && (t = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0)
  4116. failcnt++;
  4117. if (!failcnt) {
  4118. int ii;
  4119. u8 *req_as_bytes = (u8 *) req;
  4120. /*
  4121. * Stuff request words via doorbell handshake,
  4122. * with ACK from IOC for each.
  4123. */
  4124. for (ii = 0; !failcnt && ii < reqBytes/4; ii++) {
  4125. u32 word = ((req_as_bytes[(ii*4) + 0] << 0) |
  4126. (req_as_bytes[(ii*4) + 1] << 8) |
  4127. (req_as_bytes[(ii*4) + 2] << 16) |
  4128. (req_as_bytes[(ii*4) + 3] << 24));
  4129. CHIPREG_WRITE32(&ioc->chip->Doorbell, word);
  4130. if ((t = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0)
  4131. failcnt++;
  4132. }
  4133. dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Handshake request frame (@%p) header\n", ioc->name, req));
  4134. DBG_DUMP_REQUEST_FRAME_HDR(ioc, (u32 *)req);
  4135. dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "HandShake request post done, WaitCnt=%d%s\n",
  4136. ioc->name, t, failcnt ? " - MISSING DOORBELL ACK!" : ""));
  4137. /*
  4138. * Wait for completion of doorbell handshake reply from the IOC
  4139. */
  4140. if (!failcnt && (t = WaitForDoorbellReply(ioc, maxwait, sleepFlag)) < 0)
  4141. failcnt++;
  4142. dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "HandShake reply count=%d%s\n",
  4143. ioc->name, t, failcnt ? " - MISSING DOORBELL REPLY!" : ""));
  4144. /*
  4145. * Copy out the cached reply...
  4146. */
  4147. for (ii=0; ii < min(replyBytes/2,mptReply->MsgLength*2); ii++)
  4148. u16reply[ii] = ioc->hs_reply[ii];
  4149. } else {
  4150. return -99;
  4151. }
  4152. return -failcnt;
  4153. }
  4154. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  4155. /**
  4156. * WaitForDoorbellAck - Wait for IOC doorbell handshake acknowledge
  4157. * @ioc: Pointer to MPT_ADAPTER structure
  4158. * @howlong: How long to wait (in seconds)
  4159. * @sleepFlag: Specifies whether the process can sleep
  4160. *
  4161. * This routine waits (up to ~2 seconds max) for IOC doorbell
  4162. * handshake ACKnowledge, indicated by the IOP_DOORBELL_STATUS
  4163. * bit in its IntStatus register being clear.
  4164. *
  4165. * Returns a negative value on failure, else wait loop count.
  4166. */
  4167. static int
  4168. WaitForDoorbellAck(MPT_ADAPTER *ioc, int howlong, int sleepFlag)
  4169. {
  4170. int cntdn;
  4171. int count = 0;
  4172. u32 intstat=0;
  4173. cntdn = 1000 * howlong;
  4174. if (sleepFlag == CAN_SLEEP) {
  4175. while (--cntdn) {
  4176. msleep (1);
  4177. intstat = CHIPREG_READ32(&ioc->chip->IntStatus);
  4178. if (! (intstat & MPI_HIS_IOP_DOORBELL_STATUS))
  4179. break;
  4180. count++;
  4181. }
  4182. } else {
  4183. while (--cntdn) {
  4184. udelay (1000);
  4185. intstat = CHIPREG_READ32(&ioc->chip->IntStatus);
  4186. if (! (intstat & MPI_HIS_IOP_DOORBELL_STATUS))
  4187. break;
  4188. count++;
  4189. }
  4190. }
  4191. if (cntdn) {
  4192. dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "WaitForDoorbell ACK (count=%d)\n",
  4193. ioc->name, count));
  4194. return count;
  4195. }
  4196. printk(MYIOC_s_ERR_FMT "Doorbell ACK timeout (count=%d), IntStatus=%x!\n",
  4197. ioc->name, count, intstat);
  4198. return -1;
  4199. }
  4200. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  4201. /**
  4202. * WaitForDoorbellInt - Wait for IOC to set its doorbell interrupt bit
  4203. * @ioc: Pointer to MPT_ADAPTER structure
  4204. * @howlong: How long to wait (in seconds)
  4205. * @sleepFlag: Specifies whether the process can sleep
  4206. *
  4207. * This routine waits (up to ~2 seconds max) for IOC doorbell interrupt
  4208. * (MPI_HIS_DOORBELL_INTERRUPT) to be set in the IntStatus register.
  4209. *
  4210. * Returns a negative value on failure, else wait loop count.
  4211. */
  4212. static int
  4213. WaitForDoorbellInt(MPT_ADAPTER *ioc, int howlong, int sleepFlag)
  4214. {
  4215. int cntdn;
  4216. int count = 0;
  4217. u32 intstat=0;
  4218. cntdn = 1000 * howlong;
  4219. if (sleepFlag == CAN_SLEEP) {
  4220. while (--cntdn) {
  4221. intstat = CHIPREG_READ32(&ioc->chip->IntStatus);
  4222. if (intstat & MPI_HIS_DOORBELL_INTERRUPT)
  4223. break;
  4224. msleep(1);
  4225. count++;
  4226. }
  4227. } else {
  4228. while (--cntdn) {
  4229. intstat = CHIPREG_READ32(&ioc->chip->IntStatus);
  4230. if (intstat & MPI_HIS_DOORBELL_INTERRUPT)
  4231. break;
  4232. udelay (1000);
  4233. count++;
  4234. }
  4235. }
  4236. if (cntdn) {
  4237. dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "WaitForDoorbell INT (cnt=%d) howlong=%d\n",
  4238. ioc->name, count, howlong));
  4239. return count;
  4240. }
  4241. printk(MYIOC_s_ERR_FMT "Doorbell INT timeout (count=%d), IntStatus=%x!\n",
  4242. ioc->name, count, intstat);
  4243. return -1;
  4244. }
  4245. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  4246. /**
  4247. * WaitForDoorbellReply - Wait for and capture an IOC handshake reply.
  4248. * @ioc: Pointer to MPT_ADAPTER structure
  4249. * @howlong: How long to wait (in seconds)
  4250. * @sleepFlag: Specifies whether the process can sleep
  4251. *
  4252. * This routine polls the IOC for a handshake reply, 16 bits at a time.
  4253. * Reply is cached to IOC private area large enough to hold a maximum
  4254. * of 128 bytes of reply data.
  4255. *
  4256. * Returns a negative value on failure, else size of reply in WORDS.
  4257. */
  4258. static int
  4259. WaitForDoorbellReply(MPT_ADAPTER *ioc, int howlong, int sleepFlag)
  4260. {
  4261. int u16cnt = 0;
  4262. int failcnt = 0;
  4263. int t;
  4264. u16 *hs_reply = ioc->hs_reply;
  4265. volatile MPIDefaultReply_t *mptReply = (MPIDefaultReply_t *) ioc->hs_reply;
  4266. u16 hword;
  4267. hs_reply[0] = hs_reply[1] = hs_reply[7] = 0;
  4268. /*
  4269. * Get first two u16's so we can look at IOC's intended reply MsgLength
  4270. */
  4271. u16cnt=0;
  4272. if ((t = WaitForDoorbellInt(ioc, howlong, sleepFlag)) < 0) {
  4273. failcnt++;
  4274. } else {
  4275. hs_reply[u16cnt++] = le16_to_cpu(CHIPREG_READ32(&ioc->chip->Doorbell) & 0x0000FFFF);
  4276. CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
  4277. if ((t = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0)
  4278. failcnt++;
  4279. else {
  4280. hs_reply[u16cnt++] = le16_to_cpu(CHIPREG_READ32(&ioc->chip->Doorbell) & 0x0000FFFF);
  4281. CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
  4282. }
  4283. }
  4284. dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "WaitCnt=%d First handshake reply word=%08x%s\n",
  4285. ioc->name, t, le32_to_cpu(*(u32 *)hs_reply),
  4286. failcnt ? " - MISSING DOORBELL HANDSHAKE!" : ""));
  4287. /*
  4288. * If no error (and IOC said MsgLength is > 0), piece together
  4289. * reply 16 bits at a time.
  4290. */
  4291. for (u16cnt=2; !failcnt && u16cnt < (2 * mptReply->MsgLength); u16cnt++) {
  4292. if ((t = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0)
  4293. failcnt++;
  4294. hword = le16_to_cpu(CHIPREG_READ32(&ioc->chip->Doorbell) & 0x0000FFFF);
  4295. /* don't overflow our IOC hs_reply[] buffer! */
  4296. if (u16cnt < ARRAY_SIZE(ioc->hs_reply))
  4297. hs_reply[u16cnt] = hword;
  4298. CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
  4299. }
  4300. if (!failcnt && (t = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0)
  4301. failcnt++;
  4302. CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
  4303. if (failcnt) {
  4304. printk(MYIOC_s_ERR_FMT "Handshake reply failure!\n",
  4305. ioc->name);
  4306. return -failcnt;
  4307. }
  4308. #if 0
  4309. else if (u16cnt != (2 * mptReply->MsgLength)) {
  4310. return -101;
  4311. }
  4312. else if ((mptReply->IOCStatus & MPI_IOCSTATUS_MASK) != MPI_IOCSTATUS_SUCCESS) {
  4313. return -102;
  4314. }
  4315. #endif
  4316. dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Got Handshake reply:\n", ioc->name));
  4317. DBG_DUMP_REPLY_FRAME(ioc, (u32 *)mptReply);
  4318. dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "WaitForDoorbell REPLY WaitCnt=%d (sz=%d)\n",
  4319. ioc->name, t, u16cnt/2));
  4320. return u16cnt/2;
  4321. }
  4322. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  4323. /**
  4324. * GetLanConfigPages - Fetch LANConfig pages.
  4325. * @ioc: Pointer to MPT_ADAPTER structure
  4326. *
  4327. * Return: 0 for success
  4328. * -ENOMEM if no memory available
  4329. * -EPERM if not allowed due to ISR context
  4330. * -EAGAIN if no msg frames currently available
  4331. * -EFAULT for non-successful reply or no reply (timeout)
  4332. */
  4333. static int
  4334. GetLanConfigPages(MPT_ADAPTER *ioc)
  4335. {
  4336. ConfigPageHeader_t hdr;
  4337. CONFIGPARMS cfg;
  4338. LANPage0_t *ppage0_alloc;
  4339. dma_addr_t page0_dma;
  4340. LANPage1_t *ppage1_alloc;
  4341. dma_addr_t page1_dma;
  4342. int rc = 0;
  4343. int data_sz;
  4344. int copy_sz;
  4345. /* Get LAN Page 0 header */
  4346. hdr.PageVersion = 0;
  4347. hdr.PageLength = 0;
  4348. hdr.PageNumber = 0;
  4349. hdr.PageType = MPI_CONFIG_PAGETYPE_LAN;
  4350. cfg.cfghdr.hdr = &hdr;
  4351. cfg.physAddr = -1;
  4352. cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
  4353. cfg.dir = 0;
  4354. cfg.pageAddr = 0;
  4355. cfg.timeout = 0;
  4356. if ((rc = mpt_config(ioc, &cfg)) != 0)
  4357. return rc;
  4358. if (hdr.PageLength > 0) {
  4359. data_sz = hdr.PageLength * 4;
  4360. ppage0_alloc = (LANPage0_t *) pci_alloc_consistent(ioc->pcidev, data_sz, &page0_dma);
  4361. rc = -ENOMEM;
  4362. if (ppage0_alloc) {
  4363. memset((u8 *)ppage0_alloc, 0, data_sz);
  4364. cfg.physAddr = page0_dma;
  4365. cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
  4366. if ((rc = mpt_config(ioc, &cfg)) == 0) {
  4367. /* save the data */
  4368. copy_sz = min_t(int, sizeof(LANPage0_t), data_sz);
  4369. memcpy(&ioc->lan_cnfg_page0, ppage0_alloc, copy_sz);
  4370. }
  4371. pci_free_consistent(ioc->pcidev, data_sz, (u8 *) ppage0_alloc, page0_dma);
  4372. /* FIXME!
  4373. * Normalize endianness of structure data,
  4374. * by byte-swapping all > 1 byte fields!
  4375. */
  4376. }
  4377. if (rc)
  4378. return rc;
  4379. }
  4380. /* Get LAN Page 1 header */
  4381. hdr.PageVersion = 0;
  4382. hdr.PageLength = 0;
  4383. hdr.PageNumber = 1;
  4384. hdr.PageType = MPI_CONFIG_PAGETYPE_LAN;
  4385. cfg.cfghdr.hdr = &hdr;
  4386. cfg.physAddr = -1;
  4387. cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
  4388. cfg.dir = 0;
  4389. cfg.pageAddr = 0;
  4390. if ((rc = mpt_config(ioc, &cfg)) != 0)
  4391. return rc;
  4392. if (hdr.PageLength == 0)
  4393. return 0;
  4394. data_sz = hdr.PageLength * 4;
  4395. rc = -ENOMEM;
  4396. ppage1_alloc = (LANPage1_t *) pci_alloc_consistent(ioc->pcidev, data_sz, &page1_dma);
  4397. if (ppage1_alloc) {
  4398. memset((u8 *)ppage1_alloc, 0, data_sz);
  4399. cfg.physAddr = page1_dma;
  4400. cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
  4401. if ((rc = mpt_config(ioc, &cfg)) == 0) {
  4402. /* save the data */
  4403. copy_sz = min_t(int, sizeof(LANPage1_t), data_sz);
  4404. memcpy(&ioc->lan_cnfg_page1, ppage1_alloc, copy_sz);
  4405. }
  4406. pci_free_consistent(ioc->pcidev, data_sz, (u8 *) ppage1_alloc, page1_dma);
  4407. /* FIXME!
  4408. * Normalize endianness of structure data,
  4409. * by byte-swapping all > 1 byte fields!
  4410. */
  4411. }
  4412. return rc;
  4413. }
  4414. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  4415. /**
  4416. * mptbase_sas_persist_operation - Perform operation on SAS Persistent Table
  4417. * @ioc: Pointer to MPT_ADAPTER structure
  4418. * @persist_opcode: see below
  4419. *
  4420. * =============================== ======================================
  4421. * MPI_SAS_OP_CLEAR_NOT_PRESENT Free all persist TargetID mappings for
  4422. * devices not currently present.
  4423. * MPI_SAS_OP_CLEAR_ALL_PERSISTENT Clear al persist TargetID mappings
  4424. * =============================== ======================================
  4425. *
  4426. * NOTE: Don't use not this function during interrupt time.
  4427. *
  4428. * Returns 0 for success, non-zero error
  4429. */
  4430. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  4431. int
  4432. mptbase_sas_persist_operation(MPT_ADAPTER *ioc, u8 persist_opcode)
  4433. {
  4434. SasIoUnitControlRequest_t *sasIoUnitCntrReq;
  4435. SasIoUnitControlReply_t *sasIoUnitCntrReply;
  4436. MPT_FRAME_HDR *mf = NULL;
  4437. MPIHeader_t *mpi_hdr;
  4438. int ret = 0;
  4439. unsigned long timeleft;
  4440. mutex_lock(&ioc->mptbase_cmds.mutex);
  4441. /* init the internal cmd struct */
  4442. memset(ioc->mptbase_cmds.reply, 0 , MPT_DEFAULT_FRAME_SIZE);
  4443. INITIALIZE_MGMT_STATUS(ioc->mptbase_cmds.status)
  4444. /* insure garbage is not sent to fw */
  4445. switch(persist_opcode) {
  4446. case MPI_SAS_OP_CLEAR_NOT_PRESENT:
  4447. case MPI_SAS_OP_CLEAR_ALL_PERSISTENT:
  4448. break;
  4449. default:
  4450. ret = -1;
  4451. goto out;
  4452. }
  4453. printk(KERN_DEBUG "%s: persist_opcode=%x\n",
  4454. __func__, persist_opcode);
  4455. /* Get a MF for this command.
  4456. */
  4457. if ((mf = mpt_get_msg_frame(mpt_base_index, ioc)) == NULL) {
  4458. printk(KERN_DEBUG "%s: no msg frames!\n", __func__);
  4459. ret = -1;
  4460. goto out;
  4461. }
  4462. mpi_hdr = (MPIHeader_t *) mf;
  4463. sasIoUnitCntrReq = (SasIoUnitControlRequest_t *)mf;
  4464. memset(sasIoUnitCntrReq,0,sizeof(SasIoUnitControlRequest_t));
  4465. sasIoUnitCntrReq->Function = MPI_FUNCTION_SAS_IO_UNIT_CONTROL;
  4466. sasIoUnitCntrReq->MsgContext = mpi_hdr->MsgContext;
  4467. sasIoUnitCntrReq->Operation = persist_opcode;
  4468. mpt_put_msg_frame(mpt_base_index, ioc, mf);
  4469. timeleft = wait_for_completion_timeout(&ioc->mptbase_cmds.done, 10*HZ);
  4470. if (!(ioc->mptbase_cmds.status & MPT_MGMT_STATUS_COMMAND_GOOD)) {
  4471. ret = -ETIME;
  4472. printk(KERN_DEBUG "%s: failed\n", __func__);
  4473. if (ioc->mptbase_cmds.status & MPT_MGMT_STATUS_DID_IOCRESET)
  4474. goto out;
  4475. if (!timeleft) {
  4476. printk(MYIOC_s_WARN_FMT
  4477. "Issuing Reset from %s!!, doorbell=0x%08x\n",
  4478. ioc->name, __func__, mpt_GetIocState(ioc, 0));
  4479. mpt_Soft_Hard_ResetHandler(ioc, CAN_SLEEP);
  4480. mpt_free_msg_frame(ioc, mf);
  4481. }
  4482. goto out;
  4483. }
  4484. if (!(ioc->mptbase_cmds.status & MPT_MGMT_STATUS_RF_VALID)) {
  4485. ret = -1;
  4486. goto out;
  4487. }
  4488. sasIoUnitCntrReply =
  4489. (SasIoUnitControlReply_t *)ioc->mptbase_cmds.reply;
  4490. if (le16_to_cpu(sasIoUnitCntrReply->IOCStatus) != MPI_IOCSTATUS_SUCCESS) {
  4491. printk(KERN_DEBUG "%s: IOCStatus=0x%X IOCLogInfo=0x%X\n",
  4492. __func__, sasIoUnitCntrReply->IOCStatus,
  4493. sasIoUnitCntrReply->IOCLogInfo);
  4494. printk(KERN_DEBUG "%s: failed\n", __func__);
  4495. ret = -1;
  4496. } else
  4497. printk(KERN_DEBUG "%s: success\n", __func__);
  4498. out:
  4499. CLEAR_MGMT_STATUS(ioc->mptbase_cmds.status)
  4500. mutex_unlock(&ioc->mptbase_cmds.mutex);
  4501. return ret;
  4502. }
  4503. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  4504. static void
  4505. mptbase_raid_process_event_data(MPT_ADAPTER *ioc,
  4506. MpiEventDataRaid_t * pRaidEventData)
  4507. {
  4508. int volume;
  4509. int reason;
  4510. int disk;
  4511. int status;
  4512. int flags;
  4513. int state;
  4514. volume = pRaidEventData->VolumeID;
  4515. reason = pRaidEventData->ReasonCode;
  4516. disk = pRaidEventData->PhysDiskNum;
  4517. status = le32_to_cpu(pRaidEventData->SettingsStatus);
  4518. flags = (status >> 0) & 0xff;
  4519. state = (status >> 8) & 0xff;
  4520. if (reason == MPI_EVENT_RAID_RC_DOMAIN_VAL_NEEDED) {
  4521. return;
  4522. }
  4523. if ((reason >= MPI_EVENT_RAID_RC_PHYSDISK_CREATED &&
  4524. reason <= MPI_EVENT_RAID_RC_PHYSDISK_STATUS_CHANGED) ||
  4525. (reason == MPI_EVENT_RAID_RC_SMART_DATA)) {
  4526. printk(MYIOC_s_INFO_FMT "RAID STATUS CHANGE for PhysDisk %d id=%d\n",
  4527. ioc->name, disk, volume);
  4528. } else {
  4529. printk(MYIOC_s_INFO_FMT "RAID STATUS CHANGE for VolumeID %d\n",
  4530. ioc->name, volume);
  4531. }
  4532. switch(reason) {
  4533. case MPI_EVENT_RAID_RC_VOLUME_CREATED:
  4534. printk(MYIOC_s_INFO_FMT " volume has been created\n",
  4535. ioc->name);
  4536. break;
  4537. case MPI_EVENT_RAID_RC_VOLUME_DELETED:
  4538. printk(MYIOC_s_INFO_FMT " volume has been deleted\n",
  4539. ioc->name);
  4540. break;
  4541. case MPI_EVENT_RAID_RC_VOLUME_SETTINGS_CHANGED:
  4542. printk(MYIOC_s_INFO_FMT " volume settings have been changed\n",
  4543. ioc->name);
  4544. break;
  4545. case MPI_EVENT_RAID_RC_VOLUME_STATUS_CHANGED:
  4546. printk(MYIOC_s_INFO_FMT " volume is now %s%s%s%s\n",
  4547. ioc->name,
  4548. state == MPI_RAIDVOL0_STATUS_STATE_OPTIMAL
  4549. ? "optimal"
  4550. : state == MPI_RAIDVOL0_STATUS_STATE_DEGRADED
  4551. ? "degraded"
  4552. : state == MPI_RAIDVOL0_STATUS_STATE_FAILED
  4553. ? "failed"
  4554. : "state unknown",
  4555. flags & MPI_RAIDVOL0_STATUS_FLAG_ENABLED
  4556. ? ", enabled" : "",
  4557. flags & MPI_RAIDVOL0_STATUS_FLAG_QUIESCED
  4558. ? ", quiesced" : "",
  4559. flags & MPI_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS
  4560. ? ", resync in progress" : "" );
  4561. break;
  4562. case MPI_EVENT_RAID_RC_VOLUME_PHYSDISK_CHANGED:
  4563. printk(MYIOC_s_INFO_FMT " volume membership of PhysDisk %d has changed\n",
  4564. ioc->name, disk);
  4565. break;
  4566. case MPI_EVENT_RAID_RC_PHYSDISK_CREATED:
  4567. printk(MYIOC_s_INFO_FMT " PhysDisk has been created\n",
  4568. ioc->name);
  4569. break;
  4570. case MPI_EVENT_RAID_RC_PHYSDISK_DELETED:
  4571. printk(MYIOC_s_INFO_FMT " PhysDisk has been deleted\n",
  4572. ioc->name);
  4573. break;
  4574. case MPI_EVENT_RAID_RC_PHYSDISK_SETTINGS_CHANGED:
  4575. printk(MYIOC_s_INFO_FMT " PhysDisk settings have been changed\n",
  4576. ioc->name);
  4577. break;
  4578. case MPI_EVENT_RAID_RC_PHYSDISK_STATUS_CHANGED:
  4579. printk(MYIOC_s_INFO_FMT " PhysDisk is now %s%s%s\n",
  4580. ioc->name,
  4581. state == MPI_PHYSDISK0_STATUS_ONLINE
  4582. ? "online"
  4583. : state == MPI_PHYSDISK0_STATUS_MISSING
  4584. ? "missing"
  4585. : state == MPI_PHYSDISK0_STATUS_NOT_COMPATIBLE
  4586. ? "not compatible"
  4587. : state == MPI_PHYSDISK0_STATUS_FAILED
  4588. ? "failed"
  4589. : state == MPI_PHYSDISK0_STATUS_INITIALIZING
  4590. ? "initializing"
  4591. : state == MPI_PHYSDISK0_STATUS_OFFLINE_REQUESTED
  4592. ? "offline requested"
  4593. : state == MPI_PHYSDISK0_STATUS_FAILED_REQUESTED
  4594. ? "failed requested"
  4595. : state == MPI_PHYSDISK0_STATUS_OTHER_OFFLINE
  4596. ? "offline"
  4597. : "state unknown",
  4598. flags & MPI_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC
  4599. ? ", out of sync" : "",
  4600. flags & MPI_PHYSDISK0_STATUS_FLAG_QUIESCED
  4601. ? ", quiesced" : "" );
  4602. break;
  4603. case MPI_EVENT_RAID_RC_DOMAIN_VAL_NEEDED:
  4604. printk(MYIOC_s_INFO_FMT " Domain Validation needed for PhysDisk %d\n",
  4605. ioc->name, disk);
  4606. break;
  4607. case MPI_EVENT_RAID_RC_SMART_DATA:
  4608. printk(MYIOC_s_INFO_FMT " SMART data received, ASC/ASCQ = %02xh/%02xh\n",
  4609. ioc->name, pRaidEventData->ASC, pRaidEventData->ASCQ);
  4610. break;
  4611. case MPI_EVENT_RAID_RC_REPLACE_ACTION_STARTED:
  4612. printk(MYIOC_s_INFO_FMT " replacement of PhysDisk %d has started\n",
  4613. ioc->name, disk);
  4614. break;
  4615. }
  4616. }
  4617. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  4618. /**
  4619. * GetIoUnitPage2 - Retrieve BIOS version and boot order information.
  4620. * @ioc: Pointer to MPT_ADAPTER structure
  4621. *
  4622. * Returns: 0 for success
  4623. * -ENOMEM if no memory available
  4624. * -EPERM if not allowed due to ISR context
  4625. * -EAGAIN if no msg frames currently available
  4626. * -EFAULT for non-successful reply or no reply (timeout)
  4627. */
  4628. static int
  4629. GetIoUnitPage2(MPT_ADAPTER *ioc)
  4630. {
  4631. ConfigPageHeader_t hdr;
  4632. CONFIGPARMS cfg;
  4633. IOUnitPage2_t *ppage_alloc;
  4634. dma_addr_t page_dma;
  4635. int data_sz;
  4636. int rc;
  4637. /* Get the page header */
  4638. hdr.PageVersion = 0;
  4639. hdr.PageLength = 0;
  4640. hdr.PageNumber = 2;
  4641. hdr.PageType = MPI_CONFIG_PAGETYPE_IO_UNIT;
  4642. cfg.cfghdr.hdr = &hdr;
  4643. cfg.physAddr = -1;
  4644. cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
  4645. cfg.dir = 0;
  4646. cfg.pageAddr = 0;
  4647. cfg.timeout = 0;
  4648. if ((rc = mpt_config(ioc, &cfg)) != 0)
  4649. return rc;
  4650. if (hdr.PageLength == 0)
  4651. return 0;
  4652. /* Read the config page */
  4653. data_sz = hdr.PageLength * 4;
  4654. rc = -ENOMEM;
  4655. ppage_alloc = (IOUnitPage2_t *) pci_alloc_consistent(ioc->pcidev, data_sz, &page_dma);
  4656. if (ppage_alloc) {
  4657. memset((u8 *)ppage_alloc, 0, data_sz);
  4658. cfg.physAddr = page_dma;
  4659. cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
  4660. /* If Good, save data */
  4661. if ((rc = mpt_config(ioc, &cfg)) == 0)
  4662. ioc->biosVersion = le32_to_cpu(ppage_alloc->BiosVersion);
  4663. pci_free_consistent(ioc->pcidev, data_sz, (u8 *) ppage_alloc, page_dma);
  4664. }
  4665. return rc;
  4666. }
  4667. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  4668. /**
  4669. * mpt_GetScsiPortSettings - read SCSI Port Page 0 and 2
  4670. * @ioc: Pointer to a Adapter Strucutre
  4671. * @portnum: IOC port number
  4672. *
  4673. * Return: -EFAULT if read of config page header fails
  4674. * or if no nvram
  4675. * If read of SCSI Port Page 0 fails,
  4676. * NVRAM = MPT_HOST_NVRAM_INVALID (0xFFFFFFFF)
  4677. * Adapter settings: async, narrow
  4678. * Return 1
  4679. * If read of SCSI Port Page 2 fails,
  4680. * Adapter settings valid
  4681. * NVRAM = MPT_HOST_NVRAM_INVALID (0xFFFFFFFF)
  4682. * Return 1
  4683. * Else
  4684. * Both valid
  4685. * Return 0
  4686. * CHECK - what type of locking mechanisms should be used????
  4687. */
  4688. static int
  4689. mpt_GetScsiPortSettings(MPT_ADAPTER *ioc, int portnum)
  4690. {
  4691. u8 *pbuf;
  4692. dma_addr_t buf_dma;
  4693. CONFIGPARMS cfg;
  4694. ConfigPageHeader_t header;
  4695. int ii;
  4696. int data, rc = 0;
  4697. /* Allocate memory
  4698. */
  4699. if (!ioc->spi_data.nvram) {
  4700. int sz;
  4701. u8 *mem;
  4702. sz = MPT_MAX_SCSI_DEVICES * sizeof(int);
  4703. mem = kmalloc(sz, GFP_ATOMIC);
  4704. if (mem == NULL)
  4705. return -EFAULT;
  4706. ioc->spi_data.nvram = (int *) mem;
  4707. dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "SCSI device NVRAM settings @ %p, sz=%d\n",
  4708. ioc->name, ioc->spi_data.nvram, sz));
  4709. }
  4710. /* Invalidate NVRAM information
  4711. */
  4712. for (ii=0; ii < MPT_MAX_SCSI_DEVICES; ii++) {
  4713. ioc->spi_data.nvram[ii] = MPT_HOST_NVRAM_INVALID;
  4714. }
  4715. /* Read SPP0 header, allocate memory, then read page.
  4716. */
  4717. header.PageVersion = 0;
  4718. header.PageLength = 0;
  4719. header.PageNumber = 0;
  4720. header.PageType = MPI_CONFIG_PAGETYPE_SCSI_PORT;
  4721. cfg.cfghdr.hdr = &header;
  4722. cfg.physAddr = -1;
  4723. cfg.pageAddr = portnum;
  4724. cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
  4725. cfg.dir = 0;
  4726. cfg.timeout = 0; /* use default */
  4727. if (mpt_config(ioc, &cfg) != 0)
  4728. return -EFAULT;
  4729. if (header.PageLength > 0) {
  4730. pbuf = pci_alloc_consistent(ioc->pcidev, header.PageLength * 4, &buf_dma);
  4731. if (pbuf) {
  4732. cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
  4733. cfg.physAddr = buf_dma;
  4734. if (mpt_config(ioc, &cfg) != 0) {
  4735. ioc->spi_data.maxBusWidth = MPT_NARROW;
  4736. ioc->spi_data.maxSyncOffset = 0;
  4737. ioc->spi_data.minSyncFactor = MPT_ASYNC;
  4738. ioc->spi_data.busType = MPT_HOST_BUS_UNKNOWN;
  4739. rc = 1;
  4740. ddvprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  4741. "Unable to read PortPage0 minSyncFactor=%x\n",
  4742. ioc->name, ioc->spi_data.minSyncFactor));
  4743. } else {
  4744. /* Save the Port Page 0 data
  4745. */
  4746. SCSIPortPage0_t *pPP0 = (SCSIPortPage0_t *) pbuf;
  4747. pPP0->Capabilities = le32_to_cpu(pPP0->Capabilities);
  4748. pPP0->PhysicalInterface = le32_to_cpu(pPP0->PhysicalInterface);
  4749. if ( (pPP0->Capabilities & MPI_SCSIPORTPAGE0_CAP_QAS) == 0 ) {
  4750. ioc->spi_data.noQas |= MPT_TARGET_NO_NEGO_QAS;
  4751. ddvprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  4752. "noQas due to Capabilities=%x\n",
  4753. ioc->name, pPP0->Capabilities));
  4754. }
  4755. ioc->spi_data.maxBusWidth = pPP0->Capabilities & MPI_SCSIPORTPAGE0_CAP_WIDE ? 1 : 0;
  4756. data = pPP0->Capabilities & MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK;
  4757. if (data) {
  4758. ioc->spi_data.maxSyncOffset = (u8) (data >> 16);
  4759. data = pPP0->Capabilities & MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK;
  4760. ioc->spi_data.minSyncFactor = (u8) (data >> 8);
  4761. ddvprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  4762. "PortPage0 minSyncFactor=%x\n",
  4763. ioc->name, ioc->spi_data.minSyncFactor));
  4764. } else {
  4765. ioc->spi_data.maxSyncOffset = 0;
  4766. ioc->spi_data.minSyncFactor = MPT_ASYNC;
  4767. }
  4768. ioc->spi_data.busType = pPP0->PhysicalInterface & MPI_SCSIPORTPAGE0_PHY_SIGNAL_TYPE_MASK;
  4769. /* Update the minSyncFactor based on bus type.
  4770. */
  4771. if ((ioc->spi_data.busType == MPI_SCSIPORTPAGE0_PHY_SIGNAL_HVD) ||
  4772. (ioc->spi_data.busType == MPI_SCSIPORTPAGE0_PHY_SIGNAL_SE)) {
  4773. if (ioc->spi_data.minSyncFactor < MPT_ULTRA) {
  4774. ioc->spi_data.minSyncFactor = MPT_ULTRA;
  4775. ddvprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  4776. "HVD or SE detected, minSyncFactor=%x\n",
  4777. ioc->name, ioc->spi_data.minSyncFactor));
  4778. }
  4779. }
  4780. }
  4781. if (pbuf) {
  4782. pci_free_consistent(ioc->pcidev, header.PageLength * 4, pbuf, buf_dma);
  4783. }
  4784. }
  4785. }
  4786. /* SCSI Port Page 2 - Read the header then the page.
  4787. */
  4788. header.PageVersion = 0;
  4789. header.PageLength = 0;
  4790. header.PageNumber = 2;
  4791. header.PageType = MPI_CONFIG_PAGETYPE_SCSI_PORT;
  4792. cfg.cfghdr.hdr = &header;
  4793. cfg.physAddr = -1;
  4794. cfg.pageAddr = portnum;
  4795. cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
  4796. cfg.dir = 0;
  4797. if (mpt_config(ioc, &cfg) != 0)
  4798. return -EFAULT;
  4799. if (header.PageLength > 0) {
  4800. /* Allocate memory and read SCSI Port Page 2
  4801. */
  4802. pbuf = pci_alloc_consistent(ioc->pcidev, header.PageLength * 4, &buf_dma);
  4803. if (pbuf) {
  4804. cfg.action = MPI_CONFIG_ACTION_PAGE_READ_NVRAM;
  4805. cfg.physAddr = buf_dma;
  4806. if (mpt_config(ioc, &cfg) != 0) {
  4807. /* Nvram data is left with INVALID mark
  4808. */
  4809. rc = 1;
  4810. } else if (ioc->pcidev->vendor == PCI_VENDOR_ID_ATTO) {
  4811. /* This is an ATTO adapter, read Page2 accordingly
  4812. */
  4813. ATTO_SCSIPortPage2_t *pPP2 = (ATTO_SCSIPortPage2_t *) pbuf;
  4814. ATTODeviceInfo_t *pdevice = NULL;
  4815. u16 ATTOFlags;
  4816. /* Save the Port Page 2 data
  4817. * (reformat into a 32bit quantity)
  4818. */
  4819. for (ii=0; ii < MPT_MAX_SCSI_DEVICES; ii++) {
  4820. pdevice = &pPP2->DeviceSettings[ii];
  4821. ATTOFlags = le16_to_cpu(pdevice->ATTOFlags);
  4822. data = 0;
  4823. /* Translate ATTO device flags to LSI format
  4824. */
  4825. if (ATTOFlags & ATTOFLAG_DISC)
  4826. data |= (MPI_SCSIPORTPAGE2_DEVICE_DISCONNECT_ENABLE);
  4827. if (ATTOFlags & ATTOFLAG_ID_ENB)
  4828. data |= (MPI_SCSIPORTPAGE2_DEVICE_ID_SCAN_ENABLE);
  4829. if (ATTOFlags & ATTOFLAG_LUN_ENB)
  4830. data |= (MPI_SCSIPORTPAGE2_DEVICE_LUN_SCAN_ENABLE);
  4831. if (ATTOFlags & ATTOFLAG_TAGGED)
  4832. data |= (MPI_SCSIPORTPAGE2_DEVICE_TAG_QUEUE_ENABLE);
  4833. if (!(ATTOFlags & ATTOFLAG_WIDE_ENB))
  4834. data |= (MPI_SCSIPORTPAGE2_DEVICE_WIDE_DISABLE);
  4835. data = (data << 16) | (pdevice->Period << 8) | 10;
  4836. ioc->spi_data.nvram[ii] = data;
  4837. }
  4838. } else {
  4839. SCSIPortPage2_t *pPP2 = (SCSIPortPage2_t *) pbuf;
  4840. MpiDeviceInfo_t *pdevice = NULL;
  4841. /*
  4842. * Save "Set to Avoid SCSI Bus Resets" flag
  4843. */
  4844. ioc->spi_data.bus_reset =
  4845. (le32_to_cpu(pPP2->PortFlags) &
  4846. MPI_SCSIPORTPAGE2_PORT_FLAGS_AVOID_SCSI_RESET) ?
  4847. 0 : 1 ;
  4848. /* Save the Port Page 2 data
  4849. * (reformat into a 32bit quantity)
  4850. */
  4851. data = le32_to_cpu(pPP2->PortFlags) & MPI_SCSIPORTPAGE2_PORT_FLAGS_DV_MASK;
  4852. ioc->spi_data.PortFlags = data;
  4853. for (ii=0; ii < MPT_MAX_SCSI_DEVICES; ii++) {
  4854. pdevice = &pPP2->DeviceSettings[ii];
  4855. data = (le16_to_cpu(pdevice->DeviceFlags) << 16) |
  4856. (pdevice->SyncFactor << 8) | pdevice->Timeout;
  4857. ioc->spi_data.nvram[ii] = data;
  4858. }
  4859. }
  4860. pci_free_consistent(ioc->pcidev, header.PageLength * 4, pbuf, buf_dma);
  4861. }
  4862. }
  4863. /* Update Adapter limits with those from NVRAM
  4864. * Comment: Don't need to do this. Target performance
  4865. * parameters will never exceed the adapters limits.
  4866. */
  4867. return rc;
  4868. }
  4869. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  4870. /**
  4871. * mpt_readScsiDevicePageHeaders - save version and length of SDP1
  4872. * @ioc: Pointer to a Adapter Strucutre
  4873. * @portnum: IOC port number
  4874. *
  4875. * Return: -EFAULT if read of config page header fails
  4876. * or 0 if success.
  4877. */
  4878. static int
  4879. mpt_readScsiDevicePageHeaders(MPT_ADAPTER *ioc, int portnum)
  4880. {
  4881. CONFIGPARMS cfg;
  4882. ConfigPageHeader_t header;
  4883. /* Read the SCSI Device Page 1 header
  4884. */
  4885. header.PageVersion = 0;
  4886. header.PageLength = 0;
  4887. header.PageNumber = 1;
  4888. header.PageType = MPI_CONFIG_PAGETYPE_SCSI_DEVICE;
  4889. cfg.cfghdr.hdr = &header;
  4890. cfg.physAddr = -1;
  4891. cfg.pageAddr = portnum;
  4892. cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
  4893. cfg.dir = 0;
  4894. cfg.timeout = 0;
  4895. if (mpt_config(ioc, &cfg) != 0)
  4896. return -EFAULT;
  4897. ioc->spi_data.sdp1version = cfg.cfghdr.hdr->PageVersion;
  4898. ioc->spi_data.sdp1length = cfg.cfghdr.hdr->PageLength;
  4899. header.PageVersion = 0;
  4900. header.PageLength = 0;
  4901. header.PageNumber = 0;
  4902. header.PageType = MPI_CONFIG_PAGETYPE_SCSI_DEVICE;
  4903. if (mpt_config(ioc, &cfg) != 0)
  4904. return -EFAULT;
  4905. ioc->spi_data.sdp0version = cfg.cfghdr.hdr->PageVersion;
  4906. ioc->spi_data.sdp0length = cfg.cfghdr.hdr->PageLength;
  4907. dcprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Headers: 0: version %d length %d\n",
  4908. ioc->name, ioc->spi_data.sdp0version, ioc->spi_data.sdp0length));
  4909. dcprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Headers: 1: version %d length %d\n",
  4910. ioc->name, ioc->spi_data.sdp1version, ioc->spi_data.sdp1length));
  4911. return 0;
  4912. }
  4913. /**
  4914. * mpt_inactive_raid_list_free - This clears this link list.
  4915. * @ioc : pointer to per adapter structure
  4916. **/
  4917. static void
  4918. mpt_inactive_raid_list_free(MPT_ADAPTER *ioc)
  4919. {
  4920. struct inactive_raid_component_info *component_info, *pNext;
  4921. if (list_empty(&ioc->raid_data.inactive_list))
  4922. return;
  4923. mutex_lock(&ioc->raid_data.inactive_list_mutex);
  4924. list_for_each_entry_safe(component_info, pNext,
  4925. &ioc->raid_data.inactive_list, list) {
  4926. list_del(&component_info->list);
  4927. kfree(component_info);
  4928. }
  4929. mutex_unlock(&ioc->raid_data.inactive_list_mutex);
  4930. }
  4931. /**
  4932. * mpt_inactive_raid_volumes - sets up link list of phy_disk_nums for devices belonging in an inactive volume
  4933. *
  4934. * @ioc : pointer to per adapter structure
  4935. * @channel : volume channel
  4936. * @id : volume target id
  4937. **/
  4938. static void
  4939. mpt_inactive_raid_volumes(MPT_ADAPTER *ioc, u8 channel, u8 id)
  4940. {
  4941. CONFIGPARMS cfg;
  4942. ConfigPageHeader_t hdr;
  4943. dma_addr_t dma_handle;
  4944. pRaidVolumePage0_t buffer = NULL;
  4945. int i;
  4946. RaidPhysDiskPage0_t phys_disk;
  4947. struct inactive_raid_component_info *component_info;
  4948. int handle_inactive_volumes;
  4949. memset(&cfg, 0 , sizeof(CONFIGPARMS));
  4950. memset(&hdr, 0 , sizeof(ConfigPageHeader_t));
  4951. hdr.PageType = MPI_CONFIG_PAGETYPE_RAID_VOLUME;
  4952. cfg.pageAddr = (channel << 8) + id;
  4953. cfg.cfghdr.hdr = &hdr;
  4954. cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
  4955. if (mpt_config(ioc, &cfg) != 0)
  4956. goto out;
  4957. if (!hdr.PageLength)
  4958. goto out;
  4959. buffer = pci_alloc_consistent(ioc->pcidev, hdr.PageLength * 4,
  4960. &dma_handle);
  4961. if (!buffer)
  4962. goto out;
  4963. cfg.physAddr = dma_handle;
  4964. cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
  4965. if (mpt_config(ioc, &cfg) != 0)
  4966. goto out;
  4967. if (!buffer->NumPhysDisks)
  4968. goto out;
  4969. handle_inactive_volumes =
  4970. (buffer->VolumeStatus.Flags & MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE ||
  4971. (buffer->VolumeStatus.Flags & MPI_RAIDVOL0_STATUS_FLAG_ENABLED) == 0 ||
  4972. buffer->VolumeStatus.State == MPI_RAIDVOL0_STATUS_STATE_FAILED ||
  4973. buffer->VolumeStatus.State == MPI_RAIDVOL0_STATUS_STATE_MISSING) ? 1 : 0;
  4974. if (!handle_inactive_volumes)
  4975. goto out;
  4976. mutex_lock(&ioc->raid_data.inactive_list_mutex);
  4977. for (i = 0; i < buffer->NumPhysDisks; i++) {
  4978. if(mpt_raid_phys_disk_pg0(ioc,
  4979. buffer->PhysDisk[i].PhysDiskNum, &phys_disk) != 0)
  4980. continue;
  4981. if ((component_info = kmalloc(sizeof (*component_info),
  4982. GFP_KERNEL)) == NULL)
  4983. continue;
  4984. component_info->volumeID = id;
  4985. component_info->volumeBus = channel;
  4986. component_info->d.PhysDiskNum = phys_disk.PhysDiskNum;
  4987. component_info->d.PhysDiskBus = phys_disk.PhysDiskBus;
  4988. component_info->d.PhysDiskID = phys_disk.PhysDiskID;
  4989. component_info->d.PhysDiskIOC = phys_disk.PhysDiskIOC;
  4990. list_add_tail(&component_info->list,
  4991. &ioc->raid_data.inactive_list);
  4992. }
  4993. mutex_unlock(&ioc->raid_data.inactive_list_mutex);
  4994. out:
  4995. if (buffer)
  4996. pci_free_consistent(ioc->pcidev, hdr.PageLength * 4, buffer,
  4997. dma_handle);
  4998. }
  4999. /**
  5000. * mpt_raid_phys_disk_pg0 - returns phys disk page zero
  5001. * @ioc: Pointer to a Adapter Structure
  5002. * @phys_disk_num: io unit unique phys disk num generated by the ioc
  5003. * @phys_disk: requested payload data returned
  5004. *
  5005. * Return:
  5006. * 0 on success
  5007. * -EFAULT if read of config page header fails or data pointer not NULL
  5008. * -ENOMEM if pci_alloc failed
  5009. **/
  5010. int
  5011. mpt_raid_phys_disk_pg0(MPT_ADAPTER *ioc, u8 phys_disk_num,
  5012. RaidPhysDiskPage0_t *phys_disk)
  5013. {
  5014. CONFIGPARMS cfg;
  5015. ConfigPageHeader_t hdr;
  5016. dma_addr_t dma_handle;
  5017. pRaidPhysDiskPage0_t buffer = NULL;
  5018. int rc;
  5019. memset(&cfg, 0 , sizeof(CONFIGPARMS));
  5020. memset(&hdr, 0 , sizeof(ConfigPageHeader_t));
  5021. memset(phys_disk, 0, sizeof(RaidPhysDiskPage0_t));
  5022. hdr.PageVersion = MPI_RAIDPHYSDISKPAGE0_PAGEVERSION;
  5023. hdr.PageType = MPI_CONFIG_PAGETYPE_RAID_PHYSDISK;
  5024. cfg.cfghdr.hdr = &hdr;
  5025. cfg.physAddr = -1;
  5026. cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
  5027. if (mpt_config(ioc, &cfg) != 0) {
  5028. rc = -EFAULT;
  5029. goto out;
  5030. }
  5031. if (!hdr.PageLength) {
  5032. rc = -EFAULT;
  5033. goto out;
  5034. }
  5035. buffer = pci_alloc_consistent(ioc->pcidev, hdr.PageLength * 4,
  5036. &dma_handle);
  5037. if (!buffer) {
  5038. rc = -ENOMEM;
  5039. goto out;
  5040. }
  5041. cfg.physAddr = dma_handle;
  5042. cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
  5043. cfg.pageAddr = phys_disk_num;
  5044. if (mpt_config(ioc, &cfg) != 0) {
  5045. rc = -EFAULT;
  5046. goto out;
  5047. }
  5048. rc = 0;
  5049. memcpy(phys_disk, buffer, sizeof(*buffer));
  5050. phys_disk->MaxLBA = le32_to_cpu(buffer->MaxLBA);
  5051. out:
  5052. if (buffer)
  5053. pci_free_consistent(ioc->pcidev, hdr.PageLength * 4, buffer,
  5054. dma_handle);
  5055. return rc;
  5056. }
  5057. /**
  5058. * mpt_raid_phys_disk_get_num_paths - returns number paths associated to this phys_num
  5059. * @ioc: Pointer to a Adapter Structure
  5060. * @phys_disk_num: io unit unique phys disk num generated by the ioc
  5061. *
  5062. * Return:
  5063. * returns number paths
  5064. **/
  5065. int
  5066. mpt_raid_phys_disk_get_num_paths(MPT_ADAPTER *ioc, u8 phys_disk_num)
  5067. {
  5068. CONFIGPARMS cfg;
  5069. ConfigPageHeader_t hdr;
  5070. dma_addr_t dma_handle;
  5071. pRaidPhysDiskPage1_t buffer = NULL;
  5072. int rc;
  5073. memset(&cfg, 0 , sizeof(CONFIGPARMS));
  5074. memset(&hdr, 0 , sizeof(ConfigPageHeader_t));
  5075. hdr.PageVersion = MPI_RAIDPHYSDISKPAGE1_PAGEVERSION;
  5076. hdr.PageType = MPI_CONFIG_PAGETYPE_RAID_PHYSDISK;
  5077. hdr.PageNumber = 1;
  5078. cfg.cfghdr.hdr = &hdr;
  5079. cfg.physAddr = -1;
  5080. cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
  5081. if (mpt_config(ioc, &cfg) != 0) {
  5082. rc = 0;
  5083. goto out;
  5084. }
  5085. if (!hdr.PageLength) {
  5086. rc = 0;
  5087. goto out;
  5088. }
  5089. buffer = pci_alloc_consistent(ioc->pcidev, hdr.PageLength * 4,
  5090. &dma_handle);
  5091. if (!buffer) {
  5092. rc = 0;
  5093. goto out;
  5094. }
  5095. cfg.physAddr = dma_handle;
  5096. cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
  5097. cfg.pageAddr = phys_disk_num;
  5098. if (mpt_config(ioc, &cfg) != 0) {
  5099. rc = 0;
  5100. goto out;
  5101. }
  5102. rc = buffer->NumPhysDiskPaths;
  5103. out:
  5104. if (buffer)
  5105. pci_free_consistent(ioc->pcidev, hdr.PageLength * 4, buffer,
  5106. dma_handle);
  5107. return rc;
  5108. }
  5109. EXPORT_SYMBOL(mpt_raid_phys_disk_get_num_paths);
  5110. /**
  5111. * mpt_raid_phys_disk_pg1 - returns phys disk page 1
  5112. * @ioc: Pointer to a Adapter Structure
  5113. * @phys_disk_num: io unit unique phys disk num generated by the ioc
  5114. * @phys_disk: requested payload data returned
  5115. *
  5116. * Return:
  5117. * 0 on success
  5118. * -EFAULT if read of config page header fails or data pointer not NULL
  5119. * -ENOMEM if pci_alloc failed
  5120. **/
  5121. int
  5122. mpt_raid_phys_disk_pg1(MPT_ADAPTER *ioc, u8 phys_disk_num,
  5123. RaidPhysDiskPage1_t *phys_disk)
  5124. {
  5125. CONFIGPARMS cfg;
  5126. ConfigPageHeader_t hdr;
  5127. dma_addr_t dma_handle;
  5128. pRaidPhysDiskPage1_t buffer = NULL;
  5129. int rc;
  5130. int i;
  5131. __le64 sas_address;
  5132. memset(&cfg, 0 , sizeof(CONFIGPARMS));
  5133. memset(&hdr, 0 , sizeof(ConfigPageHeader_t));
  5134. rc = 0;
  5135. hdr.PageVersion = MPI_RAIDPHYSDISKPAGE1_PAGEVERSION;
  5136. hdr.PageType = MPI_CONFIG_PAGETYPE_RAID_PHYSDISK;
  5137. hdr.PageNumber = 1;
  5138. cfg.cfghdr.hdr = &hdr;
  5139. cfg.physAddr = -1;
  5140. cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
  5141. if (mpt_config(ioc, &cfg) != 0) {
  5142. rc = -EFAULT;
  5143. goto out;
  5144. }
  5145. if (!hdr.PageLength) {
  5146. rc = -EFAULT;
  5147. goto out;
  5148. }
  5149. buffer = pci_alloc_consistent(ioc->pcidev, hdr.PageLength * 4,
  5150. &dma_handle);
  5151. if (!buffer) {
  5152. rc = -ENOMEM;
  5153. goto out;
  5154. }
  5155. cfg.physAddr = dma_handle;
  5156. cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
  5157. cfg.pageAddr = phys_disk_num;
  5158. if (mpt_config(ioc, &cfg) != 0) {
  5159. rc = -EFAULT;
  5160. goto out;
  5161. }
  5162. phys_disk->NumPhysDiskPaths = buffer->NumPhysDiskPaths;
  5163. phys_disk->PhysDiskNum = phys_disk_num;
  5164. for (i = 0; i < phys_disk->NumPhysDiskPaths; i++) {
  5165. phys_disk->Path[i].PhysDiskID = buffer->Path[i].PhysDiskID;
  5166. phys_disk->Path[i].PhysDiskBus = buffer->Path[i].PhysDiskBus;
  5167. phys_disk->Path[i].OwnerIdentifier =
  5168. buffer->Path[i].OwnerIdentifier;
  5169. phys_disk->Path[i].Flags = le16_to_cpu(buffer->Path[i].Flags);
  5170. memcpy(&sas_address, &buffer->Path[i].WWID, sizeof(__le64));
  5171. sas_address = le64_to_cpu(sas_address);
  5172. memcpy(&phys_disk->Path[i].WWID, &sas_address, sizeof(__le64));
  5173. memcpy(&sas_address,
  5174. &buffer->Path[i].OwnerWWID, sizeof(__le64));
  5175. sas_address = le64_to_cpu(sas_address);
  5176. memcpy(&phys_disk->Path[i].OwnerWWID,
  5177. &sas_address, sizeof(__le64));
  5178. }
  5179. out:
  5180. if (buffer)
  5181. pci_free_consistent(ioc->pcidev, hdr.PageLength * 4, buffer,
  5182. dma_handle);
  5183. return rc;
  5184. }
  5185. EXPORT_SYMBOL(mpt_raid_phys_disk_pg1);
  5186. /**
  5187. * mpt_findImVolumes - Identify IDs of hidden disks and RAID Volumes
  5188. * @ioc: Pointer to a Adapter Strucutre
  5189. *
  5190. * Return:
  5191. * 0 on success
  5192. * -EFAULT if read of config page header fails or data pointer not NULL
  5193. * -ENOMEM if pci_alloc failed
  5194. **/
  5195. int
  5196. mpt_findImVolumes(MPT_ADAPTER *ioc)
  5197. {
  5198. IOCPage2_t *pIoc2;
  5199. u8 *mem;
  5200. dma_addr_t ioc2_dma;
  5201. CONFIGPARMS cfg;
  5202. ConfigPageHeader_t header;
  5203. int rc = 0;
  5204. int iocpage2sz;
  5205. int i;
  5206. if (!ioc->ir_firmware)
  5207. return 0;
  5208. /* Free the old page
  5209. */
  5210. kfree(ioc->raid_data.pIocPg2);
  5211. ioc->raid_data.pIocPg2 = NULL;
  5212. mpt_inactive_raid_list_free(ioc);
  5213. /* Read IOCP2 header then the page.
  5214. */
  5215. header.PageVersion = 0;
  5216. header.PageLength = 0;
  5217. header.PageNumber = 2;
  5218. header.PageType = MPI_CONFIG_PAGETYPE_IOC;
  5219. cfg.cfghdr.hdr = &header;
  5220. cfg.physAddr = -1;
  5221. cfg.pageAddr = 0;
  5222. cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
  5223. cfg.dir = 0;
  5224. cfg.timeout = 0;
  5225. if (mpt_config(ioc, &cfg) != 0)
  5226. return -EFAULT;
  5227. if (header.PageLength == 0)
  5228. return -EFAULT;
  5229. iocpage2sz = header.PageLength * 4;
  5230. pIoc2 = pci_alloc_consistent(ioc->pcidev, iocpage2sz, &ioc2_dma);
  5231. if (!pIoc2)
  5232. return -ENOMEM;
  5233. cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
  5234. cfg.physAddr = ioc2_dma;
  5235. if (mpt_config(ioc, &cfg) != 0)
  5236. goto out;
  5237. mem = kmemdup(pIoc2, iocpage2sz, GFP_KERNEL);
  5238. if (!mem) {
  5239. rc = -ENOMEM;
  5240. goto out;
  5241. }
  5242. ioc->raid_data.pIocPg2 = (IOCPage2_t *) mem;
  5243. mpt_read_ioc_pg_3(ioc);
  5244. for (i = 0; i < pIoc2->NumActiveVolumes ; i++)
  5245. mpt_inactive_raid_volumes(ioc,
  5246. pIoc2->RaidVolume[i].VolumeBus,
  5247. pIoc2->RaidVolume[i].VolumeID);
  5248. out:
  5249. pci_free_consistent(ioc->pcidev, iocpage2sz, pIoc2, ioc2_dma);
  5250. return rc;
  5251. }
  5252. static int
  5253. mpt_read_ioc_pg_3(MPT_ADAPTER *ioc)
  5254. {
  5255. IOCPage3_t *pIoc3;
  5256. u8 *mem;
  5257. CONFIGPARMS cfg;
  5258. ConfigPageHeader_t header;
  5259. dma_addr_t ioc3_dma;
  5260. int iocpage3sz = 0;
  5261. /* Free the old page
  5262. */
  5263. kfree(ioc->raid_data.pIocPg3);
  5264. ioc->raid_data.pIocPg3 = NULL;
  5265. /* There is at least one physical disk.
  5266. * Read and save IOC Page 3
  5267. */
  5268. header.PageVersion = 0;
  5269. header.PageLength = 0;
  5270. header.PageNumber = 3;
  5271. header.PageType = MPI_CONFIG_PAGETYPE_IOC;
  5272. cfg.cfghdr.hdr = &header;
  5273. cfg.physAddr = -1;
  5274. cfg.pageAddr = 0;
  5275. cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
  5276. cfg.dir = 0;
  5277. cfg.timeout = 0;
  5278. if (mpt_config(ioc, &cfg) != 0)
  5279. return 0;
  5280. if (header.PageLength == 0)
  5281. return 0;
  5282. /* Read Header good, alloc memory
  5283. */
  5284. iocpage3sz = header.PageLength * 4;
  5285. pIoc3 = pci_alloc_consistent(ioc->pcidev, iocpage3sz, &ioc3_dma);
  5286. if (!pIoc3)
  5287. return 0;
  5288. /* Read the Page and save the data
  5289. * into malloc'd memory.
  5290. */
  5291. cfg.physAddr = ioc3_dma;
  5292. cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
  5293. if (mpt_config(ioc, &cfg) == 0) {
  5294. mem = kmalloc(iocpage3sz, GFP_KERNEL);
  5295. if (mem) {
  5296. memcpy(mem, (u8 *)pIoc3, iocpage3sz);
  5297. ioc->raid_data.pIocPg3 = (IOCPage3_t *) mem;
  5298. }
  5299. }
  5300. pci_free_consistent(ioc->pcidev, iocpage3sz, pIoc3, ioc3_dma);
  5301. return 0;
  5302. }
  5303. static void
  5304. mpt_read_ioc_pg_4(MPT_ADAPTER *ioc)
  5305. {
  5306. IOCPage4_t *pIoc4;
  5307. CONFIGPARMS cfg;
  5308. ConfigPageHeader_t header;
  5309. dma_addr_t ioc4_dma;
  5310. int iocpage4sz;
  5311. /* Read and save IOC Page 4
  5312. */
  5313. header.PageVersion = 0;
  5314. header.PageLength = 0;
  5315. header.PageNumber = 4;
  5316. header.PageType = MPI_CONFIG_PAGETYPE_IOC;
  5317. cfg.cfghdr.hdr = &header;
  5318. cfg.physAddr = -1;
  5319. cfg.pageAddr = 0;
  5320. cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
  5321. cfg.dir = 0;
  5322. cfg.timeout = 0;
  5323. if (mpt_config(ioc, &cfg) != 0)
  5324. return;
  5325. if (header.PageLength == 0)
  5326. return;
  5327. if ( (pIoc4 = ioc->spi_data.pIocPg4) == NULL ) {
  5328. iocpage4sz = (header.PageLength + 4) * 4; /* Allow 4 additional SEP's */
  5329. pIoc4 = pci_alloc_consistent(ioc->pcidev, iocpage4sz, &ioc4_dma);
  5330. if (!pIoc4)
  5331. return;
  5332. ioc->alloc_total += iocpage4sz;
  5333. } else {
  5334. ioc4_dma = ioc->spi_data.IocPg4_dma;
  5335. iocpage4sz = ioc->spi_data.IocPg4Sz;
  5336. }
  5337. /* Read the Page into dma memory.
  5338. */
  5339. cfg.physAddr = ioc4_dma;
  5340. cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
  5341. if (mpt_config(ioc, &cfg) == 0) {
  5342. ioc->spi_data.pIocPg4 = (IOCPage4_t *) pIoc4;
  5343. ioc->spi_data.IocPg4_dma = ioc4_dma;
  5344. ioc->spi_data.IocPg4Sz = iocpage4sz;
  5345. } else {
  5346. pci_free_consistent(ioc->pcidev, iocpage4sz, pIoc4, ioc4_dma);
  5347. ioc->spi_data.pIocPg4 = NULL;
  5348. ioc->alloc_total -= iocpage4sz;
  5349. }
  5350. }
  5351. static void
  5352. mpt_read_ioc_pg_1(MPT_ADAPTER *ioc)
  5353. {
  5354. IOCPage1_t *pIoc1;
  5355. CONFIGPARMS cfg;
  5356. ConfigPageHeader_t header;
  5357. dma_addr_t ioc1_dma;
  5358. int iocpage1sz = 0;
  5359. u32 tmp;
  5360. /* Check the Coalescing Timeout in IOC Page 1
  5361. */
  5362. header.PageVersion = 0;
  5363. header.PageLength = 0;
  5364. header.PageNumber = 1;
  5365. header.PageType = MPI_CONFIG_PAGETYPE_IOC;
  5366. cfg.cfghdr.hdr = &header;
  5367. cfg.physAddr = -1;
  5368. cfg.pageAddr = 0;
  5369. cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
  5370. cfg.dir = 0;
  5371. cfg.timeout = 0;
  5372. if (mpt_config(ioc, &cfg) != 0)
  5373. return;
  5374. if (header.PageLength == 0)
  5375. return;
  5376. /* Read Header good, alloc memory
  5377. */
  5378. iocpage1sz = header.PageLength * 4;
  5379. pIoc1 = pci_alloc_consistent(ioc->pcidev, iocpage1sz, &ioc1_dma);
  5380. if (!pIoc1)
  5381. return;
  5382. /* Read the Page and check coalescing timeout
  5383. */
  5384. cfg.physAddr = ioc1_dma;
  5385. cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
  5386. if (mpt_config(ioc, &cfg) == 0) {
  5387. tmp = le32_to_cpu(pIoc1->Flags) & MPI_IOCPAGE1_REPLY_COALESCING;
  5388. if (tmp == MPI_IOCPAGE1_REPLY_COALESCING) {
  5389. tmp = le32_to_cpu(pIoc1->CoalescingTimeout);
  5390. dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Coalescing Enabled Timeout = %d\n",
  5391. ioc->name, tmp));
  5392. if (tmp > MPT_COALESCING_TIMEOUT) {
  5393. pIoc1->CoalescingTimeout = cpu_to_le32(MPT_COALESCING_TIMEOUT);
  5394. /* Write NVRAM and current
  5395. */
  5396. cfg.dir = 1;
  5397. cfg.action = MPI_CONFIG_ACTION_PAGE_WRITE_CURRENT;
  5398. if (mpt_config(ioc, &cfg) == 0) {
  5399. dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Reset Current Coalescing Timeout to = %d\n",
  5400. ioc->name, MPT_COALESCING_TIMEOUT));
  5401. cfg.action = MPI_CONFIG_ACTION_PAGE_WRITE_NVRAM;
  5402. if (mpt_config(ioc, &cfg) == 0) {
  5403. dprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  5404. "Reset NVRAM Coalescing Timeout to = %d\n",
  5405. ioc->name, MPT_COALESCING_TIMEOUT));
  5406. } else {
  5407. dprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  5408. "Reset NVRAM Coalescing Timeout Failed\n",
  5409. ioc->name));
  5410. }
  5411. } else {
  5412. dprintk(ioc, printk(MYIOC_s_WARN_FMT
  5413. "Reset of Current Coalescing Timeout Failed!\n",
  5414. ioc->name));
  5415. }
  5416. }
  5417. } else {
  5418. dprintk(ioc, printk(MYIOC_s_WARN_FMT "Coalescing Disabled\n", ioc->name));
  5419. }
  5420. }
  5421. pci_free_consistent(ioc->pcidev, iocpage1sz, pIoc1, ioc1_dma);
  5422. return;
  5423. }
  5424. static void
  5425. mpt_get_manufacturing_pg_0(MPT_ADAPTER *ioc)
  5426. {
  5427. CONFIGPARMS cfg;
  5428. ConfigPageHeader_t hdr;
  5429. dma_addr_t buf_dma;
  5430. ManufacturingPage0_t *pbuf = NULL;
  5431. memset(&cfg, 0 , sizeof(CONFIGPARMS));
  5432. memset(&hdr, 0 , sizeof(ConfigPageHeader_t));
  5433. hdr.PageType = MPI_CONFIG_PAGETYPE_MANUFACTURING;
  5434. cfg.cfghdr.hdr = &hdr;
  5435. cfg.physAddr = -1;
  5436. cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
  5437. cfg.timeout = 10;
  5438. if (mpt_config(ioc, &cfg) != 0)
  5439. goto out;
  5440. if (!cfg.cfghdr.hdr->PageLength)
  5441. goto out;
  5442. cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
  5443. pbuf = pci_alloc_consistent(ioc->pcidev, hdr.PageLength * 4, &buf_dma);
  5444. if (!pbuf)
  5445. goto out;
  5446. cfg.physAddr = buf_dma;
  5447. if (mpt_config(ioc, &cfg) != 0)
  5448. goto out;
  5449. memcpy(ioc->board_name, pbuf->BoardName, sizeof(ioc->board_name));
  5450. memcpy(ioc->board_assembly, pbuf->BoardAssembly, sizeof(ioc->board_assembly));
  5451. memcpy(ioc->board_tracer, pbuf->BoardTracerNumber, sizeof(ioc->board_tracer));
  5452. out:
  5453. if (pbuf)
  5454. pci_free_consistent(ioc->pcidev, hdr.PageLength * 4, pbuf, buf_dma);
  5455. }
  5456. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  5457. /**
  5458. * SendEventNotification - Send EventNotification (on or off) request to adapter
  5459. * @ioc: Pointer to MPT_ADAPTER structure
  5460. * @EvSwitch: Event switch flags
  5461. * @sleepFlag: Specifies whether the process can sleep
  5462. */
  5463. static int
  5464. SendEventNotification(MPT_ADAPTER *ioc, u8 EvSwitch, int sleepFlag)
  5465. {
  5466. EventNotification_t evn;
  5467. MPIDefaultReply_t reply_buf;
  5468. memset(&evn, 0, sizeof(EventNotification_t));
  5469. memset(&reply_buf, 0, sizeof(MPIDefaultReply_t));
  5470. evn.Function = MPI_FUNCTION_EVENT_NOTIFICATION;
  5471. evn.Switch = EvSwitch;
  5472. evn.MsgContext = cpu_to_le32(mpt_base_index << 16);
  5473. devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  5474. "Sending EventNotification (%d) request %p\n",
  5475. ioc->name, EvSwitch, &evn));
  5476. return mpt_handshake_req_reply_wait(ioc, sizeof(EventNotification_t),
  5477. (u32 *)&evn, sizeof(MPIDefaultReply_t), (u16 *)&reply_buf, 30,
  5478. sleepFlag);
  5479. }
  5480. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  5481. /**
  5482. * SendEventAck - Send EventAck request to MPT adapter.
  5483. * @ioc: Pointer to MPT_ADAPTER structure
  5484. * @evnp: Pointer to original EventNotification request
  5485. */
  5486. static int
  5487. SendEventAck(MPT_ADAPTER *ioc, EventNotificationReply_t *evnp)
  5488. {
  5489. EventAck_t *pAck;
  5490. if ((pAck = (EventAck_t *) mpt_get_msg_frame(mpt_base_index, ioc)) == NULL) {
  5491. dfailprintk(ioc, printk(MYIOC_s_WARN_FMT "%s, no msg frames!!\n",
  5492. ioc->name, __func__));
  5493. return -1;
  5494. }
  5495. devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending EventAck\n", ioc->name));
  5496. pAck->Function = MPI_FUNCTION_EVENT_ACK;
  5497. pAck->ChainOffset = 0;
  5498. pAck->Reserved[0] = pAck->Reserved[1] = 0;
  5499. pAck->MsgFlags = 0;
  5500. pAck->Reserved1[0] = pAck->Reserved1[1] = pAck->Reserved1[2] = 0;
  5501. pAck->Event = evnp->Event;
  5502. pAck->EventContext = evnp->EventContext;
  5503. mpt_put_msg_frame(mpt_base_index, ioc, (MPT_FRAME_HDR *)pAck);
  5504. return 0;
  5505. }
  5506. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  5507. /**
  5508. * mpt_config - Generic function to issue config message
  5509. * @ioc: Pointer to an adapter structure
  5510. * @pCfg: Pointer to a configuration structure. Struct contains
  5511. * action, page address, direction, physical address
  5512. * and pointer to a configuration page header
  5513. * Page header is updated.
  5514. *
  5515. * Returns 0 for success
  5516. * -EPERM if not allowed due to ISR context
  5517. * -EAGAIN if no msg frames currently available
  5518. * -EFAULT for non-successful reply or no reply (timeout)
  5519. */
  5520. int
  5521. mpt_config(MPT_ADAPTER *ioc, CONFIGPARMS *pCfg)
  5522. {
  5523. Config_t *pReq;
  5524. ConfigReply_t *pReply;
  5525. ConfigExtendedPageHeader_t *pExtHdr = NULL;
  5526. MPT_FRAME_HDR *mf;
  5527. int ii;
  5528. int flagsLength;
  5529. long timeout;
  5530. int ret;
  5531. u8 page_type = 0, extend_page;
  5532. unsigned long timeleft;
  5533. unsigned long flags;
  5534. int in_isr;
  5535. u8 issue_hard_reset = 0;
  5536. u8 retry_count = 0;
  5537. /* Prevent calling wait_event() (below), if caller happens
  5538. * to be in ISR context, because that is fatal!
  5539. */
  5540. in_isr = in_interrupt();
  5541. if (in_isr) {
  5542. dcprintk(ioc, printk(MYIOC_s_WARN_FMT "Config request not allowed in ISR context!\n",
  5543. ioc->name));
  5544. return -EPERM;
  5545. }
  5546. /* don't send a config page during diag reset */
  5547. spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
  5548. if (ioc->ioc_reset_in_progress) {
  5549. dfailprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  5550. "%s: busy with host reset\n", ioc->name, __func__));
  5551. spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
  5552. return -EBUSY;
  5553. }
  5554. spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
  5555. /* don't send if no chance of success */
  5556. if (!ioc->active ||
  5557. mpt_GetIocState(ioc, 1) != MPI_IOC_STATE_OPERATIONAL) {
  5558. dfailprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  5559. "%s: ioc not operational, %d, %xh\n",
  5560. ioc->name, __func__, ioc->active,
  5561. mpt_GetIocState(ioc, 0)));
  5562. return -EFAULT;
  5563. }
  5564. retry_config:
  5565. mutex_lock(&ioc->mptbase_cmds.mutex);
  5566. /* init the internal cmd struct */
  5567. memset(ioc->mptbase_cmds.reply, 0 , MPT_DEFAULT_FRAME_SIZE);
  5568. INITIALIZE_MGMT_STATUS(ioc->mptbase_cmds.status)
  5569. /* Get and Populate a free Frame
  5570. */
  5571. if ((mf = mpt_get_msg_frame(mpt_base_index, ioc)) == NULL) {
  5572. dcprintk(ioc, printk(MYIOC_s_WARN_FMT
  5573. "mpt_config: no msg frames!\n", ioc->name));
  5574. ret = -EAGAIN;
  5575. goto out;
  5576. }
  5577. pReq = (Config_t *)mf;
  5578. pReq->Action = pCfg->action;
  5579. pReq->Reserved = 0;
  5580. pReq->ChainOffset = 0;
  5581. pReq->Function = MPI_FUNCTION_CONFIG;
  5582. /* Assume page type is not extended and clear "reserved" fields. */
  5583. pReq->ExtPageLength = 0;
  5584. pReq->ExtPageType = 0;
  5585. pReq->MsgFlags = 0;
  5586. for (ii=0; ii < 8; ii++)
  5587. pReq->Reserved2[ii] = 0;
  5588. pReq->Header.PageVersion = pCfg->cfghdr.hdr->PageVersion;
  5589. pReq->Header.PageLength = pCfg->cfghdr.hdr->PageLength;
  5590. pReq->Header.PageNumber = pCfg->cfghdr.hdr->PageNumber;
  5591. pReq->Header.PageType = (pCfg->cfghdr.hdr->PageType & MPI_CONFIG_PAGETYPE_MASK);
  5592. if ((pCfg->cfghdr.hdr->PageType & MPI_CONFIG_PAGETYPE_MASK) == MPI_CONFIG_PAGETYPE_EXTENDED) {
  5593. pExtHdr = (ConfigExtendedPageHeader_t *)pCfg->cfghdr.ehdr;
  5594. pReq->ExtPageLength = cpu_to_le16(pExtHdr->ExtPageLength);
  5595. pReq->ExtPageType = pExtHdr->ExtPageType;
  5596. pReq->Header.PageType = MPI_CONFIG_PAGETYPE_EXTENDED;
  5597. /* Page Length must be treated as a reserved field for the
  5598. * extended header.
  5599. */
  5600. pReq->Header.PageLength = 0;
  5601. }
  5602. pReq->PageAddress = cpu_to_le32(pCfg->pageAddr);
  5603. /* Add a SGE to the config request.
  5604. */
  5605. if (pCfg->dir)
  5606. flagsLength = MPT_SGE_FLAGS_SSIMPLE_WRITE;
  5607. else
  5608. flagsLength = MPT_SGE_FLAGS_SSIMPLE_READ;
  5609. if ((pCfg->cfghdr.hdr->PageType & MPI_CONFIG_PAGETYPE_MASK) ==
  5610. MPI_CONFIG_PAGETYPE_EXTENDED) {
  5611. flagsLength |= pExtHdr->ExtPageLength * 4;
  5612. page_type = pReq->ExtPageType;
  5613. extend_page = 1;
  5614. } else {
  5615. flagsLength |= pCfg->cfghdr.hdr->PageLength * 4;
  5616. page_type = pReq->Header.PageType;
  5617. extend_page = 0;
  5618. }
  5619. dcprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  5620. "Sending Config request type 0x%x, page 0x%x and action %d\n",
  5621. ioc->name, page_type, pReq->Header.PageNumber, pReq->Action));
  5622. ioc->add_sge((char *)&pReq->PageBufferSGE, flagsLength, pCfg->physAddr);
  5623. timeout = (pCfg->timeout < 15) ? HZ*15 : HZ*pCfg->timeout;
  5624. mpt_put_msg_frame(mpt_base_index, ioc, mf);
  5625. timeleft = wait_for_completion_timeout(&ioc->mptbase_cmds.done,
  5626. timeout);
  5627. if (!(ioc->mptbase_cmds.status & MPT_MGMT_STATUS_COMMAND_GOOD)) {
  5628. ret = -ETIME;
  5629. dfailprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  5630. "Failed Sending Config request type 0x%x, page 0x%x,"
  5631. " action %d, status %xh, time left %ld\n\n",
  5632. ioc->name, page_type, pReq->Header.PageNumber,
  5633. pReq->Action, ioc->mptbase_cmds.status, timeleft));
  5634. if (ioc->mptbase_cmds.status & MPT_MGMT_STATUS_DID_IOCRESET)
  5635. goto out;
  5636. if (!timeleft) {
  5637. spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
  5638. if (ioc->ioc_reset_in_progress) {
  5639. spin_unlock_irqrestore(&ioc->taskmgmt_lock,
  5640. flags);
  5641. printk(MYIOC_s_INFO_FMT "%s: host reset in"
  5642. " progress mpt_config timed out.!!\n",
  5643. __func__, ioc->name);
  5644. mutex_unlock(&ioc->mptbase_cmds.mutex);
  5645. return -EFAULT;
  5646. }
  5647. spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
  5648. issue_hard_reset = 1;
  5649. }
  5650. goto out;
  5651. }
  5652. if (!(ioc->mptbase_cmds.status & MPT_MGMT_STATUS_RF_VALID)) {
  5653. ret = -1;
  5654. goto out;
  5655. }
  5656. pReply = (ConfigReply_t *)ioc->mptbase_cmds.reply;
  5657. ret = le16_to_cpu(pReply->IOCStatus) & MPI_IOCSTATUS_MASK;
  5658. if (ret == MPI_IOCSTATUS_SUCCESS) {
  5659. if (extend_page) {
  5660. pCfg->cfghdr.ehdr->ExtPageLength =
  5661. le16_to_cpu(pReply->ExtPageLength);
  5662. pCfg->cfghdr.ehdr->ExtPageType =
  5663. pReply->ExtPageType;
  5664. }
  5665. pCfg->cfghdr.hdr->PageVersion = pReply->Header.PageVersion;
  5666. pCfg->cfghdr.hdr->PageLength = pReply->Header.PageLength;
  5667. pCfg->cfghdr.hdr->PageNumber = pReply->Header.PageNumber;
  5668. pCfg->cfghdr.hdr->PageType = pReply->Header.PageType;
  5669. }
  5670. if (retry_count)
  5671. printk(MYIOC_s_INFO_FMT "Retry completed "
  5672. "ret=0x%x timeleft=%ld\n",
  5673. ioc->name, ret, timeleft);
  5674. dcprintk(ioc, printk(KERN_DEBUG "IOCStatus=%04xh, IOCLogInfo=%08xh\n",
  5675. ret, le32_to_cpu(pReply->IOCLogInfo)));
  5676. out:
  5677. CLEAR_MGMT_STATUS(ioc->mptbase_cmds.status)
  5678. mutex_unlock(&ioc->mptbase_cmds.mutex);
  5679. if (issue_hard_reset) {
  5680. issue_hard_reset = 0;
  5681. printk(MYIOC_s_WARN_FMT
  5682. "Issuing Reset from %s!!, doorbell=0x%08x\n",
  5683. ioc->name, __func__, mpt_GetIocState(ioc, 0));
  5684. if (retry_count == 0) {
  5685. if (mpt_Soft_Hard_ResetHandler(ioc, CAN_SLEEP) != 0)
  5686. retry_count++;
  5687. } else
  5688. mpt_HardResetHandler(ioc, CAN_SLEEP);
  5689. mpt_free_msg_frame(ioc, mf);
  5690. /* attempt one retry for a timed out command */
  5691. if (retry_count < 2) {
  5692. printk(MYIOC_s_INFO_FMT
  5693. "Attempting Retry Config request"
  5694. " type 0x%x, page 0x%x,"
  5695. " action %d\n", ioc->name, page_type,
  5696. pCfg->cfghdr.hdr->PageNumber, pCfg->action);
  5697. retry_count++;
  5698. goto retry_config;
  5699. }
  5700. }
  5701. return ret;
  5702. }
  5703. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  5704. /**
  5705. * mpt_ioc_reset - Base cleanup for hard reset
  5706. * @ioc: Pointer to the adapter structure
  5707. * @reset_phase: Indicates pre- or post-reset functionality
  5708. *
  5709. * Remark: Frees resources with internally generated commands.
  5710. */
  5711. static int
  5712. mpt_ioc_reset(MPT_ADAPTER *ioc, int reset_phase)
  5713. {
  5714. switch (reset_phase) {
  5715. case MPT_IOC_SETUP_RESET:
  5716. ioc->taskmgmt_quiesce_io = 1;
  5717. dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  5718. "%s: MPT_IOC_SETUP_RESET\n", ioc->name, __func__));
  5719. break;
  5720. case MPT_IOC_PRE_RESET:
  5721. dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  5722. "%s: MPT_IOC_PRE_RESET\n", ioc->name, __func__));
  5723. break;
  5724. case MPT_IOC_POST_RESET:
  5725. dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  5726. "%s: MPT_IOC_POST_RESET\n", ioc->name, __func__));
  5727. /* wake up mptbase_cmds */
  5728. if (ioc->mptbase_cmds.status & MPT_MGMT_STATUS_PENDING) {
  5729. ioc->mptbase_cmds.status |=
  5730. MPT_MGMT_STATUS_DID_IOCRESET;
  5731. complete(&ioc->mptbase_cmds.done);
  5732. }
  5733. /* wake up taskmgmt_cmds */
  5734. if (ioc->taskmgmt_cmds.status & MPT_MGMT_STATUS_PENDING) {
  5735. ioc->taskmgmt_cmds.status |=
  5736. MPT_MGMT_STATUS_DID_IOCRESET;
  5737. complete(&ioc->taskmgmt_cmds.done);
  5738. }
  5739. break;
  5740. default:
  5741. break;
  5742. }
  5743. return 1; /* currently means nothing really */
  5744. }
  5745. #ifdef CONFIG_PROC_FS /* { */
  5746. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  5747. /*
  5748. * procfs (%MPT_PROCFS_MPTBASEDIR/...) support stuff...
  5749. */
  5750. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  5751. /**
  5752. * procmpt_create - Create %MPT_PROCFS_MPTBASEDIR entries.
  5753. *
  5754. * Returns 0 for success, non-zero for failure.
  5755. */
  5756. static int
  5757. procmpt_create(void)
  5758. {
  5759. mpt_proc_root_dir = proc_mkdir(MPT_PROCFS_MPTBASEDIR, NULL);
  5760. if (mpt_proc_root_dir == NULL)
  5761. return -ENOTDIR;
  5762. proc_create_single("summary", S_IRUGO, mpt_proc_root_dir,
  5763. mpt_summary_proc_show);
  5764. proc_create_single("version", S_IRUGO, mpt_proc_root_dir,
  5765. mpt_version_proc_show);
  5766. return 0;
  5767. }
  5768. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  5769. /**
  5770. * procmpt_destroy - Tear down %MPT_PROCFS_MPTBASEDIR entries.
  5771. *
  5772. * Returns 0 for success, non-zero for failure.
  5773. */
  5774. static void
  5775. procmpt_destroy(void)
  5776. {
  5777. remove_proc_entry("version", mpt_proc_root_dir);
  5778. remove_proc_entry("summary", mpt_proc_root_dir);
  5779. remove_proc_entry(MPT_PROCFS_MPTBASEDIR, NULL);
  5780. }
  5781. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  5782. /*
  5783. * Handles read request from /proc/mpt/summary or /proc/mpt/iocN/summary.
  5784. */
  5785. static void seq_mpt_print_ioc_summary(MPT_ADAPTER *ioc, struct seq_file *m, int showlan);
  5786. static int mpt_summary_proc_show(struct seq_file *m, void *v)
  5787. {
  5788. MPT_ADAPTER *ioc = m->private;
  5789. if (ioc) {
  5790. seq_mpt_print_ioc_summary(ioc, m, 1);
  5791. } else {
  5792. list_for_each_entry(ioc, &ioc_list, list) {
  5793. seq_mpt_print_ioc_summary(ioc, m, 1);
  5794. }
  5795. }
  5796. return 0;
  5797. }
  5798. static int mpt_version_proc_show(struct seq_file *m, void *v)
  5799. {
  5800. u8 cb_idx;
  5801. int scsi, fc, sas, lan, ctl, targ, dmp;
  5802. char *drvname;
  5803. seq_printf(m, "%s-%s\n", "mptlinux", MPT_LINUX_VERSION_COMMON);
  5804. seq_printf(m, " Fusion MPT base driver\n");
  5805. scsi = fc = sas = lan = ctl = targ = dmp = 0;
  5806. for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
  5807. drvname = NULL;
  5808. if (MptCallbacks[cb_idx]) {
  5809. switch (MptDriverClass[cb_idx]) {
  5810. case MPTSPI_DRIVER:
  5811. if (!scsi++) drvname = "SPI host";
  5812. break;
  5813. case MPTFC_DRIVER:
  5814. if (!fc++) drvname = "FC host";
  5815. break;
  5816. case MPTSAS_DRIVER:
  5817. if (!sas++) drvname = "SAS host";
  5818. break;
  5819. case MPTLAN_DRIVER:
  5820. if (!lan++) drvname = "LAN";
  5821. break;
  5822. case MPTSTM_DRIVER:
  5823. if (!targ++) drvname = "SCSI target";
  5824. break;
  5825. case MPTCTL_DRIVER:
  5826. if (!ctl++) drvname = "ioctl";
  5827. break;
  5828. }
  5829. if (drvname)
  5830. seq_printf(m, " Fusion MPT %s driver\n", drvname);
  5831. }
  5832. }
  5833. return 0;
  5834. }
  5835. static int mpt_iocinfo_proc_show(struct seq_file *m, void *v)
  5836. {
  5837. MPT_ADAPTER *ioc = m->private;
  5838. char expVer[32];
  5839. int sz;
  5840. int p;
  5841. mpt_get_fw_exp_ver(expVer, ioc);
  5842. seq_printf(m, "%s:", ioc->name);
  5843. if (ioc->facts.Flags & MPI_IOCFACTS_FLAGS_FW_DOWNLOAD_BOOT)
  5844. seq_printf(m, " (f/w download boot flag set)");
  5845. // if (ioc->facts.IOCExceptions & MPI_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL)
  5846. // seq_printf(m, " CONFIG_CHECKSUM_FAIL!");
  5847. seq_printf(m, "\n ProductID = 0x%04x (%s)\n",
  5848. ioc->facts.ProductID,
  5849. ioc->prod_name);
  5850. seq_printf(m, " FWVersion = 0x%08x%s", ioc->facts.FWVersion.Word, expVer);
  5851. if (ioc->facts.FWImageSize)
  5852. seq_printf(m, " (fw_size=%d)", ioc->facts.FWImageSize);
  5853. seq_printf(m, "\n MsgVersion = 0x%04x\n", ioc->facts.MsgVersion);
  5854. seq_printf(m, " FirstWhoInit = 0x%02x\n", ioc->FirstWhoInit);
  5855. seq_printf(m, " EventState = 0x%02x\n", ioc->facts.EventState);
  5856. seq_printf(m, " CurrentHostMfaHighAddr = 0x%08x\n",
  5857. ioc->facts.CurrentHostMfaHighAddr);
  5858. seq_printf(m, " CurrentSenseBufferHighAddr = 0x%08x\n",
  5859. ioc->facts.CurrentSenseBufferHighAddr);
  5860. seq_printf(m, " MaxChainDepth = 0x%02x frames\n", ioc->facts.MaxChainDepth);
  5861. seq_printf(m, " MinBlockSize = 0x%02x bytes\n", 4*ioc->facts.BlockSize);
  5862. seq_printf(m, " RequestFrames @ 0x%p (Dma @ 0x%p)\n",
  5863. (void *)ioc->req_frames, (void *)(ulong)ioc->req_frames_dma);
  5864. /*
  5865. * Rounding UP to nearest 4-kB boundary here...
  5866. */
  5867. sz = (ioc->req_sz * ioc->req_depth) + 128;
  5868. sz = ((sz + 0x1000UL - 1UL) / 0x1000) * 0x1000;
  5869. seq_printf(m, " {CurReqSz=%d} x {CurReqDepth=%d} = %d bytes ^= 0x%x\n",
  5870. ioc->req_sz, ioc->req_depth, ioc->req_sz*ioc->req_depth, sz);
  5871. seq_printf(m, " {MaxReqSz=%d} {MaxReqDepth=%d}\n",
  5872. 4*ioc->facts.RequestFrameSize,
  5873. ioc->facts.GlobalCredits);
  5874. seq_printf(m, " Frames @ 0x%p (Dma @ 0x%p)\n",
  5875. (void *)ioc->alloc, (void *)(ulong)ioc->alloc_dma);
  5876. sz = (ioc->reply_sz * ioc->reply_depth) + 128;
  5877. seq_printf(m, " {CurRepSz=%d} x {CurRepDepth=%d} = %d bytes ^= 0x%x\n",
  5878. ioc->reply_sz, ioc->reply_depth, ioc->reply_sz*ioc->reply_depth, sz);
  5879. seq_printf(m, " {MaxRepSz=%d} {MaxRepDepth=%d}\n",
  5880. ioc->facts.CurReplyFrameSize,
  5881. ioc->facts.ReplyQueueDepth);
  5882. seq_printf(m, " MaxDevices = %d\n",
  5883. (ioc->facts.MaxDevices==0) ? 255 : ioc->facts.MaxDevices);
  5884. seq_printf(m, " MaxBuses = %d\n", ioc->facts.MaxBuses);
  5885. /* per-port info */
  5886. for (p=0; p < ioc->facts.NumberOfPorts; p++) {
  5887. seq_printf(m, " PortNumber = %d (of %d)\n",
  5888. p+1,
  5889. ioc->facts.NumberOfPorts);
  5890. if (ioc->bus_type == FC) {
  5891. if (ioc->pfacts[p].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_LAN) {
  5892. u8 *a = (u8*)&ioc->lan_cnfg_page1.HardwareAddressLow;
  5893. seq_printf(m, " LanAddr = %pMR\n", a);
  5894. }
  5895. seq_printf(m, " WWN = %08X%08X:%08X%08X\n",
  5896. ioc->fc_port_page0[p].WWNN.High,
  5897. ioc->fc_port_page0[p].WWNN.Low,
  5898. ioc->fc_port_page0[p].WWPN.High,
  5899. ioc->fc_port_page0[p].WWPN.Low);
  5900. }
  5901. }
  5902. return 0;
  5903. }
  5904. #endif /* CONFIG_PROC_FS } */
  5905. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  5906. static void
  5907. mpt_get_fw_exp_ver(char *buf, MPT_ADAPTER *ioc)
  5908. {
  5909. buf[0] ='\0';
  5910. if ((ioc->facts.FWVersion.Word >> 24) == 0x0E) {
  5911. sprintf(buf, " (Exp %02d%02d)",
  5912. (ioc->facts.FWVersion.Word >> 16) & 0x00FF, /* Month */
  5913. (ioc->facts.FWVersion.Word >> 8) & 0x1F); /* Day */
  5914. /* insider hack! */
  5915. if ((ioc->facts.FWVersion.Word >> 8) & 0x80)
  5916. strcat(buf, " [MDBG]");
  5917. }
  5918. }
  5919. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  5920. /**
  5921. * mpt_print_ioc_summary - Write ASCII summary of IOC to a buffer.
  5922. * @ioc: Pointer to MPT_ADAPTER structure
  5923. * @buffer: Pointer to buffer where IOC summary info should be written
  5924. * @size: Pointer to number of bytes we wrote (set by this routine)
  5925. * @len: Offset at which to start writing in buffer
  5926. * @showlan: Display LAN stuff?
  5927. *
  5928. * This routine writes (english readable) ASCII text, which represents
  5929. * a summary of IOC information, to a buffer.
  5930. */
  5931. void
  5932. mpt_print_ioc_summary(MPT_ADAPTER *ioc, char *buffer, int *size, int len, int showlan)
  5933. {
  5934. char expVer[32];
  5935. int y;
  5936. mpt_get_fw_exp_ver(expVer, ioc);
  5937. /*
  5938. * Shorter summary of attached ioc's...
  5939. */
  5940. y = sprintf(buffer+len, "%s: %s, %s%08xh%s, Ports=%d, MaxQ=%d",
  5941. ioc->name,
  5942. ioc->prod_name,
  5943. MPT_FW_REV_MAGIC_ID_STRING, /* "FwRev=" or somesuch */
  5944. ioc->facts.FWVersion.Word,
  5945. expVer,
  5946. ioc->facts.NumberOfPorts,
  5947. ioc->req_depth);
  5948. if (showlan && (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_LAN)) {
  5949. u8 *a = (u8*)&ioc->lan_cnfg_page1.HardwareAddressLow;
  5950. y += sprintf(buffer+len+y, ", LanAddr=%pMR", a);
  5951. }
  5952. y += sprintf(buffer+len+y, ", IRQ=%d", ioc->pci_irq);
  5953. if (!ioc->active)
  5954. y += sprintf(buffer+len+y, " (disabled)");
  5955. y += sprintf(buffer+len+y, "\n");
  5956. *size = y;
  5957. }
  5958. #ifdef CONFIG_PROC_FS
  5959. static void seq_mpt_print_ioc_summary(MPT_ADAPTER *ioc, struct seq_file *m, int showlan)
  5960. {
  5961. char expVer[32];
  5962. mpt_get_fw_exp_ver(expVer, ioc);
  5963. /*
  5964. * Shorter summary of attached ioc's...
  5965. */
  5966. seq_printf(m, "%s: %s, %s%08xh%s, Ports=%d, MaxQ=%d",
  5967. ioc->name,
  5968. ioc->prod_name,
  5969. MPT_FW_REV_MAGIC_ID_STRING, /* "FwRev=" or somesuch */
  5970. ioc->facts.FWVersion.Word,
  5971. expVer,
  5972. ioc->facts.NumberOfPorts,
  5973. ioc->req_depth);
  5974. if (showlan && (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_LAN)) {
  5975. u8 *a = (u8*)&ioc->lan_cnfg_page1.HardwareAddressLow;
  5976. seq_printf(m, ", LanAddr=%pMR", a);
  5977. }
  5978. seq_printf(m, ", IRQ=%d", ioc->pci_irq);
  5979. if (!ioc->active)
  5980. seq_printf(m, " (disabled)");
  5981. seq_putc(m, '\n');
  5982. }
  5983. #endif
  5984. /**
  5985. * mpt_set_taskmgmt_in_progress_flag - set flags associated with task management
  5986. * @ioc: Pointer to MPT_ADAPTER structure
  5987. *
  5988. * Returns 0 for SUCCESS or -1 if FAILED.
  5989. *
  5990. * If -1 is return, then it was not possible to set the flags
  5991. **/
  5992. int
  5993. mpt_set_taskmgmt_in_progress_flag(MPT_ADAPTER *ioc)
  5994. {
  5995. unsigned long flags;
  5996. int retval;
  5997. spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
  5998. if (ioc->ioc_reset_in_progress || ioc->taskmgmt_in_progress ||
  5999. (ioc->alt_ioc && ioc->alt_ioc->taskmgmt_in_progress)) {
  6000. retval = -1;
  6001. goto out;
  6002. }
  6003. retval = 0;
  6004. ioc->taskmgmt_in_progress = 1;
  6005. ioc->taskmgmt_quiesce_io = 1;
  6006. if (ioc->alt_ioc) {
  6007. ioc->alt_ioc->taskmgmt_in_progress = 1;
  6008. ioc->alt_ioc->taskmgmt_quiesce_io = 1;
  6009. }
  6010. out:
  6011. spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
  6012. return retval;
  6013. }
  6014. EXPORT_SYMBOL(mpt_set_taskmgmt_in_progress_flag);
  6015. /**
  6016. * mpt_clear_taskmgmt_in_progress_flag - clear flags associated with task management
  6017. * @ioc: Pointer to MPT_ADAPTER structure
  6018. *
  6019. **/
  6020. void
  6021. mpt_clear_taskmgmt_in_progress_flag(MPT_ADAPTER *ioc)
  6022. {
  6023. unsigned long flags;
  6024. spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
  6025. ioc->taskmgmt_in_progress = 0;
  6026. ioc->taskmgmt_quiesce_io = 0;
  6027. if (ioc->alt_ioc) {
  6028. ioc->alt_ioc->taskmgmt_in_progress = 0;
  6029. ioc->alt_ioc->taskmgmt_quiesce_io = 0;
  6030. }
  6031. spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
  6032. }
  6033. EXPORT_SYMBOL(mpt_clear_taskmgmt_in_progress_flag);
  6034. /**
  6035. * mpt_halt_firmware - Halts the firmware if it is operational and panic
  6036. * the kernel
  6037. * @ioc: Pointer to MPT_ADAPTER structure
  6038. *
  6039. **/
  6040. void
  6041. mpt_halt_firmware(MPT_ADAPTER *ioc)
  6042. {
  6043. u32 ioc_raw_state;
  6044. ioc_raw_state = mpt_GetIocState(ioc, 0);
  6045. if ((ioc_raw_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_FAULT) {
  6046. printk(MYIOC_s_ERR_FMT "IOC is in FAULT state (%04xh)!!!\n",
  6047. ioc->name, ioc_raw_state & MPI_DOORBELL_DATA_MASK);
  6048. panic("%s: IOC Fault (%04xh)!!!\n", ioc->name,
  6049. ioc_raw_state & MPI_DOORBELL_DATA_MASK);
  6050. } else {
  6051. CHIPREG_WRITE32(&ioc->chip->Doorbell, 0xC0FFEE00);
  6052. panic("%s: Firmware is halted due to command timeout\n",
  6053. ioc->name);
  6054. }
  6055. }
  6056. EXPORT_SYMBOL(mpt_halt_firmware);
  6057. /**
  6058. * mpt_SoftResetHandler - Issues a less expensive reset
  6059. * @ioc: Pointer to MPT_ADAPTER structure
  6060. * @sleepFlag: Indicates if sleep or schedule must be called.
  6061. *
  6062. * Returns 0 for SUCCESS or -1 if FAILED.
  6063. *
  6064. * Message Unit Reset - instructs the IOC to reset the Reply Post and
  6065. * Free FIFO's. All the Message Frames on Reply Free FIFO are discarded.
  6066. * All posted buffers are freed, and event notification is turned off.
  6067. * IOC doesn't reply to any outstanding request. This will transfer IOC
  6068. * to READY state.
  6069. **/
  6070. static int
  6071. mpt_SoftResetHandler(MPT_ADAPTER *ioc, int sleepFlag)
  6072. {
  6073. int rc;
  6074. int ii;
  6075. u8 cb_idx;
  6076. unsigned long flags;
  6077. u32 ioc_state;
  6078. unsigned long time_count;
  6079. dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT "SoftResetHandler Entered!\n",
  6080. ioc->name));
  6081. ioc_state = mpt_GetIocState(ioc, 0) & MPI_IOC_STATE_MASK;
  6082. if (mpt_fwfault_debug)
  6083. mpt_halt_firmware(ioc);
  6084. if (ioc_state == MPI_IOC_STATE_FAULT ||
  6085. ioc_state == MPI_IOC_STATE_RESET) {
  6086. dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  6087. "skipping, either in FAULT or RESET state!\n", ioc->name));
  6088. return -1;
  6089. }
  6090. if (ioc->bus_type == FC) {
  6091. dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  6092. "skipping, because the bus type is FC!\n", ioc->name));
  6093. return -1;
  6094. }
  6095. spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
  6096. if (ioc->ioc_reset_in_progress) {
  6097. spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
  6098. return -1;
  6099. }
  6100. ioc->ioc_reset_in_progress = 1;
  6101. spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
  6102. rc = -1;
  6103. for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
  6104. if (MptResetHandlers[cb_idx])
  6105. mpt_signal_reset(cb_idx, ioc, MPT_IOC_SETUP_RESET);
  6106. }
  6107. spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
  6108. if (ioc->taskmgmt_in_progress) {
  6109. ioc->ioc_reset_in_progress = 0;
  6110. spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
  6111. return -1;
  6112. }
  6113. spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
  6114. /* Disable reply interrupts (also blocks FreeQ) */
  6115. CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF);
  6116. ioc->active = 0;
  6117. time_count = jiffies;
  6118. rc = SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, sleepFlag);
  6119. for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
  6120. if (MptResetHandlers[cb_idx])
  6121. mpt_signal_reset(cb_idx, ioc, MPT_IOC_PRE_RESET);
  6122. }
  6123. if (rc)
  6124. goto out;
  6125. ioc_state = mpt_GetIocState(ioc, 0) & MPI_IOC_STATE_MASK;
  6126. if (ioc_state != MPI_IOC_STATE_READY)
  6127. goto out;
  6128. for (ii = 0; ii < 5; ii++) {
  6129. /* Get IOC facts! Allow 5 retries */
  6130. rc = GetIocFacts(ioc, sleepFlag,
  6131. MPT_HOSTEVENT_IOC_RECOVER);
  6132. if (rc == 0)
  6133. break;
  6134. if (sleepFlag == CAN_SLEEP)
  6135. msleep(100);
  6136. else
  6137. mdelay(100);
  6138. }
  6139. if (ii == 5)
  6140. goto out;
  6141. rc = PrimeIocFifos(ioc);
  6142. if (rc != 0)
  6143. goto out;
  6144. rc = SendIocInit(ioc, sleepFlag);
  6145. if (rc != 0)
  6146. goto out;
  6147. rc = SendEventNotification(ioc, 1, sleepFlag);
  6148. if (rc != 0)
  6149. goto out;
  6150. if (ioc->hard_resets < -1)
  6151. ioc->hard_resets++;
  6152. /*
  6153. * At this point, we know soft reset succeeded.
  6154. */
  6155. ioc->active = 1;
  6156. CHIPREG_WRITE32(&ioc->chip->IntMask, MPI_HIM_DIM);
  6157. out:
  6158. spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
  6159. ioc->ioc_reset_in_progress = 0;
  6160. ioc->taskmgmt_quiesce_io = 0;
  6161. ioc->taskmgmt_in_progress = 0;
  6162. spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
  6163. if (ioc->active) { /* otherwise, hard reset coming */
  6164. for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
  6165. if (MptResetHandlers[cb_idx])
  6166. mpt_signal_reset(cb_idx, ioc,
  6167. MPT_IOC_POST_RESET);
  6168. }
  6169. }
  6170. dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  6171. "SoftResetHandler: completed (%d seconds): %s\n",
  6172. ioc->name, jiffies_to_msecs(jiffies - time_count)/1000,
  6173. ((rc == 0) ? "SUCCESS" : "FAILED")));
  6174. return rc;
  6175. }
  6176. /**
  6177. * mpt_Soft_Hard_ResetHandler - Try less expensive reset
  6178. * @ioc: Pointer to MPT_ADAPTER structure
  6179. * @sleepFlag: Indicates if sleep or schedule must be called.
  6180. *
  6181. * Returns 0 for SUCCESS or -1 if FAILED.
  6182. * Try for softreset first, only if it fails go for expensive
  6183. * HardReset.
  6184. **/
  6185. int
  6186. mpt_Soft_Hard_ResetHandler(MPT_ADAPTER *ioc, int sleepFlag) {
  6187. int ret = -1;
  6188. ret = mpt_SoftResetHandler(ioc, sleepFlag);
  6189. if (ret == 0)
  6190. return ret;
  6191. ret = mpt_HardResetHandler(ioc, sleepFlag);
  6192. return ret;
  6193. }
  6194. EXPORT_SYMBOL(mpt_Soft_Hard_ResetHandler);
  6195. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  6196. /*
  6197. * Reset Handling
  6198. */
  6199. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  6200. /**
  6201. * mpt_HardResetHandler - Generic reset handler
  6202. * @ioc: Pointer to MPT_ADAPTER structure
  6203. * @sleepFlag: Indicates if sleep or schedule must be called.
  6204. *
  6205. * Issues SCSI Task Management call based on input arg values.
  6206. * If TaskMgmt fails, returns associated SCSI request.
  6207. *
  6208. * Remark: _HardResetHandler can be invoked from an interrupt thread (timer)
  6209. * or a non-interrupt thread. In the former, must not call schedule().
  6210. *
  6211. * Note: A return of -1 is a FATAL error case, as it means a
  6212. * FW reload/initialization failed.
  6213. *
  6214. * Returns 0 for SUCCESS or -1 if FAILED.
  6215. */
  6216. int
  6217. mpt_HardResetHandler(MPT_ADAPTER *ioc, int sleepFlag)
  6218. {
  6219. int rc;
  6220. u8 cb_idx;
  6221. unsigned long flags;
  6222. unsigned long time_count;
  6223. dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT "HardResetHandler Entered!\n", ioc->name));
  6224. #ifdef MFCNT
  6225. printk(MYIOC_s_INFO_FMT "HardResetHandler Entered!\n", ioc->name);
  6226. printk("MF count 0x%x !\n", ioc->mfcnt);
  6227. #endif
  6228. if (mpt_fwfault_debug)
  6229. mpt_halt_firmware(ioc);
  6230. /* Reset the adapter. Prevent more than 1 call to
  6231. * mpt_do_ioc_recovery at any instant in time.
  6232. */
  6233. spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
  6234. if (ioc->ioc_reset_in_progress) {
  6235. spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
  6236. ioc->wait_on_reset_completion = 1;
  6237. do {
  6238. ssleep(1);
  6239. } while (ioc->ioc_reset_in_progress == 1);
  6240. ioc->wait_on_reset_completion = 0;
  6241. return ioc->reset_status;
  6242. }
  6243. if (ioc->wait_on_reset_completion) {
  6244. spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
  6245. rc = 0;
  6246. time_count = jiffies;
  6247. goto exit;
  6248. }
  6249. ioc->ioc_reset_in_progress = 1;
  6250. if (ioc->alt_ioc)
  6251. ioc->alt_ioc->ioc_reset_in_progress = 1;
  6252. spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
  6253. /* The SCSI driver needs to adjust timeouts on all current
  6254. * commands prior to the diagnostic reset being issued.
  6255. * Prevents timeouts occurring during a diagnostic reset...very bad.
  6256. * For all other protocol drivers, this is a no-op.
  6257. */
  6258. for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
  6259. if (MptResetHandlers[cb_idx]) {
  6260. mpt_signal_reset(cb_idx, ioc, MPT_IOC_SETUP_RESET);
  6261. if (ioc->alt_ioc)
  6262. mpt_signal_reset(cb_idx, ioc->alt_ioc,
  6263. MPT_IOC_SETUP_RESET);
  6264. }
  6265. }
  6266. time_count = jiffies;
  6267. rc = mpt_do_ioc_recovery(ioc, MPT_HOSTEVENT_IOC_RECOVER, sleepFlag);
  6268. if (rc != 0) {
  6269. printk(KERN_WARNING MYNAM
  6270. ": WARNING - (%d) Cannot recover %s, doorbell=0x%08x\n",
  6271. rc, ioc->name, mpt_GetIocState(ioc, 0));
  6272. } else {
  6273. if (ioc->hard_resets < -1)
  6274. ioc->hard_resets++;
  6275. }
  6276. spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
  6277. ioc->ioc_reset_in_progress = 0;
  6278. ioc->taskmgmt_quiesce_io = 0;
  6279. ioc->taskmgmt_in_progress = 0;
  6280. ioc->reset_status = rc;
  6281. if (ioc->alt_ioc) {
  6282. ioc->alt_ioc->ioc_reset_in_progress = 0;
  6283. ioc->alt_ioc->taskmgmt_quiesce_io = 0;
  6284. ioc->alt_ioc->taskmgmt_in_progress = 0;
  6285. }
  6286. spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
  6287. for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
  6288. if (MptResetHandlers[cb_idx]) {
  6289. mpt_signal_reset(cb_idx, ioc, MPT_IOC_POST_RESET);
  6290. if (ioc->alt_ioc)
  6291. mpt_signal_reset(cb_idx,
  6292. ioc->alt_ioc, MPT_IOC_POST_RESET);
  6293. }
  6294. }
  6295. exit:
  6296. dtmprintk(ioc,
  6297. printk(MYIOC_s_DEBUG_FMT
  6298. "HardResetHandler: completed (%d seconds): %s\n", ioc->name,
  6299. jiffies_to_msecs(jiffies - time_count)/1000, ((rc == 0) ?
  6300. "SUCCESS" : "FAILED")));
  6301. return rc;
  6302. }
  6303. #ifdef CONFIG_FUSION_LOGGING
  6304. static void
  6305. mpt_display_event_info(MPT_ADAPTER *ioc, EventNotificationReply_t *pEventReply)
  6306. {
  6307. char *ds = NULL;
  6308. u32 evData0;
  6309. int ii;
  6310. u8 event;
  6311. char *evStr = ioc->evStr;
  6312. event = le32_to_cpu(pEventReply->Event) & 0xFF;
  6313. evData0 = le32_to_cpu(pEventReply->Data[0]);
  6314. switch(event) {
  6315. case MPI_EVENT_NONE:
  6316. ds = "None";
  6317. break;
  6318. case MPI_EVENT_LOG_DATA:
  6319. ds = "Log Data";
  6320. break;
  6321. case MPI_EVENT_STATE_CHANGE:
  6322. ds = "State Change";
  6323. break;
  6324. case MPI_EVENT_UNIT_ATTENTION:
  6325. ds = "Unit Attention";
  6326. break;
  6327. case MPI_EVENT_IOC_BUS_RESET:
  6328. ds = "IOC Bus Reset";
  6329. break;
  6330. case MPI_EVENT_EXT_BUS_RESET:
  6331. ds = "External Bus Reset";
  6332. break;
  6333. case MPI_EVENT_RESCAN:
  6334. ds = "Bus Rescan Event";
  6335. break;
  6336. case MPI_EVENT_LINK_STATUS_CHANGE:
  6337. if (evData0 == MPI_EVENT_LINK_STATUS_FAILURE)
  6338. ds = "Link Status(FAILURE) Change";
  6339. else
  6340. ds = "Link Status(ACTIVE) Change";
  6341. break;
  6342. case MPI_EVENT_LOOP_STATE_CHANGE:
  6343. if (evData0 == MPI_EVENT_LOOP_STATE_CHANGE_LIP)
  6344. ds = "Loop State(LIP) Change";
  6345. else if (evData0 == MPI_EVENT_LOOP_STATE_CHANGE_LPE)
  6346. ds = "Loop State(LPE) Change";
  6347. else
  6348. ds = "Loop State(LPB) Change";
  6349. break;
  6350. case MPI_EVENT_LOGOUT:
  6351. ds = "Logout";
  6352. break;
  6353. case MPI_EVENT_EVENT_CHANGE:
  6354. if (evData0)
  6355. ds = "Events ON";
  6356. else
  6357. ds = "Events OFF";
  6358. break;
  6359. case MPI_EVENT_INTEGRATED_RAID:
  6360. {
  6361. u8 ReasonCode = (u8)(evData0 >> 16);
  6362. switch (ReasonCode) {
  6363. case MPI_EVENT_RAID_RC_VOLUME_CREATED :
  6364. ds = "Integrated Raid: Volume Created";
  6365. break;
  6366. case MPI_EVENT_RAID_RC_VOLUME_DELETED :
  6367. ds = "Integrated Raid: Volume Deleted";
  6368. break;
  6369. case MPI_EVENT_RAID_RC_VOLUME_SETTINGS_CHANGED :
  6370. ds = "Integrated Raid: Volume Settings Changed";
  6371. break;
  6372. case MPI_EVENT_RAID_RC_VOLUME_STATUS_CHANGED :
  6373. ds = "Integrated Raid: Volume Status Changed";
  6374. break;
  6375. case MPI_EVENT_RAID_RC_VOLUME_PHYSDISK_CHANGED :
  6376. ds = "Integrated Raid: Volume Physdisk Changed";
  6377. break;
  6378. case MPI_EVENT_RAID_RC_PHYSDISK_CREATED :
  6379. ds = "Integrated Raid: Physdisk Created";
  6380. break;
  6381. case MPI_EVENT_RAID_RC_PHYSDISK_DELETED :
  6382. ds = "Integrated Raid: Physdisk Deleted";
  6383. break;
  6384. case MPI_EVENT_RAID_RC_PHYSDISK_SETTINGS_CHANGED :
  6385. ds = "Integrated Raid: Physdisk Settings Changed";
  6386. break;
  6387. case MPI_EVENT_RAID_RC_PHYSDISK_STATUS_CHANGED :
  6388. ds = "Integrated Raid: Physdisk Status Changed";
  6389. break;
  6390. case MPI_EVENT_RAID_RC_DOMAIN_VAL_NEEDED :
  6391. ds = "Integrated Raid: Domain Validation Needed";
  6392. break;
  6393. case MPI_EVENT_RAID_RC_SMART_DATA :
  6394. ds = "Integrated Raid; Smart Data";
  6395. break;
  6396. case MPI_EVENT_RAID_RC_REPLACE_ACTION_STARTED :
  6397. ds = "Integrated Raid: Replace Action Started";
  6398. break;
  6399. default:
  6400. ds = "Integrated Raid";
  6401. break;
  6402. }
  6403. break;
  6404. }
  6405. case MPI_EVENT_SCSI_DEVICE_STATUS_CHANGE:
  6406. ds = "SCSI Device Status Change";
  6407. break;
  6408. case MPI_EVENT_SAS_DEVICE_STATUS_CHANGE:
  6409. {
  6410. u8 id = (u8)(evData0);
  6411. u8 channel = (u8)(evData0 >> 8);
  6412. u8 ReasonCode = (u8)(evData0 >> 16);
  6413. switch (ReasonCode) {
  6414. case MPI_EVENT_SAS_DEV_STAT_RC_ADDED:
  6415. snprintf(evStr, EVENT_DESCR_STR_SZ,
  6416. "SAS Device Status Change: Added: "
  6417. "id=%d channel=%d", id, channel);
  6418. break;
  6419. case MPI_EVENT_SAS_DEV_STAT_RC_NOT_RESPONDING:
  6420. snprintf(evStr, EVENT_DESCR_STR_SZ,
  6421. "SAS Device Status Change: Deleted: "
  6422. "id=%d channel=%d", id, channel);
  6423. break;
  6424. case MPI_EVENT_SAS_DEV_STAT_RC_SMART_DATA:
  6425. snprintf(evStr, EVENT_DESCR_STR_SZ,
  6426. "SAS Device Status Change: SMART Data: "
  6427. "id=%d channel=%d", id, channel);
  6428. break;
  6429. case MPI_EVENT_SAS_DEV_STAT_RC_NO_PERSIST_ADDED:
  6430. snprintf(evStr, EVENT_DESCR_STR_SZ,
  6431. "SAS Device Status Change: No Persistency: "
  6432. "id=%d channel=%d", id, channel);
  6433. break;
  6434. case MPI_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED:
  6435. snprintf(evStr, EVENT_DESCR_STR_SZ,
  6436. "SAS Device Status Change: Unsupported Device "
  6437. "Discovered : id=%d channel=%d", id, channel);
  6438. break;
  6439. case MPI_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET:
  6440. snprintf(evStr, EVENT_DESCR_STR_SZ,
  6441. "SAS Device Status Change: Internal Device "
  6442. "Reset : id=%d channel=%d", id, channel);
  6443. break;
  6444. case MPI_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL:
  6445. snprintf(evStr, EVENT_DESCR_STR_SZ,
  6446. "SAS Device Status Change: Internal Task "
  6447. "Abort : id=%d channel=%d", id, channel);
  6448. break;
  6449. case MPI_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL:
  6450. snprintf(evStr, EVENT_DESCR_STR_SZ,
  6451. "SAS Device Status Change: Internal Abort "
  6452. "Task Set : id=%d channel=%d", id, channel);
  6453. break;
  6454. case MPI_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL:
  6455. snprintf(evStr, EVENT_DESCR_STR_SZ,
  6456. "SAS Device Status Change: Internal Clear "
  6457. "Task Set : id=%d channel=%d", id, channel);
  6458. break;
  6459. case MPI_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL:
  6460. snprintf(evStr, EVENT_DESCR_STR_SZ,
  6461. "SAS Device Status Change: Internal Query "
  6462. "Task : id=%d channel=%d", id, channel);
  6463. break;
  6464. default:
  6465. snprintf(evStr, EVENT_DESCR_STR_SZ,
  6466. "SAS Device Status Change: Unknown: "
  6467. "id=%d channel=%d", id, channel);
  6468. break;
  6469. }
  6470. break;
  6471. }
  6472. case MPI_EVENT_ON_BUS_TIMER_EXPIRED:
  6473. ds = "Bus Timer Expired";
  6474. break;
  6475. case MPI_EVENT_QUEUE_FULL:
  6476. {
  6477. u16 curr_depth = (u16)(evData0 >> 16);
  6478. u8 channel = (u8)(evData0 >> 8);
  6479. u8 id = (u8)(evData0);
  6480. snprintf(evStr, EVENT_DESCR_STR_SZ,
  6481. "Queue Full: channel=%d id=%d depth=%d",
  6482. channel, id, curr_depth);
  6483. break;
  6484. }
  6485. case MPI_EVENT_SAS_SES:
  6486. ds = "SAS SES Event";
  6487. break;
  6488. case MPI_EVENT_PERSISTENT_TABLE_FULL:
  6489. ds = "Persistent Table Full";
  6490. break;
  6491. case MPI_EVENT_SAS_PHY_LINK_STATUS:
  6492. {
  6493. u8 LinkRates = (u8)(evData0 >> 8);
  6494. u8 PhyNumber = (u8)(evData0);
  6495. LinkRates = (LinkRates & MPI_EVENT_SAS_PLS_LR_CURRENT_MASK) >>
  6496. MPI_EVENT_SAS_PLS_LR_CURRENT_SHIFT;
  6497. switch (LinkRates) {
  6498. case MPI_EVENT_SAS_PLS_LR_RATE_UNKNOWN:
  6499. snprintf(evStr, EVENT_DESCR_STR_SZ,
  6500. "SAS PHY Link Status: Phy=%d:"
  6501. " Rate Unknown",PhyNumber);
  6502. break;
  6503. case MPI_EVENT_SAS_PLS_LR_RATE_PHY_DISABLED:
  6504. snprintf(evStr, EVENT_DESCR_STR_SZ,
  6505. "SAS PHY Link Status: Phy=%d:"
  6506. " Phy Disabled",PhyNumber);
  6507. break;
  6508. case MPI_EVENT_SAS_PLS_LR_RATE_FAILED_SPEED_NEGOTIATION:
  6509. snprintf(evStr, EVENT_DESCR_STR_SZ,
  6510. "SAS PHY Link Status: Phy=%d:"
  6511. " Failed Speed Nego",PhyNumber);
  6512. break;
  6513. case MPI_EVENT_SAS_PLS_LR_RATE_SATA_OOB_COMPLETE:
  6514. snprintf(evStr, EVENT_DESCR_STR_SZ,
  6515. "SAS PHY Link Status: Phy=%d:"
  6516. " Sata OOB Completed",PhyNumber);
  6517. break;
  6518. case MPI_EVENT_SAS_PLS_LR_RATE_1_5:
  6519. snprintf(evStr, EVENT_DESCR_STR_SZ,
  6520. "SAS PHY Link Status: Phy=%d:"
  6521. " Rate 1.5 Gbps",PhyNumber);
  6522. break;
  6523. case MPI_EVENT_SAS_PLS_LR_RATE_3_0:
  6524. snprintf(evStr, EVENT_DESCR_STR_SZ,
  6525. "SAS PHY Link Status: Phy=%d:"
  6526. " Rate 3.0 Gbps", PhyNumber);
  6527. break;
  6528. case MPI_EVENT_SAS_PLS_LR_RATE_6_0:
  6529. snprintf(evStr, EVENT_DESCR_STR_SZ,
  6530. "SAS PHY Link Status: Phy=%d:"
  6531. " Rate 6.0 Gbps", PhyNumber);
  6532. break;
  6533. default:
  6534. snprintf(evStr, EVENT_DESCR_STR_SZ,
  6535. "SAS PHY Link Status: Phy=%d", PhyNumber);
  6536. break;
  6537. }
  6538. break;
  6539. }
  6540. case MPI_EVENT_SAS_DISCOVERY_ERROR:
  6541. ds = "SAS Discovery Error";
  6542. break;
  6543. case MPI_EVENT_IR_RESYNC_UPDATE:
  6544. {
  6545. u8 resync_complete = (u8)(evData0 >> 16);
  6546. snprintf(evStr, EVENT_DESCR_STR_SZ,
  6547. "IR Resync Update: Complete = %d:",resync_complete);
  6548. break;
  6549. }
  6550. case MPI_EVENT_IR2:
  6551. {
  6552. u8 id = (u8)(evData0);
  6553. u8 channel = (u8)(evData0 >> 8);
  6554. u8 phys_num = (u8)(evData0 >> 24);
  6555. u8 ReasonCode = (u8)(evData0 >> 16);
  6556. switch (ReasonCode) {
  6557. case MPI_EVENT_IR2_RC_LD_STATE_CHANGED:
  6558. snprintf(evStr, EVENT_DESCR_STR_SZ,
  6559. "IR2: LD State Changed: "
  6560. "id=%d channel=%d phys_num=%d",
  6561. id, channel, phys_num);
  6562. break;
  6563. case MPI_EVENT_IR2_RC_PD_STATE_CHANGED:
  6564. snprintf(evStr, EVENT_DESCR_STR_SZ,
  6565. "IR2: PD State Changed "
  6566. "id=%d channel=%d phys_num=%d",
  6567. id, channel, phys_num);
  6568. break;
  6569. case MPI_EVENT_IR2_RC_BAD_BLOCK_TABLE_FULL:
  6570. snprintf(evStr, EVENT_DESCR_STR_SZ,
  6571. "IR2: Bad Block Table Full: "
  6572. "id=%d channel=%d phys_num=%d",
  6573. id, channel, phys_num);
  6574. break;
  6575. case MPI_EVENT_IR2_RC_PD_INSERTED:
  6576. snprintf(evStr, EVENT_DESCR_STR_SZ,
  6577. "IR2: PD Inserted: "
  6578. "id=%d channel=%d phys_num=%d",
  6579. id, channel, phys_num);
  6580. break;
  6581. case MPI_EVENT_IR2_RC_PD_REMOVED:
  6582. snprintf(evStr, EVENT_DESCR_STR_SZ,
  6583. "IR2: PD Removed: "
  6584. "id=%d channel=%d phys_num=%d",
  6585. id, channel, phys_num);
  6586. break;
  6587. case MPI_EVENT_IR2_RC_FOREIGN_CFG_DETECTED:
  6588. snprintf(evStr, EVENT_DESCR_STR_SZ,
  6589. "IR2: Foreign CFG Detected: "
  6590. "id=%d channel=%d phys_num=%d",
  6591. id, channel, phys_num);
  6592. break;
  6593. case MPI_EVENT_IR2_RC_REBUILD_MEDIUM_ERROR:
  6594. snprintf(evStr, EVENT_DESCR_STR_SZ,
  6595. "IR2: Rebuild Medium Error: "
  6596. "id=%d channel=%d phys_num=%d",
  6597. id, channel, phys_num);
  6598. break;
  6599. case MPI_EVENT_IR2_RC_DUAL_PORT_ADDED:
  6600. snprintf(evStr, EVENT_DESCR_STR_SZ,
  6601. "IR2: Dual Port Added: "
  6602. "id=%d channel=%d phys_num=%d",
  6603. id, channel, phys_num);
  6604. break;
  6605. case MPI_EVENT_IR2_RC_DUAL_PORT_REMOVED:
  6606. snprintf(evStr, EVENT_DESCR_STR_SZ,
  6607. "IR2: Dual Port Removed: "
  6608. "id=%d channel=%d phys_num=%d",
  6609. id, channel, phys_num);
  6610. break;
  6611. default:
  6612. ds = "IR2";
  6613. break;
  6614. }
  6615. break;
  6616. }
  6617. case MPI_EVENT_SAS_DISCOVERY:
  6618. {
  6619. if (evData0)
  6620. ds = "SAS Discovery: Start";
  6621. else
  6622. ds = "SAS Discovery: Stop";
  6623. break;
  6624. }
  6625. case MPI_EVENT_LOG_ENTRY_ADDED:
  6626. ds = "SAS Log Entry Added";
  6627. break;
  6628. case MPI_EVENT_SAS_BROADCAST_PRIMITIVE:
  6629. {
  6630. u8 phy_num = (u8)(evData0);
  6631. u8 port_num = (u8)(evData0 >> 8);
  6632. u8 port_width = (u8)(evData0 >> 16);
  6633. u8 primitive = (u8)(evData0 >> 24);
  6634. snprintf(evStr, EVENT_DESCR_STR_SZ,
  6635. "SAS Broadcast Primitive: phy=%d port=%d "
  6636. "width=%d primitive=0x%02x",
  6637. phy_num, port_num, port_width, primitive);
  6638. break;
  6639. }
  6640. case MPI_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE:
  6641. {
  6642. u8 reason = (u8)(evData0);
  6643. switch (reason) {
  6644. case MPI_EVENT_SAS_INIT_RC_ADDED:
  6645. ds = "SAS Initiator Status Change: Added";
  6646. break;
  6647. case MPI_EVENT_SAS_INIT_RC_REMOVED:
  6648. ds = "SAS Initiator Status Change: Deleted";
  6649. break;
  6650. default:
  6651. ds = "SAS Initiator Status Change";
  6652. break;
  6653. }
  6654. break;
  6655. }
  6656. case MPI_EVENT_SAS_INIT_TABLE_OVERFLOW:
  6657. {
  6658. u8 max_init = (u8)(evData0);
  6659. u8 current_init = (u8)(evData0 >> 8);
  6660. snprintf(evStr, EVENT_DESCR_STR_SZ,
  6661. "SAS Initiator Device Table Overflow: max initiators=%02d "
  6662. "current initiators=%02d",
  6663. max_init, current_init);
  6664. break;
  6665. }
  6666. case MPI_EVENT_SAS_SMP_ERROR:
  6667. {
  6668. u8 status = (u8)(evData0);
  6669. u8 port_num = (u8)(evData0 >> 8);
  6670. u8 result = (u8)(evData0 >> 16);
  6671. if (status == MPI_EVENT_SAS_SMP_FUNCTION_RESULT_VALID)
  6672. snprintf(evStr, EVENT_DESCR_STR_SZ,
  6673. "SAS SMP Error: port=%d result=0x%02x",
  6674. port_num, result);
  6675. else if (status == MPI_EVENT_SAS_SMP_CRC_ERROR)
  6676. snprintf(evStr, EVENT_DESCR_STR_SZ,
  6677. "SAS SMP Error: port=%d : CRC Error",
  6678. port_num);
  6679. else if (status == MPI_EVENT_SAS_SMP_TIMEOUT)
  6680. snprintf(evStr, EVENT_DESCR_STR_SZ,
  6681. "SAS SMP Error: port=%d : Timeout",
  6682. port_num);
  6683. else if (status == MPI_EVENT_SAS_SMP_NO_DESTINATION)
  6684. snprintf(evStr, EVENT_DESCR_STR_SZ,
  6685. "SAS SMP Error: port=%d : No Destination",
  6686. port_num);
  6687. else if (status == MPI_EVENT_SAS_SMP_BAD_DESTINATION)
  6688. snprintf(evStr, EVENT_DESCR_STR_SZ,
  6689. "SAS SMP Error: port=%d : Bad Destination",
  6690. port_num);
  6691. else
  6692. snprintf(evStr, EVENT_DESCR_STR_SZ,
  6693. "SAS SMP Error: port=%d : status=0x%02x",
  6694. port_num, status);
  6695. break;
  6696. }
  6697. case MPI_EVENT_SAS_EXPANDER_STATUS_CHANGE:
  6698. {
  6699. u8 reason = (u8)(evData0);
  6700. switch (reason) {
  6701. case MPI_EVENT_SAS_EXP_RC_ADDED:
  6702. ds = "Expander Status Change: Added";
  6703. break;
  6704. case MPI_EVENT_SAS_EXP_RC_NOT_RESPONDING:
  6705. ds = "Expander Status Change: Deleted";
  6706. break;
  6707. default:
  6708. ds = "Expander Status Change";
  6709. break;
  6710. }
  6711. break;
  6712. }
  6713. /*
  6714. * MPT base "custom" events may be added here...
  6715. */
  6716. default:
  6717. ds = "Unknown";
  6718. break;
  6719. }
  6720. if (ds)
  6721. strlcpy(evStr, ds, EVENT_DESCR_STR_SZ);
  6722. devtprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  6723. "MPT event:(%02Xh) : %s\n",
  6724. ioc->name, event, evStr));
  6725. devtverboseprintk(ioc, printk(KERN_DEBUG MYNAM
  6726. ": Event data:\n"));
  6727. for (ii = 0; ii < le16_to_cpu(pEventReply->EventDataLength); ii++)
  6728. devtverboseprintk(ioc, printk(" %08x",
  6729. le32_to_cpu(pEventReply->Data[ii])));
  6730. devtverboseprintk(ioc, printk(KERN_DEBUG "\n"));
  6731. }
  6732. #endif
  6733. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  6734. /**
  6735. * ProcessEventNotification - Route EventNotificationReply to all event handlers
  6736. * @ioc: Pointer to MPT_ADAPTER structure
  6737. * @pEventReply: Pointer to EventNotification reply frame
  6738. * @evHandlers: Pointer to integer, number of event handlers
  6739. *
  6740. * Routes a received EventNotificationReply to all currently registered
  6741. * event handlers.
  6742. * Returns sum of event handlers return values.
  6743. */
  6744. static int
  6745. ProcessEventNotification(MPT_ADAPTER *ioc, EventNotificationReply_t *pEventReply, int *evHandlers)
  6746. {
  6747. u16 evDataLen;
  6748. u32 evData0 = 0;
  6749. int ii;
  6750. u8 cb_idx;
  6751. int r = 0;
  6752. int handlers = 0;
  6753. u8 event;
  6754. /*
  6755. * Do platform normalization of values
  6756. */
  6757. event = le32_to_cpu(pEventReply->Event) & 0xFF;
  6758. evDataLen = le16_to_cpu(pEventReply->EventDataLength);
  6759. if (evDataLen) {
  6760. evData0 = le32_to_cpu(pEventReply->Data[0]);
  6761. }
  6762. #ifdef CONFIG_FUSION_LOGGING
  6763. if (evDataLen)
  6764. mpt_display_event_info(ioc, pEventReply);
  6765. #endif
  6766. /*
  6767. * Do general / base driver event processing
  6768. */
  6769. switch(event) {
  6770. case MPI_EVENT_EVENT_CHANGE: /* 0A */
  6771. if (evDataLen) {
  6772. u8 evState = evData0 & 0xFF;
  6773. /* CHECKME! What if evState unexpectedly says OFF (0)? */
  6774. /* Update EventState field in cached IocFacts */
  6775. if (ioc->facts.Function) {
  6776. ioc->facts.EventState = evState;
  6777. }
  6778. }
  6779. break;
  6780. case MPI_EVENT_INTEGRATED_RAID:
  6781. mptbase_raid_process_event_data(ioc,
  6782. (MpiEventDataRaid_t *)pEventReply->Data);
  6783. break;
  6784. default:
  6785. break;
  6786. }
  6787. /*
  6788. * Should this event be logged? Events are written sequentially.
  6789. * When buffer is full, start again at the top.
  6790. */
  6791. if (ioc->events && (ioc->eventTypes & ( 1 << event))) {
  6792. int idx;
  6793. idx = ioc->eventContext % MPTCTL_EVENT_LOG_SIZE;
  6794. ioc->events[idx].event = event;
  6795. ioc->events[idx].eventContext = ioc->eventContext;
  6796. for (ii = 0; ii < 2; ii++) {
  6797. if (ii < evDataLen)
  6798. ioc->events[idx].data[ii] = le32_to_cpu(pEventReply->Data[ii]);
  6799. else
  6800. ioc->events[idx].data[ii] = 0;
  6801. }
  6802. ioc->eventContext++;
  6803. }
  6804. /*
  6805. * Call each currently registered protocol event handler.
  6806. */
  6807. for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
  6808. if (MptEvHandlers[cb_idx]) {
  6809. devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  6810. "Routing Event to event handler #%d\n",
  6811. ioc->name, cb_idx));
  6812. r += (*(MptEvHandlers[cb_idx]))(ioc, pEventReply);
  6813. handlers++;
  6814. }
  6815. }
  6816. /* FIXME? Examine results here? */
  6817. /*
  6818. * If needed, send (a single) EventAck.
  6819. */
  6820. if (pEventReply->AckRequired == MPI_EVENT_NOTIFICATION_ACK_REQUIRED) {
  6821. devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT
  6822. "EventAck required\n",ioc->name));
  6823. if ((ii = SendEventAck(ioc, pEventReply)) != 0) {
  6824. devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT "SendEventAck returned %d\n",
  6825. ioc->name, ii));
  6826. }
  6827. }
  6828. *evHandlers = handlers;
  6829. return r;
  6830. }
  6831. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  6832. /**
  6833. * mpt_fc_log_info - Log information returned from Fibre Channel IOC.
  6834. * @ioc: Pointer to MPT_ADAPTER structure
  6835. * @log_info: U32 LogInfo reply word from the IOC
  6836. *
  6837. * Refer to lsi/mpi_log_fc.h.
  6838. */
  6839. static void
  6840. mpt_fc_log_info(MPT_ADAPTER *ioc, u32 log_info)
  6841. {
  6842. char *desc = "unknown";
  6843. switch (log_info & 0xFF000000) {
  6844. case MPI_IOCLOGINFO_FC_INIT_BASE:
  6845. desc = "FCP Initiator";
  6846. break;
  6847. case MPI_IOCLOGINFO_FC_TARGET_BASE:
  6848. desc = "FCP Target";
  6849. break;
  6850. case MPI_IOCLOGINFO_FC_LAN_BASE:
  6851. desc = "LAN";
  6852. break;
  6853. case MPI_IOCLOGINFO_FC_MSG_BASE:
  6854. desc = "MPI Message Layer";
  6855. break;
  6856. case MPI_IOCLOGINFO_FC_LINK_BASE:
  6857. desc = "FC Link";
  6858. break;
  6859. case MPI_IOCLOGINFO_FC_CTX_BASE:
  6860. desc = "Context Manager";
  6861. break;
  6862. case MPI_IOCLOGINFO_FC_INVALID_FIELD_BYTE_OFFSET:
  6863. desc = "Invalid Field Offset";
  6864. break;
  6865. case MPI_IOCLOGINFO_FC_STATE_CHANGE:
  6866. desc = "State Change Info";
  6867. break;
  6868. }
  6869. printk(MYIOC_s_INFO_FMT "LogInfo(0x%08x): SubClass={%s}, Value=(0x%06x)\n",
  6870. ioc->name, log_info, desc, (log_info & 0xFFFFFF));
  6871. }
  6872. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  6873. /**
  6874. * mpt_spi_log_info - Log information returned from SCSI Parallel IOC.
  6875. * @ioc: Pointer to MPT_ADAPTER structure
  6876. * @log_info: U32 LogInfo word from the IOC
  6877. *
  6878. * Refer to lsi/sp_log.h.
  6879. */
  6880. static void
  6881. mpt_spi_log_info(MPT_ADAPTER *ioc, u32 log_info)
  6882. {
  6883. u32 info = log_info & 0x00FF0000;
  6884. char *desc = "unknown";
  6885. switch (info) {
  6886. case 0x00010000:
  6887. desc = "bug! MID not found";
  6888. break;
  6889. case 0x00020000:
  6890. desc = "Parity Error";
  6891. break;
  6892. case 0x00030000:
  6893. desc = "ASYNC Outbound Overrun";
  6894. break;
  6895. case 0x00040000:
  6896. desc = "SYNC Offset Error";
  6897. break;
  6898. case 0x00050000:
  6899. desc = "BM Change";
  6900. break;
  6901. case 0x00060000:
  6902. desc = "Msg In Overflow";
  6903. break;
  6904. case 0x00070000:
  6905. desc = "DMA Error";
  6906. break;
  6907. case 0x00080000:
  6908. desc = "Outbound DMA Overrun";
  6909. break;
  6910. case 0x00090000:
  6911. desc = "Task Management";
  6912. break;
  6913. case 0x000A0000:
  6914. desc = "Device Problem";
  6915. break;
  6916. case 0x000B0000:
  6917. desc = "Invalid Phase Change";
  6918. break;
  6919. case 0x000C0000:
  6920. desc = "Untagged Table Size";
  6921. break;
  6922. }
  6923. printk(MYIOC_s_INFO_FMT "LogInfo(0x%08x): F/W: %s\n", ioc->name, log_info, desc);
  6924. }
  6925. /* strings for sas loginfo */
  6926. static char *originator_str[] = {
  6927. "IOP", /* 00h */
  6928. "PL", /* 01h */
  6929. "IR" /* 02h */
  6930. };
  6931. static char *iop_code_str[] = {
  6932. NULL, /* 00h */
  6933. "Invalid SAS Address", /* 01h */
  6934. NULL, /* 02h */
  6935. "Invalid Page", /* 03h */
  6936. "Diag Message Error", /* 04h */
  6937. "Task Terminated", /* 05h */
  6938. "Enclosure Management", /* 06h */
  6939. "Target Mode" /* 07h */
  6940. };
  6941. static char *pl_code_str[] = {
  6942. NULL, /* 00h */
  6943. "Open Failure", /* 01h */
  6944. "Invalid Scatter Gather List", /* 02h */
  6945. "Wrong Relative Offset or Frame Length", /* 03h */
  6946. "Frame Transfer Error", /* 04h */
  6947. "Transmit Frame Connected Low", /* 05h */
  6948. "SATA Non-NCQ RW Error Bit Set", /* 06h */
  6949. "SATA Read Log Receive Data Error", /* 07h */
  6950. "SATA NCQ Fail All Commands After Error", /* 08h */
  6951. "SATA Error in Receive Set Device Bit FIS", /* 09h */
  6952. "Receive Frame Invalid Message", /* 0Ah */
  6953. "Receive Context Message Valid Error", /* 0Bh */
  6954. "Receive Frame Current Frame Error", /* 0Ch */
  6955. "SATA Link Down", /* 0Dh */
  6956. "Discovery SATA Init W IOS", /* 0Eh */
  6957. "Config Invalid Page", /* 0Fh */
  6958. "Discovery SATA Init Timeout", /* 10h */
  6959. "Reset", /* 11h */
  6960. "Abort", /* 12h */
  6961. "IO Not Yet Executed", /* 13h */
  6962. "IO Executed", /* 14h */
  6963. "Persistent Reservation Out Not Affiliation "
  6964. "Owner", /* 15h */
  6965. "Open Transmit DMA Abort", /* 16h */
  6966. "IO Device Missing Delay Retry", /* 17h */
  6967. "IO Cancelled Due to Receive Error", /* 18h */
  6968. NULL, /* 19h */
  6969. NULL, /* 1Ah */
  6970. NULL, /* 1Bh */
  6971. NULL, /* 1Ch */
  6972. NULL, /* 1Dh */
  6973. NULL, /* 1Eh */
  6974. NULL, /* 1Fh */
  6975. "Enclosure Management" /* 20h */
  6976. };
  6977. static char *ir_code_str[] = {
  6978. "Raid Action Error", /* 00h */
  6979. NULL, /* 00h */
  6980. NULL, /* 01h */
  6981. NULL, /* 02h */
  6982. NULL, /* 03h */
  6983. NULL, /* 04h */
  6984. NULL, /* 05h */
  6985. NULL, /* 06h */
  6986. NULL /* 07h */
  6987. };
  6988. static char *raid_sub_code_str[] = {
  6989. NULL, /* 00h */
  6990. "Volume Creation Failed: Data Passed too "
  6991. "Large", /* 01h */
  6992. "Volume Creation Failed: Duplicate Volumes "
  6993. "Attempted", /* 02h */
  6994. "Volume Creation Failed: Max Number "
  6995. "Supported Volumes Exceeded", /* 03h */
  6996. "Volume Creation Failed: DMA Error", /* 04h */
  6997. "Volume Creation Failed: Invalid Volume Type", /* 05h */
  6998. "Volume Creation Failed: Error Reading "
  6999. "MFG Page 4", /* 06h */
  7000. "Volume Creation Failed: Creating Internal "
  7001. "Structures", /* 07h */
  7002. NULL, /* 08h */
  7003. NULL, /* 09h */
  7004. NULL, /* 0Ah */
  7005. NULL, /* 0Bh */
  7006. NULL, /* 0Ch */
  7007. NULL, /* 0Dh */
  7008. NULL, /* 0Eh */
  7009. NULL, /* 0Fh */
  7010. "Activation failed: Already Active Volume", /* 10h */
  7011. "Activation failed: Unsupported Volume Type", /* 11h */
  7012. "Activation failed: Too Many Active Volumes", /* 12h */
  7013. "Activation failed: Volume ID in Use", /* 13h */
  7014. "Activation failed: Reported Failure", /* 14h */
  7015. "Activation failed: Importing a Volume", /* 15h */
  7016. NULL, /* 16h */
  7017. NULL, /* 17h */
  7018. NULL, /* 18h */
  7019. NULL, /* 19h */
  7020. NULL, /* 1Ah */
  7021. NULL, /* 1Bh */
  7022. NULL, /* 1Ch */
  7023. NULL, /* 1Dh */
  7024. NULL, /* 1Eh */
  7025. NULL, /* 1Fh */
  7026. "Phys Disk failed: Too Many Phys Disks", /* 20h */
  7027. "Phys Disk failed: Data Passed too Large", /* 21h */
  7028. "Phys Disk failed: DMA Error", /* 22h */
  7029. "Phys Disk failed: Invalid <channel:id>", /* 23h */
  7030. "Phys Disk failed: Creating Phys Disk Config "
  7031. "Page", /* 24h */
  7032. NULL, /* 25h */
  7033. NULL, /* 26h */
  7034. NULL, /* 27h */
  7035. NULL, /* 28h */
  7036. NULL, /* 29h */
  7037. NULL, /* 2Ah */
  7038. NULL, /* 2Bh */
  7039. NULL, /* 2Ch */
  7040. NULL, /* 2Dh */
  7041. NULL, /* 2Eh */
  7042. NULL, /* 2Fh */
  7043. "Compatibility Error: IR Disabled", /* 30h */
  7044. "Compatibility Error: Inquiry Command Failed", /* 31h */
  7045. "Compatibility Error: Device not Direct Access "
  7046. "Device ", /* 32h */
  7047. "Compatibility Error: Removable Device Found", /* 33h */
  7048. "Compatibility Error: Device SCSI Version not "
  7049. "2 or Higher", /* 34h */
  7050. "Compatibility Error: SATA Device, 48 BIT LBA "
  7051. "not Supported", /* 35h */
  7052. "Compatibility Error: Device doesn't have "
  7053. "512 Byte Block Sizes", /* 36h */
  7054. "Compatibility Error: Volume Type Check Failed", /* 37h */
  7055. "Compatibility Error: Volume Type is "
  7056. "Unsupported by FW", /* 38h */
  7057. "Compatibility Error: Disk Drive too Small for "
  7058. "use in Volume", /* 39h */
  7059. "Compatibility Error: Phys Disk for Create "
  7060. "Volume not Found", /* 3Ah */
  7061. "Compatibility Error: Too Many or too Few "
  7062. "Disks for Volume Type", /* 3Bh */
  7063. "Compatibility Error: Disk stripe Sizes "
  7064. "Must be 64KB", /* 3Ch */
  7065. "Compatibility Error: IME Size Limited to < 2TB", /* 3Dh */
  7066. };
  7067. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  7068. /**
  7069. * mpt_sas_log_info - Log information returned from SAS IOC.
  7070. * @ioc: Pointer to MPT_ADAPTER structure
  7071. * @log_info: U32 LogInfo reply word from the IOC
  7072. * @cb_idx: callback function's handle
  7073. *
  7074. * Refer to lsi/mpi_log_sas.h.
  7075. **/
  7076. static void
  7077. mpt_sas_log_info(MPT_ADAPTER *ioc, u32 log_info, u8 cb_idx)
  7078. {
  7079. union loginfo_type {
  7080. u32 loginfo;
  7081. struct {
  7082. u32 subcode:16;
  7083. u32 code:8;
  7084. u32 originator:4;
  7085. u32 bus_type:4;
  7086. } dw;
  7087. };
  7088. union loginfo_type sas_loginfo;
  7089. char *originator_desc = NULL;
  7090. char *code_desc = NULL;
  7091. char *sub_code_desc = NULL;
  7092. sas_loginfo.loginfo = log_info;
  7093. if ((sas_loginfo.dw.bus_type != 3 /*SAS*/) &&
  7094. (sas_loginfo.dw.originator < ARRAY_SIZE(originator_str)))
  7095. return;
  7096. originator_desc = originator_str[sas_loginfo.dw.originator];
  7097. switch (sas_loginfo.dw.originator) {
  7098. case 0: /* IOP */
  7099. if (sas_loginfo.dw.code <
  7100. ARRAY_SIZE(iop_code_str))
  7101. code_desc = iop_code_str[sas_loginfo.dw.code];
  7102. break;
  7103. case 1: /* PL */
  7104. if (sas_loginfo.dw.code <
  7105. ARRAY_SIZE(pl_code_str))
  7106. code_desc = pl_code_str[sas_loginfo.dw.code];
  7107. break;
  7108. case 2: /* IR */
  7109. if (sas_loginfo.dw.code >=
  7110. ARRAY_SIZE(ir_code_str))
  7111. break;
  7112. code_desc = ir_code_str[sas_loginfo.dw.code];
  7113. if (sas_loginfo.dw.subcode >=
  7114. ARRAY_SIZE(raid_sub_code_str))
  7115. break;
  7116. if (sas_loginfo.dw.code == 0)
  7117. sub_code_desc =
  7118. raid_sub_code_str[sas_loginfo.dw.subcode];
  7119. break;
  7120. default:
  7121. return;
  7122. }
  7123. if (sub_code_desc != NULL)
  7124. printk(MYIOC_s_INFO_FMT
  7125. "LogInfo(0x%08x): Originator={%s}, Code={%s},"
  7126. " SubCode={%s} cb_idx %s\n",
  7127. ioc->name, log_info, originator_desc, code_desc,
  7128. sub_code_desc, MptCallbacksName[cb_idx]);
  7129. else if (code_desc != NULL)
  7130. printk(MYIOC_s_INFO_FMT
  7131. "LogInfo(0x%08x): Originator={%s}, Code={%s},"
  7132. " SubCode(0x%04x) cb_idx %s\n",
  7133. ioc->name, log_info, originator_desc, code_desc,
  7134. sas_loginfo.dw.subcode, MptCallbacksName[cb_idx]);
  7135. else
  7136. printk(MYIOC_s_INFO_FMT
  7137. "LogInfo(0x%08x): Originator={%s}, Code=(0x%02x),"
  7138. " SubCode(0x%04x) cb_idx %s\n",
  7139. ioc->name, log_info, originator_desc,
  7140. sas_loginfo.dw.code, sas_loginfo.dw.subcode,
  7141. MptCallbacksName[cb_idx]);
  7142. }
  7143. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  7144. /**
  7145. * mpt_iocstatus_info_config - IOCSTATUS information for config pages
  7146. * @ioc: Pointer to MPT_ADAPTER structure
  7147. * @ioc_status: U32 IOCStatus word from IOC
  7148. * @mf: Pointer to MPT request frame
  7149. *
  7150. * Refer to lsi/mpi.h.
  7151. **/
  7152. static void
  7153. mpt_iocstatus_info_config(MPT_ADAPTER *ioc, u32 ioc_status, MPT_FRAME_HDR *mf)
  7154. {
  7155. Config_t *pReq = (Config_t *)mf;
  7156. char extend_desc[EVENT_DESCR_STR_SZ];
  7157. char *desc = NULL;
  7158. u32 form;
  7159. u8 page_type;
  7160. if (pReq->Header.PageType == MPI_CONFIG_PAGETYPE_EXTENDED)
  7161. page_type = pReq->ExtPageType;
  7162. else
  7163. page_type = pReq->Header.PageType;
  7164. /*
  7165. * ignore invalid page messages for GET_NEXT_HANDLE
  7166. */
  7167. form = le32_to_cpu(pReq->PageAddress);
  7168. if (ioc_status == MPI_IOCSTATUS_CONFIG_INVALID_PAGE) {
  7169. if (page_type == MPI_CONFIG_EXTPAGETYPE_SAS_DEVICE ||
  7170. page_type == MPI_CONFIG_EXTPAGETYPE_SAS_EXPANDER ||
  7171. page_type == MPI_CONFIG_EXTPAGETYPE_ENCLOSURE) {
  7172. if ((form >> MPI_SAS_DEVICE_PGAD_FORM_SHIFT) ==
  7173. MPI_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE)
  7174. return;
  7175. }
  7176. if (page_type == MPI_CONFIG_PAGETYPE_FC_DEVICE)
  7177. if ((form & MPI_FC_DEVICE_PGAD_FORM_MASK) ==
  7178. MPI_FC_DEVICE_PGAD_FORM_NEXT_DID)
  7179. return;
  7180. }
  7181. snprintf(extend_desc, EVENT_DESCR_STR_SZ,
  7182. "type=%02Xh, page=%02Xh, action=%02Xh, form=%08Xh",
  7183. page_type, pReq->Header.PageNumber, pReq->Action, form);
  7184. switch (ioc_status) {
  7185. case MPI_IOCSTATUS_CONFIG_INVALID_ACTION: /* 0x0020 */
  7186. desc = "Config Page Invalid Action";
  7187. break;
  7188. case MPI_IOCSTATUS_CONFIG_INVALID_TYPE: /* 0x0021 */
  7189. desc = "Config Page Invalid Type";
  7190. break;
  7191. case MPI_IOCSTATUS_CONFIG_INVALID_PAGE: /* 0x0022 */
  7192. desc = "Config Page Invalid Page";
  7193. break;
  7194. case MPI_IOCSTATUS_CONFIG_INVALID_DATA: /* 0x0023 */
  7195. desc = "Config Page Invalid Data";
  7196. break;
  7197. case MPI_IOCSTATUS_CONFIG_NO_DEFAULTS: /* 0x0024 */
  7198. desc = "Config Page No Defaults";
  7199. break;
  7200. case MPI_IOCSTATUS_CONFIG_CANT_COMMIT: /* 0x0025 */
  7201. desc = "Config Page Can't Commit";
  7202. break;
  7203. }
  7204. if (!desc)
  7205. return;
  7206. dreplyprintk(ioc, printk(MYIOC_s_DEBUG_FMT "IOCStatus(0x%04X): %s: %s\n",
  7207. ioc->name, ioc_status, desc, extend_desc));
  7208. }
  7209. /**
  7210. * mpt_iocstatus_info - IOCSTATUS information returned from IOC.
  7211. * @ioc: Pointer to MPT_ADAPTER structure
  7212. * @ioc_status: U32 IOCStatus word from IOC
  7213. * @mf: Pointer to MPT request frame
  7214. *
  7215. * Refer to lsi/mpi.h.
  7216. **/
  7217. static void
  7218. mpt_iocstatus_info(MPT_ADAPTER *ioc, u32 ioc_status, MPT_FRAME_HDR *mf)
  7219. {
  7220. u32 status = ioc_status & MPI_IOCSTATUS_MASK;
  7221. char *desc = NULL;
  7222. switch (status) {
  7223. /****************************************************************************/
  7224. /* Common IOCStatus values for all replies */
  7225. /****************************************************************************/
  7226. case MPI_IOCSTATUS_INVALID_FUNCTION: /* 0x0001 */
  7227. desc = "Invalid Function";
  7228. break;
  7229. case MPI_IOCSTATUS_BUSY: /* 0x0002 */
  7230. desc = "Busy";
  7231. break;
  7232. case MPI_IOCSTATUS_INVALID_SGL: /* 0x0003 */
  7233. desc = "Invalid SGL";
  7234. break;
  7235. case MPI_IOCSTATUS_INTERNAL_ERROR: /* 0x0004 */
  7236. desc = "Internal Error";
  7237. break;
  7238. case MPI_IOCSTATUS_RESERVED: /* 0x0005 */
  7239. desc = "Reserved";
  7240. break;
  7241. case MPI_IOCSTATUS_INSUFFICIENT_RESOURCES: /* 0x0006 */
  7242. desc = "Insufficient Resources";
  7243. break;
  7244. case MPI_IOCSTATUS_INVALID_FIELD: /* 0x0007 */
  7245. desc = "Invalid Field";
  7246. break;
  7247. case MPI_IOCSTATUS_INVALID_STATE: /* 0x0008 */
  7248. desc = "Invalid State";
  7249. break;
  7250. /****************************************************************************/
  7251. /* Config IOCStatus values */
  7252. /****************************************************************************/
  7253. case MPI_IOCSTATUS_CONFIG_INVALID_ACTION: /* 0x0020 */
  7254. case MPI_IOCSTATUS_CONFIG_INVALID_TYPE: /* 0x0021 */
  7255. case MPI_IOCSTATUS_CONFIG_INVALID_PAGE: /* 0x0022 */
  7256. case MPI_IOCSTATUS_CONFIG_INVALID_DATA: /* 0x0023 */
  7257. case MPI_IOCSTATUS_CONFIG_NO_DEFAULTS: /* 0x0024 */
  7258. case MPI_IOCSTATUS_CONFIG_CANT_COMMIT: /* 0x0025 */
  7259. mpt_iocstatus_info_config(ioc, status, mf);
  7260. break;
  7261. /****************************************************************************/
  7262. /* SCSIIO Reply (SPI, FCP, SAS) initiator values */
  7263. /* */
  7264. /* Look at mptscsih_iocstatus_info_scsiio in mptscsih.c */
  7265. /* */
  7266. /****************************************************************************/
  7267. case MPI_IOCSTATUS_SCSI_RECOVERED_ERROR: /* 0x0040 */
  7268. case MPI_IOCSTATUS_SCSI_DATA_UNDERRUN: /* 0x0045 */
  7269. case MPI_IOCSTATUS_SCSI_INVALID_BUS: /* 0x0041 */
  7270. case MPI_IOCSTATUS_SCSI_INVALID_TARGETID: /* 0x0042 */
  7271. case MPI_IOCSTATUS_SCSI_DEVICE_NOT_THERE: /* 0x0043 */
  7272. case MPI_IOCSTATUS_SCSI_DATA_OVERRUN: /* 0x0044 */
  7273. case MPI_IOCSTATUS_SCSI_IO_DATA_ERROR: /* 0x0046 */
  7274. case MPI_IOCSTATUS_SCSI_PROTOCOL_ERROR: /* 0x0047 */
  7275. case MPI_IOCSTATUS_SCSI_TASK_TERMINATED: /* 0x0048 */
  7276. case MPI_IOCSTATUS_SCSI_RESIDUAL_MISMATCH: /* 0x0049 */
  7277. case MPI_IOCSTATUS_SCSI_TASK_MGMT_FAILED: /* 0x004A */
  7278. case MPI_IOCSTATUS_SCSI_IOC_TERMINATED: /* 0x004B */
  7279. case MPI_IOCSTATUS_SCSI_EXT_TERMINATED: /* 0x004C */
  7280. break;
  7281. /****************************************************************************/
  7282. /* SCSI Target values */
  7283. /****************************************************************************/
  7284. case MPI_IOCSTATUS_TARGET_PRIORITY_IO: /* 0x0060 */
  7285. desc = "Target: Priority IO";
  7286. break;
  7287. case MPI_IOCSTATUS_TARGET_INVALID_PORT: /* 0x0061 */
  7288. desc = "Target: Invalid Port";
  7289. break;
  7290. case MPI_IOCSTATUS_TARGET_INVALID_IO_INDEX: /* 0x0062 */
  7291. desc = "Target Invalid IO Index:";
  7292. break;
  7293. case MPI_IOCSTATUS_TARGET_ABORTED: /* 0x0063 */
  7294. desc = "Target: Aborted";
  7295. break;
  7296. case MPI_IOCSTATUS_TARGET_NO_CONN_RETRYABLE: /* 0x0064 */
  7297. desc = "Target: No Conn Retryable";
  7298. break;
  7299. case MPI_IOCSTATUS_TARGET_NO_CONNECTION: /* 0x0065 */
  7300. desc = "Target: No Connection";
  7301. break;
  7302. case MPI_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH: /* 0x006A */
  7303. desc = "Target: Transfer Count Mismatch";
  7304. break;
  7305. case MPI_IOCSTATUS_TARGET_STS_DATA_NOT_SENT: /* 0x006B */
  7306. desc = "Target: STS Data not Sent";
  7307. break;
  7308. case MPI_IOCSTATUS_TARGET_DATA_OFFSET_ERROR: /* 0x006D */
  7309. desc = "Target: Data Offset Error";
  7310. break;
  7311. case MPI_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA: /* 0x006E */
  7312. desc = "Target: Too Much Write Data";
  7313. break;
  7314. case MPI_IOCSTATUS_TARGET_IU_TOO_SHORT: /* 0x006F */
  7315. desc = "Target: IU Too Short";
  7316. break;
  7317. case MPI_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT: /* 0x0070 */
  7318. desc = "Target: ACK NAK Timeout";
  7319. break;
  7320. case MPI_IOCSTATUS_TARGET_NAK_RECEIVED: /* 0x0071 */
  7321. desc = "Target: Nak Received";
  7322. break;
  7323. /****************************************************************************/
  7324. /* Fibre Channel Direct Access values */
  7325. /****************************************************************************/
  7326. case MPI_IOCSTATUS_FC_ABORTED: /* 0x0066 */
  7327. desc = "FC: Aborted";
  7328. break;
  7329. case MPI_IOCSTATUS_FC_RX_ID_INVALID: /* 0x0067 */
  7330. desc = "FC: RX ID Invalid";
  7331. break;
  7332. case MPI_IOCSTATUS_FC_DID_INVALID: /* 0x0068 */
  7333. desc = "FC: DID Invalid";
  7334. break;
  7335. case MPI_IOCSTATUS_FC_NODE_LOGGED_OUT: /* 0x0069 */
  7336. desc = "FC: Node Logged Out";
  7337. break;
  7338. case MPI_IOCSTATUS_FC_EXCHANGE_CANCELED: /* 0x006C */
  7339. desc = "FC: Exchange Canceled";
  7340. break;
  7341. /****************************************************************************/
  7342. /* LAN values */
  7343. /****************************************************************************/
  7344. case MPI_IOCSTATUS_LAN_DEVICE_NOT_FOUND: /* 0x0080 */
  7345. desc = "LAN: Device not Found";
  7346. break;
  7347. case MPI_IOCSTATUS_LAN_DEVICE_FAILURE: /* 0x0081 */
  7348. desc = "LAN: Device Failure";
  7349. break;
  7350. case MPI_IOCSTATUS_LAN_TRANSMIT_ERROR: /* 0x0082 */
  7351. desc = "LAN: Transmit Error";
  7352. break;
  7353. case MPI_IOCSTATUS_LAN_TRANSMIT_ABORTED: /* 0x0083 */
  7354. desc = "LAN: Transmit Aborted";
  7355. break;
  7356. case MPI_IOCSTATUS_LAN_RECEIVE_ERROR: /* 0x0084 */
  7357. desc = "LAN: Receive Error";
  7358. break;
  7359. case MPI_IOCSTATUS_LAN_RECEIVE_ABORTED: /* 0x0085 */
  7360. desc = "LAN: Receive Aborted";
  7361. break;
  7362. case MPI_IOCSTATUS_LAN_PARTIAL_PACKET: /* 0x0086 */
  7363. desc = "LAN: Partial Packet";
  7364. break;
  7365. case MPI_IOCSTATUS_LAN_CANCELED: /* 0x0087 */
  7366. desc = "LAN: Canceled";
  7367. break;
  7368. /****************************************************************************/
  7369. /* Serial Attached SCSI values */
  7370. /****************************************************************************/
  7371. case MPI_IOCSTATUS_SAS_SMP_REQUEST_FAILED: /* 0x0090 */
  7372. desc = "SAS: SMP Request Failed";
  7373. break;
  7374. case MPI_IOCSTATUS_SAS_SMP_DATA_OVERRUN: /* 0x0090 */
  7375. desc = "SAS: SMP Data Overrun";
  7376. break;
  7377. default:
  7378. desc = "Others";
  7379. break;
  7380. }
  7381. if (!desc)
  7382. return;
  7383. dreplyprintk(ioc, printk(MYIOC_s_DEBUG_FMT "IOCStatus(0x%04X): %s\n",
  7384. ioc->name, status, desc));
  7385. }
  7386. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  7387. EXPORT_SYMBOL(mpt_attach);
  7388. EXPORT_SYMBOL(mpt_detach);
  7389. #ifdef CONFIG_PM
  7390. EXPORT_SYMBOL(mpt_resume);
  7391. EXPORT_SYMBOL(mpt_suspend);
  7392. #endif
  7393. EXPORT_SYMBOL(ioc_list);
  7394. EXPORT_SYMBOL(mpt_register);
  7395. EXPORT_SYMBOL(mpt_deregister);
  7396. EXPORT_SYMBOL(mpt_event_register);
  7397. EXPORT_SYMBOL(mpt_event_deregister);
  7398. EXPORT_SYMBOL(mpt_reset_register);
  7399. EXPORT_SYMBOL(mpt_reset_deregister);
  7400. EXPORT_SYMBOL(mpt_device_driver_register);
  7401. EXPORT_SYMBOL(mpt_device_driver_deregister);
  7402. EXPORT_SYMBOL(mpt_get_msg_frame);
  7403. EXPORT_SYMBOL(mpt_put_msg_frame);
  7404. EXPORT_SYMBOL(mpt_put_msg_frame_hi_pri);
  7405. EXPORT_SYMBOL(mpt_free_msg_frame);
  7406. EXPORT_SYMBOL(mpt_send_handshake_request);
  7407. EXPORT_SYMBOL(mpt_verify_adapter);
  7408. EXPORT_SYMBOL(mpt_GetIocState);
  7409. EXPORT_SYMBOL(mpt_print_ioc_summary);
  7410. EXPORT_SYMBOL(mpt_HardResetHandler);
  7411. EXPORT_SYMBOL(mpt_config);
  7412. EXPORT_SYMBOL(mpt_findImVolumes);
  7413. EXPORT_SYMBOL(mpt_alloc_fw_memory);
  7414. EXPORT_SYMBOL(mpt_free_fw_memory);
  7415. EXPORT_SYMBOL(mptbase_sas_persist_operation);
  7416. EXPORT_SYMBOL(mpt_raid_phys_disk_pg0);
  7417. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  7418. /**
  7419. * fusion_init - Fusion MPT base driver initialization routine.
  7420. *
  7421. * Returns 0 for success, non-zero for failure.
  7422. */
  7423. static int __init
  7424. fusion_init(void)
  7425. {
  7426. u8 cb_idx;
  7427. show_mptmod_ver(my_NAME, my_VERSION);
  7428. printk(KERN_INFO COPYRIGHT "\n");
  7429. for (cb_idx = 0; cb_idx < MPT_MAX_PROTOCOL_DRIVERS; cb_idx++) {
  7430. MptCallbacks[cb_idx] = NULL;
  7431. MptDriverClass[cb_idx] = MPTUNKNOWN_DRIVER;
  7432. MptEvHandlers[cb_idx] = NULL;
  7433. MptResetHandlers[cb_idx] = NULL;
  7434. }
  7435. /* Register ourselves (mptbase) in order to facilitate
  7436. * EventNotification handling.
  7437. */
  7438. mpt_base_index = mpt_register(mptbase_reply, MPTBASE_DRIVER,
  7439. "mptbase_reply");
  7440. /* Register for hard reset handling callbacks.
  7441. */
  7442. mpt_reset_register(mpt_base_index, mpt_ioc_reset);
  7443. #ifdef CONFIG_PROC_FS
  7444. (void) procmpt_create();
  7445. #endif
  7446. return 0;
  7447. }
  7448. /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
  7449. /**
  7450. * fusion_exit - Perform driver unload cleanup.
  7451. *
  7452. * This routine frees all resources associated with each MPT adapter
  7453. * and removes all %MPT_PROCFS_MPTBASEDIR entries.
  7454. */
  7455. static void __exit
  7456. fusion_exit(void)
  7457. {
  7458. mpt_reset_deregister(mpt_base_index);
  7459. #ifdef CONFIG_PROC_FS
  7460. procmpt_destroy();
  7461. #endif
  7462. }
  7463. module_init(fusion_init);
  7464. module_exit(fusion_exit);