ti-aemif.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * TI AEMIF driver
  4. *
  5. * Copyright (C) 2010 - 2013 Texas Instruments Incorporated. http://www.ti.com/
  6. *
  7. * Authors:
  8. * Murali Karicheri <m-karicheri2@ti.com>
  9. * Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
  10. */
  11. #include <linux/clk.h>
  12. #include <linux/err.h>
  13. #include <linux/io.h>
  14. #include <linux/kernel.h>
  15. #include <linux/module.h>
  16. #include <linux/of.h>
  17. #include <linux/of_platform.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/platform_data/ti-aemif.h>
  20. #define TA_SHIFT 2
  21. #define RHOLD_SHIFT 4
  22. #define RSTROBE_SHIFT 7
  23. #define RSETUP_SHIFT 13
  24. #define WHOLD_SHIFT 17
  25. #define WSTROBE_SHIFT 20
  26. #define WSETUP_SHIFT 26
  27. #define EW_SHIFT 30
  28. #define SSTROBE_SHIFT 31
  29. #define TA(x) ((x) << TA_SHIFT)
  30. #define RHOLD(x) ((x) << RHOLD_SHIFT)
  31. #define RSTROBE(x) ((x) << RSTROBE_SHIFT)
  32. #define RSETUP(x) ((x) << RSETUP_SHIFT)
  33. #define WHOLD(x) ((x) << WHOLD_SHIFT)
  34. #define WSTROBE(x) ((x) << WSTROBE_SHIFT)
  35. #define WSETUP(x) ((x) << WSETUP_SHIFT)
  36. #define EW(x) ((x) << EW_SHIFT)
  37. #define SSTROBE(x) ((x) << SSTROBE_SHIFT)
  38. #define ASIZE_MAX 0x1
  39. #define TA_MAX 0x3
  40. #define RHOLD_MAX 0x7
  41. #define RSTROBE_MAX 0x3f
  42. #define RSETUP_MAX 0xf
  43. #define WHOLD_MAX 0x7
  44. #define WSTROBE_MAX 0x3f
  45. #define WSETUP_MAX 0xf
  46. #define EW_MAX 0x1
  47. #define SSTROBE_MAX 0x1
  48. #define NUM_CS 4
  49. #define TA_VAL(x) (((x) & TA(TA_MAX)) >> TA_SHIFT)
  50. #define RHOLD_VAL(x) (((x) & RHOLD(RHOLD_MAX)) >> RHOLD_SHIFT)
  51. #define RSTROBE_VAL(x) (((x) & RSTROBE(RSTROBE_MAX)) >> RSTROBE_SHIFT)
  52. #define RSETUP_VAL(x) (((x) & RSETUP(RSETUP_MAX)) >> RSETUP_SHIFT)
  53. #define WHOLD_VAL(x) (((x) & WHOLD(WHOLD_MAX)) >> WHOLD_SHIFT)
  54. #define WSTROBE_VAL(x) (((x) & WSTROBE(WSTROBE_MAX)) >> WSTROBE_SHIFT)
  55. #define WSETUP_VAL(x) (((x) & WSETUP(WSETUP_MAX)) >> WSETUP_SHIFT)
  56. #define EW_VAL(x) (((x) & EW(EW_MAX)) >> EW_SHIFT)
  57. #define SSTROBE_VAL(x) (((x) & SSTROBE(SSTROBE_MAX)) >> SSTROBE_SHIFT)
  58. #define NRCSR_OFFSET 0x00
  59. #define AWCCR_OFFSET 0x04
  60. #define A1CR_OFFSET 0x10
  61. #define ACR_ASIZE_MASK 0x3
  62. #define ACR_EW_MASK BIT(30)
  63. #define ACR_SSTROBE_MASK BIT(31)
  64. #define ASIZE_16BIT 1
  65. #define CONFIG_MASK (TA(TA_MAX) | \
  66. RHOLD(RHOLD_MAX) | \
  67. RSTROBE(RSTROBE_MAX) | \
  68. RSETUP(RSETUP_MAX) | \
  69. WHOLD(WHOLD_MAX) | \
  70. WSTROBE(WSTROBE_MAX) | \
  71. WSETUP(WSETUP_MAX) | \
  72. EW(EW_MAX) | SSTROBE(SSTROBE_MAX) | \
  73. ASIZE_MAX)
  74. /**
  75. * struct aemif_cs_data: structure to hold cs parameters
  76. * @cs: chip-select number
  77. * @wstrobe: write strobe width, ns
  78. * @rstrobe: read strobe width, ns
  79. * @wsetup: write setup width, ns
  80. * @whold: write hold width, ns
  81. * @rsetup: read setup width, ns
  82. * @rhold: read hold width, ns
  83. * @ta: minimum turn around time, ns
  84. * @enable_ss: enable/disable select strobe mode
  85. * @enable_ew: enable/disable extended wait mode
  86. * @asize: width of the asynchronous device's data bus
  87. */
  88. struct aemif_cs_data {
  89. u8 cs;
  90. u16 wstrobe;
  91. u16 rstrobe;
  92. u8 wsetup;
  93. u8 whold;
  94. u8 rsetup;
  95. u8 rhold;
  96. u8 ta;
  97. u8 enable_ss;
  98. u8 enable_ew;
  99. u8 asize;
  100. };
  101. /**
  102. * struct aemif_device: structure to hold device data
  103. * @base: base address of AEMIF registers
  104. * @clk: source clock
  105. * @clk_rate: clock's rate in kHz
  106. * @num_cs: number of assigned chip-selects
  107. * @cs_offset: start number of cs nodes
  108. * @cs_data: array of chip-select settings
  109. */
  110. struct aemif_device {
  111. void __iomem *base;
  112. struct clk *clk;
  113. unsigned long clk_rate;
  114. u8 num_cs;
  115. int cs_offset;
  116. struct aemif_cs_data cs_data[NUM_CS];
  117. };
  118. /**
  119. * aemif_calc_rate - calculate timing data.
  120. * @pdev: platform device to calculate for
  121. * @wanted: The cycle time needed in nanoseconds.
  122. * @clk: The input clock rate in kHz.
  123. * @max: The maximum divider value that can be programmed.
  124. *
  125. * On success, returns the calculated timing value minus 1 for easy
  126. * programming into AEMIF timing registers, else negative errno.
  127. */
  128. static int aemif_calc_rate(struct platform_device *pdev, int wanted,
  129. unsigned long clk, int max)
  130. {
  131. int result;
  132. result = DIV_ROUND_UP((wanted * clk), NSEC_PER_MSEC) - 1;
  133. dev_dbg(&pdev->dev, "%s: result %d from %ld, %d\n", __func__, result,
  134. clk, wanted);
  135. /* It is generally OK to have a more relaxed timing than requested... */
  136. if (result < 0)
  137. result = 0;
  138. /* ... But configuring tighter timings is not an option. */
  139. else if (result > max)
  140. result = -EINVAL;
  141. return result;
  142. }
  143. /**
  144. * aemif_config_abus - configure async bus parameters
  145. * @pdev: platform device to configure for
  146. * @csnum: aemif chip select number
  147. *
  148. * This function programs the given timing values (in real clock) into the
  149. * AEMIF registers taking the AEMIF clock into account.
  150. *
  151. * This function does not use any locking while programming the AEMIF
  152. * because it is expected that there is only one user of a given
  153. * chip-select.
  154. *
  155. * Returns 0 on success, else negative errno.
  156. */
  157. static int aemif_config_abus(struct platform_device *pdev, int csnum)
  158. {
  159. struct aemif_device *aemif = platform_get_drvdata(pdev);
  160. struct aemif_cs_data *data = &aemif->cs_data[csnum];
  161. int ta, rhold, rstrobe, rsetup, whold, wstrobe, wsetup;
  162. unsigned long clk_rate = aemif->clk_rate;
  163. unsigned offset;
  164. u32 set, val;
  165. offset = A1CR_OFFSET + (data->cs - aemif->cs_offset) * 4;
  166. ta = aemif_calc_rate(pdev, data->ta, clk_rate, TA_MAX);
  167. rhold = aemif_calc_rate(pdev, data->rhold, clk_rate, RHOLD_MAX);
  168. rstrobe = aemif_calc_rate(pdev, data->rstrobe, clk_rate, RSTROBE_MAX);
  169. rsetup = aemif_calc_rate(pdev, data->rsetup, clk_rate, RSETUP_MAX);
  170. whold = aemif_calc_rate(pdev, data->whold, clk_rate, WHOLD_MAX);
  171. wstrobe = aemif_calc_rate(pdev, data->wstrobe, clk_rate, WSTROBE_MAX);
  172. wsetup = aemif_calc_rate(pdev, data->wsetup, clk_rate, WSETUP_MAX);
  173. if (ta < 0 || rhold < 0 || rstrobe < 0 || rsetup < 0 ||
  174. whold < 0 || wstrobe < 0 || wsetup < 0) {
  175. dev_err(&pdev->dev, "%s: cannot get suitable timings\n",
  176. __func__);
  177. return -EINVAL;
  178. }
  179. set = TA(ta) | RHOLD(rhold) | RSTROBE(rstrobe) | RSETUP(rsetup) |
  180. WHOLD(whold) | WSTROBE(wstrobe) | WSETUP(wsetup);
  181. set |= (data->asize & ACR_ASIZE_MASK);
  182. if (data->enable_ew)
  183. set |= ACR_EW_MASK;
  184. if (data->enable_ss)
  185. set |= ACR_SSTROBE_MASK;
  186. val = readl(aemif->base + offset);
  187. val &= ~CONFIG_MASK;
  188. val |= set;
  189. writel(val, aemif->base + offset);
  190. return 0;
  191. }
  192. static inline int aemif_cycles_to_nsec(int val, unsigned long clk_rate)
  193. {
  194. return ((val + 1) * NSEC_PER_MSEC) / clk_rate;
  195. }
  196. /**
  197. * aemif_get_hw_params - function to read hw register values
  198. * @pdev: platform device to read for
  199. * @csnum: aemif chip select number
  200. *
  201. * This function reads the defaults from the registers and update
  202. * the timing values. Required for get/set commands and also for
  203. * the case when driver needs to use defaults in hardware.
  204. */
  205. static void aemif_get_hw_params(struct platform_device *pdev, int csnum)
  206. {
  207. struct aemif_device *aemif = platform_get_drvdata(pdev);
  208. struct aemif_cs_data *data = &aemif->cs_data[csnum];
  209. unsigned long clk_rate = aemif->clk_rate;
  210. u32 val, offset;
  211. offset = A1CR_OFFSET + (data->cs - aemif->cs_offset) * 4;
  212. val = readl(aemif->base + offset);
  213. data->ta = aemif_cycles_to_nsec(TA_VAL(val), clk_rate);
  214. data->rhold = aemif_cycles_to_nsec(RHOLD_VAL(val), clk_rate);
  215. data->rstrobe = aemif_cycles_to_nsec(RSTROBE_VAL(val), clk_rate);
  216. data->rsetup = aemif_cycles_to_nsec(RSETUP_VAL(val), clk_rate);
  217. data->whold = aemif_cycles_to_nsec(WHOLD_VAL(val), clk_rate);
  218. data->wstrobe = aemif_cycles_to_nsec(WSTROBE_VAL(val), clk_rate);
  219. data->wsetup = aemif_cycles_to_nsec(WSETUP_VAL(val), clk_rate);
  220. data->enable_ew = EW_VAL(val);
  221. data->enable_ss = SSTROBE_VAL(val);
  222. data->asize = val & ASIZE_MAX;
  223. }
  224. /**
  225. * of_aemif_parse_abus_config - parse CS configuration from DT
  226. * @pdev: platform device to parse for
  227. * @np: device node ptr
  228. *
  229. * This function update the emif async bus configuration based on the values
  230. * configured in a cs device binding node.
  231. */
  232. static int of_aemif_parse_abus_config(struct platform_device *pdev,
  233. struct device_node *np)
  234. {
  235. struct aemif_device *aemif = platform_get_drvdata(pdev);
  236. struct aemif_cs_data *data;
  237. u32 cs;
  238. u32 val;
  239. if (of_property_read_u32(np, "ti,cs-chipselect", &cs)) {
  240. dev_dbg(&pdev->dev, "cs property is required");
  241. return -EINVAL;
  242. }
  243. if (cs - aemif->cs_offset >= NUM_CS || cs < aemif->cs_offset) {
  244. dev_dbg(&pdev->dev, "cs number is incorrect %d", cs);
  245. return -EINVAL;
  246. }
  247. if (aemif->num_cs >= NUM_CS) {
  248. dev_dbg(&pdev->dev, "cs count is more than %d", NUM_CS);
  249. return -EINVAL;
  250. }
  251. data = &aemif->cs_data[aemif->num_cs];
  252. data->cs = cs;
  253. /* read the current value in the hw register */
  254. aemif_get_hw_params(pdev, aemif->num_cs++);
  255. /* override the values from device node */
  256. if (!of_property_read_u32(np, "ti,cs-min-turnaround-ns", &val))
  257. data->ta = val;
  258. if (!of_property_read_u32(np, "ti,cs-read-hold-ns", &val))
  259. data->rhold = val;
  260. if (!of_property_read_u32(np, "ti,cs-read-strobe-ns", &val))
  261. data->rstrobe = val;
  262. if (!of_property_read_u32(np, "ti,cs-read-setup-ns", &val))
  263. data->rsetup = val;
  264. if (!of_property_read_u32(np, "ti,cs-write-hold-ns", &val))
  265. data->whold = val;
  266. if (!of_property_read_u32(np, "ti,cs-write-strobe-ns", &val))
  267. data->wstrobe = val;
  268. if (!of_property_read_u32(np, "ti,cs-write-setup-ns", &val))
  269. data->wsetup = val;
  270. if (!of_property_read_u32(np, "ti,cs-bus-width", &val))
  271. if (val == 16)
  272. data->asize = 1;
  273. data->enable_ew = of_property_read_bool(np, "ti,cs-extended-wait-mode");
  274. data->enable_ss = of_property_read_bool(np, "ti,cs-select-strobe-mode");
  275. return 0;
  276. }
  277. static const struct of_device_id aemif_of_match[] = {
  278. { .compatible = "ti,davinci-aemif", },
  279. { .compatible = "ti,da850-aemif", },
  280. {},
  281. };
  282. MODULE_DEVICE_TABLE(of, aemif_of_match);
  283. static int aemif_probe(struct platform_device *pdev)
  284. {
  285. int i;
  286. int ret = -ENODEV;
  287. struct resource *res;
  288. struct device *dev = &pdev->dev;
  289. struct device_node *np = dev->of_node;
  290. struct device_node *child_np;
  291. struct aemif_device *aemif;
  292. struct aemif_platform_data *pdata;
  293. struct of_dev_auxdata *dev_lookup;
  294. aemif = devm_kzalloc(dev, sizeof(*aemif), GFP_KERNEL);
  295. if (!aemif)
  296. return -ENOMEM;
  297. pdata = dev_get_platdata(&pdev->dev);
  298. dev_lookup = pdata ? pdata->dev_lookup : NULL;
  299. platform_set_drvdata(pdev, aemif);
  300. aemif->clk = devm_clk_get(dev, NULL);
  301. if (IS_ERR(aemif->clk)) {
  302. dev_err(dev, "cannot get clock 'aemif'\n");
  303. return PTR_ERR(aemif->clk);
  304. }
  305. ret = clk_prepare_enable(aemif->clk);
  306. if (ret)
  307. return ret;
  308. aemif->clk_rate = clk_get_rate(aemif->clk) / MSEC_PER_SEC;
  309. if (np && of_device_is_compatible(np, "ti,da850-aemif"))
  310. aemif->cs_offset = 2;
  311. else if (pdata)
  312. aemif->cs_offset = pdata->cs_offset;
  313. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  314. aemif->base = devm_ioremap_resource(dev, res);
  315. if (IS_ERR(aemif->base)) {
  316. ret = PTR_ERR(aemif->base);
  317. goto error;
  318. }
  319. if (np) {
  320. /*
  321. * For every controller device node, there is a cs device node
  322. * that describe the bus configuration parameters. This
  323. * functions iterate over these nodes and update the cs data
  324. * array.
  325. */
  326. for_each_available_child_of_node(np, child_np) {
  327. ret = of_aemif_parse_abus_config(pdev, child_np);
  328. if (ret < 0) {
  329. of_node_put(child_np);
  330. goto error;
  331. }
  332. }
  333. } else if (pdata && pdata->num_abus_data > 0) {
  334. for (i = 0; i < pdata->num_abus_data; i++, aemif->num_cs++) {
  335. aemif->cs_data[i].cs = pdata->abus_data[i].cs;
  336. aemif_get_hw_params(pdev, i);
  337. }
  338. }
  339. for (i = 0; i < aemif->num_cs; i++) {
  340. ret = aemif_config_abus(pdev, i);
  341. if (ret < 0) {
  342. dev_err(dev, "Error configuring chip select %d\n",
  343. aemif->cs_data[i].cs);
  344. goto error;
  345. }
  346. }
  347. /*
  348. * Create a child devices explicitly from here to guarantee that the
  349. * child will be probed after the AEMIF timing parameters are set.
  350. */
  351. if (np) {
  352. for_each_available_child_of_node(np, child_np) {
  353. ret = of_platform_populate(child_np, NULL,
  354. dev_lookup, dev);
  355. if (ret < 0) {
  356. of_node_put(child_np);
  357. goto error;
  358. }
  359. }
  360. } else if (pdata) {
  361. for (i = 0; i < pdata->num_sub_devices; i++) {
  362. pdata->sub_devices[i].dev.parent = dev;
  363. ret = platform_device_register(&pdata->sub_devices[i]);
  364. if (ret) {
  365. dev_warn(dev, "Error register sub device %s\n",
  366. pdata->sub_devices[i].name);
  367. }
  368. }
  369. }
  370. return 0;
  371. error:
  372. clk_disable_unprepare(aemif->clk);
  373. return ret;
  374. }
  375. static int aemif_remove(struct platform_device *pdev)
  376. {
  377. struct aemif_device *aemif = platform_get_drvdata(pdev);
  378. clk_disable_unprepare(aemif->clk);
  379. return 0;
  380. }
  381. static struct platform_driver aemif_driver = {
  382. .probe = aemif_probe,
  383. .remove = aemif_remove,
  384. .driver = {
  385. .name = "ti-aemif",
  386. .of_match_table = of_match_ptr(aemif_of_match),
  387. },
  388. };
  389. module_platform_driver(aemif_driver);
  390. MODULE_AUTHOR("Murali Karicheri <m-karicheri2@ti.com>");
  391. MODULE_AUTHOR("Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>");
  392. MODULE_DESCRIPTION("Texas Instruments AEMIF driver");
  393. MODULE_LICENSE("GPL v2");
  394. MODULE_ALIAS("platform:" KBUILD_MODNAME);