pl353-smc.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * ARM PL353 SMC driver
  4. *
  5. * Copyright (C) 2012 - 2018 Xilinx, Inc
  6. * Author: Punnaiah Choudary Kalluri <punnaiah@xilinx.com>
  7. * Author: Naga Sureshkumar Relli <nagasure@xilinx.com>
  8. */
  9. #include <linux/clk.h>
  10. #include <linux/io.h>
  11. #include <linux/kernel.h>
  12. #include <linux/module.h>
  13. #include <linux/of_platform.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/slab.h>
  16. #include <linux/pl353-smc.h>
  17. #include <linux/amba/bus.h>
  18. /* Register definitions */
  19. #define PL353_SMC_MEMC_STATUS_OFFS 0 /* Controller status reg, RO */
  20. #define PL353_SMC_CFG_CLR_OFFS 0xC /* Clear config reg, WO */
  21. #define PL353_SMC_DIRECT_CMD_OFFS 0x10 /* Direct command reg, WO */
  22. #define PL353_SMC_SET_CYCLES_OFFS 0x14 /* Set cycles register, WO */
  23. #define PL353_SMC_SET_OPMODE_OFFS 0x18 /* Set opmode register, WO */
  24. #define PL353_SMC_ECC_STATUS_OFFS 0x400 /* ECC status register */
  25. #define PL353_SMC_ECC_MEMCFG_OFFS 0x404 /* ECC mem config reg */
  26. #define PL353_SMC_ECC_MEMCMD1_OFFS 0x408 /* ECC mem cmd1 reg */
  27. #define PL353_SMC_ECC_MEMCMD2_OFFS 0x40C /* ECC mem cmd2 reg */
  28. #define PL353_SMC_ECC_VALUE0_OFFS 0x418 /* ECC value 0 reg */
  29. /* Controller status register specific constants */
  30. #define PL353_SMC_MEMC_STATUS_RAW_INT_1_SHIFT 6
  31. /* Clear configuration register specific constants */
  32. #define PL353_SMC_CFG_CLR_INT_CLR_1 0x10
  33. #define PL353_SMC_CFG_CLR_ECC_INT_DIS_1 0x40
  34. #define PL353_SMC_CFG_CLR_INT_DIS_1 0x2
  35. #define PL353_SMC_CFG_CLR_DEFAULT_MASK (PL353_SMC_CFG_CLR_INT_CLR_1 | \
  36. PL353_SMC_CFG_CLR_ECC_INT_DIS_1 | \
  37. PL353_SMC_CFG_CLR_INT_DIS_1)
  38. /* Set cycles register specific constants */
  39. #define PL353_SMC_SET_CYCLES_T0_MASK 0xF
  40. #define PL353_SMC_SET_CYCLES_T0_SHIFT 0
  41. #define PL353_SMC_SET_CYCLES_T1_MASK 0xF
  42. #define PL353_SMC_SET_CYCLES_T1_SHIFT 4
  43. #define PL353_SMC_SET_CYCLES_T2_MASK 0x7
  44. #define PL353_SMC_SET_CYCLES_T2_SHIFT 8
  45. #define PL353_SMC_SET_CYCLES_T3_MASK 0x7
  46. #define PL353_SMC_SET_CYCLES_T3_SHIFT 11
  47. #define PL353_SMC_SET_CYCLES_T4_MASK 0x7
  48. #define PL353_SMC_SET_CYCLES_T4_SHIFT 14
  49. #define PL353_SMC_SET_CYCLES_T5_MASK 0x7
  50. #define PL353_SMC_SET_CYCLES_T5_SHIFT 17
  51. #define PL353_SMC_SET_CYCLES_T6_MASK 0xF
  52. #define PL353_SMC_SET_CYCLES_T6_SHIFT 20
  53. /* ECC status register specific constants */
  54. #define PL353_SMC_ECC_STATUS_BUSY BIT(6)
  55. #define PL353_SMC_ECC_REG_SIZE_OFFS 4
  56. /* ECC memory config register specific constants */
  57. #define PL353_SMC_ECC_MEMCFG_MODE_MASK 0xC
  58. #define PL353_SMC_ECC_MEMCFG_MODE_SHIFT 2
  59. #define PL353_SMC_ECC_MEMCFG_PGSIZE_MASK 0x3
  60. #define PL353_SMC_DC_UPT_NAND_REGS ((4 << 23) | /* CS: NAND chip */ \
  61. (2 << 21)) /* UpdateRegs operation */
  62. #define PL353_NAND_ECC_CMD1 ((0x80) | /* Write command */ \
  63. (0 << 8) | /* Read command */ \
  64. (0x30 << 16) | /* Read End command */ \
  65. (1 << 24)) /* Read End command calid */
  66. #define PL353_NAND_ECC_CMD2 ((0x85) | /* Write col change cmd */ \
  67. (5 << 8) | /* Read col change cmd */ \
  68. (0xE0 << 16) | /* Read col change end cmd */ \
  69. (1 << 24)) /* Read col change end cmd valid */
  70. #define PL353_NAND_ECC_BUSY_TIMEOUT (1 * HZ)
  71. /**
  72. * struct pl353_smc_data - Private smc driver structure
  73. * @memclk: Pointer to the peripheral clock
  74. * @aclk: Pointer to the APER clock
  75. */
  76. struct pl353_smc_data {
  77. struct clk *memclk;
  78. struct clk *aclk;
  79. };
  80. /* SMC virtual register base */
  81. static void __iomem *pl353_smc_base;
  82. /**
  83. * pl353_smc_set_buswidth - Set memory buswidth
  84. * @bw: Memory buswidth (8 | 16)
  85. * Return: 0 on success or negative errno.
  86. */
  87. int pl353_smc_set_buswidth(unsigned int bw)
  88. {
  89. if (bw != PL353_SMC_MEM_WIDTH_8 && bw != PL353_SMC_MEM_WIDTH_16)
  90. return -EINVAL;
  91. writel(bw, pl353_smc_base + PL353_SMC_SET_OPMODE_OFFS);
  92. writel(PL353_SMC_DC_UPT_NAND_REGS, pl353_smc_base +
  93. PL353_SMC_DIRECT_CMD_OFFS);
  94. return 0;
  95. }
  96. EXPORT_SYMBOL_GPL(pl353_smc_set_buswidth);
  97. /**
  98. * pl353_smc_set_cycles - Set memory timing parameters
  99. * @timings: NAND controller timing parameters
  100. *
  101. * Sets NAND chip specific timing parameters.
  102. */
  103. void pl353_smc_set_cycles(u32 timings[])
  104. {
  105. /*
  106. * Set write pulse timing. This one is easy to extract:
  107. *
  108. * NWE_PULSE = tWP
  109. */
  110. timings[0] &= PL353_SMC_SET_CYCLES_T0_MASK;
  111. timings[1] = (timings[1] & PL353_SMC_SET_CYCLES_T1_MASK) <<
  112. PL353_SMC_SET_CYCLES_T1_SHIFT;
  113. timings[2] = (timings[2] & PL353_SMC_SET_CYCLES_T2_MASK) <<
  114. PL353_SMC_SET_CYCLES_T2_SHIFT;
  115. timings[3] = (timings[3] & PL353_SMC_SET_CYCLES_T3_MASK) <<
  116. PL353_SMC_SET_CYCLES_T3_SHIFT;
  117. timings[4] = (timings[4] & PL353_SMC_SET_CYCLES_T4_MASK) <<
  118. PL353_SMC_SET_CYCLES_T4_SHIFT;
  119. timings[5] = (timings[5] & PL353_SMC_SET_CYCLES_T5_MASK) <<
  120. PL353_SMC_SET_CYCLES_T5_SHIFT;
  121. timings[6] = (timings[6] & PL353_SMC_SET_CYCLES_T6_MASK) <<
  122. PL353_SMC_SET_CYCLES_T6_SHIFT;
  123. timings[0] |= timings[1] | timings[2] | timings[3] |
  124. timings[4] | timings[5] | timings[6];
  125. writel(timings[0], pl353_smc_base + PL353_SMC_SET_CYCLES_OFFS);
  126. writel(PL353_SMC_DC_UPT_NAND_REGS, pl353_smc_base +
  127. PL353_SMC_DIRECT_CMD_OFFS);
  128. }
  129. EXPORT_SYMBOL_GPL(pl353_smc_set_cycles);
  130. /**
  131. * pl353_smc_ecc_is_busy - Read ecc busy flag
  132. * Return: the ecc_status bit from the ecc_status register. 1 = busy, 0 = idle
  133. */
  134. bool pl353_smc_ecc_is_busy(void)
  135. {
  136. return ((readl(pl353_smc_base + PL353_SMC_ECC_STATUS_OFFS) &
  137. PL353_SMC_ECC_STATUS_BUSY) == PL353_SMC_ECC_STATUS_BUSY);
  138. }
  139. EXPORT_SYMBOL_GPL(pl353_smc_ecc_is_busy);
  140. /**
  141. * pl353_smc_get_ecc_val - Read ecc_valueN registers
  142. * @ecc_reg: Index of the ecc_value reg (0..3)
  143. * Return: the content of the requested ecc_value register.
  144. *
  145. * There are four valid ecc_value registers. The argument is truncated to stay
  146. * within this valid boundary.
  147. */
  148. u32 pl353_smc_get_ecc_val(int ecc_reg)
  149. {
  150. u32 addr, reg;
  151. addr = PL353_SMC_ECC_VALUE0_OFFS +
  152. (ecc_reg * PL353_SMC_ECC_REG_SIZE_OFFS);
  153. reg = readl(pl353_smc_base + addr);
  154. return reg;
  155. }
  156. EXPORT_SYMBOL_GPL(pl353_smc_get_ecc_val);
  157. /**
  158. * pl353_smc_get_nand_int_status_raw - Get NAND interrupt status bit
  159. * Return: the raw_int_status1 bit from the memc_status register
  160. */
  161. int pl353_smc_get_nand_int_status_raw(void)
  162. {
  163. u32 reg;
  164. reg = readl(pl353_smc_base + PL353_SMC_MEMC_STATUS_OFFS);
  165. reg >>= PL353_SMC_MEMC_STATUS_RAW_INT_1_SHIFT;
  166. reg &= 1;
  167. return reg;
  168. }
  169. EXPORT_SYMBOL_GPL(pl353_smc_get_nand_int_status_raw);
  170. /**
  171. * pl353_smc_clr_nand_int - Clear NAND interrupt
  172. */
  173. void pl353_smc_clr_nand_int(void)
  174. {
  175. writel(PL353_SMC_CFG_CLR_INT_CLR_1,
  176. pl353_smc_base + PL353_SMC_CFG_CLR_OFFS);
  177. }
  178. EXPORT_SYMBOL_GPL(pl353_smc_clr_nand_int);
  179. /**
  180. * pl353_smc_set_ecc_mode - Set SMC ECC mode
  181. * @mode: ECC mode (BYPASS, APB, MEM)
  182. * Return: 0 on success or negative errno.
  183. */
  184. int pl353_smc_set_ecc_mode(enum pl353_smc_ecc_mode mode)
  185. {
  186. u32 reg;
  187. int ret = 0;
  188. switch (mode) {
  189. case PL353_SMC_ECCMODE_BYPASS:
  190. case PL353_SMC_ECCMODE_APB:
  191. case PL353_SMC_ECCMODE_MEM:
  192. reg = readl(pl353_smc_base + PL353_SMC_ECC_MEMCFG_OFFS);
  193. reg &= ~PL353_SMC_ECC_MEMCFG_MODE_MASK;
  194. reg |= mode << PL353_SMC_ECC_MEMCFG_MODE_SHIFT;
  195. writel(reg, pl353_smc_base + PL353_SMC_ECC_MEMCFG_OFFS);
  196. break;
  197. default:
  198. ret = -EINVAL;
  199. }
  200. return ret;
  201. }
  202. EXPORT_SYMBOL_GPL(pl353_smc_set_ecc_mode);
  203. /**
  204. * pl353_smc_set_ecc_pg_size - Set SMC ECC page size
  205. * @pg_sz: ECC page size
  206. * Return: 0 on success or negative errno.
  207. */
  208. int pl353_smc_set_ecc_pg_size(unsigned int pg_sz)
  209. {
  210. u32 reg, sz;
  211. switch (pg_sz) {
  212. case 0:
  213. sz = 0;
  214. break;
  215. case SZ_512:
  216. sz = 1;
  217. break;
  218. case SZ_1K:
  219. sz = 2;
  220. break;
  221. case SZ_2K:
  222. sz = 3;
  223. break;
  224. default:
  225. return -EINVAL;
  226. }
  227. reg = readl(pl353_smc_base + PL353_SMC_ECC_MEMCFG_OFFS);
  228. reg &= ~PL353_SMC_ECC_MEMCFG_PGSIZE_MASK;
  229. reg |= sz;
  230. writel(reg, pl353_smc_base + PL353_SMC_ECC_MEMCFG_OFFS);
  231. return 0;
  232. }
  233. EXPORT_SYMBOL_GPL(pl353_smc_set_ecc_pg_size);
  234. static int __maybe_unused pl353_smc_suspend(struct device *dev)
  235. {
  236. struct pl353_smc_data *pl353_smc = dev_get_drvdata(dev);
  237. clk_disable(pl353_smc->memclk);
  238. clk_disable(pl353_smc->aclk);
  239. return 0;
  240. }
  241. static int __maybe_unused pl353_smc_resume(struct device *dev)
  242. {
  243. int ret;
  244. struct pl353_smc_data *pl353_smc = dev_get_drvdata(dev);
  245. ret = clk_enable(pl353_smc->aclk);
  246. if (ret) {
  247. dev_err(dev, "Cannot enable axi domain clock.\n");
  248. return ret;
  249. }
  250. ret = clk_enable(pl353_smc->memclk);
  251. if (ret) {
  252. dev_err(dev, "Cannot enable memory clock.\n");
  253. clk_disable(pl353_smc->aclk);
  254. return ret;
  255. }
  256. return ret;
  257. }
  258. static struct amba_driver pl353_smc_driver;
  259. static SIMPLE_DEV_PM_OPS(pl353_smc_dev_pm_ops, pl353_smc_suspend,
  260. pl353_smc_resume);
  261. /**
  262. * pl353_smc_init_nand_interface - Initialize the NAND interface
  263. * @adev: Pointer to the amba_device struct
  264. * @nand_node: Pointer to the pl353_nand device_node struct
  265. */
  266. static void pl353_smc_init_nand_interface(struct amba_device *adev,
  267. struct device_node *nand_node)
  268. {
  269. unsigned long timeout;
  270. pl353_smc_set_buswidth(PL353_SMC_MEM_WIDTH_8);
  271. writel(PL353_SMC_CFG_CLR_INT_CLR_1,
  272. pl353_smc_base + PL353_SMC_CFG_CLR_OFFS);
  273. writel(PL353_SMC_DC_UPT_NAND_REGS, pl353_smc_base +
  274. PL353_SMC_DIRECT_CMD_OFFS);
  275. timeout = jiffies + PL353_NAND_ECC_BUSY_TIMEOUT;
  276. /* Wait till the ECC operation is complete */
  277. do {
  278. if (pl353_smc_ecc_is_busy())
  279. cpu_relax();
  280. else
  281. break;
  282. } while (!time_after_eq(jiffies, timeout));
  283. if (time_after_eq(jiffies, timeout))
  284. return;
  285. writel(PL353_NAND_ECC_CMD1,
  286. pl353_smc_base + PL353_SMC_ECC_MEMCMD1_OFFS);
  287. writel(PL353_NAND_ECC_CMD2,
  288. pl353_smc_base + PL353_SMC_ECC_MEMCMD2_OFFS);
  289. }
  290. static const struct of_device_id pl353_smc_supported_children[] = {
  291. {
  292. .compatible = "cfi-flash"
  293. },
  294. {
  295. .compatible = "arm,pl353-nand-r2p1",
  296. .data = pl353_smc_init_nand_interface
  297. },
  298. {}
  299. };
  300. static int pl353_smc_probe(struct amba_device *adev, const struct amba_id *id)
  301. {
  302. struct pl353_smc_data *pl353_smc;
  303. struct device_node *child;
  304. struct resource *res;
  305. int err;
  306. struct device_node *of_node = adev->dev.of_node;
  307. static void (*init)(struct amba_device *adev,
  308. struct device_node *nand_node);
  309. const struct of_device_id *match = NULL;
  310. pl353_smc = devm_kzalloc(&adev->dev, sizeof(*pl353_smc), GFP_KERNEL);
  311. if (!pl353_smc)
  312. return -ENOMEM;
  313. /* Get the NAND controller virtual address */
  314. res = &adev->res;
  315. pl353_smc_base = devm_ioremap_resource(&adev->dev, res);
  316. if (IS_ERR(pl353_smc_base))
  317. return PTR_ERR(pl353_smc_base);
  318. pl353_smc->aclk = devm_clk_get(&adev->dev, "apb_pclk");
  319. if (IS_ERR(pl353_smc->aclk)) {
  320. dev_err(&adev->dev, "aclk clock not found.\n");
  321. return PTR_ERR(pl353_smc->aclk);
  322. }
  323. pl353_smc->memclk = devm_clk_get(&adev->dev, "memclk");
  324. if (IS_ERR(pl353_smc->memclk)) {
  325. dev_err(&adev->dev, "memclk clock not found.\n");
  326. return PTR_ERR(pl353_smc->memclk);
  327. }
  328. err = clk_prepare_enable(pl353_smc->aclk);
  329. if (err) {
  330. dev_err(&adev->dev, "Unable to enable AXI clock.\n");
  331. return err;
  332. }
  333. err = clk_prepare_enable(pl353_smc->memclk);
  334. if (err) {
  335. dev_err(&adev->dev, "Unable to enable memory clock.\n");
  336. goto out_clk_dis_aper;
  337. }
  338. amba_set_drvdata(adev, pl353_smc);
  339. /* clear interrupts */
  340. writel(PL353_SMC_CFG_CLR_DEFAULT_MASK,
  341. pl353_smc_base + PL353_SMC_CFG_CLR_OFFS);
  342. /* Find compatible children. Only a single child is supported */
  343. for_each_available_child_of_node(of_node, child) {
  344. match = of_match_node(pl353_smc_supported_children, child);
  345. if (!match) {
  346. dev_warn(&adev->dev, "unsupported child node\n");
  347. continue;
  348. }
  349. break;
  350. }
  351. if (!match) {
  352. err = -ENODEV;
  353. dev_err(&adev->dev, "no matching children\n");
  354. goto out_clk_disable;
  355. }
  356. init = match->data;
  357. if (init)
  358. init(adev, child);
  359. of_platform_device_create(child, NULL, &adev->dev);
  360. return 0;
  361. out_clk_disable:
  362. clk_disable_unprepare(pl353_smc->memclk);
  363. out_clk_dis_aper:
  364. clk_disable_unprepare(pl353_smc->aclk);
  365. return err;
  366. }
  367. static void pl353_smc_remove(struct amba_device *adev)
  368. {
  369. struct pl353_smc_data *pl353_smc = amba_get_drvdata(adev);
  370. clk_disable_unprepare(pl353_smc->memclk);
  371. clk_disable_unprepare(pl353_smc->aclk);
  372. }
  373. static const struct amba_id pl353_ids[] = {
  374. {
  375. .id = 0x00041353,
  376. .mask = 0x000fffff,
  377. },
  378. { 0, 0 },
  379. };
  380. MODULE_DEVICE_TABLE(amba, pl353_ids);
  381. static struct amba_driver pl353_smc_driver = {
  382. .drv = {
  383. .owner = THIS_MODULE,
  384. .name = "pl353-smc",
  385. .pm = &pl353_smc_dev_pm_ops,
  386. },
  387. .id_table = pl353_ids,
  388. .probe = pl353_smc_probe,
  389. .remove = pl353_smc_remove,
  390. };
  391. module_amba_driver(pl353_smc_driver);
  392. MODULE_AUTHOR("Xilinx, Inc.");
  393. MODULE_DESCRIPTION("ARM PL353 SMC Driver");
  394. MODULE_LICENSE("GPL");