jz4780-nemc.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * JZ4780 NAND/external memory controller (NEMC)
  4. *
  5. * Copyright (c) 2015 Imagination Technologies
  6. * Author: Alex Smith <alex@alex-smith.me.uk>
  7. */
  8. #include <linux/clk.h>
  9. #include <linux/init.h>
  10. #include <linux/io.h>
  11. #include <linux/math64.h>
  12. #include <linux/of.h>
  13. #include <linux/of_address.h>
  14. #include <linux/of_device.h>
  15. #include <linux/of_platform.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/slab.h>
  18. #include <linux/spinlock.h>
  19. #include <linux/jz4780-nemc.h>
  20. #define NEMC_SMCRn(n) (0x14 + (((n) - 1) * 4))
  21. #define NEMC_NFCSR 0x50
  22. #define NEMC_REG_LEN 0x54
  23. #define NEMC_SMCR_SMT BIT(0)
  24. #define NEMC_SMCR_BW_SHIFT 6
  25. #define NEMC_SMCR_BW_MASK (0x3 << NEMC_SMCR_BW_SHIFT)
  26. #define NEMC_SMCR_BW_8 (0 << 6)
  27. #define NEMC_SMCR_TAS_SHIFT 8
  28. #define NEMC_SMCR_TAS_MASK (0xf << NEMC_SMCR_TAS_SHIFT)
  29. #define NEMC_SMCR_TAH_SHIFT 12
  30. #define NEMC_SMCR_TAH_MASK (0xf << NEMC_SMCR_TAH_SHIFT)
  31. #define NEMC_SMCR_TBP_SHIFT 16
  32. #define NEMC_SMCR_TBP_MASK (0xf << NEMC_SMCR_TBP_SHIFT)
  33. #define NEMC_SMCR_TAW_SHIFT 20
  34. #define NEMC_SMCR_TAW_MASK (0xf << NEMC_SMCR_TAW_SHIFT)
  35. #define NEMC_SMCR_TSTRV_SHIFT 24
  36. #define NEMC_SMCR_TSTRV_MASK (0x3f << NEMC_SMCR_TSTRV_SHIFT)
  37. #define NEMC_NFCSR_NFEn(n) BIT(((n) - 1) << 1)
  38. #define NEMC_NFCSR_NFCEn(n) BIT((((n) - 1) << 1) + 1)
  39. #define NEMC_NFCSR_TNFEn(n) BIT(16 + (n) - 1)
  40. struct jz_soc_info {
  41. u8 tas_tah_cycles_max;
  42. };
  43. struct jz4780_nemc {
  44. spinlock_t lock;
  45. struct device *dev;
  46. const struct jz_soc_info *soc_info;
  47. void __iomem *base;
  48. struct clk *clk;
  49. uint32_t clk_period;
  50. unsigned long banks_present;
  51. };
  52. /**
  53. * jz4780_nemc_num_banks() - count the number of banks referenced by a device
  54. * @dev: device to count banks for, must be a child of the NEMC.
  55. *
  56. * Return: The number of unique NEMC banks referred to by the specified NEMC
  57. * child device. Unique here means that a device that references the same bank
  58. * multiple times in its "reg" property will only count once.
  59. */
  60. unsigned int jz4780_nemc_num_banks(struct device *dev)
  61. {
  62. const __be32 *prop;
  63. unsigned int bank, count = 0;
  64. unsigned long referenced = 0;
  65. int i = 0;
  66. while ((prop = of_get_address(dev->of_node, i++, NULL, NULL))) {
  67. bank = of_read_number(prop, 1);
  68. if (!(referenced & BIT(bank))) {
  69. referenced |= BIT(bank);
  70. count++;
  71. }
  72. }
  73. return count;
  74. }
  75. EXPORT_SYMBOL(jz4780_nemc_num_banks);
  76. /**
  77. * jz4780_nemc_set_type() - set the type of device connected to a bank
  78. * @dev: child device of the NEMC.
  79. * @bank: bank number to configure.
  80. * @type: type of device connected to the bank.
  81. */
  82. void jz4780_nemc_set_type(struct device *dev, unsigned int bank,
  83. enum jz4780_nemc_bank_type type)
  84. {
  85. struct jz4780_nemc *nemc = dev_get_drvdata(dev->parent);
  86. uint32_t nfcsr;
  87. nfcsr = readl(nemc->base + NEMC_NFCSR);
  88. /* TODO: Support toggle NAND devices. */
  89. switch (type) {
  90. case JZ4780_NEMC_BANK_SRAM:
  91. nfcsr &= ~(NEMC_NFCSR_TNFEn(bank) | NEMC_NFCSR_NFEn(bank));
  92. break;
  93. case JZ4780_NEMC_BANK_NAND:
  94. nfcsr &= ~NEMC_NFCSR_TNFEn(bank);
  95. nfcsr |= NEMC_NFCSR_NFEn(bank);
  96. break;
  97. }
  98. writel(nfcsr, nemc->base + NEMC_NFCSR);
  99. }
  100. EXPORT_SYMBOL(jz4780_nemc_set_type);
  101. /**
  102. * jz4780_nemc_assert() - (de-)assert a NAND device's chip enable pin
  103. * @dev: child device of the NEMC.
  104. * @bank: bank number of device.
  105. * @assert: whether the chip enable pin should be asserted.
  106. *
  107. * (De-)asserts the chip enable pin for the NAND device connected to the
  108. * specified bank.
  109. */
  110. void jz4780_nemc_assert(struct device *dev, unsigned int bank, bool assert)
  111. {
  112. struct jz4780_nemc *nemc = dev_get_drvdata(dev->parent);
  113. uint32_t nfcsr;
  114. nfcsr = readl(nemc->base + NEMC_NFCSR);
  115. if (assert)
  116. nfcsr |= NEMC_NFCSR_NFCEn(bank);
  117. else
  118. nfcsr &= ~NEMC_NFCSR_NFCEn(bank);
  119. writel(nfcsr, nemc->base + NEMC_NFCSR);
  120. }
  121. EXPORT_SYMBOL(jz4780_nemc_assert);
  122. static uint32_t jz4780_nemc_clk_period(struct jz4780_nemc *nemc)
  123. {
  124. unsigned long rate;
  125. rate = clk_get_rate(nemc->clk);
  126. if (!rate)
  127. return 0;
  128. /* Return in picoseconds. */
  129. return div64_ul(1000000000000ull, rate);
  130. }
  131. static uint32_t jz4780_nemc_ns_to_cycles(struct jz4780_nemc *nemc, uint32_t ns)
  132. {
  133. return ((ns * 1000) + nemc->clk_period - 1) / nemc->clk_period;
  134. }
  135. static bool jz4780_nemc_configure_bank(struct jz4780_nemc *nemc,
  136. unsigned int bank,
  137. struct device_node *node)
  138. {
  139. uint32_t smcr, val, cycles;
  140. /*
  141. * Conversion of tBP and tAW cycle counts to values supported by the
  142. * hardware (round up to the next supported value).
  143. */
  144. static const u8 convert_tBP_tAW[] = {
  145. 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
  146. /* 11 - 12 -> 12 cycles */
  147. 11, 11,
  148. /* 13 - 15 -> 15 cycles */
  149. 12, 12, 12,
  150. /* 16 - 20 -> 20 cycles */
  151. 13, 13, 13, 13, 13,
  152. /* 21 - 25 -> 25 cycles */
  153. 14, 14, 14, 14, 14,
  154. /* 26 - 31 -> 31 cycles */
  155. 15, 15, 15, 15, 15, 15
  156. };
  157. smcr = readl(nemc->base + NEMC_SMCRn(bank));
  158. smcr &= ~NEMC_SMCR_SMT;
  159. if (!of_property_read_u32(node, "ingenic,nemc-bus-width", &val)) {
  160. smcr &= ~NEMC_SMCR_BW_MASK;
  161. switch (val) {
  162. case 8:
  163. smcr |= NEMC_SMCR_BW_8;
  164. break;
  165. default:
  166. /*
  167. * Earlier SoCs support a 16 bit bus width (the 4780
  168. * does not), until those are properly supported, error.
  169. */
  170. dev_err(nemc->dev, "unsupported bus width: %u\n", val);
  171. return false;
  172. }
  173. }
  174. if (of_property_read_u32(node, "ingenic,nemc-tAS", &val) == 0) {
  175. smcr &= ~NEMC_SMCR_TAS_MASK;
  176. cycles = jz4780_nemc_ns_to_cycles(nemc, val);
  177. if (cycles > nemc->soc_info->tas_tah_cycles_max) {
  178. dev_err(nemc->dev, "tAS %u is too high (%u cycles)\n",
  179. val, cycles);
  180. return false;
  181. }
  182. smcr |= cycles << NEMC_SMCR_TAS_SHIFT;
  183. }
  184. if (of_property_read_u32(node, "ingenic,nemc-tAH", &val) == 0) {
  185. smcr &= ~NEMC_SMCR_TAH_MASK;
  186. cycles = jz4780_nemc_ns_to_cycles(nemc, val);
  187. if (cycles > nemc->soc_info->tas_tah_cycles_max) {
  188. dev_err(nemc->dev, "tAH %u is too high (%u cycles)\n",
  189. val, cycles);
  190. return false;
  191. }
  192. smcr |= cycles << NEMC_SMCR_TAH_SHIFT;
  193. }
  194. if (of_property_read_u32(node, "ingenic,nemc-tBP", &val) == 0) {
  195. smcr &= ~NEMC_SMCR_TBP_MASK;
  196. cycles = jz4780_nemc_ns_to_cycles(nemc, val);
  197. if (cycles > 31) {
  198. dev_err(nemc->dev, "tBP %u is too high (%u cycles)\n",
  199. val, cycles);
  200. return false;
  201. }
  202. smcr |= convert_tBP_tAW[cycles] << NEMC_SMCR_TBP_SHIFT;
  203. }
  204. if (of_property_read_u32(node, "ingenic,nemc-tAW", &val) == 0) {
  205. smcr &= ~NEMC_SMCR_TAW_MASK;
  206. cycles = jz4780_nemc_ns_to_cycles(nemc, val);
  207. if (cycles > 31) {
  208. dev_err(nemc->dev, "tAW %u is too high (%u cycles)\n",
  209. val, cycles);
  210. return false;
  211. }
  212. smcr |= convert_tBP_tAW[cycles] << NEMC_SMCR_TAW_SHIFT;
  213. }
  214. if (of_property_read_u32(node, "ingenic,nemc-tSTRV", &val) == 0) {
  215. smcr &= ~NEMC_SMCR_TSTRV_MASK;
  216. cycles = jz4780_nemc_ns_to_cycles(nemc, val);
  217. if (cycles > 63) {
  218. dev_err(nemc->dev, "tSTRV %u is too high (%u cycles)\n",
  219. val, cycles);
  220. return false;
  221. }
  222. smcr |= cycles << NEMC_SMCR_TSTRV_SHIFT;
  223. }
  224. writel(smcr, nemc->base + NEMC_SMCRn(bank));
  225. return true;
  226. }
  227. static int jz4780_nemc_probe(struct platform_device *pdev)
  228. {
  229. struct device *dev = &pdev->dev;
  230. struct jz4780_nemc *nemc;
  231. struct resource *res;
  232. struct device_node *child;
  233. const __be32 *prop;
  234. unsigned int bank;
  235. unsigned long referenced;
  236. int i, ret;
  237. nemc = devm_kzalloc(dev, sizeof(*nemc), GFP_KERNEL);
  238. if (!nemc)
  239. return -ENOMEM;
  240. nemc->soc_info = device_get_match_data(dev);
  241. if (!nemc->soc_info)
  242. return -EINVAL;
  243. spin_lock_init(&nemc->lock);
  244. nemc->dev = dev;
  245. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  246. if (!res)
  247. return -EINVAL;
  248. /*
  249. * The driver currently only uses the registers up to offset
  250. * NEMC_REG_LEN. Since the EFUSE registers are in the middle of the
  251. * NEMC registers, we only request the registers we will use for now;
  252. * that way the EFUSE driver can probe too.
  253. */
  254. if (!devm_request_mem_region(dev, res->start, NEMC_REG_LEN, dev_name(dev))) {
  255. dev_err(dev, "unable to request I/O memory region\n");
  256. return -EBUSY;
  257. }
  258. nemc->base = devm_ioremap(dev, res->start, NEMC_REG_LEN);
  259. if (!nemc->base) {
  260. dev_err(dev, "failed to get I/O memory\n");
  261. return -ENOMEM;
  262. }
  263. writel(0, nemc->base + NEMC_NFCSR);
  264. nemc->clk = devm_clk_get(dev, NULL);
  265. if (IS_ERR(nemc->clk)) {
  266. dev_err(dev, "failed to get clock\n");
  267. return PTR_ERR(nemc->clk);
  268. }
  269. ret = clk_prepare_enable(nemc->clk);
  270. if (ret) {
  271. dev_err(dev, "failed to enable clock: %d\n", ret);
  272. return ret;
  273. }
  274. nemc->clk_period = jz4780_nemc_clk_period(nemc);
  275. if (!nemc->clk_period) {
  276. dev_err(dev, "failed to calculate clock period\n");
  277. clk_disable_unprepare(nemc->clk);
  278. return -EINVAL;
  279. }
  280. /*
  281. * Iterate over child devices, check that they do not conflict with
  282. * each other, and register child devices for them. If a child device
  283. * has invalid properties, it is ignored and no platform device is
  284. * registered for it.
  285. */
  286. for_each_child_of_node(nemc->dev->of_node, child) {
  287. referenced = 0;
  288. i = 0;
  289. while ((prop = of_get_address(child, i++, NULL, NULL))) {
  290. bank = of_read_number(prop, 1);
  291. if (bank < 1 || bank >= JZ4780_NEMC_NUM_BANKS) {
  292. dev_err(nemc->dev,
  293. "%pOF requests invalid bank %u\n",
  294. child, bank);
  295. /* Will continue the outer loop below. */
  296. referenced = 0;
  297. break;
  298. }
  299. referenced |= BIT(bank);
  300. }
  301. if (!referenced) {
  302. dev_err(nemc->dev, "%pOF has no addresses\n",
  303. child);
  304. continue;
  305. } else if (nemc->banks_present & referenced) {
  306. dev_err(nemc->dev, "%pOF conflicts with another node\n",
  307. child);
  308. continue;
  309. }
  310. /* Configure bank parameters. */
  311. for_each_set_bit(bank, &referenced, JZ4780_NEMC_NUM_BANKS) {
  312. if (!jz4780_nemc_configure_bank(nemc, bank, child)) {
  313. referenced = 0;
  314. break;
  315. }
  316. }
  317. if (referenced) {
  318. if (of_platform_device_create(child, NULL, nemc->dev))
  319. nemc->banks_present |= referenced;
  320. }
  321. }
  322. platform_set_drvdata(pdev, nemc);
  323. dev_info(dev, "JZ4780 NEMC initialised\n");
  324. return 0;
  325. }
  326. static int jz4780_nemc_remove(struct platform_device *pdev)
  327. {
  328. struct jz4780_nemc *nemc = platform_get_drvdata(pdev);
  329. clk_disable_unprepare(nemc->clk);
  330. return 0;
  331. }
  332. static const struct jz_soc_info jz4740_soc_info = {
  333. .tas_tah_cycles_max = 7,
  334. };
  335. static const struct jz_soc_info jz4780_soc_info = {
  336. .tas_tah_cycles_max = 15,
  337. };
  338. static const struct of_device_id jz4780_nemc_dt_match[] = {
  339. { .compatible = "ingenic,jz4740-nemc", .data = &jz4740_soc_info, },
  340. { .compatible = "ingenic,jz4780-nemc", .data = &jz4780_soc_info, },
  341. {},
  342. };
  343. static struct platform_driver jz4780_nemc_driver = {
  344. .probe = jz4780_nemc_probe,
  345. .remove = jz4780_nemc_remove,
  346. .driver = {
  347. .name = "jz4780-nemc",
  348. .of_match_table = of_match_ptr(jz4780_nemc_dt_match),
  349. },
  350. };
  351. static int __init jz4780_nemc_init(void)
  352. {
  353. return platform_driver_register(&jz4780_nemc_driver);
  354. }
  355. subsys_initcall(jz4780_nemc_init);