jedec_ddr.h 4.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Definitions for DDR memories based on JEDEC specs
  4. *
  5. * Copyright (C) 2012 Texas Instruments, Inc.
  6. *
  7. * Aneesh V <aneesh@ti.com>
  8. */
  9. #ifndef __JEDEC_DDR_H
  10. #define __JEDEC_DDR_H
  11. #include <linux/types.h>
  12. /* DDR Densities */
  13. #define DDR_DENSITY_64Mb 1
  14. #define DDR_DENSITY_128Mb 2
  15. #define DDR_DENSITY_256Mb 3
  16. #define DDR_DENSITY_512Mb 4
  17. #define DDR_DENSITY_1Gb 5
  18. #define DDR_DENSITY_2Gb 6
  19. #define DDR_DENSITY_4Gb 7
  20. #define DDR_DENSITY_8Gb 8
  21. #define DDR_DENSITY_16Gb 9
  22. #define DDR_DENSITY_32Gb 10
  23. /* DDR type */
  24. #define DDR_TYPE_DDR2 1
  25. #define DDR_TYPE_DDR3 2
  26. #define DDR_TYPE_LPDDR2_S4 3
  27. #define DDR_TYPE_LPDDR2_S2 4
  28. #define DDR_TYPE_LPDDR2_NVM 5
  29. #define DDR_TYPE_LPDDR3 6
  30. /* DDR IO width */
  31. #define DDR_IO_WIDTH_4 1
  32. #define DDR_IO_WIDTH_8 2
  33. #define DDR_IO_WIDTH_16 3
  34. #define DDR_IO_WIDTH_32 4
  35. /* Number of Row bits */
  36. #define R9 9
  37. #define R10 10
  38. #define R11 11
  39. #define R12 12
  40. #define R13 13
  41. #define R14 14
  42. #define R15 15
  43. #define R16 16
  44. /* Number of Column bits */
  45. #define C7 7
  46. #define C8 8
  47. #define C9 9
  48. #define C10 10
  49. #define C11 11
  50. #define C12 12
  51. /* Number of Banks */
  52. #define B1 0
  53. #define B2 1
  54. #define B4 2
  55. #define B8 3
  56. /* Refresh rate in nano-seconds */
  57. #define T_REFI_15_6 15600
  58. #define T_REFI_7_8 7800
  59. #define T_REFI_3_9 3900
  60. /* tRFC values */
  61. #define T_RFC_90 90000
  62. #define T_RFC_110 110000
  63. #define T_RFC_130 130000
  64. #define T_RFC_160 160000
  65. #define T_RFC_210 210000
  66. #define T_RFC_300 300000
  67. #define T_RFC_350 350000
  68. /* Mode register numbers */
  69. #define DDR_MR0 0
  70. #define DDR_MR1 1
  71. #define DDR_MR2 2
  72. #define DDR_MR3 3
  73. #define DDR_MR4 4
  74. #define DDR_MR5 5
  75. #define DDR_MR6 6
  76. #define DDR_MR7 7
  77. #define DDR_MR8 8
  78. #define DDR_MR9 9
  79. #define DDR_MR10 10
  80. #define DDR_MR11 11
  81. #define DDR_MR16 16
  82. #define DDR_MR17 17
  83. #define DDR_MR18 18
  84. /*
  85. * LPDDR2 related defines
  86. */
  87. /* MR4 register fields */
  88. #define MR4_SDRAM_REF_RATE_SHIFT 0
  89. #define MR4_SDRAM_REF_RATE_MASK 7
  90. #define MR4_TUF_SHIFT 7
  91. #define MR4_TUF_MASK (1 << 7)
  92. /* MR4 SDRAM Refresh Rate field values */
  93. #define SDRAM_TEMP_NOMINAL 0x3
  94. #define SDRAM_TEMP_RESERVED_4 0x4
  95. #define SDRAM_TEMP_HIGH_DERATE_REFRESH 0x5
  96. #define SDRAM_TEMP_HIGH_DERATE_REFRESH_AND_TIMINGS 0x6
  97. #define SDRAM_TEMP_VERY_HIGH_SHUTDOWN 0x7
  98. #define NUM_DDR_ADDR_TABLE_ENTRIES 11
  99. #define NUM_DDR_TIMING_TABLE_ENTRIES 4
  100. /* Structure for DDR addressing info from the JEDEC spec */
  101. struct lpddr2_addressing {
  102. u32 num_banks;
  103. u32 tREFI_ns;
  104. u32 tRFCab_ps;
  105. };
  106. /*
  107. * Structure for timings from the LPDDR2 datasheet
  108. * All parameters are in pico seconds(ps) unless explicitly indicated
  109. * with a suffix like tRAS_max_ns below
  110. */
  111. struct lpddr2_timings {
  112. u32 max_freq;
  113. u32 min_freq;
  114. u32 tRPab;
  115. u32 tRCD;
  116. u32 tWR;
  117. u32 tRAS_min;
  118. u32 tRRD;
  119. u32 tWTR;
  120. u32 tXP;
  121. u32 tRTP;
  122. u32 tCKESR;
  123. u32 tDQSCK_max;
  124. u32 tDQSCK_max_derated;
  125. u32 tFAW;
  126. u32 tZQCS;
  127. u32 tZQCL;
  128. u32 tZQinit;
  129. u32 tRAS_max_ns;
  130. };
  131. /*
  132. * Min value for some parameters in terms of number of tCK cycles(nCK)
  133. * Please set to zero parameters that are not valid for a given memory
  134. * type
  135. */
  136. struct lpddr2_min_tck {
  137. u32 tRPab;
  138. u32 tRCD;
  139. u32 tWR;
  140. u32 tRASmin;
  141. u32 tRRD;
  142. u32 tWTR;
  143. u32 tXP;
  144. u32 tRTP;
  145. u32 tCKE;
  146. u32 tCKESR;
  147. u32 tFAW;
  148. };
  149. extern const struct lpddr2_addressing
  150. lpddr2_jedec_addressing_table[NUM_DDR_ADDR_TABLE_ENTRIES];
  151. extern const struct lpddr2_timings
  152. lpddr2_jedec_timings[NUM_DDR_TIMING_TABLE_ENTRIES];
  153. extern const struct lpddr2_min_tck lpddr2_jedec_min_tck;
  154. /*
  155. * Structure for timings for LPDDR3 based on LPDDR2 plus additional fields.
  156. * All parameters are in pico seconds(ps) excluding max_freq, min_freq which
  157. * are in Hz.
  158. */
  159. struct lpddr3_timings {
  160. u32 max_freq;
  161. u32 min_freq;
  162. u32 tRFC;
  163. u32 tRRD;
  164. u32 tRPab;
  165. u32 tRPpb;
  166. u32 tRCD;
  167. u32 tRC;
  168. u32 tRAS;
  169. u32 tWTR;
  170. u32 tWR;
  171. u32 tRTP;
  172. u32 tW2W_C2C;
  173. u32 tR2R_C2C;
  174. u32 tWL;
  175. u32 tDQSCK;
  176. u32 tRL;
  177. u32 tFAW;
  178. u32 tXSR;
  179. u32 tXP;
  180. u32 tCKE;
  181. u32 tCKESR;
  182. u32 tMRD;
  183. };
  184. /*
  185. * Min value for some parameters in terms of number of tCK cycles(nCK)
  186. * Please set to zero parameters that are not valid for a given memory
  187. * type
  188. */
  189. struct lpddr3_min_tck {
  190. u32 tRFC;
  191. u32 tRRD;
  192. u32 tRPab;
  193. u32 tRPpb;
  194. u32 tRCD;
  195. u32 tRC;
  196. u32 tRAS;
  197. u32 tWTR;
  198. u32 tWR;
  199. u32 tRTP;
  200. u32 tW2W_C2C;
  201. u32 tR2R_C2C;
  202. u32 tWL;
  203. u32 tDQSCK;
  204. u32 tRL;
  205. u32 tFAW;
  206. u32 tXSR;
  207. u32 tXP;
  208. u32 tCKE;
  209. u32 tCKESR;
  210. u32 tMRD;
  211. };
  212. #endif /* __JEDEC_DDR_H */