emif.h 20 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Defines for the EMIF driver
  4. *
  5. * Copyright (C) 2012 Texas Instruments, Inc.
  6. *
  7. * Benoit Cousson (b-cousson@ti.com)
  8. */
  9. #ifndef __EMIF_H
  10. #define __EMIF_H
  11. /*
  12. * Maximum number of different frequencies supported by EMIF driver
  13. * Determines the number of entries in the pointer array for register
  14. * cache
  15. */
  16. #define EMIF_MAX_NUM_FREQUENCIES 6
  17. /* State of the core voltage */
  18. #define DDR_VOLTAGE_STABLE 0
  19. #define DDR_VOLTAGE_RAMPING 1
  20. /* Defines for timing De-rating */
  21. #define EMIF_NORMAL_TIMINGS 0
  22. #define EMIF_DERATED_TIMINGS 1
  23. /* Length of the forced read idle period in terms of cycles */
  24. #define EMIF_READ_IDLE_LEN_VAL 5
  25. /*
  26. * forced read idle interval to be used when voltage
  27. * is changed as part of DVFS/DPS - 1ms
  28. */
  29. #define READ_IDLE_INTERVAL_DVFS (1*1000000)
  30. /*
  31. * Forced read idle interval to be used when voltage is stable
  32. * 50us - or maximum value will do
  33. */
  34. #define READ_IDLE_INTERVAL_NORMAL (50*1000000)
  35. /* DLL calibration interval when voltage is NOT stable - 1us */
  36. #define DLL_CALIB_INTERVAL_DVFS (1*1000000)
  37. #define DLL_CALIB_ACK_WAIT_VAL 5
  38. /* Interval between ZQCS commands - hw team recommended value */
  39. #define EMIF_ZQCS_INTERVAL_US (50*1000)
  40. /* Enable ZQ Calibration on exiting Self-refresh */
  41. #define ZQ_SFEXITEN_ENABLE 1
  42. /*
  43. * ZQ Calibration simultaneously on both chip-selects:
  44. * Needs one calibration resistor per CS
  45. */
  46. #define ZQ_DUALCALEN_DISABLE 0
  47. #define ZQ_DUALCALEN_ENABLE 1
  48. #define T_ZQCS_DEFAULT_NS 90
  49. #define T_ZQCL_DEFAULT_NS 360
  50. #define T_ZQINIT_DEFAULT_NS 1000
  51. /* DPD_EN */
  52. #define DPD_DISABLE 0
  53. #define DPD_ENABLE 1
  54. /*
  55. * Default values for the low-power entry to be used if not provided by user.
  56. * OMAP4/5 has a hw bug(i735) due to which this value can not be less than 512
  57. * Timeout values are in DDR clock 'cycles' and frequency threshold in Hz
  58. */
  59. #define EMIF_LP_MODE_TIMEOUT_PERFORMANCE 2048
  60. #define EMIF_LP_MODE_TIMEOUT_POWER 512
  61. #define EMIF_LP_MODE_FREQ_THRESHOLD 400000000
  62. /* DDR_PHY_CTRL_1 values for EMIF4D - ATTILA PHY combination */
  63. #define EMIF_DDR_PHY_CTRL_1_BASE_VAL_ATTILAPHY 0x049FF000
  64. #define EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ_ATTILAPHY 0x41
  65. #define EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ_ATTILAPHY 0x80
  66. #define EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS_ATTILAPHY 0xFF
  67. /* DDR_PHY_CTRL_1 values for EMIF4D5 INTELLIPHY combination */
  68. #define EMIF_DDR_PHY_CTRL_1_BASE_VAL_INTELLIPHY 0x0E084200
  69. #define EMIF_PHY_TOTAL_READ_LATENCY_INTELLIPHY_PS 10000
  70. /* TEMP_ALERT_CONFIG - corresponding to temp gradient 5 C/s */
  71. #define TEMP_ALERT_POLL_INTERVAL_DEFAULT_MS 360
  72. #define EMIF_T_CSTA 3
  73. #define EMIF_T_PDLL_UL 128
  74. /* External PHY control registers magic values */
  75. #define EMIF_EXT_PHY_CTRL_1_VAL 0x04020080
  76. #define EMIF_EXT_PHY_CTRL_5_VAL 0x04010040
  77. #define EMIF_EXT_PHY_CTRL_6_VAL 0x01004010
  78. #define EMIF_EXT_PHY_CTRL_7_VAL 0x00001004
  79. #define EMIF_EXT_PHY_CTRL_8_VAL 0x04010040
  80. #define EMIF_EXT_PHY_CTRL_9_VAL 0x01004010
  81. #define EMIF_EXT_PHY_CTRL_10_VAL 0x00001004
  82. #define EMIF_EXT_PHY_CTRL_11_VAL 0x00000000
  83. #define EMIF_EXT_PHY_CTRL_12_VAL 0x00000000
  84. #define EMIF_EXT_PHY_CTRL_13_VAL 0x00000000
  85. #define EMIF_EXT_PHY_CTRL_14_VAL 0x80080080
  86. #define EMIF_EXT_PHY_CTRL_15_VAL 0x00800800
  87. #define EMIF_EXT_PHY_CTRL_16_VAL 0x08102040
  88. #define EMIF_EXT_PHY_CTRL_17_VAL 0x00000001
  89. #define EMIF_EXT_PHY_CTRL_18_VAL 0x540A8150
  90. #define EMIF_EXT_PHY_CTRL_19_VAL 0xA81502A0
  91. #define EMIF_EXT_PHY_CTRL_20_VAL 0x002A0540
  92. #define EMIF_EXT_PHY_CTRL_21_VAL 0x00000000
  93. #define EMIF_EXT_PHY_CTRL_22_VAL 0x00000000
  94. #define EMIF_EXT_PHY_CTRL_23_VAL 0x00000000
  95. #define EMIF_EXT_PHY_CTRL_24_VAL 0x00000077
  96. #define EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS 1200
  97. /* Registers offset */
  98. #define EMIF_MODULE_ID_AND_REVISION 0x0000
  99. #define EMIF_STATUS 0x0004
  100. #define EMIF_SDRAM_CONFIG 0x0008
  101. #define EMIF_SDRAM_CONFIG_2 0x000c
  102. #define EMIF_SDRAM_REFRESH_CONTROL 0x0010
  103. #define EMIF_SDRAM_REFRESH_CTRL_SHDW 0x0014
  104. #define EMIF_SDRAM_TIMING_1 0x0018
  105. #define EMIF_SDRAM_TIMING_1_SHDW 0x001c
  106. #define EMIF_SDRAM_TIMING_2 0x0020
  107. #define EMIF_SDRAM_TIMING_2_SHDW 0x0024
  108. #define EMIF_SDRAM_TIMING_3 0x0028
  109. #define EMIF_SDRAM_TIMING_3_SHDW 0x002c
  110. #define EMIF_LPDDR2_NVM_TIMING 0x0030
  111. #define EMIF_LPDDR2_NVM_TIMING_SHDW 0x0034
  112. #define EMIF_POWER_MANAGEMENT_CONTROL 0x0038
  113. #define EMIF_POWER_MANAGEMENT_CTRL_SHDW 0x003c
  114. #define EMIF_LPDDR2_MODE_REG_DATA 0x0040
  115. #define EMIF_LPDDR2_MODE_REG_CONFIG 0x0050
  116. #define EMIF_OCP_CONFIG 0x0054
  117. #define EMIF_OCP_CONFIG_VALUE_1 0x0058
  118. #define EMIF_OCP_CONFIG_VALUE_2 0x005c
  119. #define EMIF_IODFT_TEST_LOGIC_GLOBAL_CONTROL 0x0060
  120. #define EMIF_IODFT_TEST_LOGIC_CTRL_MISR_RESULT 0x0064
  121. #define EMIF_IODFT_TEST_LOGIC_ADDRESS_MISR_RESULT 0x0068
  122. #define EMIF_IODFT_TEST_LOGIC_DATA_MISR_RESULT_1 0x006c
  123. #define EMIF_IODFT_TEST_LOGIC_DATA_MISR_RESULT_2 0x0070
  124. #define EMIF_IODFT_TEST_LOGIC_DATA_MISR_RESULT_3 0x0074
  125. #define EMIF_PERFORMANCE_COUNTER_1 0x0080
  126. #define EMIF_PERFORMANCE_COUNTER_2 0x0084
  127. #define EMIF_PERFORMANCE_COUNTER_CONFIG 0x0088
  128. #define EMIF_PERFORMANCE_COUNTER_MASTER_REGION_SELECT 0x008c
  129. #define EMIF_PERFORMANCE_COUNTER_TIME 0x0090
  130. #define EMIF_MISC_REG 0x0094
  131. #define EMIF_DLL_CALIB_CTRL 0x0098
  132. #define EMIF_DLL_CALIB_CTRL_SHDW 0x009c
  133. #define EMIF_END_OF_INTERRUPT 0x00a0
  134. #define EMIF_SYSTEM_OCP_INTERRUPT_RAW_STATUS 0x00a4
  135. #define EMIF_LL_OCP_INTERRUPT_RAW_STATUS 0x00a8
  136. #define EMIF_SYSTEM_OCP_INTERRUPT_STATUS 0x00ac
  137. #define EMIF_LL_OCP_INTERRUPT_STATUS 0x00b0
  138. #define EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET 0x00b4
  139. #define EMIF_LL_OCP_INTERRUPT_ENABLE_SET 0x00b8
  140. #define EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_CLEAR 0x00bc
  141. #define EMIF_LL_OCP_INTERRUPT_ENABLE_CLEAR 0x00c0
  142. #define EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG 0x00c8
  143. #define EMIF_TEMPERATURE_ALERT_CONFIG 0x00cc
  144. #define EMIF_OCP_ERROR_LOG 0x00d0
  145. #define EMIF_READ_WRITE_LEVELING_RAMP_WINDOW 0x00d4
  146. #define EMIF_READ_WRITE_LEVELING_RAMP_CONTROL 0x00d8
  147. #define EMIF_READ_WRITE_LEVELING_CONTROL 0x00dc
  148. #define EMIF_DDR_PHY_CTRL_1 0x00e4
  149. #define EMIF_DDR_PHY_CTRL_1_SHDW 0x00e8
  150. #define EMIF_DDR_PHY_CTRL_2 0x00ec
  151. #define EMIF_PRIORITY_TO_CLASS_OF_SERVICE_MAPPING 0x0100
  152. #define EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_1_MAPPING 0x0104
  153. #define EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_2_MAPPING 0x0108
  154. #define EMIF_READ_WRITE_EXECUTION_THRESHOLD 0x0120
  155. #define EMIF_COS_CONFIG 0x0124
  156. #define EMIF_PHY_STATUS_1 0x0140
  157. #define EMIF_PHY_STATUS_2 0x0144
  158. #define EMIF_PHY_STATUS_3 0x0148
  159. #define EMIF_PHY_STATUS_4 0x014c
  160. #define EMIF_PHY_STATUS_5 0x0150
  161. #define EMIF_PHY_STATUS_6 0x0154
  162. #define EMIF_PHY_STATUS_7 0x0158
  163. #define EMIF_PHY_STATUS_8 0x015c
  164. #define EMIF_PHY_STATUS_9 0x0160
  165. #define EMIF_PHY_STATUS_10 0x0164
  166. #define EMIF_PHY_STATUS_11 0x0168
  167. #define EMIF_PHY_STATUS_12 0x016c
  168. #define EMIF_PHY_STATUS_13 0x0170
  169. #define EMIF_PHY_STATUS_14 0x0174
  170. #define EMIF_PHY_STATUS_15 0x0178
  171. #define EMIF_PHY_STATUS_16 0x017c
  172. #define EMIF_PHY_STATUS_17 0x0180
  173. #define EMIF_PHY_STATUS_18 0x0184
  174. #define EMIF_PHY_STATUS_19 0x0188
  175. #define EMIF_PHY_STATUS_20 0x018c
  176. #define EMIF_PHY_STATUS_21 0x0190
  177. #define EMIF_EXT_PHY_CTRL_1 0x0200
  178. #define EMIF_EXT_PHY_CTRL_1_SHDW 0x0204
  179. #define EMIF_EXT_PHY_CTRL_2 0x0208
  180. #define EMIF_EXT_PHY_CTRL_2_SHDW 0x020c
  181. #define EMIF_EXT_PHY_CTRL_3 0x0210
  182. #define EMIF_EXT_PHY_CTRL_3_SHDW 0x0214
  183. #define EMIF_EXT_PHY_CTRL_4 0x0218
  184. #define EMIF_EXT_PHY_CTRL_4_SHDW 0x021c
  185. #define EMIF_EXT_PHY_CTRL_5 0x0220
  186. #define EMIF_EXT_PHY_CTRL_5_SHDW 0x0224
  187. #define EMIF_EXT_PHY_CTRL_6 0x0228
  188. #define EMIF_EXT_PHY_CTRL_6_SHDW 0x022c
  189. #define EMIF_EXT_PHY_CTRL_7 0x0230
  190. #define EMIF_EXT_PHY_CTRL_7_SHDW 0x0234
  191. #define EMIF_EXT_PHY_CTRL_8 0x0238
  192. #define EMIF_EXT_PHY_CTRL_8_SHDW 0x023c
  193. #define EMIF_EXT_PHY_CTRL_9 0x0240
  194. #define EMIF_EXT_PHY_CTRL_9_SHDW 0x0244
  195. #define EMIF_EXT_PHY_CTRL_10 0x0248
  196. #define EMIF_EXT_PHY_CTRL_10_SHDW 0x024c
  197. #define EMIF_EXT_PHY_CTRL_11 0x0250
  198. #define EMIF_EXT_PHY_CTRL_11_SHDW 0x0254
  199. #define EMIF_EXT_PHY_CTRL_12 0x0258
  200. #define EMIF_EXT_PHY_CTRL_12_SHDW 0x025c
  201. #define EMIF_EXT_PHY_CTRL_13 0x0260
  202. #define EMIF_EXT_PHY_CTRL_13_SHDW 0x0264
  203. #define EMIF_EXT_PHY_CTRL_14 0x0268
  204. #define EMIF_EXT_PHY_CTRL_14_SHDW 0x026c
  205. #define EMIF_EXT_PHY_CTRL_15 0x0270
  206. #define EMIF_EXT_PHY_CTRL_15_SHDW 0x0274
  207. #define EMIF_EXT_PHY_CTRL_16 0x0278
  208. #define EMIF_EXT_PHY_CTRL_16_SHDW 0x027c
  209. #define EMIF_EXT_PHY_CTRL_17 0x0280
  210. #define EMIF_EXT_PHY_CTRL_17_SHDW 0x0284
  211. #define EMIF_EXT_PHY_CTRL_18 0x0288
  212. #define EMIF_EXT_PHY_CTRL_18_SHDW 0x028c
  213. #define EMIF_EXT_PHY_CTRL_19 0x0290
  214. #define EMIF_EXT_PHY_CTRL_19_SHDW 0x0294
  215. #define EMIF_EXT_PHY_CTRL_20 0x0298
  216. #define EMIF_EXT_PHY_CTRL_20_SHDW 0x029c
  217. #define EMIF_EXT_PHY_CTRL_21 0x02a0
  218. #define EMIF_EXT_PHY_CTRL_21_SHDW 0x02a4
  219. #define EMIF_EXT_PHY_CTRL_22 0x02a8
  220. #define EMIF_EXT_PHY_CTRL_22_SHDW 0x02ac
  221. #define EMIF_EXT_PHY_CTRL_23 0x02b0
  222. #define EMIF_EXT_PHY_CTRL_23_SHDW 0x02b4
  223. #define EMIF_EXT_PHY_CTRL_24 0x02b8
  224. #define EMIF_EXT_PHY_CTRL_24_SHDW 0x02bc
  225. #define EMIF_EXT_PHY_CTRL_25 0x02c0
  226. #define EMIF_EXT_PHY_CTRL_25_SHDW 0x02c4
  227. #define EMIF_EXT_PHY_CTRL_26 0x02c8
  228. #define EMIF_EXT_PHY_CTRL_26_SHDW 0x02cc
  229. #define EMIF_EXT_PHY_CTRL_27 0x02d0
  230. #define EMIF_EXT_PHY_CTRL_27_SHDW 0x02d4
  231. #define EMIF_EXT_PHY_CTRL_28 0x02d8
  232. #define EMIF_EXT_PHY_CTRL_28_SHDW 0x02dc
  233. #define EMIF_EXT_PHY_CTRL_29 0x02e0
  234. #define EMIF_EXT_PHY_CTRL_29_SHDW 0x02e4
  235. #define EMIF_EXT_PHY_CTRL_30 0x02e8
  236. #define EMIF_EXT_PHY_CTRL_30_SHDW 0x02ec
  237. /* Registers shifts and masks */
  238. /* EMIF_MODULE_ID_AND_REVISION */
  239. #define SCHEME_SHIFT 30
  240. #define SCHEME_MASK (0x3 << 30)
  241. #define MODULE_ID_SHIFT 16
  242. #define MODULE_ID_MASK (0xfff << 16)
  243. #define RTL_VERSION_SHIFT 11
  244. #define RTL_VERSION_MASK (0x1f << 11)
  245. #define MAJOR_REVISION_SHIFT 8
  246. #define MAJOR_REVISION_MASK (0x7 << 8)
  247. #define MINOR_REVISION_SHIFT 0
  248. #define MINOR_REVISION_MASK (0x3f << 0)
  249. /* STATUS */
  250. #define BE_SHIFT 31
  251. #define BE_MASK (1 << 31)
  252. #define DUAL_CLK_MODE_SHIFT 30
  253. #define DUAL_CLK_MODE_MASK (1 << 30)
  254. #define FAST_INIT_SHIFT 29
  255. #define FAST_INIT_MASK (1 << 29)
  256. #define RDLVLGATETO_SHIFT 6
  257. #define RDLVLGATETO_MASK (1 << 6)
  258. #define RDLVLTO_SHIFT 5
  259. #define RDLVLTO_MASK (1 << 5)
  260. #define WRLVLTO_SHIFT 4
  261. #define WRLVLTO_MASK (1 << 4)
  262. #define PHY_DLL_READY_SHIFT 2
  263. #define PHY_DLL_READY_MASK (1 << 2)
  264. /* SDRAM_CONFIG */
  265. #define SDRAM_TYPE_SHIFT 29
  266. #define SDRAM_TYPE_MASK (0x7 << 29)
  267. #define IBANK_POS_SHIFT 27
  268. #define IBANK_POS_MASK (0x3 << 27)
  269. #define DDR_TERM_SHIFT 24
  270. #define DDR_TERM_MASK (0x7 << 24)
  271. #define DDR2_DDQS_SHIFT 23
  272. #define DDR2_DDQS_MASK (1 << 23)
  273. #define DYN_ODT_SHIFT 21
  274. #define DYN_ODT_MASK (0x3 << 21)
  275. #define DDR_DISABLE_DLL_SHIFT 20
  276. #define DDR_DISABLE_DLL_MASK (1 << 20)
  277. #define SDRAM_DRIVE_SHIFT 18
  278. #define SDRAM_DRIVE_MASK (0x3 << 18)
  279. #define CWL_SHIFT 16
  280. #define CWL_MASK (0x3 << 16)
  281. #define NARROW_MODE_SHIFT 14
  282. #define NARROW_MODE_MASK (0x3 << 14)
  283. #define CL_SHIFT 10
  284. #define CL_MASK (0xf << 10)
  285. #define ROWSIZE_SHIFT 7
  286. #define ROWSIZE_MASK (0x7 << 7)
  287. #define IBANK_SHIFT 4
  288. #define IBANK_MASK (0x7 << 4)
  289. #define EBANK_SHIFT 3
  290. #define EBANK_MASK (1 << 3)
  291. #define PAGESIZE_SHIFT 0
  292. #define PAGESIZE_MASK (0x7 << 0)
  293. /* SDRAM_CONFIG_2 */
  294. #define CS1NVMEN_SHIFT 30
  295. #define CS1NVMEN_MASK (1 << 30)
  296. #define EBANK_POS_SHIFT 27
  297. #define EBANK_POS_MASK (1 << 27)
  298. #define RDBNUM_SHIFT 4
  299. #define RDBNUM_MASK (0x3 << 4)
  300. #define RDBSIZE_SHIFT 0
  301. #define RDBSIZE_MASK (0x7 << 0)
  302. /* SDRAM_REFRESH_CONTROL */
  303. #define INITREF_DIS_SHIFT 31
  304. #define INITREF_DIS_MASK (1 << 31)
  305. #define SRT_SHIFT 29
  306. #define SRT_MASK (1 << 29)
  307. #define ASR_SHIFT 28
  308. #define ASR_MASK (1 << 28)
  309. #define PASR_SHIFT 24
  310. #define PASR_MASK (0x7 << 24)
  311. #define REFRESH_RATE_SHIFT 0
  312. #define REFRESH_RATE_MASK (0xffff << 0)
  313. /* SDRAM_TIMING_1 */
  314. #define T_RTW_SHIFT 29
  315. #define T_RTW_MASK (0x7 << 29)
  316. #define T_RP_SHIFT 25
  317. #define T_RP_MASK (0xf << 25)
  318. #define T_RCD_SHIFT 21
  319. #define T_RCD_MASK (0xf << 21)
  320. #define T_WR_SHIFT 17
  321. #define T_WR_MASK (0xf << 17)
  322. #define T_RAS_SHIFT 12
  323. #define T_RAS_MASK (0x1f << 12)
  324. #define T_RC_SHIFT 6
  325. #define T_RC_MASK (0x3f << 6)
  326. #define T_RRD_SHIFT 3
  327. #define T_RRD_MASK (0x7 << 3)
  328. #define T_WTR_SHIFT 0
  329. #define T_WTR_MASK (0x7 << 0)
  330. /* SDRAM_TIMING_2 */
  331. #define T_XP_SHIFT 28
  332. #define T_XP_MASK (0x7 << 28)
  333. #define T_ODT_SHIFT 25
  334. #define T_ODT_MASK (0x7 << 25)
  335. #define T_XSNR_SHIFT 16
  336. #define T_XSNR_MASK (0x1ff << 16)
  337. #define T_XSRD_SHIFT 6
  338. #define T_XSRD_MASK (0x3ff << 6)
  339. #define T_RTP_SHIFT 3
  340. #define T_RTP_MASK (0x7 << 3)
  341. #define T_CKE_SHIFT 0
  342. #define T_CKE_MASK (0x7 << 0)
  343. /* SDRAM_TIMING_3 */
  344. #define T_PDLL_UL_SHIFT 28
  345. #define T_PDLL_UL_MASK (0xf << 28)
  346. #define T_CSTA_SHIFT 24
  347. #define T_CSTA_MASK (0xf << 24)
  348. #define T_CKESR_SHIFT 21
  349. #define T_CKESR_MASK (0x7 << 21)
  350. #define ZQ_ZQCS_SHIFT 15
  351. #define ZQ_ZQCS_MASK (0x3f << 15)
  352. #define T_TDQSCKMAX_SHIFT 13
  353. #define T_TDQSCKMAX_MASK (0x3 << 13)
  354. #define T_RFC_SHIFT 4
  355. #define T_RFC_MASK (0x1ff << 4)
  356. #define T_RAS_MAX_SHIFT 0
  357. #define T_RAS_MAX_MASK (0xf << 0)
  358. /* POWER_MANAGEMENT_CONTROL */
  359. #define PD_TIM_SHIFT 12
  360. #define PD_TIM_MASK (0xf << 12)
  361. #define DPD_EN_SHIFT 11
  362. #define DPD_EN_MASK (1 << 11)
  363. #define LP_MODE_SHIFT 8
  364. #define LP_MODE_MASK (0x7 << 8)
  365. #define SR_TIM_SHIFT 4
  366. #define SR_TIM_MASK (0xf << 4)
  367. #define CS_TIM_SHIFT 0
  368. #define CS_TIM_MASK (0xf << 0)
  369. /* LPDDR2_MODE_REG_DATA */
  370. #define VALUE_0_SHIFT 0
  371. #define VALUE_0_MASK (0x7f << 0)
  372. /* LPDDR2_MODE_REG_CONFIG */
  373. #define CS_SHIFT 31
  374. #define CS_MASK (1 << 31)
  375. #define REFRESH_EN_SHIFT 30
  376. #define REFRESH_EN_MASK (1 << 30)
  377. #define ADDRESS_SHIFT 0
  378. #define ADDRESS_MASK (0xff << 0)
  379. /* OCP_CONFIG */
  380. #define SYS_THRESH_MAX_SHIFT 24
  381. #define SYS_THRESH_MAX_MASK (0xf << 24)
  382. #define MPU_THRESH_MAX_SHIFT 20
  383. #define MPU_THRESH_MAX_MASK (0xf << 20)
  384. #define LL_THRESH_MAX_SHIFT 16
  385. #define LL_THRESH_MAX_MASK (0xf << 16)
  386. /* PERFORMANCE_COUNTER_1 */
  387. #define COUNTER1_SHIFT 0
  388. #define COUNTER1_MASK (0xffffffff << 0)
  389. /* PERFORMANCE_COUNTER_2 */
  390. #define COUNTER2_SHIFT 0
  391. #define COUNTER2_MASK (0xffffffff << 0)
  392. /* PERFORMANCE_COUNTER_CONFIG */
  393. #define CNTR2_MCONNID_EN_SHIFT 31
  394. #define CNTR2_MCONNID_EN_MASK (1 << 31)
  395. #define CNTR2_REGION_EN_SHIFT 30
  396. #define CNTR2_REGION_EN_MASK (1 << 30)
  397. #define CNTR2_CFG_SHIFT 16
  398. #define CNTR2_CFG_MASK (0xf << 16)
  399. #define CNTR1_MCONNID_EN_SHIFT 15
  400. #define CNTR1_MCONNID_EN_MASK (1 << 15)
  401. #define CNTR1_REGION_EN_SHIFT 14
  402. #define CNTR1_REGION_EN_MASK (1 << 14)
  403. #define CNTR1_CFG_SHIFT 0
  404. #define CNTR1_CFG_MASK (0xf << 0)
  405. /* PERFORMANCE_COUNTER_MASTER_REGION_SELECT */
  406. #define MCONNID2_SHIFT 24
  407. #define MCONNID2_MASK (0xff << 24)
  408. #define REGION_SEL2_SHIFT 16
  409. #define REGION_SEL2_MASK (0x3 << 16)
  410. #define MCONNID1_SHIFT 8
  411. #define MCONNID1_MASK (0xff << 8)
  412. #define REGION_SEL1_SHIFT 0
  413. #define REGION_SEL1_MASK (0x3 << 0)
  414. /* PERFORMANCE_COUNTER_TIME */
  415. #define TOTAL_TIME_SHIFT 0
  416. #define TOTAL_TIME_MASK (0xffffffff << 0)
  417. /* DLL_CALIB_CTRL */
  418. #define ACK_WAIT_SHIFT 16
  419. #define ACK_WAIT_MASK (0xf << 16)
  420. #define DLL_CALIB_INTERVAL_SHIFT 0
  421. #define DLL_CALIB_INTERVAL_MASK (0x1ff << 0)
  422. /* END_OF_INTERRUPT */
  423. #define EOI_SHIFT 0
  424. #define EOI_MASK (1 << 0)
  425. /* SYSTEM_OCP_INTERRUPT_RAW_STATUS */
  426. #define DNV_SYS_SHIFT 2
  427. #define DNV_SYS_MASK (1 << 2)
  428. #define TA_SYS_SHIFT 1
  429. #define TA_SYS_MASK (1 << 1)
  430. #define ERR_SYS_SHIFT 0
  431. #define ERR_SYS_MASK (1 << 0)
  432. /* LOW_LATENCY_OCP_INTERRUPT_RAW_STATUS */
  433. #define DNV_LL_SHIFT 2
  434. #define DNV_LL_MASK (1 << 2)
  435. #define TA_LL_SHIFT 1
  436. #define TA_LL_MASK (1 << 1)
  437. #define ERR_LL_SHIFT 0
  438. #define ERR_LL_MASK (1 << 0)
  439. /* SYSTEM_OCP_INTERRUPT_ENABLE_SET */
  440. #define EN_DNV_SYS_SHIFT 2
  441. #define EN_DNV_SYS_MASK (1 << 2)
  442. #define EN_TA_SYS_SHIFT 1
  443. #define EN_TA_SYS_MASK (1 << 1)
  444. #define EN_ERR_SYS_SHIFT 0
  445. #define EN_ERR_SYS_MASK (1 << 0)
  446. /* LOW_LATENCY_OCP_INTERRUPT_ENABLE_SET */
  447. #define EN_DNV_LL_SHIFT 2
  448. #define EN_DNV_LL_MASK (1 << 2)
  449. #define EN_TA_LL_SHIFT 1
  450. #define EN_TA_LL_MASK (1 << 1)
  451. #define EN_ERR_LL_SHIFT 0
  452. #define EN_ERR_LL_MASK (1 << 0)
  453. /* SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG */
  454. #define ZQ_CS1EN_SHIFT 31
  455. #define ZQ_CS1EN_MASK (1 << 31)
  456. #define ZQ_CS0EN_SHIFT 30
  457. #define ZQ_CS0EN_MASK (1 << 30)
  458. #define ZQ_DUALCALEN_SHIFT 29
  459. #define ZQ_DUALCALEN_MASK (1 << 29)
  460. #define ZQ_SFEXITEN_SHIFT 28
  461. #define ZQ_SFEXITEN_MASK (1 << 28)
  462. #define ZQ_ZQINIT_MULT_SHIFT 18
  463. #define ZQ_ZQINIT_MULT_MASK (0x3 << 18)
  464. #define ZQ_ZQCL_MULT_SHIFT 16
  465. #define ZQ_ZQCL_MULT_MASK (0x3 << 16)
  466. #define ZQ_REFINTERVAL_SHIFT 0
  467. #define ZQ_REFINTERVAL_MASK (0xffff << 0)
  468. /* TEMPERATURE_ALERT_CONFIG */
  469. #define TA_CS1EN_SHIFT 31
  470. #define TA_CS1EN_MASK (1 << 31)
  471. #define TA_CS0EN_SHIFT 30
  472. #define TA_CS0EN_MASK (1 << 30)
  473. #define TA_SFEXITEN_SHIFT 28
  474. #define TA_SFEXITEN_MASK (1 << 28)
  475. #define TA_DEVWDT_SHIFT 26
  476. #define TA_DEVWDT_MASK (0x3 << 26)
  477. #define TA_DEVCNT_SHIFT 24
  478. #define TA_DEVCNT_MASK (0x3 << 24)
  479. #define TA_REFINTERVAL_SHIFT 0
  480. #define TA_REFINTERVAL_MASK (0x3fffff << 0)
  481. /* OCP_ERROR_LOG */
  482. #define MADDRSPACE_SHIFT 14
  483. #define MADDRSPACE_MASK (0x3 << 14)
  484. #define MBURSTSEQ_SHIFT 11
  485. #define MBURSTSEQ_MASK (0x7 << 11)
  486. #define MCMD_SHIFT 8
  487. #define MCMD_MASK (0x7 << 8)
  488. #define MCONNID_SHIFT 0
  489. #define MCONNID_MASK (0xff << 0)
  490. /* READ_WRITE_LEVELING_CONTROL */
  491. #define RDWRLVLFULL_START 0x80000000
  492. /* DDR_PHY_CTRL_1 - EMIF4D */
  493. #define DLL_SLAVE_DLY_CTRL_SHIFT_4D 4
  494. #define DLL_SLAVE_DLY_CTRL_MASK_4D (0xFF << 4)
  495. #define READ_LATENCY_SHIFT_4D 0
  496. #define READ_LATENCY_MASK_4D (0xf << 0)
  497. /* DDR_PHY_CTRL_1 - EMIF4D5 */
  498. #define DLL_HALF_DELAY_SHIFT_4D5 21
  499. #define DLL_HALF_DELAY_MASK_4D5 (1 << 21)
  500. #define READ_LATENCY_SHIFT_4D5 0
  501. #define READ_LATENCY_MASK_4D5 (0x1f << 0)
  502. /* DDR_PHY_CTRL_1_SHDW */
  503. #define DDR_PHY_CTRL_1_SHDW_SHIFT 5
  504. #define DDR_PHY_CTRL_1_SHDW_MASK (0x7ffffff << 5)
  505. #define READ_LATENCY_SHDW_SHIFT 0
  506. #define READ_LATENCY_SHDW_MASK (0x1f << 0)
  507. #define EMIF_SRAM_AM33_REG_LAYOUT 0x00000000
  508. #define EMIF_SRAM_AM43_REG_LAYOUT 0x00000001
  509. #ifndef __ASSEMBLY__
  510. /*
  511. * Structure containing shadow of important registers in EMIF
  512. * The calculation function fills in this structure to be later used for
  513. * initialisation and DVFS
  514. */
  515. struct emif_regs {
  516. u32 freq;
  517. u32 ref_ctrl_shdw;
  518. u32 ref_ctrl_shdw_derated;
  519. u32 sdram_tim1_shdw;
  520. u32 sdram_tim1_shdw_derated;
  521. u32 sdram_tim2_shdw;
  522. u32 sdram_tim3_shdw;
  523. u32 sdram_tim3_shdw_derated;
  524. u32 pwr_mgmt_ctrl_shdw;
  525. union {
  526. u32 read_idle_ctrl_shdw_normal;
  527. u32 dll_calib_ctrl_shdw_normal;
  528. };
  529. union {
  530. u32 read_idle_ctrl_shdw_volt_ramp;
  531. u32 dll_calib_ctrl_shdw_volt_ramp;
  532. };
  533. u32 phy_ctrl_1_shdw;
  534. u32 ext_phy_ctrl_2_shdw;
  535. u32 ext_phy_ctrl_3_shdw;
  536. u32 ext_phy_ctrl_4_shdw;
  537. };
  538. struct ti_emif_pm_functions;
  539. extern unsigned int ti_emif_sram;
  540. extern unsigned int ti_emif_sram_sz;
  541. extern struct ti_emif_pm_data ti_emif_pm_sram_data;
  542. extern struct emif_regs_amx3 ti_emif_regs_amx3;
  543. void ti_emif_save_context(void);
  544. void ti_emif_restore_context(void);
  545. void ti_emif_run_hw_leveling(void);
  546. void ti_emif_enter_sr(void);
  547. void ti_emif_exit_sr(void);
  548. void ti_emif_abort_sr(void);
  549. #endif /* __ASSEMBLY__ */
  550. #endif /* __EMIF_H */