emif.c 54 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * EMIF driver
  4. *
  5. * Copyright (C) 2012 Texas Instruments, Inc.
  6. *
  7. * Aneesh V <aneesh@ti.com>
  8. * Santosh Shilimkar <santosh.shilimkar@ti.com>
  9. */
  10. #include <linux/err.h>
  11. #include <linux/kernel.h>
  12. #include <linux/reboot.h>
  13. #include <linux/platform_data/emif_plat.h>
  14. #include <linux/io.h>
  15. #include <linux/device.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/slab.h>
  19. #include <linux/of.h>
  20. #include <linux/debugfs.h>
  21. #include <linux/seq_file.h>
  22. #include <linux/module.h>
  23. #include <linux/list.h>
  24. #include <linux/spinlock.h>
  25. #include <linux/pm.h>
  26. #include "emif.h"
  27. #include "jedec_ddr.h"
  28. #include "of_memory.h"
  29. /**
  30. * struct emif_data - Per device static data for driver's use
  31. * @duplicate: Whether the DDR devices attached to this EMIF
  32. * instance are exactly same as that on EMIF1. In
  33. * this case we can save some memory and processing
  34. * @temperature_level: Maximum temperature of LPDDR2 devices attached
  35. * to this EMIF - read from MR4 register. If there
  36. * are two devices attached to this EMIF, this
  37. * value is the maximum of the two temperature
  38. * levels.
  39. * @node: node in the device list
  40. * @base: base address of memory-mapped IO registers.
  41. * @dev: device pointer.
  42. * @addressing table with addressing information from the spec
  43. * @regs_cache: An array of 'struct emif_regs' that stores
  44. * calculated register values for different
  45. * frequencies, to avoid re-calculating them on
  46. * each DVFS transition.
  47. * @curr_regs: The set of register values used in the last
  48. * frequency change (i.e. corresponding to the
  49. * frequency in effect at the moment)
  50. * @plat_data: Pointer to saved platform data.
  51. * @debugfs_root: dentry to the root folder for EMIF in debugfs
  52. * @np_ddr: Pointer to ddr device tree node
  53. */
  54. struct emif_data {
  55. u8 duplicate;
  56. u8 temperature_level;
  57. u8 lpmode;
  58. struct list_head node;
  59. unsigned long irq_state;
  60. void __iomem *base;
  61. struct device *dev;
  62. const struct lpddr2_addressing *addressing;
  63. struct emif_regs *regs_cache[EMIF_MAX_NUM_FREQUENCIES];
  64. struct emif_regs *curr_regs;
  65. struct emif_platform_data *plat_data;
  66. struct dentry *debugfs_root;
  67. struct device_node *np_ddr;
  68. };
  69. static struct emif_data *emif1;
  70. static spinlock_t emif_lock;
  71. static unsigned long irq_state;
  72. static u32 t_ck; /* DDR clock period in ps */
  73. static LIST_HEAD(device_list);
  74. #ifdef CONFIG_DEBUG_FS
  75. static void do_emif_regdump_show(struct seq_file *s, struct emif_data *emif,
  76. struct emif_regs *regs)
  77. {
  78. u32 type = emif->plat_data->device_info->type;
  79. u32 ip_rev = emif->plat_data->ip_rev;
  80. seq_printf(s, "EMIF register cache dump for %dMHz\n",
  81. regs->freq/1000000);
  82. seq_printf(s, "ref_ctrl_shdw\t: 0x%08x\n", regs->ref_ctrl_shdw);
  83. seq_printf(s, "sdram_tim1_shdw\t: 0x%08x\n", regs->sdram_tim1_shdw);
  84. seq_printf(s, "sdram_tim2_shdw\t: 0x%08x\n", regs->sdram_tim2_shdw);
  85. seq_printf(s, "sdram_tim3_shdw\t: 0x%08x\n", regs->sdram_tim3_shdw);
  86. if (ip_rev == EMIF_4D) {
  87. seq_printf(s, "read_idle_ctrl_shdw_normal\t: 0x%08x\n",
  88. regs->read_idle_ctrl_shdw_normal);
  89. seq_printf(s, "read_idle_ctrl_shdw_volt_ramp\t: 0x%08x\n",
  90. regs->read_idle_ctrl_shdw_volt_ramp);
  91. } else if (ip_rev == EMIF_4D5) {
  92. seq_printf(s, "dll_calib_ctrl_shdw_normal\t: 0x%08x\n",
  93. regs->dll_calib_ctrl_shdw_normal);
  94. seq_printf(s, "dll_calib_ctrl_shdw_volt_ramp\t: 0x%08x\n",
  95. regs->dll_calib_ctrl_shdw_volt_ramp);
  96. }
  97. if (type == DDR_TYPE_LPDDR2_S2 || type == DDR_TYPE_LPDDR2_S4) {
  98. seq_printf(s, "ref_ctrl_shdw_derated\t: 0x%08x\n",
  99. regs->ref_ctrl_shdw_derated);
  100. seq_printf(s, "sdram_tim1_shdw_derated\t: 0x%08x\n",
  101. regs->sdram_tim1_shdw_derated);
  102. seq_printf(s, "sdram_tim3_shdw_derated\t: 0x%08x\n",
  103. regs->sdram_tim3_shdw_derated);
  104. }
  105. }
  106. static int emif_regdump_show(struct seq_file *s, void *unused)
  107. {
  108. struct emif_data *emif = s->private;
  109. struct emif_regs **regs_cache;
  110. int i;
  111. if (emif->duplicate)
  112. regs_cache = emif1->regs_cache;
  113. else
  114. regs_cache = emif->regs_cache;
  115. for (i = 0; i < EMIF_MAX_NUM_FREQUENCIES && regs_cache[i]; i++) {
  116. do_emif_regdump_show(s, emif, regs_cache[i]);
  117. seq_putc(s, '\n');
  118. }
  119. return 0;
  120. }
  121. DEFINE_SHOW_ATTRIBUTE(emif_regdump);
  122. static int emif_mr4_show(struct seq_file *s, void *unused)
  123. {
  124. struct emif_data *emif = s->private;
  125. seq_printf(s, "MR4=%d\n", emif->temperature_level);
  126. return 0;
  127. }
  128. DEFINE_SHOW_ATTRIBUTE(emif_mr4);
  129. static int __init_or_module emif_debugfs_init(struct emif_data *emif)
  130. {
  131. emif->debugfs_root = debugfs_create_dir(dev_name(emif->dev), NULL);
  132. debugfs_create_file("regcache_dump", S_IRUGO, emif->debugfs_root, emif,
  133. &emif_regdump_fops);
  134. debugfs_create_file("mr4", S_IRUGO, emif->debugfs_root, emif,
  135. &emif_mr4_fops);
  136. return 0;
  137. }
  138. static void __exit emif_debugfs_exit(struct emif_data *emif)
  139. {
  140. debugfs_remove_recursive(emif->debugfs_root);
  141. emif->debugfs_root = NULL;
  142. }
  143. #else
  144. static inline int __init_or_module emif_debugfs_init(struct emif_data *emif)
  145. {
  146. return 0;
  147. }
  148. static inline void __exit emif_debugfs_exit(struct emif_data *emif)
  149. {
  150. }
  151. #endif
  152. /*
  153. * Calculate the period of DDR clock from frequency value
  154. */
  155. static void set_ddr_clk_period(u32 freq)
  156. {
  157. /* Divide 10^12 by frequency to get period in ps */
  158. t_ck = (u32)DIV_ROUND_UP_ULL(1000000000000ull, freq);
  159. }
  160. /*
  161. * Get bus width used by EMIF. Note that this may be different from the
  162. * bus width of the DDR devices used. For instance two 16-bit DDR devices
  163. * may be connected to a given CS of EMIF. In this case bus width as far
  164. * as EMIF is concerned is 32, where as the DDR bus width is 16 bits.
  165. */
  166. static u32 get_emif_bus_width(struct emif_data *emif)
  167. {
  168. u32 width;
  169. void __iomem *base = emif->base;
  170. width = (readl(base + EMIF_SDRAM_CONFIG) & NARROW_MODE_MASK)
  171. >> NARROW_MODE_SHIFT;
  172. width = width == 0 ? 32 : 16;
  173. return width;
  174. }
  175. /*
  176. * Get the CL from SDRAM_CONFIG register
  177. */
  178. static u32 get_cl(struct emif_data *emif)
  179. {
  180. u32 cl;
  181. void __iomem *base = emif->base;
  182. cl = (readl(base + EMIF_SDRAM_CONFIG) & CL_MASK) >> CL_SHIFT;
  183. return cl;
  184. }
  185. static void set_lpmode(struct emif_data *emif, u8 lpmode)
  186. {
  187. u32 temp;
  188. void __iomem *base = emif->base;
  189. /*
  190. * Workaround for errata i743 - LPDDR2 Power-Down State is Not
  191. * Efficient
  192. *
  193. * i743 DESCRIPTION:
  194. * The EMIF supports power-down state for low power. The EMIF
  195. * automatically puts the SDRAM into power-down after the memory is
  196. * not accessed for a defined number of cycles and the
  197. * EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE bit field is set to 0x4.
  198. * As the EMIF supports automatic output impedance calibration, a ZQ
  199. * calibration long command is issued every time it exits active
  200. * power-down and precharge power-down modes. The EMIF waits and
  201. * blocks any other command during this calibration.
  202. * The EMIF does not allow selective disabling of ZQ calibration upon
  203. * exit of power-down mode. Due to very short periods of power-down
  204. * cycles, ZQ calibration overhead creates bandwidth issues and
  205. * increases overall system power consumption. On the other hand,
  206. * issuing ZQ calibration long commands when exiting self-refresh is
  207. * still required.
  208. *
  209. * WORKAROUND
  210. * Because there is no power consumption benefit of the power-down due
  211. * to the calibration and there is a performance risk, the guideline
  212. * is to not allow power-down state and, therefore, to not have set
  213. * the EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE bit field to 0x4.
  214. */
  215. if ((emif->plat_data->ip_rev == EMIF_4D) &&
  216. (lpmode == EMIF_LP_MODE_PWR_DN)) {
  217. WARN_ONCE(1,
  218. "REG_LP_MODE = LP_MODE_PWR_DN(4) is prohibited by erratum i743 switch to LP_MODE_SELF_REFRESH(2)\n");
  219. /* rollback LP_MODE to Self-refresh mode */
  220. lpmode = EMIF_LP_MODE_SELF_REFRESH;
  221. }
  222. temp = readl(base + EMIF_POWER_MANAGEMENT_CONTROL);
  223. temp &= ~LP_MODE_MASK;
  224. temp |= (lpmode << LP_MODE_SHIFT);
  225. writel(temp, base + EMIF_POWER_MANAGEMENT_CONTROL);
  226. }
  227. static void do_freq_update(void)
  228. {
  229. struct emif_data *emif;
  230. /*
  231. * Workaround for errata i728: Disable LPMODE during FREQ_UPDATE
  232. *
  233. * i728 DESCRIPTION:
  234. * The EMIF automatically puts the SDRAM into self-refresh mode
  235. * after the EMIF has not performed accesses during
  236. * EMIF_PWR_MGMT_CTRL[7:4] REG_SR_TIM number of DDR clock cycles
  237. * and the EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE bit field is set
  238. * to 0x2. If during a small window the following three events
  239. * occur:
  240. * - The SR_TIMING counter expires
  241. * - And frequency change is requested
  242. * - And OCP access is requested
  243. * Then it causes instable clock on the DDR interface.
  244. *
  245. * WORKAROUND
  246. * To avoid the occurrence of the three events, the workaround
  247. * is to disable the self-refresh when requesting a frequency
  248. * change. Before requesting a frequency change the software must
  249. * program EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE to 0x0. When the
  250. * frequency change has been done, the software can reprogram
  251. * EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE to 0x2
  252. */
  253. list_for_each_entry(emif, &device_list, node) {
  254. if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH)
  255. set_lpmode(emif, EMIF_LP_MODE_DISABLE);
  256. }
  257. /*
  258. * TODO: Do FREQ_UPDATE here when an API
  259. * is available for this as part of the new
  260. * clock framework
  261. */
  262. list_for_each_entry(emif, &device_list, node) {
  263. if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH)
  264. set_lpmode(emif, EMIF_LP_MODE_SELF_REFRESH);
  265. }
  266. }
  267. /* Find addressing table entry based on the device's type and density */
  268. static const struct lpddr2_addressing *get_addressing_table(
  269. const struct ddr_device_info *device_info)
  270. {
  271. u32 index, type, density;
  272. type = device_info->type;
  273. density = device_info->density;
  274. switch (type) {
  275. case DDR_TYPE_LPDDR2_S4:
  276. index = density - 1;
  277. break;
  278. case DDR_TYPE_LPDDR2_S2:
  279. switch (density) {
  280. case DDR_DENSITY_1Gb:
  281. case DDR_DENSITY_2Gb:
  282. index = density + 3;
  283. break;
  284. default:
  285. index = density - 1;
  286. }
  287. break;
  288. default:
  289. return NULL;
  290. }
  291. return &lpddr2_jedec_addressing_table[index];
  292. }
  293. /*
  294. * Find the the right timing table from the array of timing
  295. * tables of the device using DDR clock frequency
  296. */
  297. static const struct lpddr2_timings *get_timings_table(struct emif_data *emif,
  298. u32 freq)
  299. {
  300. u32 i, min, max, freq_nearest;
  301. const struct lpddr2_timings *timings = NULL;
  302. const struct lpddr2_timings *timings_arr = emif->plat_data->timings;
  303. struct device *dev = emif->dev;
  304. /* Start with a very high frequency - 1GHz */
  305. freq_nearest = 1000000000;
  306. /*
  307. * Find the timings table such that:
  308. * 1. the frequency range covers the required frequency(safe) AND
  309. * 2. the max_freq is closest to the required frequency(optimal)
  310. */
  311. for (i = 0; i < emif->plat_data->timings_arr_size; i++) {
  312. max = timings_arr[i].max_freq;
  313. min = timings_arr[i].min_freq;
  314. if ((freq >= min) && (freq <= max) && (max < freq_nearest)) {
  315. freq_nearest = max;
  316. timings = &timings_arr[i];
  317. }
  318. }
  319. if (!timings)
  320. dev_err(dev, "%s: couldn't find timings for - %dHz\n",
  321. __func__, freq);
  322. dev_dbg(dev, "%s: timings table: freq %d, speed bin freq %d\n",
  323. __func__, freq, freq_nearest);
  324. return timings;
  325. }
  326. static u32 get_sdram_ref_ctrl_shdw(u32 freq,
  327. const struct lpddr2_addressing *addressing)
  328. {
  329. u32 ref_ctrl_shdw = 0, val = 0, freq_khz, t_refi;
  330. /* Scale down frequency and t_refi to avoid overflow */
  331. freq_khz = freq / 1000;
  332. t_refi = addressing->tREFI_ns / 100;
  333. /*
  334. * refresh rate to be set is 'tREFI(in us) * freq in MHz
  335. * division by 10000 to account for change in units
  336. */
  337. val = t_refi * freq_khz / 10000;
  338. ref_ctrl_shdw |= val << REFRESH_RATE_SHIFT;
  339. return ref_ctrl_shdw;
  340. }
  341. static u32 get_sdram_tim_1_shdw(const struct lpddr2_timings *timings,
  342. const struct lpddr2_min_tck *min_tck,
  343. const struct lpddr2_addressing *addressing)
  344. {
  345. u32 tim1 = 0, val = 0;
  346. val = max(min_tck->tWTR, DIV_ROUND_UP(timings->tWTR, t_ck)) - 1;
  347. tim1 |= val << T_WTR_SHIFT;
  348. if (addressing->num_banks == B8)
  349. val = DIV_ROUND_UP(timings->tFAW, t_ck*4);
  350. else
  351. val = max(min_tck->tRRD, DIV_ROUND_UP(timings->tRRD, t_ck));
  352. tim1 |= (val - 1) << T_RRD_SHIFT;
  353. val = DIV_ROUND_UP(timings->tRAS_min + timings->tRPab, t_ck) - 1;
  354. tim1 |= val << T_RC_SHIFT;
  355. val = max(min_tck->tRASmin, DIV_ROUND_UP(timings->tRAS_min, t_ck));
  356. tim1 |= (val - 1) << T_RAS_SHIFT;
  357. val = max(min_tck->tWR, DIV_ROUND_UP(timings->tWR, t_ck)) - 1;
  358. tim1 |= val << T_WR_SHIFT;
  359. val = max(min_tck->tRCD, DIV_ROUND_UP(timings->tRCD, t_ck)) - 1;
  360. tim1 |= val << T_RCD_SHIFT;
  361. val = max(min_tck->tRPab, DIV_ROUND_UP(timings->tRPab, t_ck)) - 1;
  362. tim1 |= val << T_RP_SHIFT;
  363. return tim1;
  364. }
  365. static u32 get_sdram_tim_1_shdw_derated(const struct lpddr2_timings *timings,
  366. const struct lpddr2_min_tck *min_tck,
  367. const struct lpddr2_addressing *addressing)
  368. {
  369. u32 tim1 = 0, val = 0;
  370. val = max(min_tck->tWTR, DIV_ROUND_UP(timings->tWTR, t_ck)) - 1;
  371. tim1 = val << T_WTR_SHIFT;
  372. /*
  373. * tFAW is approximately 4 times tRRD. So add 1875*4 = 7500ps
  374. * to tFAW for de-rating
  375. */
  376. if (addressing->num_banks == B8) {
  377. val = DIV_ROUND_UP(timings->tFAW + 7500, 4 * t_ck) - 1;
  378. } else {
  379. val = DIV_ROUND_UP(timings->tRRD + 1875, t_ck);
  380. val = max(min_tck->tRRD, val) - 1;
  381. }
  382. tim1 |= val << T_RRD_SHIFT;
  383. val = DIV_ROUND_UP(timings->tRAS_min + timings->tRPab + 1875, t_ck);
  384. tim1 |= (val - 1) << T_RC_SHIFT;
  385. val = DIV_ROUND_UP(timings->tRAS_min + 1875, t_ck);
  386. val = max(min_tck->tRASmin, val) - 1;
  387. tim1 |= val << T_RAS_SHIFT;
  388. val = max(min_tck->tWR, DIV_ROUND_UP(timings->tWR, t_ck)) - 1;
  389. tim1 |= val << T_WR_SHIFT;
  390. val = max(min_tck->tRCD, DIV_ROUND_UP(timings->tRCD + 1875, t_ck));
  391. tim1 |= (val - 1) << T_RCD_SHIFT;
  392. val = max(min_tck->tRPab, DIV_ROUND_UP(timings->tRPab + 1875, t_ck));
  393. tim1 |= (val - 1) << T_RP_SHIFT;
  394. return tim1;
  395. }
  396. static u32 get_sdram_tim_2_shdw(const struct lpddr2_timings *timings,
  397. const struct lpddr2_min_tck *min_tck,
  398. const struct lpddr2_addressing *addressing,
  399. u32 type)
  400. {
  401. u32 tim2 = 0, val = 0;
  402. val = min_tck->tCKE - 1;
  403. tim2 |= val << T_CKE_SHIFT;
  404. val = max(min_tck->tRTP, DIV_ROUND_UP(timings->tRTP, t_ck)) - 1;
  405. tim2 |= val << T_RTP_SHIFT;
  406. /* tXSNR = tRFCab_ps + 10 ns(tRFCab_ps for LPDDR2). */
  407. val = DIV_ROUND_UP(addressing->tRFCab_ps + 10000, t_ck) - 1;
  408. tim2 |= val << T_XSNR_SHIFT;
  409. /* XSRD same as XSNR for LPDDR2 */
  410. tim2 |= val << T_XSRD_SHIFT;
  411. val = max(min_tck->tXP, DIV_ROUND_UP(timings->tXP, t_ck)) - 1;
  412. tim2 |= val << T_XP_SHIFT;
  413. return tim2;
  414. }
  415. static u32 get_sdram_tim_3_shdw(const struct lpddr2_timings *timings,
  416. const struct lpddr2_min_tck *min_tck,
  417. const struct lpddr2_addressing *addressing,
  418. u32 type, u32 ip_rev, u32 derated)
  419. {
  420. u32 tim3 = 0, val = 0, t_dqsck;
  421. val = timings->tRAS_max_ns / addressing->tREFI_ns - 1;
  422. val = val > 0xF ? 0xF : val;
  423. tim3 |= val << T_RAS_MAX_SHIFT;
  424. val = DIV_ROUND_UP(addressing->tRFCab_ps, t_ck) - 1;
  425. tim3 |= val << T_RFC_SHIFT;
  426. t_dqsck = (derated == EMIF_DERATED_TIMINGS) ?
  427. timings->tDQSCK_max_derated : timings->tDQSCK_max;
  428. if (ip_rev == EMIF_4D5)
  429. val = DIV_ROUND_UP(t_dqsck + 1000, t_ck) - 1;
  430. else
  431. val = DIV_ROUND_UP(t_dqsck, t_ck) - 1;
  432. tim3 |= val << T_TDQSCKMAX_SHIFT;
  433. val = DIV_ROUND_UP(timings->tZQCS, t_ck) - 1;
  434. tim3 |= val << ZQ_ZQCS_SHIFT;
  435. val = DIV_ROUND_UP(timings->tCKESR, t_ck);
  436. val = max(min_tck->tCKESR, val) - 1;
  437. tim3 |= val << T_CKESR_SHIFT;
  438. if (ip_rev == EMIF_4D5) {
  439. tim3 |= (EMIF_T_CSTA - 1) << T_CSTA_SHIFT;
  440. val = DIV_ROUND_UP(EMIF_T_PDLL_UL, 128) - 1;
  441. tim3 |= val << T_PDLL_UL_SHIFT;
  442. }
  443. return tim3;
  444. }
  445. static u32 get_zq_config_reg(const struct lpddr2_addressing *addressing,
  446. bool cs1_used, bool cal_resistors_per_cs)
  447. {
  448. u32 zq = 0, val = 0;
  449. val = EMIF_ZQCS_INTERVAL_US * 1000 / addressing->tREFI_ns;
  450. zq |= val << ZQ_REFINTERVAL_SHIFT;
  451. val = DIV_ROUND_UP(T_ZQCL_DEFAULT_NS, T_ZQCS_DEFAULT_NS) - 1;
  452. zq |= val << ZQ_ZQCL_MULT_SHIFT;
  453. val = DIV_ROUND_UP(T_ZQINIT_DEFAULT_NS, T_ZQCL_DEFAULT_NS) - 1;
  454. zq |= val << ZQ_ZQINIT_MULT_SHIFT;
  455. zq |= ZQ_SFEXITEN_ENABLE << ZQ_SFEXITEN_SHIFT;
  456. if (cal_resistors_per_cs)
  457. zq |= ZQ_DUALCALEN_ENABLE << ZQ_DUALCALEN_SHIFT;
  458. else
  459. zq |= ZQ_DUALCALEN_DISABLE << ZQ_DUALCALEN_SHIFT;
  460. zq |= ZQ_CS0EN_MASK; /* CS0 is used for sure */
  461. val = cs1_used ? 1 : 0;
  462. zq |= val << ZQ_CS1EN_SHIFT;
  463. return zq;
  464. }
  465. static u32 get_temp_alert_config(const struct lpddr2_addressing *addressing,
  466. const struct emif_custom_configs *custom_configs, bool cs1_used,
  467. u32 sdram_io_width, u32 emif_bus_width)
  468. {
  469. u32 alert = 0, interval, devcnt;
  470. if (custom_configs && (custom_configs->mask &
  471. EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL))
  472. interval = custom_configs->temp_alert_poll_interval_ms;
  473. else
  474. interval = TEMP_ALERT_POLL_INTERVAL_DEFAULT_MS;
  475. interval *= 1000000; /* Convert to ns */
  476. interval /= addressing->tREFI_ns; /* Convert to refresh cycles */
  477. alert |= (interval << TA_REFINTERVAL_SHIFT);
  478. /*
  479. * sdram_io_width is in 'log2(x) - 1' form. Convert emif_bus_width
  480. * also to this form and subtract to get TA_DEVCNT, which is
  481. * in log2(x) form.
  482. */
  483. emif_bus_width = __fls(emif_bus_width) - 1;
  484. devcnt = emif_bus_width - sdram_io_width;
  485. alert |= devcnt << TA_DEVCNT_SHIFT;
  486. /* DEVWDT is in 'log2(x) - 3' form */
  487. alert |= (sdram_io_width - 2) << TA_DEVWDT_SHIFT;
  488. alert |= 1 << TA_SFEXITEN_SHIFT;
  489. alert |= 1 << TA_CS0EN_SHIFT;
  490. alert |= (cs1_used ? 1 : 0) << TA_CS1EN_SHIFT;
  491. return alert;
  492. }
  493. static u32 get_read_idle_ctrl_shdw(u8 volt_ramp)
  494. {
  495. u32 idle = 0, val = 0;
  496. /*
  497. * Maximum value in normal conditions and increased frequency
  498. * when voltage is ramping
  499. */
  500. if (volt_ramp)
  501. val = READ_IDLE_INTERVAL_DVFS / t_ck / 64 - 1;
  502. else
  503. val = 0x1FF;
  504. /*
  505. * READ_IDLE_CTRL register in EMIF4D has same offset and fields
  506. * as DLL_CALIB_CTRL in EMIF4D5, so use the same shifts
  507. */
  508. idle |= val << DLL_CALIB_INTERVAL_SHIFT;
  509. idle |= EMIF_READ_IDLE_LEN_VAL << ACK_WAIT_SHIFT;
  510. return idle;
  511. }
  512. static u32 get_dll_calib_ctrl_shdw(u8 volt_ramp)
  513. {
  514. u32 calib = 0, val = 0;
  515. if (volt_ramp == DDR_VOLTAGE_RAMPING)
  516. val = DLL_CALIB_INTERVAL_DVFS / t_ck / 16 - 1;
  517. else
  518. val = 0; /* Disabled when voltage is stable */
  519. calib |= val << DLL_CALIB_INTERVAL_SHIFT;
  520. calib |= DLL_CALIB_ACK_WAIT_VAL << ACK_WAIT_SHIFT;
  521. return calib;
  522. }
  523. static u32 get_ddr_phy_ctrl_1_attilaphy_4d(const struct lpddr2_timings *timings,
  524. u32 freq, u8 RL)
  525. {
  526. u32 phy = EMIF_DDR_PHY_CTRL_1_BASE_VAL_ATTILAPHY, val = 0;
  527. val = RL + DIV_ROUND_UP(timings->tDQSCK_max, t_ck) - 1;
  528. phy |= val << READ_LATENCY_SHIFT_4D;
  529. if (freq <= 100000000)
  530. val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS_ATTILAPHY;
  531. else if (freq <= 200000000)
  532. val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ_ATTILAPHY;
  533. else
  534. val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ_ATTILAPHY;
  535. phy |= val << DLL_SLAVE_DLY_CTRL_SHIFT_4D;
  536. return phy;
  537. }
  538. static u32 get_phy_ctrl_1_intelliphy_4d5(u32 freq, u8 cl)
  539. {
  540. u32 phy = EMIF_DDR_PHY_CTRL_1_BASE_VAL_INTELLIPHY, half_delay;
  541. /*
  542. * DLL operates at 266 MHz. If DDR frequency is near 266 MHz,
  543. * half-delay is not needed else set half-delay
  544. */
  545. if (freq >= 265000000 && freq < 267000000)
  546. half_delay = 0;
  547. else
  548. half_delay = 1;
  549. phy |= half_delay << DLL_HALF_DELAY_SHIFT_4D5;
  550. phy |= ((cl + DIV_ROUND_UP(EMIF_PHY_TOTAL_READ_LATENCY_INTELLIPHY_PS,
  551. t_ck) - 1) << READ_LATENCY_SHIFT_4D5);
  552. return phy;
  553. }
  554. static u32 get_ext_phy_ctrl_2_intelliphy_4d5(void)
  555. {
  556. u32 fifo_we_slave_ratio;
  557. fifo_we_slave_ratio = DIV_ROUND_CLOSEST(
  558. EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS * 256, t_ck);
  559. return fifo_we_slave_ratio | fifo_we_slave_ratio << 11 |
  560. fifo_we_slave_ratio << 22;
  561. }
  562. static u32 get_ext_phy_ctrl_3_intelliphy_4d5(void)
  563. {
  564. u32 fifo_we_slave_ratio;
  565. fifo_we_slave_ratio = DIV_ROUND_CLOSEST(
  566. EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS * 256, t_ck);
  567. return fifo_we_slave_ratio >> 10 | fifo_we_slave_ratio << 1 |
  568. fifo_we_slave_ratio << 12 | fifo_we_slave_ratio << 23;
  569. }
  570. static u32 get_ext_phy_ctrl_4_intelliphy_4d5(void)
  571. {
  572. u32 fifo_we_slave_ratio;
  573. fifo_we_slave_ratio = DIV_ROUND_CLOSEST(
  574. EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS * 256, t_ck);
  575. return fifo_we_slave_ratio >> 9 | fifo_we_slave_ratio << 2 |
  576. fifo_we_slave_ratio << 13;
  577. }
  578. static u32 get_pwr_mgmt_ctrl(u32 freq, struct emif_data *emif, u32 ip_rev)
  579. {
  580. u32 pwr_mgmt_ctrl = 0, timeout;
  581. u32 lpmode = EMIF_LP_MODE_SELF_REFRESH;
  582. u32 timeout_perf = EMIF_LP_MODE_TIMEOUT_PERFORMANCE;
  583. u32 timeout_pwr = EMIF_LP_MODE_TIMEOUT_POWER;
  584. u32 freq_threshold = EMIF_LP_MODE_FREQ_THRESHOLD;
  585. u32 mask;
  586. u8 shift;
  587. struct emif_custom_configs *cust_cfgs = emif->plat_data->custom_configs;
  588. if (cust_cfgs && (cust_cfgs->mask & EMIF_CUSTOM_CONFIG_LPMODE)) {
  589. lpmode = cust_cfgs->lpmode;
  590. timeout_perf = cust_cfgs->lpmode_timeout_performance;
  591. timeout_pwr = cust_cfgs->lpmode_timeout_power;
  592. freq_threshold = cust_cfgs->lpmode_freq_threshold;
  593. }
  594. /* Timeout based on DDR frequency */
  595. timeout = freq >= freq_threshold ? timeout_perf : timeout_pwr;
  596. /*
  597. * The value to be set in register is "log2(timeout) - 3"
  598. * if timeout < 16 load 0 in register
  599. * if timeout is not a power of 2, round to next highest power of 2
  600. */
  601. if (timeout < 16) {
  602. timeout = 0;
  603. } else {
  604. if (timeout & (timeout - 1))
  605. timeout <<= 1;
  606. timeout = __fls(timeout) - 3;
  607. }
  608. switch (lpmode) {
  609. case EMIF_LP_MODE_CLOCK_STOP:
  610. shift = CS_TIM_SHIFT;
  611. mask = CS_TIM_MASK;
  612. break;
  613. case EMIF_LP_MODE_SELF_REFRESH:
  614. /* Workaround for errata i735 */
  615. if (timeout < 6)
  616. timeout = 6;
  617. shift = SR_TIM_SHIFT;
  618. mask = SR_TIM_MASK;
  619. break;
  620. case EMIF_LP_MODE_PWR_DN:
  621. shift = PD_TIM_SHIFT;
  622. mask = PD_TIM_MASK;
  623. break;
  624. case EMIF_LP_MODE_DISABLE:
  625. default:
  626. mask = 0;
  627. shift = 0;
  628. break;
  629. }
  630. /* Round to maximum in case of overflow, BUT warn! */
  631. if (lpmode != EMIF_LP_MODE_DISABLE && timeout > mask >> shift) {
  632. pr_err("TIMEOUT Overflow - lpmode=%d perf=%d pwr=%d freq=%d\n",
  633. lpmode,
  634. timeout_perf,
  635. timeout_pwr,
  636. freq_threshold);
  637. WARN(1, "timeout=0x%02x greater than 0x%02x. Using max\n",
  638. timeout, mask >> shift);
  639. timeout = mask >> shift;
  640. }
  641. /* Setup required timing */
  642. pwr_mgmt_ctrl = (timeout << shift) & mask;
  643. /* setup a default mask for rest of the modes */
  644. pwr_mgmt_ctrl |= (SR_TIM_MASK | CS_TIM_MASK | PD_TIM_MASK) &
  645. ~mask;
  646. /* No CS_TIM in EMIF_4D5 */
  647. if (ip_rev == EMIF_4D5)
  648. pwr_mgmt_ctrl &= ~CS_TIM_MASK;
  649. pwr_mgmt_ctrl |= lpmode << LP_MODE_SHIFT;
  650. return pwr_mgmt_ctrl;
  651. }
  652. /*
  653. * Get the temperature level of the EMIF instance:
  654. * Reads the MR4 register of attached SDRAM parts to find out the temperature
  655. * level. If there are two parts attached(one on each CS), then the temperature
  656. * level for the EMIF instance is the higher of the two temperatures.
  657. */
  658. static void get_temperature_level(struct emif_data *emif)
  659. {
  660. u32 temp, temperature_level;
  661. void __iomem *base;
  662. base = emif->base;
  663. /* Read mode register 4 */
  664. writel(DDR_MR4, base + EMIF_LPDDR2_MODE_REG_CONFIG);
  665. temperature_level = readl(base + EMIF_LPDDR2_MODE_REG_DATA);
  666. temperature_level = (temperature_level & MR4_SDRAM_REF_RATE_MASK) >>
  667. MR4_SDRAM_REF_RATE_SHIFT;
  668. if (emif->plat_data->device_info->cs1_used) {
  669. writel(DDR_MR4 | CS_MASK, base + EMIF_LPDDR2_MODE_REG_CONFIG);
  670. temp = readl(base + EMIF_LPDDR2_MODE_REG_DATA);
  671. temp = (temp & MR4_SDRAM_REF_RATE_MASK)
  672. >> MR4_SDRAM_REF_RATE_SHIFT;
  673. temperature_level = max(temp, temperature_level);
  674. }
  675. /* treat everything less than nominal(3) in MR4 as nominal */
  676. if (unlikely(temperature_level < SDRAM_TEMP_NOMINAL))
  677. temperature_level = SDRAM_TEMP_NOMINAL;
  678. /* if we get reserved value in MR4 persist with the existing value */
  679. if (likely(temperature_level != SDRAM_TEMP_RESERVED_4))
  680. emif->temperature_level = temperature_level;
  681. }
  682. /*
  683. * Program EMIF shadow registers that are not dependent on temperature
  684. * or voltage
  685. */
  686. static void setup_registers(struct emif_data *emif, struct emif_regs *regs)
  687. {
  688. void __iomem *base = emif->base;
  689. writel(regs->sdram_tim2_shdw, base + EMIF_SDRAM_TIMING_2_SHDW);
  690. writel(regs->phy_ctrl_1_shdw, base + EMIF_DDR_PHY_CTRL_1_SHDW);
  691. writel(regs->pwr_mgmt_ctrl_shdw,
  692. base + EMIF_POWER_MANAGEMENT_CTRL_SHDW);
  693. /* Settings specific for EMIF4D5 */
  694. if (emif->plat_data->ip_rev != EMIF_4D5)
  695. return;
  696. writel(regs->ext_phy_ctrl_2_shdw, base + EMIF_EXT_PHY_CTRL_2_SHDW);
  697. writel(regs->ext_phy_ctrl_3_shdw, base + EMIF_EXT_PHY_CTRL_3_SHDW);
  698. writel(regs->ext_phy_ctrl_4_shdw, base + EMIF_EXT_PHY_CTRL_4_SHDW);
  699. }
  700. /*
  701. * When voltage ramps dll calibration and forced read idle should
  702. * happen more often
  703. */
  704. static void setup_volt_sensitive_regs(struct emif_data *emif,
  705. struct emif_regs *regs, u32 volt_state)
  706. {
  707. u32 calib_ctrl;
  708. void __iomem *base = emif->base;
  709. /*
  710. * EMIF_READ_IDLE_CTRL in EMIF4D refers to the same register as
  711. * EMIF_DLL_CALIB_CTRL in EMIF4D5 and dll_calib_ctrl_shadow_*
  712. * is an alias of the respective read_idle_ctrl_shdw_* (members of
  713. * a union). So, the below code takes care of both cases
  714. */
  715. if (volt_state == DDR_VOLTAGE_RAMPING)
  716. calib_ctrl = regs->dll_calib_ctrl_shdw_volt_ramp;
  717. else
  718. calib_ctrl = regs->dll_calib_ctrl_shdw_normal;
  719. writel(calib_ctrl, base + EMIF_DLL_CALIB_CTRL_SHDW);
  720. }
  721. /*
  722. * setup_temperature_sensitive_regs() - set the timings for temperature
  723. * sensitive registers. This happens once at initialisation time based
  724. * on the temperature at boot time and subsequently based on the temperature
  725. * alert interrupt. Temperature alert can happen when the temperature
  726. * increases or drops. So this function can have the effect of either
  727. * derating the timings or going back to nominal values.
  728. */
  729. static void setup_temperature_sensitive_regs(struct emif_data *emif,
  730. struct emif_regs *regs)
  731. {
  732. u32 tim1, tim3, ref_ctrl, type;
  733. void __iomem *base = emif->base;
  734. u32 temperature;
  735. type = emif->plat_data->device_info->type;
  736. tim1 = regs->sdram_tim1_shdw;
  737. tim3 = regs->sdram_tim3_shdw;
  738. ref_ctrl = regs->ref_ctrl_shdw;
  739. /* No de-rating for non-lpddr2 devices */
  740. if (type != DDR_TYPE_LPDDR2_S2 && type != DDR_TYPE_LPDDR2_S4)
  741. goto out;
  742. temperature = emif->temperature_level;
  743. if (temperature == SDRAM_TEMP_HIGH_DERATE_REFRESH) {
  744. ref_ctrl = regs->ref_ctrl_shdw_derated;
  745. } else if (temperature == SDRAM_TEMP_HIGH_DERATE_REFRESH_AND_TIMINGS) {
  746. tim1 = regs->sdram_tim1_shdw_derated;
  747. tim3 = regs->sdram_tim3_shdw_derated;
  748. ref_ctrl = regs->ref_ctrl_shdw_derated;
  749. }
  750. out:
  751. writel(tim1, base + EMIF_SDRAM_TIMING_1_SHDW);
  752. writel(tim3, base + EMIF_SDRAM_TIMING_3_SHDW);
  753. writel(ref_ctrl, base + EMIF_SDRAM_REFRESH_CTRL_SHDW);
  754. }
  755. static irqreturn_t handle_temp_alert(void __iomem *base, struct emif_data *emif)
  756. {
  757. u32 old_temp_level;
  758. irqreturn_t ret = IRQ_HANDLED;
  759. struct emif_custom_configs *custom_configs;
  760. spin_lock_irqsave(&emif_lock, irq_state);
  761. old_temp_level = emif->temperature_level;
  762. get_temperature_level(emif);
  763. if (unlikely(emif->temperature_level == old_temp_level)) {
  764. goto out;
  765. } else if (!emif->curr_regs) {
  766. dev_err(emif->dev, "temperature alert before registers are calculated, not de-rating timings\n");
  767. goto out;
  768. }
  769. custom_configs = emif->plat_data->custom_configs;
  770. /*
  771. * IF we detect higher than "nominal rating" from DDR sensor
  772. * on an unsupported DDR part, shutdown system
  773. */
  774. if (custom_configs && !(custom_configs->mask &
  775. EMIF_CUSTOM_CONFIG_EXTENDED_TEMP_PART)) {
  776. if (emif->temperature_level >= SDRAM_TEMP_HIGH_DERATE_REFRESH) {
  777. dev_err(emif->dev,
  778. "%s:NOT Extended temperature capable memory. Converting MR4=0x%02x as shutdown event\n",
  779. __func__, emif->temperature_level);
  780. /*
  781. * Temperature far too high - do kernel_power_off()
  782. * from thread context
  783. */
  784. emif->temperature_level = SDRAM_TEMP_VERY_HIGH_SHUTDOWN;
  785. ret = IRQ_WAKE_THREAD;
  786. goto out;
  787. }
  788. }
  789. if (emif->temperature_level < old_temp_level ||
  790. emif->temperature_level == SDRAM_TEMP_VERY_HIGH_SHUTDOWN) {
  791. /*
  792. * Temperature coming down - defer handling to thread OR
  793. * Temperature far too high - do kernel_power_off() from
  794. * thread context
  795. */
  796. ret = IRQ_WAKE_THREAD;
  797. } else {
  798. /* Temperature is going up - handle immediately */
  799. setup_temperature_sensitive_regs(emif, emif->curr_regs);
  800. do_freq_update();
  801. }
  802. out:
  803. spin_unlock_irqrestore(&emif_lock, irq_state);
  804. return ret;
  805. }
  806. static irqreturn_t emif_interrupt_handler(int irq, void *dev_id)
  807. {
  808. u32 interrupts;
  809. struct emif_data *emif = dev_id;
  810. void __iomem *base = emif->base;
  811. struct device *dev = emif->dev;
  812. irqreturn_t ret = IRQ_HANDLED;
  813. /* Save the status and clear it */
  814. interrupts = readl(base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS);
  815. writel(interrupts, base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS);
  816. /*
  817. * Handle temperature alert
  818. * Temperature alert should be same for all ports
  819. * So, it's enough to process it only for one of the ports
  820. */
  821. if (interrupts & TA_SYS_MASK)
  822. ret = handle_temp_alert(base, emif);
  823. if (interrupts & ERR_SYS_MASK)
  824. dev_err(dev, "Access error from SYS port - %x\n", interrupts);
  825. if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE) {
  826. /* Save the status and clear it */
  827. interrupts = readl(base + EMIF_LL_OCP_INTERRUPT_STATUS);
  828. writel(interrupts, base + EMIF_LL_OCP_INTERRUPT_STATUS);
  829. if (interrupts & ERR_LL_MASK)
  830. dev_err(dev, "Access error from LL port - %x\n",
  831. interrupts);
  832. }
  833. return ret;
  834. }
  835. static irqreturn_t emif_threaded_isr(int irq, void *dev_id)
  836. {
  837. struct emif_data *emif = dev_id;
  838. if (emif->temperature_level == SDRAM_TEMP_VERY_HIGH_SHUTDOWN) {
  839. dev_emerg(emif->dev, "SDRAM temperature exceeds operating limit.. Needs shut down!!!\n");
  840. /* If we have Power OFF ability, use it, else try restarting */
  841. if (pm_power_off) {
  842. kernel_power_off();
  843. } else {
  844. WARN(1, "FIXME: NO pm_power_off!!! trying restart\n");
  845. kernel_restart("SDRAM Over-temp Emergency restart");
  846. }
  847. return IRQ_HANDLED;
  848. }
  849. spin_lock_irqsave(&emif_lock, irq_state);
  850. if (emif->curr_regs) {
  851. setup_temperature_sensitive_regs(emif, emif->curr_regs);
  852. do_freq_update();
  853. } else {
  854. dev_err(emif->dev, "temperature alert before registers are calculated, not de-rating timings\n");
  855. }
  856. spin_unlock_irqrestore(&emif_lock, irq_state);
  857. return IRQ_HANDLED;
  858. }
  859. static void clear_all_interrupts(struct emif_data *emif)
  860. {
  861. void __iomem *base = emif->base;
  862. writel(readl(base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS),
  863. base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS);
  864. if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE)
  865. writel(readl(base + EMIF_LL_OCP_INTERRUPT_STATUS),
  866. base + EMIF_LL_OCP_INTERRUPT_STATUS);
  867. }
  868. static void disable_and_clear_all_interrupts(struct emif_data *emif)
  869. {
  870. void __iomem *base = emif->base;
  871. /* Disable all interrupts */
  872. writel(readl(base + EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET),
  873. base + EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_CLEAR);
  874. if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE)
  875. writel(readl(base + EMIF_LL_OCP_INTERRUPT_ENABLE_SET),
  876. base + EMIF_LL_OCP_INTERRUPT_ENABLE_CLEAR);
  877. /* Clear all interrupts */
  878. clear_all_interrupts(emif);
  879. }
  880. static int __init_or_module setup_interrupts(struct emif_data *emif, u32 irq)
  881. {
  882. u32 interrupts, type;
  883. void __iomem *base = emif->base;
  884. type = emif->plat_data->device_info->type;
  885. clear_all_interrupts(emif);
  886. /* Enable interrupts for SYS interface */
  887. interrupts = EN_ERR_SYS_MASK;
  888. if (type == DDR_TYPE_LPDDR2_S2 || type == DDR_TYPE_LPDDR2_S4)
  889. interrupts |= EN_TA_SYS_MASK;
  890. writel(interrupts, base + EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET);
  891. /* Enable interrupts for LL interface */
  892. if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE) {
  893. /* TA need not be enabled for LL */
  894. interrupts = EN_ERR_LL_MASK;
  895. writel(interrupts, base + EMIF_LL_OCP_INTERRUPT_ENABLE_SET);
  896. }
  897. /* setup IRQ handlers */
  898. return devm_request_threaded_irq(emif->dev, irq,
  899. emif_interrupt_handler,
  900. emif_threaded_isr,
  901. 0, dev_name(emif->dev),
  902. emif);
  903. }
  904. static void __init_or_module emif_onetime_settings(struct emif_data *emif)
  905. {
  906. u32 pwr_mgmt_ctrl, zq, temp_alert_cfg;
  907. void __iomem *base = emif->base;
  908. const struct lpddr2_addressing *addressing;
  909. const struct ddr_device_info *device_info;
  910. device_info = emif->plat_data->device_info;
  911. addressing = get_addressing_table(device_info);
  912. /*
  913. * Init power management settings
  914. * We don't know the frequency yet. Use a high frequency
  915. * value for a conservative timeout setting
  916. */
  917. pwr_mgmt_ctrl = get_pwr_mgmt_ctrl(1000000000, emif,
  918. emif->plat_data->ip_rev);
  919. emif->lpmode = (pwr_mgmt_ctrl & LP_MODE_MASK) >> LP_MODE_SHIFT;
  920. writel(pwr_mgmt_ctrl, base + EMIF_POWER_MANAGEMENT_CONTROL);
  921. /* Init ZQ calibration settings */
  922. zq = get_zq_config_reg(addressing, device_info->cs1_used,
  923. device_info->cal_resistors_per_cs);
  924. writel(zq, base + EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG);
  925. /* Check temperature level temperature level*/
  926. get_temperature_level(emif);
  927. if (emif->temperature_level == SDRAM_TEMP_VERY_HIGH_SHUTDOWN)
  928. dev_emerg(emif->dev, "SDRAM temperature exceeds operating limit.. Needs shut down!!!\n");
  929. /* Init temperature polling */
  930. temp_alert_cfg = get_temp_alert_config(addressing,
  931. emif->plat_data->custom_configs, device_info->cs1_used,
  932. device_info->io_width, get_emif_bus_width(emif));
  933. writel(temp_alert_cfg, base + EMIF_TEMPERATURE_ALERT_CONFIG);
  934. /*
  935. * Program external PHY control registers that are not frequency
  936. * dependent
  937. */
  938. if (emif->plat_data->phy_type != EMIF_PHY_TYPE_INTELLIPHY)
  939. return;
  940. writel(EMIF_EXT_PHY_CTRL_1_VAL, base + EMIF_EXT_PHY_CTRL_1_SHDW);
  941. writel(EMIF_EXT_PHY_CTRL_5_VAL, base + EMIF_EXT_PHY_CTRL_5_SHDW);
  942. writel(EMIF_EXT_PHY_CTRL_6_VAL, base + EMIF_EXT_PHY_CTRL_6_SHDW);
  943. writel(EMIF_EXT_PHY_CTRL_7_VAL, base + EMIF_EXT_PHY_CTRL_7_SHDW);
  944. writel(EMIF_EXT_PHY_CTRL_8_VAL, base + EMIF_EXT_PHY_CTRL_8_SHDW);
  945. writel(EMIF_EXT_PHY_CTRL_9_VAL, base + EMIF_EXT_PHY_CTRL_9_SHDW);
  946. writel(EMIF_EXT_PHY_CTRL_10_VAL, base + EMIF_EXT_PHY_CTRL_10_SHDW);
  947. writel(EMIF_EXT_PHY_CTRL_11_VAL, base + EMIF_EXT_PHY_CTRL_11_SHDW);
  948. writel(EMIF_EXT_PHY_CTRL_12_VAL, base + EMIF_EXT_PHY_CTRL_12_SHDW);
  949. writel(EMIF_EXT_PHY_CTRL_13_VAL, base + EMIF_EXT_PHY_CTRL_13_SHDW);
  950. writel(EMIF_EXT_PHY_CTRL_14_VAL, base + EMIF_EXT_PHY_CTRL_14_SHDW);
  951. writel(EMIF_EXT_PHY_CTRL_15_VAL, base + EMIF_EXT_PHY_CTRL_15_SHDW);
  952. writel(EMIF_EXT_PHY_CTRL_16_VAL, base + EMIF_EXT_PHY_CTRL_16_SHDW);
  953. writel(EMIF_EXT_PHY_CTRL_17_VAL, base + EMIF_EXT_PHY_CTRL_17_SHDW);
  954. writel(EMIF_EXT_PHY_CTRL_18_VAL, base + EMIF_EXT_PHY_CTRL_18_SHDW);
  955. writel(EMIF_EXT_PHY_CTRL_19_VAL, base + EMIF_EXT_PHY_CTRL_19_SHDW);
  956. writel(EMIF_EXT_PHY_CTRL_20_VAL, base + EMIF_EXT_PHY_CTRL_20_SHDW);
  957. writel(EMIF_EXT_PHY_CTRL_21_VAL, base + EMIF_EXT_PHY_CTRL_21_SHDW);
  958. writel(EMIF_EXT_PHY_CTRL_22_VAL, base + EMIF_EXT_PHY_CTRL_22_SHDW);
  959. writel(EMIF_EXT_PHY_CTRL_23_VAL, base + EMIF_EXT_PHY_CTRL_23_SHDW);
  960. writel(EMIF_EXT_PHY_CTRL_24_VAL, base + EMIF_EXT_PHY_CTRL_24_SHDW);
  961. }
  962. static void get_default_timings(struct emif_data *emif)
  963. {
  964. struct emif_platform_data *pd = emif->plat_data;
  965. pd->timings = lpddr2_jedec_timings;
  966. pd->timings_arr_size = ARRAY_SIZE(lpddr2_jedec_timings);
  967. dev_warn(emif->dev, "%s: using default timings\n", __func__);
  968. }
  969. static int is_dev_data_valid(u32 type, u32 density, u32 io_width, u32 phy_type,
  970. u32 ip_rev, struct device *dev)
  971. {
  972. int valid;
  973. valid = (type == DDR_TYPE_LPDDR2_S4 ||
  974. type == DDR_TYPE_LPDDR2_S2)
  975. && (density >= DDR_DENSITY_64Mb
  976. && density <= DDR_DENSITY_8Gb)
  977. && (io_width >= DDR_IO_WIDTH_8
  978. && io_width <= DDR_IO_WIDTH_32);
  979. /* Combinations of EMIF and PHY revisions that we support today */
  980. switch (ip_rev) {
  981. case EMIF_4D:
  982. valid = valid && (phy_type == EMIF_PHY_TYPE_ATTILAPHY);
  983. break;
  984. case EMIF_4D5:
  985. valid = valid && (phy_type == EMIF_PHY_TYPE_INTELLIPHY);
  986. break;
  987. default:
  988. valid = 0;
  989. }
  990. if (!valid)
  991. dev_err(dev, "%s: invalid DDR details\n", __func__);
  992. return valid;
  993. }
  994. static int is_custom_config_valid(struct emif_custom_configs *cust_cfgs,
  995. struct device *dev)
  996. {
  997. int valid = 1;
  998. if ((cust_cfgs->mask & EMIF_CUSTOM_CONFIG_LPMODE) &&
  999. (cust_cfgs->lpmode != EMIF_LP_MODE_DISABLE))
  1000. valid = cust_cfgs->lpmode_freq_threshold &&
  1001. cust_cfgs->lpmode_timeout_performance &&
  1002. cust_cfgs->lpmode_timeout_power;
  1003. if (cust_cfgs->mask & EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL)
  1004. valid = valid && cust_cfgs->temp_alert_poll_interval_ms;
  1005. if (!valid)
  1006. dev_warn(dev, "%s: invalid custom configs\n", __func__);
  1007. return valid;
  1008. }
  1009. #if defined(CONFIG_OF)
  1010. static void __init_or_module of_get_custom_configs(struct device_node *np_emif,
  1011. struct emif_data *emif)
  1012. {
  1013. struct emif_custom_configs *cust_cfgs = NULL;
  1014. int len;
  1015. const __be32 *lpmode, *poll_intvl;
  1016. lpmode = of_get_property(np_emif, "low-power-mode", &len);
  1017. poll_intvl = of_get_property(np_emif, "temp-alert-poll-interval", &len);
  1018. if (lpmode || poll_intvl)
  1019. cust_cfgs = devm_kzalloc(emif->dev, sizeof(*cust_cfgs),
  1020. GFP_KERNEL);
  1021. if (!cust_cfgs)
  1022. return;
  1023. if (lpmode) {
  1024. cust_cfgs->mask |= EMIF_CUSTOM_CONFIG_LPMODE;
  1025. cust_cfgs->lpmode = be32_to_cpup(lpmode);
  1026. of_property_read_u32(np_emif,
  1027. "low-power-mode-timeout-performance",
  1028. &cust_cfgs->lpmode_timeout_performance);
  1029. of_property_read_u32(np_emif,
  1030. "low-power-mode-timeout-power",
  1031. &cust_cfgs->lpmode_timeout_power);
  1032. of_property_read_u32(np_emif,
  1033. "low-power-mode-freq-threshold",
  1034. &cust_cfgs->lpmode_freq_threshold);
  1035. }
  1036. if (poll_intvl) {
  1037. cust_cfgs->mask |=
  1038. EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL;
  1039. cust_cfgs->temp_alert_poll_interval_ms =
  1040. be32_to_cpup(poll_intvl);
  1041. }
  1042. if (of_find_property(np_emif, "extended-temp-part", &len))
  1043. cust_cfgs->mask |= EMIF_CUSTOM_CONFIG_EXTENDED_TEMP_PART;
  1044. if (!is_custom_config_valid(cust_cfgs, emif->dev)) {
  1045. devm_kfree(emif->dev, cust_cfgs);
  1046. return;
  1047. }
  1048. emif->plat_data->custom_configs = cust_cfgs;
  1049. }
  1050. static void __init_or_module of_get_ddr_info(struct device_node *np_emif,
  1051. struct device_node *np_ddr,
  1052. struct ddr_device_info *dev_info)
  1053. {
  1054. u32 density = 0, io_width = 0;
  1055. int len;
  1056. if (of_find_property(np_emif, "cs1-used", &len))
  1057. dev_info->cs1_used = true;
  1058. if (of_find_property(np_emif, "cal-resistor-per-cs", &len))
  1059. dev_info->cal_resistors_per_cs = true;
  1060. if (of_device_is_compatible(np_ddr, "jedec,lpddr2-s4"))
  1061. dev_info->type = DDR_TYPE_LPDDR2_S4;
  1062. else if (of_device_is_compatible(np_ddr, "jedec,lpddr2-s2"))
  1063. dev_info->type = DDR_TYPE_LPDDR2_S2;
  1064. of_property_read_u32(np_ddr, "density", &density);
  1065. of_property_read_u32(np_ddr, "io-width", &io_width);
  1066. /* Convert from density in Mb to the density encoding in jedc_ddr.h */
  1067. if (density & (density - 1))
  1068. dev_info->density = 0;
  1069. else
  1070. dev_info->density = __fls(density) - 5;
  1071. /* Convert from io_width in bits to io_width encoding in jedc_ddr.h */
  1072. if (io_width & (io_width - 1))
  1073. dev_info->io_width = 0;
  1074. else
  1075. dev_info->io_width = __fls(io_width) - 1;
  1076. }
  1077. static struct emif_data * __init_or_module of_get_memory_device_details(
  1078. struct device_node *np_emif, struct device *dev)
  1079. {
  1080. struct emif_data *emif = NULL;
  1081. struct ddr_device_info *dev_info = NULL;
  1082. struct emif_platform_data *pd = NULL;
  1083. struct device_node *np_ddr;
  1084. int len;
  1085. np_ddr = of_parse_phandle(np_emif, "device-handle", 0);
  1086. if (!np_ddr)
  1087. goto error;
  1088. emif = devm_kzalloc(dev, sizeof(struct emif_data), GFP_KERNEL);
  1089. pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
  1090. dev_info = devm_kzalloc(dev, sizeof(*dev_info), GFP_KERNEL);
  1091. if (!emif || !pd || !dev_info) {
  1092. dev_err(dev, "%s: Out of memory!!\n",
  1093. __func__);
  1094. goto error;
  1095. }
  1096. emif->plat_data = pd;
  1097. pd->device_info = dev_info;
  1098. emif->dev = dev;
  1099. emif->np_ddr = np_ddr;
  1100. emif->temperature_level = SDRAM_TEMP_NOMINAL;
  1101. if (of_device_is_compatible(np_emif, "ti,emif-4d"))
  1102. emif->plat_data->ip_rev = EMIF_4D;
  1103. else if (of_device_is_compatible(np_emif, "ti,emif-4d5"))
  1104. emif->plat_data->ip_rev = EMIF_4D5;
  1105. of_property_read_u32(np_emif, "phy-type", &pd->phy_type);
  1106. if (of_find_property(np_emif, "hw-caps-ll-interface", &len))
  1107. pd->hw_caps |= EMIF_HW_CAPS_LL_INTERFACE;
  1108. of_get_ddr_info(np_emif, np_ddr, dev_info);
  1109. if (!is_dev_data_valid(pd->device_info->type, pd->device_info->density,
  1110. pd->device_info->io_width, pd->phy_type, pd->ip_rev,
  1111. emif->dev)) {
  1112. dev_err(dev, "%s: invalid device data!!\n", __func__);
  1113. goto error;
  1114. }
  1115. /*
  1116. * For EMIF instances other than EMIF1 see if the devices connected
  1117. * are exactly same as on EMIF1(which is typically the case). If so,
  1118. * mark it as a duplicate of EMIF1. This will save some memory and
  1119. * computation.
  1120. */
  1121. if (emif1 && emif1->np_ddr == np_ddr) {
  1122. emif->duplicate = true;
  1123. goto out;
  1124. } else if (emif1) {
  1125. dev_warn(emif->dev, "%s: Non-symmetric DDR geometry\n",
  1126. __func__);
  1127. }
  1128. of_get_custom_configs(np_emif, emif);
  1129. emif->plat_data->timings = of_get_ddr_timings(np_ddr, emif->dev,
  1130. emif->plat_data->device_info->type,
  1131. &emif->plat_data->timings_arr_size);
  1132. emif->plat_data->min_tck = of_get_min_tck(np_ddr, emif->dev);
  1133. goto out;
  1134. error:
  1135. return NULL;
  1136. out:
  1137. return emif;
  1138. }
  1139. #else
  1140. static struct emif_data * __init_or_module of_get_memory_device_details(
  1141. struct device_node *np_emif, struct device *dev)
  1142. {
  1143. return NULL;
  1144. }
  1145. #endif
  1146. static struct emif_data *__init_or_module get_device_details(
  1147. struct platform_device *pdev)
  1148. {
  1149. u32 size;
  1150. struct emif_data *emif = NULL;
  1151. struct ddr_device_info *dev_info;
  1152. struct emif_custom_configs *cust_cfgs;
  1153. struct emif_platform_data *pd;
  1154. struct device *dev;
  1155. void *temp;
  1156. pd = pdev->dev.platform_data;
  1157. dev = &pdev->dev;
  1158. if (!(pd && pd->device_info && is_dev_data_valid(pd->device_info->type,
  1159. pd->device_info->density, pd->device_info->io_width,
  1160. pd->phy_type, pd->ip_rev, dev))) {
  1161. dev_err(dev, "%s: invalid device data\n", __func__);
  1162. goto error;
  1163. }
  1164. emif = devm_kzalloc(dev, sizeof(*emif), GFP_KERNEL);
  1165. temp = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
  1166. dev_info = devm_kzalloc(dev, sizeof(*dev_info), GFP_KERNEL);
  1167. if (!emif || !temp || !dev_info) {
  1168. dev_err(dev, "%s:%d: allocation error\n", __func__, __LINE__);
  1169. goto error;
  1170. }
  1171. memcpy(temp, pd, sizeof(*pd));
  1172. pd = temp;
  1173. memcpy(dev_info, pd->device_info, sizeof(*dev_info));
  1174. pd->device_info = dev_info;
  1175. emif->plat_data = pd;
  1176. emif->dev = dev;
  1177. emif->temperature_level = SDRAM_TEMP_NOMINAL;
  1178. /*
  1179. * For EMIF instances other than EMIF1 see if the devices connected
  1180. * are exactly same as on EMIF1(which is typically the case). If so,
  1181. * mark it as a duplicate of EMIF1 and skip copying timings data.
  1182. * This will save some memory and some computation later.
  1183. */
  1184. emif->duplicate = emif1 && (memcmp(dev_info,
  1185. emif1->plat_data->device_info,
  1186. sizeof(struct ddr_device_info)) == 0);
  1187. if (emif->duplicate) {
  1188. pd->timings = NULL;
  1189. pd->min_tck = NULL;
  1190. goto out;
  1191. } else if (emif1) {
  1192. dev_warn(emif->dev, "%s: Non-symmetric DDR geometry\n",
  1193. __func__);
  1194. }
  1195. /*
  1196. * Copy custom configs - ignore allocation error, if any, as
  1197. * custom_configs is not very critical
  1198. */
  1199. cust_cfgs = pd->custom_configs;
  1200. if (cust_cfgs && is_custom_config_valid(cust_cfgs, dev)) {
  1201. temp = devm_kzalloc(dev, sizeof(*cust_cfgs), GFP_KERNEL);
  1202. if (temp)
  1203. memcpy(temp, cust_cfgs, sizeof(*cust_cfgs));
  1204. else
  1205. dev_warn(dev, "%s:%d: allocation error\n", __func__,
  1206. __LINE__);
  1207. pd->custom_configs = temp;
  1208. }
  1209. /*
  1210. * Copy timings and min-tck values from platform data. If it is not
  1211. * available or if memory allocation fails, use JEDEC defaults
  1212. */
  1213. size = sizeof(struct lpddr2_timings) * pd->timings_arr_size;
  1214. if (pd->timings) {
  1215. temp = devm_kzalloc(dev, size, GFP_KERNEL);
  1216. if (temp) {
  1217. memcpy(temp, pd->timings, size);
  1218. pd->timings = temp;
  1219. } else {
  1220. dev_warn(dev, "%s:%d: allocation error\n", __func__,
  1221. __LINE__);
  1222. get_default_timings(emif);
  1223. }
  1224. } else {
  1225. get_default_timings(emif);
  1226. }
  1227. if (pd->min_tck) {
  1228. temp = devm_kzalloc(dev, sizeof(*pd->min_tck), GFP_KERNEL);
  1229. if (temp) {
  1230. memcpy(temp, pd->min_tck, sizeof(*pd->min_tck));
  1231. pd->min_tck = temp;
  1232. } else {
  1233. dev_warn(dev, "%s:%d: allocation error\n", __func__,
  1234. __LINE__);
  1235. pd->min_tck = &lpddr2_jedec_min_tck;
  1236. }
  1237. } else {
  1238. pd->min_tck = &lpddr2_jedec_min_tck;
  1239. }
  1240. out:
  1241. return emif;
  1242. error:
  1243. return NULL;
  1244. }
  1245. static int __init_or_module emif_probe(struct platform_device *pdev)
  1246. {
  1247. struct emif_data *emif;
  1248. struct resource *res;
  1249. int irq, ret;
  1250. if (pdev->dev.of_node)
  1251. emif = of_get_memory_device_details(pdev->dev.of_node, &pdev->dev);
  1252. else
  1253. emif = get_device_details(pdev);
  1254. if (!emif) {
  1255. pr_err("%s: error getting device data\n", __func__);
  1256. goto error;
  1257. }
  1258. list_add(&emif->node, &device_list);
  1259. emif->addressing = get_addressing_table(emif->plat_data->device_info);
  1260. /* Save pointers to each other in emif and device structures */
  1261. emif->dev = &pdev->dev;
  1262. platform_set_drvdata(pdev, emif);
  1263. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1264. emif->base = devm_ioremap_resource(emif->dev, res);
  1265. if (IS_ERR(emif->base))
  1266. goto error;
  1267. irq = platform_get_irq(pdev, 0);
  1268. if (irq < 0)
  1269. goto error;
  1270. emif_onetime_settings(emif);
  1271. emif_debugfs_init(emif);
  1272. disable_and_clear_all_interrupts(emif);
  1273. ret = setup_interrupts(emif, irq);
  1274. if (ret)
  1275. goto error;
  1276. /* One-time actions taken on probing the first device */
  1277. if (!emif1) {
  1278. emif1 = emif;
  1279. spin_lock_init(&emif_lock);
  1280. /*
  1281. * TODO: register notifiers for frequency and voltage
  1282. * change here once the respective frameworks are
  1283. * available
  1284. */
  1285. }
  1286. dev_info(&pdev->dev, "%s: device configured with addr = %p and IRQ%d\n",
  1287. __func__, emif->base, irq);
  1288. return 0;
  1289. error:
  1290. return -ENODEV;
  1291. }
  1292. static int __exit emif_remove(struct platform_device *pdev)
  1293. {
  1294. struct emif_data *emif = platform_get_drvdata(pdev);
  1295. emif_debugfs_exit(emif);
  1296. return 0;
  1297. }
  1298. static void emif_shutdown(struct platform_device *pdev)
  1299. {
  1300. struct emif_data *emif = platform_get_drvdata(pdev);
  1301. disable_and_clear_all_interrupts(emif);
  1302. }
  1303. static int get_emif_reg_values(struct emif_data *emif, u32 freq,
  1304. struct emif_regs *regs)
  1305. {
  1306. u32 ip_rev, phy_type;
  1307. u32 cl, type;
  1308. const struct lpddr2_timings *timings;
  1309. const struct lpddr2_min_tck *min_tck;
  1310. const struct ddr_device_info *device_info;
  1311. const struct lpddr2_addressing *addressing;
  1312. struct emif_data *emif_for_calc;
  1313. struct device *dev;
  1314. dev = emif->dev;
  1315. /*
  1316. * If the devices on this EMIF instance is duplicate of EMIF1,
  1317. * use EMIF1 details for the calculation
  1318. */
  1319. emif_for_calc = emif->duplicate ? emif1 : emif;
  1320. timings = get_timings_table(emif_for_calc, freq);
  1321. addressing = emif_for_calc->addressing;
  1322. if (!timings || !addressing) {
  1323. dev_err(dev, "%s: not enough data available for %dHz",
  1324. __func__, freq);
  1325. return -1;
  1326. }
  1327. device_info = emif_for_calc->plat_data->device_info;
  1328. type = device_info->type;
  1329. ip_rev = emif_for_calc->plat_data->ip_rev;
  1330. phy_type = emif_for_calc->plat_data->phy_type;
  1331. min_tck = emif_for_calc->plat_data->min_tck;
  1332. set_ddr_clk_period(freq);
  1333. regs->ref_ctrl_shdw = get_sdram_ref_ctrl_shdw(freq, addressing);
  1334. regs->sdram_tim1_shdw = get_sdram_tim_1_shdw(timings, min_tck,
  1335. addressing);
  1336. regs->sdram_tim2_shdw = get_sdram_tim_2_shdw(timings, min_tck,
  1337. addressing, type);
  1338. regs->sdram_tim3_shdw = get_sdram_tim_3_shdw(timings, min_tck,
  1339. addressing, type, ip_rev, EMIF_NORMAL_TIMINGS);
  1340. cl = get_cl(emif);
  1341. if (phy_type == EMIF_PHY_TYPE_ATTILAPHY && ip_rev == EMIF_4D) {
  1342. regs->phy_ctrl_1_shdw = get_ddr_phy_ctrl_1_attilaphy_4d(
  1343. timings, freq, cl);
  1344. } else if (phy_type == EMIF_PHY_TYPE_INTELLIPHY && ip_rev == EMIF_4D5) {
  1345. regs->phy_ctrl_1_shdw = get_phy_ctrl_1_intelliphy_4d5(freq, cl);
  1346. regs->ext_phy_ctrl_2_shdw = get_ext_phy_ctrl_2_intelliphy_4d5();
  1347. regs->ext_phy_ctrl_3_shdw = get_ext_phy_ctrl_3_intelliphy_4d5();
  1348. regs->ext_phy_ctrl_4_shdw = get_ext_phy_ctrl_4_intelliphy_4d5();
  1349. } else {
  1350. return -1;
  1351. }
  1352. /* Only timeout values in pwr_mgmt_ctrl_shdw register */
  1353. regs->pwr_mgmt_ctrl_shdw =
  1354. get_pwr_mgmt_ctrl(freq, emif_for_calc, ip_rev) &
  1355. (CS_TIM_MASK | SR_TIM_MASK | PD_TIM_MASK);
  1356. if (ip_rev & EMIF_4D) {
  1357. regs->read_idle_ctrl_shdw_normal =
  1358. get_read_idle_ctrl_shdw(DDR_VOLTAGE_STABLE);
  1359. regs->read_idle_ctrl_shdw_volt_ramp =
  1360. get_read_idle_ctrl_shdw(DDR_VOLTAGE_RAMPING);
  1361. } else if (ip_rev & EMIF_4D5) {
  1362. regs->dll_calib_ctrl_shdw_normal =
  1363. get_dll_calib_ctrl_shdw(DDR_VOLTAGE_STABLE);
  1364. regs->dll_calib_ctrl_shdw_volt_ramp =
  1365. get_dll_calib_ctrl_shdw(DDR_VOLTAGE_RAMPING);
  1366. }
  1367. if (type == DDR_TYPE_LPDDR2_S2 || type == DDR_TYPE_LPDDR2_S4) {
  1368. regs->ref_ctrl_shdw_derated = get_sdram_ref_ctrl_shdw(freq / 4,
  1369. addressing);
  1370. regs->sdram_tim1_shdw_derated =
  1371. get_sdram_tim_1_shdw_derated(timings, min_tck,
  1372. addressing);
  1373. regs->sdram_tim3_shdw_derated = get_sdram_tim_3_shdw(timings,
  1374. min_tck, addressing, type, ip_rev,
  1375. EMIF_DERATED_TIMINGS);
  1376. }
  1377. regs->freq = freq;
  1378. return 0;
  1379. }
  1380. /*
  1381. * get_regs() - gets the cached emif_regs structure for a given EMIF instance
  1382. * given frequency(freq):
  1383. *
  1384. * As an optimisation, every EMIF instance other than EMIF1 shares the
  1385. * register cache with EMIF1 if the devices connected on this instance
  1386. * are same as that on EMIF1(indicated by the duplicate flag)
  1387. *
  1388. * If we do not have an entry corresponding to the frequency given, we
  1389. * allocate a new entry and calculate the values
  1390. *
  1391. * Upon finding the right reg dump, save it in curr_regs. It can be
  1392. * directly used for thermal de-rating and voltage ramping changes.
  1393. */
  1394. static struct emif_regs *get_regs(struct emif_data *emif, u32 freq)
  1395. {
  1396. int i;
  1397. struct emif_regs **regs_cache;
  1398. struct emif_regs *regs = NULL;
  1399. struct device *dev;
  1400. dev = emif->dev;
  1401. if (emif->curr_regs && emif->curr_regs->freq == freq) {
  1402. dev_dbg(dev, "%s: using curr_regs - %u Hz", __func__, freq);
  1403. return emif->curr_regs;
  1404. }
  1405. if (emif->duplicate)
  1406. regs_cache = emif1->regs_cache;
  1407. else
  1408. regs_cache = emif->regs_cache;
  1409. for (i = 0; i < EMIF_MAX_NUM_FREQUENCIES && regs_cache[i]; i++) {
  1410. if (regs_cache[i]->freq == freq) {
  1411. regs = regs_cache[i];
  1412. dev_dbg(dev,
  1413. "%s: reg dump found in reg cache for %u Hz\n",
  1414. __func__, freq);
  1415. break;
  1416. }
  1417. }
  1418. /*
  1419. * If we don't have an entry for this frequency in the cache create one
  1420. * and calculate the values
  1421. */
  1422. if (!regs) {
  1423. regs = devm_kzalloc(emif->dev, sizeof(*regs), GFP_ATOMIC);
  1424. if (!regs)
  1425. return NULL;
  1426. if (get_emif_reg_values(emif, freq, regs)) {
  1427. devm_kfree(emif->dev, regs);
  1428. return NULL;
  1429. }
  1430. /*
  1431. * Now look for an un-used entry in the cache and save the
  1432. * newly created struct. If there are no free entries
  1433. * over-write the last entry
  1434. */
  1435. for (i = 0; i < EMIF_MAX_NUM_FREQUENCIES && regs_cache[i]; i++)
  1436. ;
  1437. if (i >= EMIF_MAX_NUM_FREQUENCIES) {
  1438. dev_warn(dev, "%s: regs_cache full - reusing a slot!!\n",
  1439. __func__);
  1440. i = EMIF_MAX_NUM_FREQUENCIES - 1;
  1441. devm_kfree(emif->dev, regs_cache[i]);
  1442. }
  1443. regs_cache[i] = regs;
  1444. }
  1445. return regs;
  1446. }
  1447. static void do_volt_notify_handling(struct emif_data *emif, u32 volt_state)
  1448. {
  1449. dev_dbg(emif->dev, "%s: voltage notification : %d", __func__,
  1450. volt_state);
  1451. if (!emif->curr_regs) {
  1452. dev_err(emif->dev,
  1453. "%s: volt-notify before registers are ready: %d\n",
  1454. __func__, volt_state);
  1455. return;
  1456. }
  1457. setup_volt_sensitive_regs(emif, emif->curr_regs, volt_state);
  1458. }
  1459. /*
  1460. * TODO: voltage notify handling should be hooked up to
  1461. * regulator framework as soon as the necessary support
  1462. * is available in mainline kernel. This function is un-used
  1463. * right now.
  1464. */
  1465. static void __attribute__((unused)) volt_notify_handling(u32 volt_state)
  1466. {
  1467. struct emif_data *emif;
  1468. spin_lock_irqsave(&emif_lock, irq_state);
  1469. list_for_each_entry(emif, &device_list, node)
  1470. do_volt_notify_handling(emif, volt_state);
  1471. do_freq_update();
  1472. spin_unlock_irqrestore(&emif_lock, irq_state);
  1473. }
  1474. static void do_freq_pre_notify_handling(struct emif_data *emif, u32 new_freq)
  1475. {
  1476. struct emif_regs *regs;
  1477. regs = get_regs(emif, new_freq);
  1478. if (!regs)
  1479. return;
  1480. emif->curr_regs = regs;
  1481. /*
  1482. * Update the shadow registers:
  1483. * Temperature and voltage-ramp sensitive settings are also configured
  1484. * in terms of DDR cycles. So, we need to update them too when there
  1485. * is a freq change
  1486. */
  1487. dev_dbg(emif->dev, "%s: setting up shadow registers for %uHz",
  1488. __func__, new_freq);
  1489. setup_registers(emif, regs);
  1490. setup_temperature_sensitive_regs(emif, regs);
  1491. setup_volt_sensitive_regs(emif, regs, DDR_VOLTAGE_STABLE);
  1492. /*
  1493. * Part of workaround for errata i728. See do_freq_update()
  1494. * for more details
  1495. */
  1496. if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH)
  1497. set_lpmode(emif, EMIF_LP_MODE_DISABLE);
  1498. }
  1499. /*
  1500. * TODO: frequency notify handling should be hooked up to
  1501. * clock framework as soon as the necessary support is
  1502. * available in mainline kernel. This function is un-used
  1503. * right now.
  1504. */
  1505. static void __attribute__((unused)) freq_pre_notify_handling(u32 new_freq)
  1506. {
  1507. struct emif_data *emif;
  1508. /*
  1509. * NOTE: we are taking the spin-lock here and releases it
  1510. * only in post-notifier. This doesn't look good and
  1511. * Sparse complains about it, but this seems to be
  1512. * un-avoidable. We need to lock a sequence of events
  1513. * that is split between EMIF and clock framework.
  1514. *
  1515. * 1. EMIF driver updates EMIF timings in shadow registers in the
  1516. * frequency pre-notify callback from clock framework
  1517. * 2. clock framework sets up the registers for the new frequency
  1518. * 3. clock framework initiates a hw-sequence that updates
  1519. * the frequency EMIF timings synchronously.
  1520. *
  1521. * All these 3 steps should be performed as an atomic operation
  1522. * vis-a-vis similar sequence in the EMIF interrupt handler
  1523. * for temperature events. Otherwise, there could be race
  1524. * conditions that could result in incorrect EMIF timings for
  1525. * a given frequency
  1526. */
  1527. spin_lock_irqsave(&emif_lock, irq_state);
  1528. list_for_each_entry(emif, &device_list, node)
  1529. do_freq_pre_notify_handling(emif, new_freq);
  1530. }
  1531. static void do_freq_post_notify_handling(struct emif_data *emif)
  1532. {
  1533. /*
  1534. * Part of workaround for errata i728. See do_freq_update()
  1535. * for more details
  1536. */
  1537. if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH)
  1538. set_lpmode(emif, EMIF_LP_MODE_SELF_REFRESH);
  1539. }
  1540. /*
  1541. * TODO: frequency notify handling should be hooked up to
  1542. * clock framework as soon as the necessary support is
  1543. * available in mainline kernel. This function is un-used
  1544. * right now.
  1545. */
  1546. static void __attribute__((unused)) freq_post_notify_handling(void)
  1547. {
  1548. struct emif_data *emif;
  1549. list_for_each_entry(emif, &device_list, node)
  1550. do_freq_post_notify_handling(emif);
  1551. /*
  1552. * Lock is done in pre-notify handler. See freq_pre_notify_handling()
  1553. * for more details
  1554. */
  1555. spin_unlock_irqrestore(&emif_lock, irq_state);
  1556. }
  1557. #if defined(CONFIG_OF)
  1558. static const struct of_device_id emif_of_match[] = {
  1559. { .compatible = "ti,emif-4d" },
  1560. { .compatible = "ti,emif-4d5" },
  1561. {},
  1562. };
  1563. MODULE_DEVICE_TABLE(of, emif_of_match);
  1564. #endif
  1565. static struct platform_driver emif_driver = {
  1566. .remove = __exit_p(emif_remove),
  1567. .shutdown = emif_shutdown,
  1568. .driver = {
  1569. .name = "emif",
  1570. .of_match_table = of_match_ptr(emif_of_match),
  1571. },
  1572. };
  1573. module_platform_driver_probe(emif_driver, emif_probe);
  1574. MODULE_DESCRIPTION("TI EMIF SDRAM Controller Driver");
  1575. MODULE_LICENSE("GPL");
  1576. MODULE_ALIAS("platform:emif");
  1577. MODULE_AUTHOR("Texas Instruments Inc");