tda18250.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * NXP TDA18250 silicon tuner driver
  4. *
  5. * Copyright (C) 2017 Olli Salonen <olli.salonen@iki.fi>
  6. */
  7. #include "tda18250_priv.h"
  8. #include <linux/regmap.h>
  9. static const struct dvb_tuner_ops tda18250_ops;
  10. static int tda18250_power_control(struct dvb_frontend *fe,
  11. unsigned int power_state)
  12. {
  13. struct i2c_client *client = fe->tuner_priv;
  14. struct tda18250_dev *dev = i2c_get_clientdata(client);
  15. int ret;
  16. unsigned int utmp;
  17. dev_dbg(&client->dev, "power state: %d", power_state);
  18. switch (power_state) {
  19. case TDA18250_POWER_NORMAL:
  20. ret = regmap_write_bits(dev->regmap, R06_POWER2, 0x07, 0x00);
  21. if (ret)
  22. goto err;
  23. ret = regmap_write_bits(dev->regmap, R25_REF, 0xc0, 0xc0);
  24. if (ret)
  25. goto err;
  26. break;
  27. case TDA18250_POWER_STANDBY:
  28. if (dev->loopthrough) {
  29. ret = regmap_write_bits(dev->regmap,
  30. R25_REF, 0xc0, 0x80);
  31. if (ret)
  32. goto err;
  33. ret = regmap_write_bits(dev->regmap,
  34. R06_POWER2, 0x07, 0x02);
  35. if (ret)
  36. goto err;
  37. ret = regmap_write_bits(dev->regmap,
  38. R10_LT1, 0x80, 0x00);
  39. if (ret)
  40. goto err;
  41. } else {
  42. ret = regmap_write_bits(dev->regmap,
  43. R25_REF, 0xc0, 0x80);
  44. if (ret)
  45. goto err;
  46. ret = regmap_write_bits(dev->regmap,
  47. R06_POWER2, 0x07, 0x01);
  48. if (ret)
  49. goto err;
  50. ret = regmap_read(dev->regmap,
  51. R0D_AGC12, &utmp);
  52. if (ret)
  53. goto err;
  54. ret = regmap_write_bits(dev->regmap,
  55. R0D_AGC12, 0x03, 0x03);
  56. if (ret)
  57. goto err;
  58. ret = regmap_write_bits(dev->regmap,
  59. R10_LT1, 0x80, 0x80);
  60. if (ret)
  61. goto err;
  62. ret = regmap_write_bits(dev->regmap,
  63. R0D_AGC12, 0x03, utmp & 0x03);
  64. if (ret)
  65. goto err;
  66. }
  67. break;
  68. default:
  69. ret = -EINVAL;
  70. goto err;
  71. }
  72. return 0;
  73. err:
  74. return ret;
  75. }
  76. static int tda18250_wait_for_irq(struct dvb_frontend *fe,
  77. int maxwait, int step, u8 irq)
  78. {
  79. struct i2c_client *client = fe->tuner_priv;
  80. struct tda18250_dev *dev = i2c_get_clientdata(client);
  81. int ret;
  82. unsigned long timeout;
  83. bool triggered;
  84. unsigned int utmp;
  85. triggered = false;
  86. timeout = jiffies + msecs_to_jiffies(maxwait);
  87. while (!time_after(jiffies, timeout)) {
  88. // check for the IRQ
  89. ret = regmap_read(dev->regmap, R08_IRQ1, &utmp);
  90. if (ret)
  91. goto err;
  92. if ((utmp & irq) == irq) {
  93. triggered = true;
  94. break;
  95. }
  96. msleep(step);
  97. }
  98. dev_dbg(&client->dev, "waited IRQ (0x%02x) %d ms, triggered: %s", irq,
  99. jiffies_to_msecs(jiffies) -
  100. (jiffies_to_msecs(timeout) - maxwait),
  101. triggered ? "true" : "false");
  102. if (!triggered)
  103. return -ETIMEDOUT;
  104. return 0;
  105. err:
  106. return ret;
  107. }
  108. static int tda18250_init(struct dvb_frontend *fe)
  109. {
  110. struct i2c_client *client = fe->tuner_priv;
  111. struct tda18250_dev *dev = i2c_get_clientdata(client);
  112. int ret, i;
  113. /* default values for various regs */
  114. static const u8 init_regs[][2] = {
  115. { R0C_AGC11, 0xc7 },
  116. { R0D_AGC12, 0x5d },
  117. { R0E_AGC13, 0x40 },
  118. { R0F_AGC14, 0x0e },
  119. { R10_LT1, 0x47 },
  120. { R11_LT2, 0x4e },
  121. { R12_AGC21, 0x26 },
  122. { R13_AGC22, 0x60 },
  123. { R18_AGC32, 0x37 },
  124. { R19_AGC33, 0x09 },
  125. { R1A_AGCK, 0x00 },
  126. { R1E_WI_FI, 0x29 },
  127. { R1F_RF_BPF, 0x06 },
  128. { R20_IR_MIX, 0xc6 },
  129. { R21_IF_AGC, 0x00 },
  130. { R2C_PS1, 0x75 },
  131. { R2D_PS2, 0x06 },
  132. { R2E_PS3, 0x07 },
  133. { R30_RSSI2, 0x0e },
  134. { R31_IRQ_CTRL, 0x00 },
  135. { R39_SD5, 0x00 },
  136. { R3B_REGU, 0x55 },
  137. { R3C_RCCAL1, 0xa7 },
  138. { R3F_IRCAL2, 0x85 },
  139. { R40_IRCAL3, 0x87 },
  140. { R41_IRCAL4, 0xc0 },
  141. { R43_PD1, 0x40 },
  142. { R44_PD2, 0xc0 },
  143. { R46_CPUMP, 0x0c },
  144. { R47_LNAPOL, 0x64 },
  145. { R4B_XTALOSC1, 0x30 },
  146. { R59_AGC2_UP2, 0x05 },
  147. { R5B_AGC_AUTO, 0x07 },
  148. { R5C_AGC_DEBUG, 0x00 },
  149. };
  150. /* crystal related regs depend on frequency */
  151. static const u8 xtal_regs[][5] = {
  152. /* reg: 4d 4e 4f 50 51 */
  153. [TDA18250_XTAL_FREQ_16MHZ] = { 0x3e, 0x80, 0x50, 0x00, 0x20 },
  154. [TDA18250_XTAL_FREQ_24MHZ] = { 0x5d, 0xc0, 0xec, 0x00, 0x18 },
  155. [TDA18250_XTAL_FREQ_25MHZ] = { 0x61, 0xa8, 0xec, 0x80, 0x19 },
  156. [TDA18250_XTAL_FREQ_27MHZ] = { 0x69, 0x78, 0x8d, 0x80, 0x1b },
  157. [TDA18250_XTAL_FREQ_30MHZ] = { 0x75, 0x30, 0x8f, 0x00, 0x1e },
  158. };
  159. dev_dbg(&client->dev, "\n");
  160. ret = tda18250_power_control(fe, TDA18250_POWER_NORMAL);
  161. if (ret)
  162. goto err;
  163. msleep(20);
  164. if (dev->warm)
  165. goto warm;
  166. /* set initial register values */
  167. for (i = 0; i < ARRAY_SIZE(init_regs); i++) {
  168. ret = regmap_write(dev->regmap, init_regs[i][0],
  169. init_regs[i][1]);
  170. if (ret)
  171. goto err;
  172. }
  173. /* set xtal related regs */
  174. ret = regmap_bulk_write(dev->regmap, R4D_XTALFLX1,
  175. xtal_regs[dev->xtal_freq], 5);
  176. if (ret)
  177. goto err;
  178. ret = regmap_write_bits(dev->regmap, R10_LT1, 0x80,
  179. dev->loopthrough ? 0x00 : 0x80);
  180. if (ret)
  181. goto err;
  182. /* clear IRQ */
  183. ret = regmap_write(dev->regmap, R0A_IRQ3, TDA18250_IRQ_HW_INIT);
  184. if (ret)
  185. goto err;
  186. /* start HW init */
  187. ret = regmap_write(dev->regmap, R2A_MSM1, 0x70);
  188. if (ret)
  189. goto err;
  190. ret = regmap_write(dev->regmap, R2B_MSM2, 0x01);
  191. if (ret)
  192. goto err;
  193. ret = tda18250_wait_for_irq(fe, 500, 10, TDA18250_IRQ_HW_INIT);
  194. if (ret)
  195. goto err;
  196. /* tuner calibration */
  197. ret = regmap_write(dev->regmap, R2A_MSM1, 0x02);
  198. if (ret)
  199. goto err;
  200. ret = regmap_write(dev->regmap, R2B_MSM2, 0x01);
  201. if (ret)
  202. goto err;
  203. ret = tda18250_wait_for_irq(fe, 500, 10, TDA18250_IRQ_CAL);
  204. if (ret)
  205. goto err;
  206. dev->warm = true;
  207. warm:
  208. /* power up LNA */
  209. ret = regmap_write_bits(dev->regmap, R0C_AGC11, 0x80, 0x00);
  210. if (ret)
  211. goto err;
  212. return 0;
  213. err:
  214. dev_dbg(&client->dev, "failed=%d", ret);
  215. return ret;
  216. }
  217. static int tda18250_set_agc(struct dvb_frontend *fe)
  218. {
  219. struct i2c_client *client = fe->tuner_priv;
  220. struct tda18250_dev *dev = i2c_get_clientdata(client);
  221. struct dtv_frontend_properties *c = &fe->dtv_property_cache;
  222. int ret;
  223. u8 utmp, utmp2;
  224. dev_dbg(&client->dev, "\n");
  225. ret = regmap_write_bits(dev->regmap, R1F_RF_BPF, 0x87, 0x06);
  226. if (ret)
  227. goto err;
  228. utmp = ((c->frequency < 100000000) &&
  229. ((c->delivery_system == SYS_DVBC_ANNEX_A) ||
  230. (c->delivery_system == SYS_DVBC_ANNEX_C)) &&
  231. (c->bandwidth_hz == 6000000)) ? 0x80 : 0x00;
  232. ret = regmap_write(dev->regmap, R5A_H3H5, utmp);
  233. if (ret)
  234. goto err;
  235. /* AGC1 */
  236. switch (c->delivery_system) {
  237. case SYS_ATSC:
  238. case SYS_DVBT:
  239. case SYS_DVBT2:
  240. utmp = 4;
  241. break;
  242. default: /* DVB-C/QAM */
  243. switch (c->bandwidth_hz) {
  244. case 6000000:
  245. utmp = (c->frequency < 800000000) ? 6 : 4;
  246. break;
  247. default: /* 7.935 and 8 MHz */
  248. utmp = (c->frequency < 100000000) ? 2 : 3;
  249. break;
  250. }
  251. break;
  252. }
  253. ret = regmap_write_bits(dev->regmap, R0C_AGC11, 0x07, utmp);
  254. if (ret)
  255. goto err;
  256. /* AGC2 */
  257. switch (c->delivery_system) {
  258. case SYS_ATSC:
  259. case SYS_DVBT:
  260. case SYS_DVBT2:
  261. utmp = (c->frequency < 320000000) ? 20 : 16;
  262. utmp2 = (c->frequency < 320000000) ? 22 : 18;
  263. break;
  264. default: /* DVB-C/QAM */
  265. switch (c->bandwidth_hz) {
  266. case 6000000:
  267. if (c->frequency < 600000000) {
  268. utmp = 18;
  269. utmp2 = 22;
  270. } else if (c->frequency < 800000000) {
  271. utmp = 16;
  272. utmp2 = 20;
  273. } else {
  274. utmp = 14;
  275. utmp2 = 16;
  276. }
  277. break;
  278. default: /* 7.935 and 8 MHz */
  279. utmp = (c->frequency < 320000000) ? 16 : 18;
  280. utmp2 = (c->frequency < 320000000) ? 18 : 20;
  281. break;
  282. }
  283. break;
  284. }
  285. ret = regmap_write_bits(dev->regmap, R58_AGC2_UP1, 0x1f, utmp2+8);
  286. if (ret)
  287. goto err;
  288. ret = regmap_write_bits(dev->regmap, R13_AGC22, 0x1f, utmp);
  289. if (ret)
  290. goto err;
  291. ret = regmap_write_bits(dev->regmap, R14_AGC23, 0x1f, utmp2);
  292. if (ret)
  293. goto err;
  294. switch (c->delivery_system) {
  295. case SYS_ATSC:
  296. case SYS_DVBT:
  297. case SYS_DVBT2:
  298. utmp = 98;
  299. break;
  300. default: /* DVB-C/QAM */
  301. utmp = 90;
  302. break;
  303. }
  304. ret = regmap_write_bits(dev->regmap, R16_AGC25, 0xf8, utmp);
  305. if (ret)
  306. goto err;
  307. ret = regmap_write_bits(dev->regmap, R12_AGC21, 0x60,
  308. (c->frequency > 800000000) ? 0x40 : 0x20);
  309. if (ret)
  310. goto err;
  311. /* AGC3 */
  312. switch (c->delivery_system) {
  313. case SYS_ATSC:
  314. case SYS_DVBT:
  315. case SYS_DVBT2:
  316. utmp = (c->frequency < 320000000) ? 5 : 7;
  317. utmp2 = (c->frequency < 320000000) ? 10 : 12;
  318. break;
  319. default: /* DVB-C/QAM */
  320. utmp = 7;
  321. utmp2 = 12;
  322. break;
  323. }
  324. ret = regmap_write(dev->regmap, R17_AGC31, (utmp << 4) | utmp2);
  325. if (ret)
  326. goto err;
  327. /* S2D */
  328. switch (c->delivery_system) {
  329. case SYS_ATSC:
  330. case SYS_DVBT:
  331. case SYS_DVBT2:
  332. if (c->bandwidth_hz == 8000000)
  333. utmp = 0x04;
  334. else
  335. utmp = (c->frequency < 320000000) ? 0x04 : 0x02;
  336. break;
  337. default: /* DVB-C/QAM */
  338. if (c->bandwidth_hz == 6000000)
  339. utmp = ((c->frequency > 172544000) &&
  340. (c->frequency < 320000000)) ? 0x04 : 0x02;
  341. else /* 7.935 and 8 MHz */
  342. utmp = ((c->frequency > 320000000) &&
  343. (c->frequency < 600000000)) ? 0x02 : 0x04;
  344. break;
  345. }
  346. ret = regmap_write_bits(dev->regmap, R20_IR_MIX, 0x06, utmp);
  347. if (ret)
  348. goto err;
  349. switch (c->delivery_system) {
  350. case SYS_ATSC:
  351. case SYS_DVBT:
  352. case SYS_DVBT2:
  353. utmp = 0;
  354. break;
  355. default: /* DVB-C/QAM */
  356. utmp = (c->frequency < 600000000) ? 0 : 3;
  357. break;
  358. }
  359. ret = regmap_write_bits(dev->regmap, R16_AGC25, 0x03, utmp);
  360. if (ret)
  361. goto err;
  362. utmp = 0x09;
  363. switch (c->delivery_system) {
  364. case SYS_ATSC:
  365. case SYS_DVBT:
  366. case SYS_DVBT2:
  367. if (c->bandwidth_hz == 8000000)
  368. utmp = 0x0c;
  369. break;
  370. default: /* DVB-C/QAM */
  371. utmp = 0x0c;
  372. break;
  373. }
  374. ret = regmap_write_bits(dev->regmap, R0F_AGC14, 0x3f, utmp);
  375. if (ret)
  376. goto err;
  377. return 0;
  378. err:
  379. dev_dbg(&client->dev, "failed=%d", ret);
  380. return ret;
  381. }
  382. static int tda18250_pll_calc(struct dvb_frontend *fe, u8 *rdiv,
  383. u8 *ndiv, u8 *icp)
  384. {
  385. struct i2c_client *client = fe->tuner_priv;
  386. struct tda18250_dev *dev = i2c_get_clientdata(client);
  387. struct dtv_frontend_properties *c = &fe->dtv_property_cache;
  388. int ret;
  389. unsigned int uval, exp, lopd, scale;
  390. unsigned long fvco;
  391. ret = regmap_read(dev->regmap, R34_MD1, &uval);
  392. if (ret)
  393. goto err;
  394. exp = (uval & 0x70) >> 4;
  395. if (exp > 5)
  396. exp = 0;
  397. lopd = 1 << (exp - 1);
  398. scale = uval & 0x0f;
  399. fvco = lopd * scale * ((c->frequency / 1000) + dev->if_frequency);
  400. switch (dev->xtal_freq) {
  401. case TDA18250_XTAL_FREQ_16MHZ:
  402. *rdiv = 1;
  403. *ndiv = 0;
  404. *icp = (fvco < 6622000) ? 0x05 : 0x02;
  405. break;
  406. case TDA18250_XTAL_FREQ_24MHZ:
  407. case TDA18250_XTAL_FREQ_25MHZ:
  408. *rdiv = 3;
  409. *ndiv = 1;
  410. *icp = (fvco < 6622000) ? 0x05 : 0x02;
  411. break;
  412. case TDA18250_XTAL_FREQ_27MHZ:
  413. if (fvco < 6643000) {
  414. *rdiv = 2;
  415. *ndiv = 0;
  416. *icp = 0x05;
  417. } else if (fvco < 6811000) {
  418. *rdiv = 2;
  419. *ndiv = 0;
  420. *icp = 0x06;
  421. } else {
  422. *rdiv = 3;
  423. *ndiv = 1;
  424. *icp = 0x02;
  425. }
  426. break;
  427. case TDA18250_XTAL_FREQ_30MHZ:
  428. *rdiv = 2;
  429. *ndiv = 0;
  430. *icp = (fvco < 6811000) ? 0x05 : 0x02;
  431. break;
  432. default:
  433. return -EINVAL;
  434. }
  435. dev_dbg(&client->dev,
  436. "lopd=%d scale=%u fvco=%lu, rdiv=%d ndiv=%d icp=%d",
  437. lopd, scale, fvco, *rdiv, *ndiv, *icp);
  438. return 0;
  439. err:
  440. return ret;
  441. }
  442. static int tda18250_set_params(struct dvb_frontend *fe)
  443. {
  444. struct i2c_client *client = fe->tuner_priv;
  445. struct tda18250_dev *dev = i2c_get_clientdata(client);
  446. struct dtv_frontend_properties *c = &fe->dtv_property_cache;
  447. u32 if_khz;
  448. int ret;
  449. unsigned int i, j;
  450. u8 utmp;
  451. u8 buf[3];
  452. #define REG 0
  453. #define MASK 1
  454. #define DVBT_6 2
  455. #define DVBT_7 3
  456. #define DVBT_8 4
  457. #define DVBC_6 5
  458. #define DVBC_8 6
  459. #define ATSC 7
  460. static const u8 delsys_params[][16] = {
  461. [REG] = { 0x22, 0x23, 0x24, 0x21, 0x0d, 0x0c, 0x0f, 0x14,
  462. 0x0e, 0x12, 0x58, 0x59, 0x1a, 0x19, 0x1e, 0x30 },
  463. [MASK] = { 0x77, 0xff, 0xff, 0x87, 0xf0, 0x78, 0x07, 0xe0,
  464. 0x60, 0x0f, 0x60, 0x0f, 0x33, 0x30, 0x80, 0x06 },
  465. [DVBT_6] = { 0x51, 0x03, 0x83, 0x82, 0x40, 0x48, 0x01, 0xe0,
  466. 0x60, 0x0f, 0x60, 0x05, 0x03, 0x10, 0x00, 0x04 },
  467. [DVBT_7] = { 0x52, 0x03, 0x85, 0x82, 0x40, 0x48, 0x01, 0xe0,
  468. 0x60, 0x0f, 0x60, 0x05, 0x03, 0x10, 0x00, 0x04 },
  469. [DVBT_8] = { 0x53, 0x03, 0x87, 0x82, 0x40, 0x48, 0x06, 0xe0,
  470. 0x60, 0x07, 0x60, 0x05, 0x03, 0x10, 0x00, 0x04 },
  471. [DVBC_6] = { 0x32, 0x05, 0x86, 0x82, 0x50, 0x00, 0x06, 0x60,
  472. 0x40, 0x0e, 0x60, 0x05, 0x33, 0x10, 0x00, 0x04 },
  473. [DVBC_8] = { 0x53, 0x03, 0x88, 0x82, 0x50, 0x00, 0x06, 0x60,
  474. 0x40, 0x0e, 0x60, 0x05, 0x33, 0x10, 0x00, 0x04 },
  475. [ATSC] = { 0x51, 0x03, 0x83, 0x82, 0x40, 0x48, 0x01, 0xe0,
  476. 0x40, 0x0e, 0x60, 0x05, 0x03, 0x00, 0x80, 0x04 },
  477. };
  478. dev_dbg(&client->dev,
  479. "delivery_system=%d frequency=%u bandwidth_hz=%u",
  480. c->delivery_system, c->frequency, c->bandwidth_hz);
  481. switch (c->delivery_system) {
  482. case SYS_ATSC:
  483. j = ATSC;
  484. if_khz = dev->if_atsc;
  485. break;
  486. case SYS_DVBT:
  487. case SYS_DVBT2:
  488. if (c->bandwidth_hz == 0) {
  489. ret = -EINVAL;
  490. goto err;
  491. } else if (c->bandwidth_hz <= 6000000) {
  492. j = DVBT_6;
  493. if_khz = dev->if_dvbt_6;
  494. } else if (c->bandwidth_hz <= 7000000) {
  495. j = DVBT_7;
  496. if_khz = dev->if_dvbt_7;
  497. } else if (c->bandwidth_hz <= 8000000) {
  498. j = DVBT_8;
  499. if_khz = dev->if_dvbt_8;
  500. } else {
  501. ret = -EINVAL;
  502. goto err;
  503. }
  504. break;
  505. case SYS_DVBC_ANNEX_A:
  506. case SYS_DVBC_ANNEX_C:
  507. if (c->bandwidth_hz == 0) {
  508. ret = -EINVAL;
  509. goto err;
  510. } else if (c->bandwidth_hz <= 6000000) {
  511. j = DVBC_6;
  512. if_khz = dev->if_dvbc_6;
  513. } else if (c->bandwidth_hz <= 8000000) {
  514. j = DVBC_8;
  515. if_khz = dev->if_dvbc_8;
  516. } else {
  517. ret = -EINVAL;
  518. goto err;
  519. }
  520. break;
  521. default:
  522. ret = -EINVAL;
  523. dev_err(&client->dev, "unsupported delivery system=%d",
  524. c->delivery_system);
  525. goto err;
  526. }
  527. /* set delivery system dependent registers */
  528. for (i = 0; i < 16; i++) {
  529. ret = regmap_write_bits(dev->regmap, delsys_params[REG][i],
  530. delsys_params[MASK][i], delsys_params[j][i]);
  531. if (ret)
  532. goto err;
  533. }
  534. /* set IF if needed */
  535. if (dev->if_frequency != if_khz) {
  536. utmp = DIV_ROUND_CLOSEST(if_khz, 50);
  537. ret = regmap_write(dev->regmap, R26_IF, utmp);
  538. if (ret)
  539. goto err;
  540. dev->if_frequency = if_khz;
  541. dev_dbg(&client->dev, "set IF=%u kHz", if_khz);
  542. }
  543. ret = tda18250_set_agc(fe);
  544. if (ret)
  545. goto err;
  546. ret = regmap_write_bits(dev->regmap, R1A_AGCK, 0x03, 0x01);
  547. if (ret)
  548. goto err;
  549. ret = regmap_write_bits(dev->regmap, R14_AGC23, 0x40, 0x00);
  550. if (ret)
  551. goto err;
  552. /* set frequency */
  553. buf[0] = ((c->frequency / 1000) >> 16) & 0xff;
  554. buf[1] = ((c->frequency / 1000) >> 8) & 0xff;
  555. buf[2] = ((c->frequency / 1000) >> 0) & 0xff;
  556. ret = regmap_bulk_write(dev->regmap, R27_RF1, buf, 3);
  557. if (ret)
  558. goto err;
  559. ret = regmap_write(dev->regmap, R0A_IRQ3, TDA18250_IRQ_TUNE);
  560. if (ret)
  561. goto err;
  562. /* initial tune */
  563. ret = regmap_write(dev->regmap, R2A_MSM1, 0x01);
  564. if (ret)
  565. goto err;
  566. ret = regmap_write(dev->regmap, R2B_MSM2, 0x01);
  567. if (ret)
  568. goto err;
  569. ret = tda18250_wait_for_irq(fe, 500, 10, TDA18250_IRQ_TUNE);
  570. if (ret)
  571. goto err;
  572. /* calc ndiv and rdiv */
  573. ret = tda18250_pll_calc(fe, &buf[0], &buf[1], &buf[2]);
  574. if (ret)
  575. goto err;
  576. ret = regmap_write_bits(dev->regmap, R4F_XTALFLX3, 0xe0,
  577. (buf[0] << 6) | (buf[1] << 5));
  578. if (ret)
  579. goto err;
  580. /* clear IRQ */
  581. ret = regmap_write(dev->regmap, R0A_IRQ3, TDA18250_IRQ_TUNE);
  582. if (ret)
  583. goto err;
  584. ret = regmap_write_bits(dev->regmap, R46_CPUMP, 0x07, 0x00);
  585. if (ret)
  586. goto err;
  587. ret = regmap_write_bits(dev->regmap, R39_SD5, 0x03, 0x00);
  588. if (ret)
  589. goto err;
  590. /* tune again */
  591. ret = regmap_write(dev->regmap, R2A_MSM1, 0x01); /* tune */
  592. if (ret)
  593. goto err;
  594. ret = regmap_write(dev->regmap, R2B_MSM2, 0x01); /* go */
  595. if (ret)
  596. goto err;
  597. ret = tda18250_wait_for_irq(fe, 500, 10, TDA18250_IRQ_TUNE);
  598. if (ret)
  599. goto err;
  600. /* pll locking */
  601. msleep(20);
  602. ret = regmap_write_bits(dev->regmap, R2B_MSM2, 0x04, 0x04);
  603. if (ret)
  604. goto err;
  605. msleep(20);
  606. /* restore AGCK */
  607. ret = regmap_write_bits(dev->regmap, R1A_AGCK, 0x03, 0x03);
  608. if (ret)
  609. goto err;
  610. ret = regmap_write_bits(dev->regmap, R14_AGC23, 0x40, 0x40);
  611. if (ret)
  612. goto err;
  613. /* charge pump */
  614. ret = regmap_write_bits(dev->regmap, R46_CPUMP, 0x07, buf[2]);
  615. return 0;
  616. err:
  617. return ret;
  618. }
  619. static int tda18250_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
  620. {
  621. struct i2c_client *client = fe->tuner_priv;
  622. struct tda18250_dev *dev = i2c_get_clientdata(client);
  623. *frequency = dev->if_frequency * 1000;
  624. return 0;
  625. }
  626. static int tda18250_sleep(struct dvb_frontend *fe)
  627. {
  628. struct i2c_client *client = fe->tuner_priv;
  629. struct tda18250_dev *dev = i2c_get_clientdata(client);
  630. int ret;
  631. dev_dbg(&client->dev, "\n");
  632. /* power down LNA */
  633. ret = regmap_write_bits(dev->regmap, R0C_AGC11, 0x80, 0x00);
  634. if (ret)
  635. return ret;
  636. /* set if freq to 0 in order to make sure it's set after wake up */
  637. dev->if_frequency = 0;
  638. ret = tda18250_power_control(fe, TDA18250_POWER_STANDBY);
  639. return ret;
  640. }
  641. static const struct dvb_tuner_ops tda18250_ops = {
  642. .info = {
  643. .name = "NXP TDA18250",
  644. .frequency_min_hz = 42 * MHz,
  645. .frequency_max_hz = 870 * MHz,
  646. },
  647. .init = tda18250_init,
  648. .set_params = tda18250_set_params,
  649. .get_if_frequency = tda18250_get_if_frequency,
  650. .sleep = tda18250_sleep,
  651. };
  652. static int tda18250_probe(struct i2c_client *client,
  653. const struct i2c_device_id *id)
  654. {
  655. struct tda18250_config *cfg = client->dev.platform_data;
  656. struct dvb_frontend *fe = cfg->fe;
  657. struct tda18250_dev *dev;
  658. int ret;
  659. unsigned char chip_id[3];
  660. /* some registers are always read from HW */
  661. static const struct regmap_range tda18250_yes_ranges[] = {
  662. regmap_reg_range(R05_POWER1, R0B_IRQ4),
  663. regmap_reg_range(R21_IF_AGC, R21_IF_AGC),
  664. regmap_reg_range(R2A_MSM1, R2B_MSM2),
  665. regmap_reg_range(R2F_RSSI1, R31_IRQ_CTRL),
  666. };
  667. static const struct regmap_access_table tda18250_volatile_table = {
  668. .yes_ranges = tda18250_yes_ranges,
  669. .n_yes_ranges = ARRAY_SIZE(tda18250_yes_ranges),
  670. };
  671. static const struct regmap_config tda18250_regmap_config = {
  672. .reg_bits = 8,
  673. .val_bits = 8,
  674. .max_register = TDA18250_NUM_REGS - 1,
  675. .volatile_table = &tda18250_volatile_table,
  676. };
  677. dev = kzalloc(sizeof(*dev), GFP_KERNEL);
  678. if (!dev) {
  679. ret = -ENOMEM;
  680. goto err;
  681. }
  682. i2c_set_clientdata(client, dev);
  683. dev->fe = cfg->fe;
  684. dev->loopthrough = cfg->loopthrough;
  685. if (cfg->xtal_freq < TDA18250_XTAL_FREQ_MAX) {
  686. dev->xtal_freq = cfg->xtal_freq;
  687. } else {
  688. ret = -EINVAL;
  689. dev_err(&client->dev, "xtal_freq invalid=%d", cfg->xtal_freq);
  690. goto err_kfree;
  691. }
  692. dev->if_dvbt_6 = cfg->if_dvbt_6;
  693. dev->if_dvbt_7 = cfg->if_dvbt_7;
  694. dev->if_dvbt_8 = cfg->if_dvbt_8;
  695. dev->if_dvbc_6 = cfg->if_dvbc_6;
  696. dev->if_dvbc_8 = cfg->if_dvbc_8;
  697. dev->if_atsc = cfg->if_atsc;
  698. dev->if_frequency = 0;
  699. dev->warm = false;
  700. dev->regmap = devm_regmap_init_i2c(client, &tda18250_regmap_config);
  701. if (IS_ERR(dev->regmap)) {
  702. ret = PTR_ERR(dev->regmap);
  703. goto err_kfree;
  704. }
  705. /* read the three chip ID registers */
  706. regmap_bulk_read(dev->regmap, R00_ID1, &chip_id, 3);
  707. dev_dbg(&client->dev, "chip_id=%02x:%02x:%02x",
  708. chip_id[0], chip_id[1], chip_id[2]);
  709. switch (chip_id[0]) {
  710. case 0xc7:
  711. dev->slave = false;
  712. break;
  713. case 0x47:
  714. dev->slave = true;
  715. break;
  716. default:
  717. ret = -ENODEV;
  718. goto err_kfree;
  719. }
  720. if (chip_id[1] != 0x4a) {
  721. ret = -ENODEV;
  722. goto err_kfree;
  723. }
  724. switch (chip_id[2]) {
  725. case 0x20:
  726. dev_info(&client->dev,
  727. "NXP TDA18250AHN/%s successfully identified",
  728. dev->slave ? "S" : "M");
  729. break;
  730. case 0x21:
  731. dev_info(&client->dev,
  732. "NXP TDA18250BHN/%s successfully identified",
  733. dev->slave ? "S" : "M");
  734. break;
  735. default:
  736. ret = -ENODEV;
  737. goto err_kfree;
  738. }
  739. fe->tuner_priv = client;
  740. memcpy(&fe->ops.tuner_ops, &tda18250_ops,
  741. sizeof(struct dvb_tuner_ops));
  742. /* put the tuner in standby */
  743. tda18250_power_control(fe, TDA18250_POWER_STANDBY);
  744. return 0;
  745. err_kfree:
  746. kfree(dev);
  747. err:
  748. dev_dbg(&client->dev, "failed=%d", ret);
  749. return ret;
  750. }
  751. static int tda18250_remove(struct i2c_client *client)
  752. {
  753. struct tda18250_dev *dev = i2c_get_clientdata(client);
  754. struct dvb_frontend *fe = dev->fe;
  755. dev_dbg(&client->dev, "\n");
  756. memset(&fe->ops.tuner_ops, 0, sizeof(struct dvb_tuner_ops));
  757. fe->tuner_priv = NULL;
  758. kfree(dev);
  759. return 0;
  760. }
  761. static const struct i2c_device_id tda18250_id_table[] = {
  762. {"tda18250", 0},
  763. {}
  764. };
  765. MODULE_DEVICE_TABLE(i2c, tda18250_id_table);
  766. static struct i2c_driver tda18250_driver = {
  767. .driver = {
  768. .name = "tda18250",
  769. },
  770. .probe = tda18250_probe,
  771. .remove = tda18250_remove,
  772. .id_table = tda18250_id_table,
  773. };
  774. module_i2c_driver(tda18250_driver);
  775. MODULE_DESCRIPTION("NXP TDA18250 silicon tuner driver");
  776. MODULE_AUTHOR("Olli Salonen <olli.salonen@iki.fi>");
  777. MODULE_LICENSE("GPL");