r820t.c 55 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. // Rafael Micro R820T driver
  3. //
  4. // Copyright (C) 2013 Mauro Carvalho Chehab
  5. //
  6. // This driver was written from scratch, based on an existing driver
  7. // that it is part of rtl-sdr git tree, released under GPLv2:
  8. // https://groups.google.com/forum/#!topic/ultra-cheap-sdr/Y3rBEOFtHug
  9. // https://github.com/n1gp/gr-baz
  10. //
  11. // From what I understood from the threads, the original driver was converted
  12. // to userspace from a Realtek tree. I couldn't find the original tree.
  13. // However, the original driver look awkward on my eyes. So, I decided to
  14. // write a new version from it from the scratch, while trying to reproduce
  15. // everything found there.
  16. //
  17. // TODO:
  18. // After locking, the original driver seems to have some routines to
  19. // improve reception. This was not implemented here yet.
  20. //
  21. // RF Gain set/get is not implemented.
  22. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  23. #include <linux/videodev2.h>
  24. #include <linux/mutex.h>
  25. #include <linux/slab.h>
  26. #include <linux/bitrev.h>
  27. #include "tuner-i2c.h"
  28. #include "r820t.h"
  29. /*
  30. * FIXME: I think that there are only 32 registers, but better safe than
  31. * sorry. After finishing the driver, we may review it.
  32. */
  33. #define REG_SHADOW_START 5
  34. #define NUM_REGS 27
  35. #define NUM_IMR 5
  36. #define IMR_TRIAL 9
  37. #define VER_NUM 49
  38. static int debug;
  39. module_param(debug, int, 0644);
  40. MODULE_PARM_DESC(debug, "enable verbose debug messages");
  41. static int no_imr_cal;
  42. module_param(no_imr_cal, int, 0444);
  43. MODULE_PARM_DESC(no_imr_cal, "Disable IMR calibration at module init");
  44. /*
  45. * enums and structures
  46. */
  47. enum xtal_cap_value {
  48. XTAL_LOW_CAP_30P = 0,
  49. XTAL_LOW_CAP_20P,
  50. XTAL_LOW_CAP_10P,
  51. XTAL_LOW_CAP_0P,
  52. XTAL_HIGH_CAP_0P
  53. };
  54. struct r820t_sect_type {
  55. u8 phase_y;
  56. u8 gain_x;
  57. u16 value;
  58. };
  59. struct r820t_priv {
  60. struct list_head hybrid_tuner_instance_list;
  61. const struct r820t_config *cfg;
  62. struct tuner_i2c_props i2c_props;
  63. struct mutex lock;
  64. u8 regs[NUM_REGS];
  65. u8 buf[NUM_REGS + 1];
  66. enum xtal_cap_value xtal_cap_sel;
  67. u16 pll; /* kHz */
  68. u32 int_freq;
  69. u8 fil_cal_code;
  70. bool imr_done;
  71. bool has_lock;
  72. bool init_done;
  73. struct r820t_sect_type imr_data[NUM_IMR];
  74. /* Store current mode */
  75. u32 delsys;
  76. enum v4l2_tuner_type type;
  77. v4l2_std_id std;
  78. u32 bw; /* in MHz */
  79. };
  80. struct r820t_freq_range {
  81. u32 freq;
  82. u8 open_d;
  83. u8 rf_mux_ploy;
  84. u8 tf_c;
  85. u8 xtal_cap20p;
  86. u8 xtal_cap10p;
  87. u8 xtal_cap0p;
  88. u8 imr_mem; /* Not used, currently */
  89. };
  90. #define VCO_POWER_REF 0x02
  91. #define DIP_FREQ 32000000
  92. /*
  93. * Static constants
  94. */
  95. static LIST_HEAD(hybrid_tuner_instance_list);
  96. static DEFINE_MUTEX(r820t_list_mutex);
  97. /* Those initial values start from REG_SHADOW_START */
  98. static const u8 r820t_init_array[NUM_REGS] = {
  99. 0x83, 0x32, 0x75, /* 05 to 07 */
  100. 0xc0, 0x40, 0xd6, 0x6c, /* 08 to 0b */
  101. 0xf5, 0x63, 0x75, 0x68, /* 0c to 0f */
  102. 0x6c, 0x83, 0x80, 0x00, /* 10 to 13 */
  103. 0x0f, 0x00, 0xc0, 0x30, /* 14 to 17 */
  104. 0x48, 0xcc, 0x60, 0x00, /* 18 to 1b */
  105. 0x54, 0xae, 0x4a, 0xc0 /* 1c to 1f */
  106. };
  107. /* Tuner frequency ranges */
  108. static const struct r820t_freq_range freq_ranges[] = {
  109. {
  110. .freq = 0,
  111. .open_d = 0x08, /* low */
  112. .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
  113. .tf_c = 0xdf, /* R27[7:0] band2,band0 */
  114. .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
  115. .xtal_cap10p = 0x01,
  116. .xtal_cap0p = 0x00,
  117. .imr_mem = 0,
  118. }, {
  119. .freq = 50, /* Start freq, in MHz */
  120. .open_d = 0x08, /* low */
  121. .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
  122. .tf_c = 0xbe, /* R27[7:0] band4,band1 */
  123. .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
  124. .xtal_cap10p = 0x01,
  125. .xtal_cap0p = 0x00,
  126. .imr_mem = 0,
  127. }, {
  128. .freq = 55, /* Start freq, in MHz */
  129. .open_d = 0x08, /* low */
  130. .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
  131. .tf_c = 0x8b, /* R27[7:0] band7,band4 */
  132. .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
  133. .xtal_cap10p = 0x01,
  134. .xtal_cap0p = 0x00,
  135. .imr_mem = 0,
  136. }, {
  137. .freq = 60, /* Start freq, in MHz */
  138. .open_d = 0x08, /* low */
  139. .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
  140. .tf_c = 0x7b, /* R27[7:0] band8,band4 */
  141. .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
  142. .xtal_cap10p = 0x01,
  143. .xtal_cap0p = 0x00,
  144. .imr_mem = 0,
  145. }, {
  146. .freq = 65, /* Start freq, in MHz */
  147. .open_d = 0x08, /* low */
  148. .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
  149. .tf_c = 0x69, /* R27[7:0] band9,band6 */
  150. .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
  151. .xtal_cap10p = 0x01,
  152. .xtal_cap0p = 0x00,
  153. .imr_mem = 0,
  154. }, {
  155. .freq = 70, /* Start freq, in MHz */
  156. .open_d = 0x08, /* low */
  157. .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
  158. .tf_c = 0x58, /* R27[7:0] band10,band7 */
  159. .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
  160. .xtal_cap10p = 0x01,
  161. .xtal_cap0p = 0x00,
  162. .imr_mem = 0,
  163. }, {
  164. .freq = 75, /* Start freq, in MHz */
  165. .open_d = 0x00, /* high */
  166. .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
  167. .tf_c = 0x44, /* R27[7:0] band11,band11 */
  168. .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
  169. .xtal_cap10p = 0x01,
  170. .xtal_cap0p = 0x00,
  171. .imr_mem = 0,
  172. }, {
  173. .freq = 80, /* Start freq, in MHz */
  174. .open_d = 0x00, /* high */
  175. .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
  176. .tf_c = 0x44, /* R27[7:0] band11,band11 */
  177. .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
  178. .xtal_cap10p = 0x01,
  179. .xtal_cap0p = 0x00,
  180. .imr_mem = 0,
  181. }, {
  182. .freq = 90, /* Start freq, in MHz */
  183. .open_d = 0x00, /* high */
  184. .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
  185. .tf_c = 0x34, /* R27[7:0] band12,band11 */
  186. .xtal_cap20p = 0x01, /* R16[1:0] 10pF (01) */
  187. .xtal_cap10p = 0x01,
  188. .xtal_cap0p = 0x00,
  189. .imr_mem = 0,
  190. }, {
  191. .freq = 100, /* Start freq, in MHz */
  192. .open_d = 0x00, /* high */
  193. .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
  194. .tf_c = 0x34, /* R27[7:0] band12,band11 */
  195. .xtal_cap20p = 0x01, /* R16[1:0] 10pF (01) */
  196. .xtal_cap10p = 0x01,
  197. .xtal_cap0p = 0x00,
  198. .imr_mem = 0,
  199. }, {
  200. .freq = 110, /* Start freq, in MHz */
  201. .open_d = 0x00, /* high */
  202. .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
  203. .tf_c = 0x24, /* R27[7:0] band13,band11 */
  204. .xtal_cap20p = 0x01, /* R16[1:0] 10pF (01) */
  205. .xtal_cap10p = 0x01,
  206. .xtal_cap0p = 0x00,
  207. .imr_mem = 1,
  208. }, {
  209. .freq = 120, /* Start freq, in MHz */
  210. .open_d = 0x00, /* high */
  211. .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
  212. .tf_c = 0x24, /* R27[7:0] band13,band11 */
  213. .xtal_cap20p = 0x01, /* R16[1:0] 10pF (01) */
  214. .xtal_cap10p = 0x01,
  215. .xtal_cap0p = 0x00,
  216. .imr_mem = 1,
  217. }, {
  218. .freq = 140, /* Start freq, in MHz */
  219. .open_d = 0x00, /* high */
  220. .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
  221. .tf_c = 0x14, /* R27[7:0] band14,band11 */
  222. .xtal_cap20p = 0x01, /* R16[1:0] 10pF (01) */
  223. .xtal_cap10p = 0x01,
  224. .xtal_cap0p = 0x00,
  225. .imr_mem = 1,
  226. }, {
  227. .freq = 180, /* Start freq, in MHz */
  228. .open_d = 0x00, /* high */
  229. .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
  230. .tf_c = 0x13, /* R27[7:0] band14,band12 */
  231. .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */
  232. .xtal_cap10p = 0x00,
  233. .xtal_cap0p = 0x00,
  234. .imr_mem = 1,
  235. }, {
  236. .freq = 220, /* Start freq, in MHz */
  237. .open_d = 0x00, /* high */
  238. .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
  239. .tf_c = 0x13, /* R27[7:0] band14,band12 */
  240. .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */
  241. .xtal_cap10p = 0x00,
  242. .xtal_cap0p = 0x00,
  243. .imr_mem = 2,
  244. }, {
  245. .freq = 250, /* Start freq, in MHz */
  246. .open_d = 0x00, /* high */
  247. .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
  248. .tf_c = 0x11, /* R27[7:0] highest,highest */
  249. .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */
  250. .xtal_cap10p = 0x00,
  251. .xtal_cap0p = 0x00,
  252. .imr_mem = 2,
  253. }, {
  254. .freq = 280, /* Start freq, in MHz */
  255. .open_d = 0x00, /* high */
  256. .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
  257. .tf_c = 0x00, /* R27[7:0] highest,highest */
  258. .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */
  259. .xtal_cap10p = 0x00,
  260. .xtal_cap0p = 0x00,
  261. .imr_mem = 2,
  262. }, {
  263. .freq = 310, /* Start freq, in MHz */
  264. .open_d = 0x00, /* high */
  265. .rf_mux_ploy = 0x41, /* R26[7:6]=1 (bypass) R26[1:0]=1 (middle) */
  266. .tf_c = 0x00, /* R27[7:0] highest,highest */
  267. .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */
  268. .xtal_cap10p = 0x00,
  269. .xtal_cap0p = 0x00,
  270. .imr_mem = 2,
  271. }, {
  272. .freq = 450, /* Start freq, in MHz */
  273. .open_d = 0x00, /* high */
  274. .rf_mux_ploy = 0x41, /* R26[7:6]=1 (bypass) R26[1:0]=1 (middle) */
  275. .tf_c = 0x00, /* R27[7:0] highest,highest */
  276. .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */
  277. .xtal_cap10p = 0x00,
  278. .xtal_cap0p = 0x00,
  279. .imr_mem = 3,
  280. }, {
  281. .freq = 588, /* Start freq, in MHz */
  282. .open_d = 0x00, /* high */
  283. .rf_mux_ploy = 0x40, /* R26[7:6]=1 (bypass) R26[1:0]=0 (highest) */
  284. .tf_c = 0x00, /* R27[7:0] highest,highest */
  285. .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */
  286. .xtal_cap10p = 0x00,
  287. .xtal_cap0p = 0x00,
  288. .imr_mem = 3,
  289. }, {
  290. .freq = 650, /* Start freq, in MHz */
  291. .open_d = 0x00, /* high */
  292. .rf_mux_ploy = 0x40, /* R26[7:6]=1 (bypass) R26[1:0]=0 (highest) */
  293. .tf_c = 0x00, /* R27[7:0] highest,highest */
  294. .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */
  295. .xtal_cap10p = 0x00,
  296. .xtal_cap0p = 0x00,
  297. .imr_mem = 4,
  298. }
  299. };
  300. static int r820t_xtal_capacitor[][2] = {
  301. { 0x0b, XTAL_LOW_CAP_30P },
  302. { 0x02, XTAL_LOW_CAP_20P },
  303. { 0x01, XTAL_LOW_CAP_10P },
  304. { 0x00, XTAL_LOW_CAP_0P },
  305. { 0x10, XTAL_HIGH_CAP_0P },
  306. };
  307. /*
  308. * I2C read/write code and shadow registers logic
  309. */
  310. static void shadow_store(struct r820t_priv *priv, u8 reg, const u8 *val,
  311. int len)
  312. {
  313. int r = reg - REG_SHADOW_START;
  314. if (r < 0) {
  315. len += r;
  316. r = 0;
  317. }
  318. if (len <= 0)
  319. return;
  320. if (len > NUM_REGS - r)
  321. len = NUM_REGS - r;
  322. tuner_dbg("%s: prev reg=%02x len=%d: %*ph\n",
  323. __func__, r + REG_SHADOW_START, len, len, val);
  324. memcpy(&priv->regs[r], val, len);
  325. }
  326. static int r820t_write(struct r820t_priv *priv, u8 reg, const u8 *val,
  327. int len)
  328. {
  329. int rc, size, pos = 0;
  330. /* Store the shadow registers */
  331. shadow_store(priv, reg, val, len);
  332. do {
  333. if (len > priv->cfg->max_i2c_msg_len - 1)
  334. size = priv->cfg->max_i2c_msg_len - 1;
  335. else
  336. size = len;
  337. /* Fill I2C buffer */
  338. priv->buf[0] = reg;
  339. memcpy(&priv->buf[1], &val[pos], size);
  340. rc = tuner_i2c_xfer_send(&priv->i2c_props, priv->buf, size + 1);
  341. if (rc != size + 1) {
  342. tuner_info("%s: i2c wr failed=%d reg=%02x len=%d: %*ph\n",
  343. __func__, rc, reg, size, size, &priv->buf[1]);
  344. if (rc < 0)
  345. return rc;
  346. return -EREMOTEIO;
  347. }
  348. tuner_dbg("%s: i2c wr reg=%02x len=%d: %*ph\n",
  349. __func__, reg, size, size, &priv->buf[1]);
  350. reg += size;
  351. len -= size;
  352. pos += size;
  353. } while (len > 0);
  354. return 0;
  355. }
  356. static inline int r820t_write_reg(struct r820t_priv *priv, u8 reg, u8 val)
  357. {
  358. u8 tmp = val; /* work around GCC PR81715 with asan-stack=1 */
  359. return r820t_write(priv, reg, &tmp, 1);
  360. }
  361. static int r820t_read_cache_reg(struct r820t_priv *priv, int reg)
  362. {
  363. reg -= REG_SHADOW_START;
  364. if (reg >= 0 && reg < NUM_REGS)
  365. return priv->regs[reg];
  366. else
  367. return -EINVAL;
  368. }
  369. static inline int r820t_write_reg_mask(struct r820t_priv *priv, u8 reg, u8 val,
  370. u8 bit_mask)
  371. {
  372. u8 tmp = val;
  373. int rc = r820t_read_cache_reg(priv, reg);
  374. if (rc < 0)
  375. return rc;
  376. tmp = (rc & ~bit_mask) | (tmp & bit_mask);
  377. return r820t_write(priv, reg, &tmp, 1);
  378. }
  379. static int r820t_read(struct r820t_priv *priv, u8 reg, u8 *val, int len)
  380. {
  381. int rc, i;
  382. u8 *p = &priv->buf[1];
  383. priv->buf[0] = reg;
  384. rc = tuner_i2c_xfer_send_recv(&priv->i2c_props, priv->buf, 1, p, len);
  385. if (rc != len) {
  386. tuner_info("%s: i2c rd failed=%d reg=%02x len=%d: %*ph\n",
  387. __func__, rc, reg, len, len, p);
  388. if (rc < 0)
  389. return rc;
  390. return -EREMOTEIO;
  391. }
  392. /* Copy data to the output buffer */
  393. for (i = 0; i < len; i++)
  394. val[i] = bitrev8(p[i]);
  395. tuner_dbg("%s: i2c rd reg=%02x len=%d: %*ph\n",
  396. __func__, reg, len, len, val);
  397. return 0;
  398. }
  399. /*
  400. * r820t tuning logic
  401. */
  402. static int r820t_set_mux(struct r820t_priv *priv, u32 freq)
  403. {
  404. const struct r820t_freq_range *range;
  405. int i, rc;
  406. u8 val, reg08, reg09;
  407. /* Get the proper frequency range */
  408. freq = freq / 1000000;
  409. for (i = 0; i < ARRAY_SIZE(freq_ranges) - 1; i++) {
  410. if (freq < freq_ranges[i + 1].freq)
  411. break;
  412. }
  413. range = &freq_ranges[i];
  414. tuner_dbg("set r820t range#%d for frequency %d MHz\n", i, freq);
  415. /* Open Drain */
  416. rc = r820t_write_reg_mask(priv, 0x17, range->open_d, 0x08);
  417. if (rc < 0)
  418. return rc;
  419. /* RF_MUX,Polymux */
  420. rc = r820t_write_reg_mask(priv, 0x1a, range->rf_mux_ploy, 0xc3);
  421. if (rc < 0)
  422. return rc;
  423. /* TF BAND */
  424. rc = r820t_write_reg(priv, 0x1b, range->tf_c);
  425. if (rc < 0)
  426. return rc;
  427. /* XTAL CAP & Drive */
  428. switch (priv->xtal_cap_sel) {
  429. case XTAL_LOW_CAP_30P:
  430. case XTAL_LOW_CAP_20P:
  431. val = range->xtal_cap20p | 0x08;
  432. break;
  433. case XTAL_LOW_CAP_10P:
  434. val = range->xtal_cap10p | 0x08;
  435. break;
  436. case XTAL_HIGH_CAP_0P:
  437. val = range->xtal_cap0p | 0x00;
  438. break;
  439. default:
  440. case XTAL_LOW_CAP_0P:
  441. val = range->xtal_cap0p | 0x08;
  442. break;
  443. }
  444. rc = r820t_write_reg_mask(priv, 0x10, val, 0x0b);
  445. if (rc < 0)
  446. return rc;
  447. if (priv->imr_done) {
  448. reg08 = priv->imr_data[range->imr_mem].gain_x;
  449. reg09 = priv->imr_data[range->imr_mem].phase_y;
  450. } else {
  451. reg08 = 0;
  452. reg09 = 0;
  453. }
  454. rc = r820t_write_reg_mask(priv, 0x08, reg08, 0x3f);
  455. if (rc < 0)
  456. return rc;
  457. rc = r820t_write_reg_mask(priv, 0x09, reg09, 0x3f);
  458. return rc;
  459. }
  460. static int r820t_set_pll(struct r820t_priv *priv, enum v4l2_tuner_type type,
  461. u32 freq)
  462. {
  463. u32 vco_freq;
  464. int rc, i;
  465. unsigned sleep_time = 10000;
  466. u32 vco_fra; /* VCO contribution by SDM (kHz) */
  467. u32 vco_min = 1770000;
  468. u32 vco_max = vco_min * 2;
  469. u32 pll_ref;
  470. u16 n_sdm = 2;
  471. u16 sdm = 0;
  472. u8 mix_div = 2;
  473. u8 div_buf = 0;
  474. u8 div_num = 0;
  475. u8 refdiv2 = 0;
  476. u8 ni, si, nint, vco_fine_tune, val;
  477. u8 data[5];
  478. /* Frequency in kHz */
  479. freq = freq / 1000;
  480. pll_ref = priv->cfg->xtal / 1000;
  481. #if 0
  482. /* Doesn't exist on rtl-sdk, and on field tests, caused troubles */
  483. if ((priv->cfg->rafael_chip == CHIP_R620D) ||
  484. (priv->cfg->rafael_chip == CHIP_R828D) ||
  485. (priv->cfg->rafael_chip == CHIP_R828)) {
  486. /* ref set refdiv2, reffreq = Xtal/2 on ATV application */
  487. if (type != V4L2_TUNER_DIGITAL_TV) {
  488. pll_ref /= 2;
  489. refdiv2 = 0x10;
  490. sleep_time = 20000;
  491. }
  492. } else {
  493. if (priv->cfg->xtal > 24000000) {
  494. pll_ref /= 2;
  495. refdiv2 = 0x10;
  496. }
  497. }
  498. #endif
  499. rc = r820t_write_reg_mask(priv, 0x10, refdiv2, 0x10);
  500. if (rc < 0)
  501. return rc;
  502. /* set pll autotune = 128kHz */
  503. rc = r820t_write_reg_mask(priv, 0x1a, 0x00, 0x0c);
  504. if (rc < 0)
  505. return rc;
  506. /* set VCO current = 100 */
  507. rc = r820t_write_reg_mask(priv, 0x12, 0x80, 0xe0);
  508. if (rc < 0)
  509. return rc;
  510. /* Calculate divider */
  511. while (mix_div <= 64) {
  512. if (((freq * mix_div) >= vco_min) &&
  513. ((freq * mix_div) < vco_max)) {
  514. div_buf = mix_div;
  515. while (div_buf > 2) {
  516. div_buf = div_buf >> 1;
  517. div_num++;
  518. }
  519. break;
  520. }
  521. mix_div = mix_div << 1;
  522. }
  523. rc = r820t_read(priv, 0x00, data, sizeof(data));
  524. if (rc < 0)
  525. return rc;
  526. vco_fine_tune = (data[4] & 0x30) >> 4;
  527. tuner_dbg("mix_div=%d div_num=%d vco_fine_tune=%d\n",
  528. mix_div, div_num, vco_fine_tune);
  529. /*
  530. * XXX: R828D/16MHz seems to have always vco_fine_tune=1.
  531. * Due to that, this calculation goes wrong.
  532. */
  533. if (priv->cfg->rafael_chip != CHIP_R828D) {
  534. if (vco_fine_tune > VCO_POWER_REF)
  535. div_num = div_num - 1;
  536. else if (vco_fine_tune < VCO_POWER_REF)
  537. div_num = div_num + 1;
  538. }
  539. rc = r820t_write_reg_mask(priv, 0x10, div_num << 5, 0xe0);
  540. if (rc < 0)
  541. return rc;
  542. vco_freq = freq * mix_div;
  543. nint = vco_freq / (2 * pll_ref);
  544. vco_fra = vco_freq - 2 * pll_ref * nint;
  545. /* boundary spur prevention */
  546. if (vco_fra < pll_ref / 64) {
  547. vco_fra = 0;
  548. } else if (vco_fra > pll_ref * 127 / 64) {
  549. vco_fra = 0;
  550. nint++;
  551. } else if ((vco_fra > pll_ref * 127 / 128) && (vco_fra < pll_ref)) {
  552. vco_fra = pll_ref * 127 / 128;
  553. } else if ((vco_fra > pll_ref) && (vco_fra < pll_ref * 129 / 128)) {
  554. vco_fra = pll_ref * 129 / 128;
  555. }
  556. ni = (nint - 13) / 4;
  557. si = nint - 4 * ni - 13;
  558. rc = r820t_write_reg(priv, 0x14, ni + (si << 6));
  559. if (rc < 0)
  560. return rc;
  561. /* pw_sdm */
  562. if (!vco_fra)
  563. val = 0x08;
  564. else
  565. val = 0x00;
  566. rc = r820t_write_reg_mask(priv, 0x12, val, 0x08);
  567. if (rc < 0)
  568. return rc;
  569. /* sdm calculator */
  570. while (vco_fra > 1) {
  571. if (vco_fra > (2 * pll_ref / n_sdm)) {
  572. sdm = sdm + 32768 / (n_sdm / 2);
  573. vco_fra = vco_fra - 2 * pll_ref / n_sdm;
  574. if (n_sdm >= 0x8000)
  575. break;
  576. }
  577. n_sdm = n_sdm << 1;
  578. }
  579. tuner_dbg("freq %d kHz, pll ref %d%s, sdm=0x%04x\n",
  580. freq, pll_ref, refdiv2 ? " / 2" : "", sdm);
  581. rc = r820t_write_reg(priv, 0x16, sdm >> 8);
  582. if (rc < 0)
  583. return rc;
  584. rc = r820t_write_reg(priv, 0x15, sdm & 0xff);
  585. if (rc < 0)
  586. return rc;
  587. for (i = 0; i < 2; i++) {
  588. usleep_range(sleep_time, sleep_time + 1000);
  589. /* Check if PLL has locked */
  590. rc = r820t_read(priv, 0x00, data, 3);
  591. if (rc < 0)
  592. return rc;
  593. if (data[2] & 0x40)
  594. break;
  595. if (!i) {
  596. /* Didn't lock. Increase VCO current */
  597. rc = r820t_write_reg_mask(priv, 0x12, 0x60, 0xe0);
  598. if (rc < 0)
  599. return rc;
  600. }
  601. }
  602. if (!(data[2] & 0x40)) {
  603. priv->has_lock = false;
  604. return 0;
  605. }
  606. priv->has_lock = true;
  607. tuner_dbg("tuner has lock at frequency %d kHz\n", freq);
  608. /* set pll autotune = 8kHz */
  609. rc = r820t_write_reg_mask(priv, 0x1a, 0x08, 0x08);
  610. return rc;
  611. }
  612. static int r820t_sysfreq_sel(struct r820t_priv *priv, u32 freq,
  613. enum v4l2_tuner_type type,
  614. v4l2_std_id std,
  615. u32 delsys)
  616. {
  617. int rc;
  618. u8 mixer_top, lna_top, cp_cur, div_buf_cur, lna_vth_l, mixer_vth_l;
  619. u8 air_cable1_in, cable2_in, pre_dect, lna_discharge, filter_cur;
  620. tuner_dbg("adjusting tuner parameters for the standard\n");
  621. switch (delsys) {
  622. case SYS_DVBT:
  623. if ((freq == 506000000) || (freq == 666000000) ||
  624. (freq == 818000000)) {
  625. mixer_top = 0x14; /* mixer top:14 , top-1, low-discharge */
  626. lna_top = 0xe5; /* detect bw 3, lna top:4, predet top:2 */
  627. cp_cur = 0x28; /* 101, 0.2 */
  628. div_buf_cur = 0x20; /* 10, 200u */
  629. } else {
  630. mixer_top = 0x24; /* mixer top:13 , top-1, low-discharge */
  631. lna_top = 0xe5; /* detect bw 3, lna top:4, predet top:2 */
  632. cp_cur = 0x38; /* 111, auto */
  633. div_buf_cur = 0x30; /* 11, 150u */
  634. }
  635. lna_vth_l = 0x53; /* lna vth 0.84 , vtl 0.64 */
  636. mixer_vth_l = 0x75; /* mixer vth 1.04, vtl 0.84 */
  637. air_cable1_in = 0x00;
  638. cable2_in = 0x00;
  639. pre_dect = 0x40;
  640. lna_discharge = 14;
  641. filter_cur = 0x40; /* 10, low */
  642. break;
  643. case SYS_DVBT2:
  644. mixer_top = 0x24; /* mixer top:13 , top-1, low-discharge */
  645. lna_top = 0xe5; /* detect bw 3, lna top:4, predet top:2 */
  646. lna_vth_l = 0x53; /* lna vth 0.84 , vtl 0.64 */
  647. mixer_vth_l = 0x75; /* mixer vth 1.04, vtl 0.84 */
  648. air_cable1_in = 0x00;
  649. cable2_in = 0x00;
  650. pre_dect = 0x40;
  651. lna_discharge = 14;
  652. cp_cur = 0x38; /* 111, auto */
  653. div_buf_cur = 0x30; /* 11, 150u */
  654. filter_cur = 0x40; /* 10, low */
  655. break;
  656. case SYS_ISDBT:
  657. mixer_top = 0x24; /* mixer top:13 , top-1, low-discharge */
  658. lna_top = 0xe5; /* detect bw 3, lna top:4, predet top:2 */
  659. lna_vth_l = 0x75; /* lna vth 1.04 , vtl 0.84 */
  660. mixer_vth_l = 0x75; /* mixer vth 1.04, vtl 0.84 */
  661. air_cable1_in = 0x00;
  662. cable2_in = 0x00;
  663. pre_dect = 0x40;
  664. lna_discharge = 14;
  665. cp_cur = 0x38; /* 111, auto */
  666. div_buf_cur = 0x30; /* 11, 150u */
  667. filter_cur = 0x40; /* 10, low */
  668. break;
  669. case SYS_DVBC_ANNEX_A:
  670. mixer_top = 0x24; /* mixer top:13 , top-1, low-discharge */
  671. lna_top = 0xe5;
  672. lna_vth_l = 0x62;
  673. mixer_vth_l = 0x75;
  674. air_cable1_in = 0x60;
  675. cable2_in = 0x00;
  676. pre_dect = 0x40;
  677. lna_discharge = 14;
  678. cp_cur = 0x38; /* 111, auto */
  679. div_buf_cur = 0x30; /* 11, 150u */
  680. filter_cur = 0x40; /* 10, low */
  681. break;
  682. default: /* DVB-T 8M */
  683. mixer_top = 0x24; /* mixer top:13 , top-1, low-discharge */
  684. lna_top = 0xe5; /* detect bw 3, lna top:4, predet top:2 */
  685. lna_vth_l = 0x53; /* lna vth 0.84 , vtl 0.64 */
  686. mixer_vth_l = 0x75; /* mixer vth 1.04, vtl 0.84 */
  687. air_cable1_in = 0x00;
  688. cable2_in = 0x00;
  689. pre_dect = 0x40;
  690. lna_discharge = 14;
  691. cp_cur = 0x38; /* 111, auto */
  692. div_buf_cur = 0x30; /* 11, 150u */
  693. filter_cur = 0x40; /* 10, low */
  694. break;
  695. }
  696. if (priv->cfg->use_diplexer &&
  697. ((priv->cfg->rafael_chip == CHIP_R820T) ||
  698. (priv->cfg->rafael_chip == CHIP_R828S) ||
  699. (priv->cfg->rafael_chip == CHIP_R820C))) {
  700. if (freq > DIP_FREQ)
  701. air_cable1_in = 0x00;
  702. else
  703. air_cable1_in = 0x60;
  704. cable2_in = 0x00;
  705. }
  706. if (priv->cfg->use_predetect) {
  707. rc = r820t_write_reg_mask(priv, 0x06, pre_dect, 0x40);
  708. if (rc < 0)
  709. return rc;
  710. }
  711. rc = r820t_write_reg_mask(priv, 0x1d, lna_top, 0xc7);
  712. if (rc < 0)
  713. return rc;
  714. rc = r820t_write_reg_mask(priv, 0x1c, mixer_top, 0xf8);
  715. if (rc < 0)
  716. return rc;
  717. rc = r820t_write_reg(priv, 0x0d, lna_vth_l);
  718. if (rc < 0)
  719. return rc;
  720. rc = r820t_write_reg(priv, 0x0e, mixer_vth_l);
  721. if (rc < 0)
  722. return rc;
  723. /* Air-IN only for Astrometa */
  724. rc = r820t_write_reg_mask(priv, 0x05, air_cable1_in, 0x60);
  725. if (rc < 0)
  726. return rc;
  727. rc = r820t_write_reg_mask(priv, 0x06, cable2_in, 0x08);
  728. if (rc < 0)
  729. return rc;
  730. rc = r820t_write_reg_mask(priv, 0x11, cp_cur, 0x38);
  731. if (rc < 0)
  732. return rc;
  733. rc = r820t_write_reg_mask(priv, 0x17, div_buf_cur, 0x30);
  734. if (rc < 0)
  735. return rc;
  736. rc = r820t_write_reg_mask(priv, 0x0a, filter_cur, 0x60);
  737. if (rc < 0)
  738. return rc;
  739. /*
  740. * Original driver initializes regs 0x05 and 0x06 with the
  741. * same value again on this point. Probably, it is just an
  742. * error there
  743. */
  744. /*
  745. * Set LNA
  746. */
  747. tuner_dbg("adjusting LNA parameters\n");
  748. if (type != V4L2_TUNER_ANALOG_TV) {
  749. /* LNA TOP: lowest */
  750. rc = r820t_write_reg_mask(priv, 0x1d, 0, 0x38);
  751. if (rc < 0)
  752. return rc;
  753. /* 0: normal mode */
  754. rc = r820t_write_reg_mask(priv, 0x1c, 0, 0x04);
  755. if (rc < 0)
  756. return rc;
  757. /* 0: PRE_DECT off */
  758. rc = r820t_write_reg_mask(priv, 0x06, 0, 0x40);
  759. if (rc < 0)
  760. return rc;
  761. /* agc clk 250hz */
  762. rc = r820t_write_reg_mask(priv, 0x1a, 0x30, 0x30);
  763. if (rc < 0)
  764. return rc;
  765. msleep(250);
  766. /* write LNA TOP = 3 */
  767. rc = r820t_write_reg_mask(priv, 0x1d, 0x18, 0x38);
  768. if (rc < 0)
  769. return rc;
  770. /*
  771. * write discharge mode
  772. * FIXME: IMHO, the mask here is wrong, but it matches
  773. * what's there at the original driver
  774. */
  775. rc = r820t_write_reg_mask(priv, 0x1c, mixer_top, 0x04);
  776. if (rc < 0)
  777. return rc;
  778. /* LNA discharge current */
  779. rc = r820t_write_reg_mask(priv, 0x1e, lna_discharge, 0x1f);
  780. if (rc < 0)
  781. return rc;
  782. /* agc clk 60hz */
  783. rc = r820t_write_reg_mask(priv, 0x1a, 0x20, 0x30);
  784. if (rc < 0)
  785. return rc;
  786. } else {
  787. /* PRE_DECT off */
  788. rc = r820t_write_reg_mask(priv, 0x06, 0, 0x40);
  789. if (rc < 0)
  790. return rc;
  791. /* write LNA TOP */
  792. rc = r820t_write_reg_mask(priv, 0x1d, lna_top, 0x38);
  793. if (rc < 0)
  794. return rc;
  795. /*
  796. * write discharge mode
  797. * FIXME: IMHO, the mask here is wrong, but it matches
  798. * what's there at the original driver
  799. */
  800. rc = r820t_write_reg_mask(priv, 0x1c, mixer_top, 0x04);
  801. if (rc < 0)
  802. return rc;
  803. /* LNA discharge current */
  804. rc = r820t_write_reg_mask(priv, 0x1e, lna_discharge, 0x1f);
  805. if (rc < 0)
  806. return rc;
  807. /* agc clk 1Khz, external det1 cap 1u */
  808. rc = r820t_write_reg_mask(priv, 0x1a, 0x00, 0x30);
  809. if (rc < 0)
  810. return rc;
  811. rc = r820t_write_reg_mask(priv, 0x10, 0x00, 0x04);
  812. if (rc < 0)
  813. return rc;
  814. }
  815. return 0;
  816. }
  817. static int r820t_set_tv_standard(struct r820t_priv *priv,
  818. unsigned bw,
  819. enum v4l2_tuner_type type,
  820. v4l2_std_id std, u32 delsys)
  821. {
  822. int rc, i;
  823. u32 if_khz, filt_cal_lo;
  824. u8 data[5], val;
  825. u8 filt_gain, img_r, filt_q, hp_cor, ext_enable, loop_through;
  826. u8 lt_att, flt_ext_widest, polyfil_cur;
  827. bool need_calibration;
  828. tuner_dbg("selecting the delivery system\n");
  829. if (delsys == SYS_ISDBT) {
  830. if_khz = 4063;
  831. filt_cal_lo = 59000;
  832. filt_gain = 0x10; /* +3db, 6mhz on */
  833. img_r = 0x00; /* image negative */
  834. filt_q = 0x10; /* r10[4]:low q(1'b1) */
  835. hp_cor = 0x6a; /* 1.7m disable, +2cap, 1.25mhz */
  836. ext_enable = 0x40; /* r30[6], ext enable; r30[5]:0 ext at lna max */
  837. loop_through = 0x00; /* r5[7], lt on */
  838. lt_att = 0x00; /* r31[7], lt att enable */
  839. flt_ext_widest = 0x80; /* r15[7]: flt_ext_wide on */
  840. polyfil_cur = 0x60; /* r25[6:5]:min */
  841. } else if (delsys == SYS_DVBC_ANNEX_A) {
  842. if_khz = 5070;
  843. filt_cal_lo = 73500;
  844. filt_gain = 0x10; /* +3db, 6mhz on */
  845. img_r = 0x00; /* image negative */
  846. filt_q = 0x10; /* r10[4]:low q(1'b1) */
  847. hp_cor = 0x0b; /* 1.7m disable, +0cap, 1.0mhz */
  848. ext_enable = 0x40; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */
  849. loop_through = 0x00; /* r5[7], lt on */
  850. lt_att = 0x00; /* r31[7], lt att enable */
  851. flt_ext_widest = 0x00; /* r15[7]: flt_ext_wide off */
  852. polyfil_cur = 0x60; /* r25[6:5]:min */
  853. } else if (delsys == SYS_DVBC_ANNEX_C) {
  854. if_khz = 4063;
  855. filt_cal_lo = 55000;
  856. filt_gain = 0x10; /* +3db, 6mhz on */
  857. img_r = 0x00; /* image negative */
  858. filt_q = 0x10; /* r10[4]:low q(1'b1) */
  859. hp_cor = 0x6a; /* 1.7m disable, +0cap, 1.0mhz */
  860. ext_enable = 0x40; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */
  861. loop_through = 0x00; /* r5[7], lt on */
  862. lt_att = 0x00; /* r31[7], lt att enable */
  863. flt_ext_widest = 0x80; /* r15[7]: flt_ext_wide on */
  864. polyfil_cur = 0x60; /* r25[6:5]:min */
  865. } else {
  866. if (bw <= 6) {
  867. if_khz = 3570;
  868. filt_cal_lo = 56000; /* 52000->56000 */
  869. filt_gain = 0x10; /* +3db, 6mhz on */
  870. img_r = 0x00; /* image negative */
  871. filt_q = 0x10; /* r10[4]:low q(1'b1) */
  872. hp_cor = 0x6b; /* 1.7m disable, +2cap, 1.0mhz */
  873. ext_enable = 0x60; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */
  874. loop_through = 0x00; /* r5[7], lt on */
  875. lt_att = 0x00; /* r31[7], lt att enable */
  876. flt_ext_widest = 0x00; /* r15[7]: flt_ext_wide off */
  877. polyfil_cur = 0x60; /* r25[6:5]:min */
  878. } else if (bw == 7) {
  879. #if 0
  880. /*
  881. * There are two 7 MHz tables defined on the original
  882. * driver, but just the second one seems to be visible
  883. * by rtl2832. Keep this one here commented, as it
  884. * might be needed in the future
  885. */
  886. if_khz = 4070;
  887. filt_cal_lo = 60000;
  888. filt_gain = 0x10; /* +3db, 6mhz on */
  889. img_r = 0x00; /* image negative */
  890. filt_q = 0x10; /* r10[4]:low q(1'b1) */
  891. hp_cor = 0x2b; /* 1.7m disable, +1cap, 1.0mhz */
  892. ext_enable = 0x60; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */
  893. loop_through = 0x00; /* r5[7], lt on */
  894. lt_att = 0x00; /* r31[7], lt att enable */
  895. flt_ext_widest = 0x00; /* r15[7]: flt_ext_wide off */
  896. polyfil_cur = 0x60; /* r25[6:5]:min */
  897. #endif
  898. /* 7 MHz, second table */
  899. if_khz = 4570;
  900. filt_cal_lo = 63000;
  901. filt_gain = 0x10; /* +3db, 6mhz on */
  902. img_r = 0x00; /* image negative */
  903. filt_q = 0x10; /* r10[4]:low q(1'b1) */
  904. hp_cor = 0x2a; /* 1.7m disable, +1cap, 1.25mhz */
  905. ext_enable = 0x60; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */
  906. loop_through = 0x00; /* r5[7], lt on */
  907. lt_att = 0x00; /* r31[7], lt att enable */
  908. flt_ext_widest = 0x00; /* r15[7]: flt_ext_wide off */
  909. polyfil_cur = 0x60; /* r25[6:5]:min */
  910. } else {
  911. if_khz = 4570;
  912. filt_cal_lo = 68500;
  913. filt_gain = 0x10; /* +3db, 6mhz on */
  914. img_r = 0x00; /* image negative */
  915. filt_q = 0x10; /* r10[4]:low q(1'b1) */
  916. hp_cor = 0x0b; /* 1.7m disable, +0cap, 1.0mhz */
  917. ext_enable = 0x60; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */
  918. loop_through = 0x00; /* r5[7], lt on */
  919. lt_att = 0x00; /* r31[7], lt att enable */
  920. flt_ext_widest = 0x00; /* r15[7]: flt_ext_wide off */
  921. polyfil_cur = 0x60; /* r25[6:5]:min */
  922. }
  923. }
  924. /* Initialize the shadow registers */
  925. memcpy(priv->regs, r820t_init_array, sizeof(r820t_init_array));
  926. /* Init Flag & Xtal_check Result */
  927. if (priv->imr_done)
  928. val = 1 | priv->xtal_cap_sel << 1;
  929. else
  930. val = 0;
  931. rc = r820t_write_reg_mask(priv, 0x0c, val, 0x0f);
  932. if (rc < 0)
  933. return rc;
  934. /* version */
  935. rc = r820t_write_reg_mask(priv, 0x13, VER_NUM, 0x3f);
  936. if (rc < 0)
  937. return rc;
  938. /* for LT Gain test */
  939. if (type != V4L2_TUNER_ANALOG_TV) {
  940. rc = r820t_write_reg_mask(priv, 0x1d, 0x00, 0x38);
  941. if (rc < 0)
  942. return rc;
  943. usleep_range(1000, 2000);
  944. }
  945. priv->int_freq = if_khz * 1000;
  946. /* Check if standard changed. If so, filter calibration is needed */
  947. if (type != priv->type)
  948. need_calibration = true;
  949. else if ((type == V4L2_TUNER_ANALOG_TV) && (std != priv->std))
  950. need_calibration = true;
  951. else if ((type == V4L2_TUNER_DIGITAL_TV) &&
  952. ((delsys != priv->delsys) || bw != priv->bw))
  953. need_calibration = true;
  954. else
  955. need_calibration = false;
  956. if (need_calibration) {
  957. tuner_dbg("calibrating the tuner\n");
  958. for (i = 0; i < 2; i++) {
  959. /* Set filt_cap */
  960. rc = r820t_write_reg_mask(priv, 0x0b, hp_cor, 0x60);
  961. if (rc < 0)
  962. return rc;
  963. /* set cali clk =on */
  964. rc = r820t_write_reg_mask(priv, 0x0f, 0x04, 0x04);
  965. if (rc < 0)
  966. return rc;
  967. /* X'tal cap 0pF for PLL */
  968. rc = r820t_write_reg_mask(priv, 0x10, 0x00, 0x03);
  969. if (rc < 0)
  970. return rc;
  971. rc = r820t_set_pll(priv, type, filt_cal_lo * 1000);
  972. if (rc < 0 || !priv->has_lock)
  973. return rc;
  974. /* Start Trigger */
  975. rc = r820t_write_reg_mask(priv, 0x0b, 0x10, 0x10);
  976. if (rc < 0)
  977. return rc;
  978. usleep_range(1000, 2000);
  979. /* Stop Trigger */
  980. rc = r820t_write_reg_mask(priv, 0x0b, 0x00, 0x10);
  981. if (rc < 0)
  982. return rc;
  983. /* set cali clk =off */
  984. rc = r820t_write_reg_mask(priv, 0x0f, 0x00, 0x04);
  985. if (rc < 0)
  986. return rc;
  987. /* Check if calibration worked */
  988. rc = r820t_read(priv, 0x00, data, sizeof(data));
  989. if (rc < 0)
  990. return rc;
  991. priv->fil_cal_code = data[4] & 0x0f;
  992. if (priv->fil_cal_code && priv->fil_cal_code != 0x0f)
  993. break;
  994. }
  995. /* narrowest */
  996. if (priv->fil_cal_code == 0x0f)
  997. priv->fil_cal_code = 0;
  998. }
  999. rc = r820t_write_reg_mask(priv, 0x0a,
  1000. filt_q | priv->fil_cal_code, 0x1f);
  1001. if (rc < 0)
  1002. return rc;
  1003. /* Set BW, Filter_gain, & HP corner */
  1004. rc = r820t_write_reg_mask(priv, 0x0b, hp_cor, 0xef);
  1005. if (rc < 0)
  1006. return rc;
  1007. /* Set Img_R */
  1008. rc = r820t_write_reg_mask(priv, 0x07, img_r, 0x80);
  1009. if (rc < 0)
  1010. return rc;
  1011. /* Set filt_3dB, V6MHz */
  1012. rc = r820t_write_reg_mask(priv, 0x06, filt_gain, 0x30);
  1013. if (rc < 0)
  1014. return rc;
  1015. /* channel filter extension */
  1016. rc = r820t_write_reg_mask(priv, 0x1e, ext_enable, 0x60);
  1017. if (rc < 0)
  1018. return rc;
  1019. /* Loop through */
  1020. rc = r820t_write_reg_mask(priv, 0x05, loop_through, 0x80);
  1021. if (rc < 0)
  1022. return rc;
  1023. /* Loop through attenuation */
  1024. rc = r820t_write_reg_mask(priv, 0x1f, lt_att, 0x80);
  1025. if (rc < 0)
  1026. return rc;
  1027. /* filter extension widest */
  1028. rc = r820t_write_reg_mask(priv, 0x0f, flt_ext_widest, 0x80);
  1029. if (rc < 0)
  1030. return rc;
  1031. /* RF poly filter current */
  1032. rc = r820t_write_reg_mask(priv, 0x19, polyfil_cur, 0x60);
  1033. if (rc < 0)
  1034. return rc;
  1035. /* Store current standard. If it changes, re-calibrate the tuner */
  1036. priv->delsys = delsys;
  1037. priv->type = type;
  1038. priv->std = std;
  1039. priv->bw = bw;
  1040. return 0;
  1041. }
  1042. static int r820t_read_gain(struct r820t_priv *priv)
  1043. {
  1044. u8 data[4];
  1045. int rc;
  1046. rc = r820t_read(priv, 0x00, data, sizeof(data));
  1047. if (rc < 0)
  1048. return rc;
  1049. return ((data[3] & 0x08) << 1) + ((data[3] & 0xf0) >> 4);
  1050. }
  1051. #if 0
  1052. /* FIXME: This routine requires more testing */
  1053. /*
  1054. * measured with a Racal 6103E GSM test set at 928 MHz with -60 dBm
  1055. * input power, for raw results see:
  1056. * http://steve-m.de/projects/rtl-sdr/gain_measurement/r820t/
  1057. */
  1058. static const int r820t_lna_gain_steps[] = {
  1059. 0, 9, 13, 40, 38, 13, 31, 22, 26, 31, 26, 14, 19, 5, 35, 13
  1060. };
  1061. static const int r820t_mixer_gain_steps[] = {
  1062. 0, 5, 10, 10, 19, 9, 10, 25, 17, 10, 8, 16, 13, 6, 3, -8
  1063. };
  1064. static int r820t_set_gain_mode(struct r820t_priv *priv,
  1065. bool set_manual_gain,
  1066. int gain)
  1067. {
  1068. int rc;
  1069. if (set_manual_gain) {
  1070. int i, total_gain = 0;
  1071. uint8_t mix_index = 0, lna_index = 0;
  1072. u8 data[4];
  1073. /* LNA auto off */
  1074. rc = r820t_write_reg_mask(priv, 0x05, 0x10, 0x10);
  1075. if (rc < 0)
  1076. return rc;
  1077. /* Mixer auto off */
  1078. rc = r820t_write_reg_mask(priv, 0x07, 0, 0x10);
  1079. if (rc < 0)
  1080. return rc;
  1081. rc = r820t_read(priv, 0x00, data, sizeof(data));
  1082. if (rc < 0)
  1083. return rc;
  1084. /* set fixed VGA gain for now (16.3 dB) */
  1085. rc = r820t_write_reg_mask(priv, 0x0c, 0x08, 0x9f);
  1086. if (rc < 0)
  1087. return rc;
  1088. for (i = 0; i < 15; i++) {
  1089. if (total_gain >= gain)
  1090. break;
  1091. total_gain += r820t_lna_gain_steps[++lna_index];
  1092. if (total_gain >= gain)
  1093. break;
  1094. total_gain += r820t_mixer_gain_steps[++mix_index];
  1095. }
  1096. /* set LNA gain */
  1097. rc = r820t_write_reg_mask(priv, 0x05, lna_index, 0x0f);
  1098. if (rc < 0)
  1099. return rc;
  1100. /* set Mixer gain */
  1101. rc = r820t_write_reg_mask(priv, 0x07, mix_index, 0x0f);
  1102. if (rc < 0)
  1103. return rc;
  1104. } else {
  1105. /* LNA */
  1106. rc = r820t_write_reg_mask(priv, 0x05, 0, 0x10);
  1107. if (rc < 0)
  1108. return rc;
  1109. /* Mixer */
  1110. rc = r820t_write_reg_mask(priv, 0x07, 0x10, 0x10);
  1111. if (rc < 0)
  1112. return rc;
  1113. /* set fixed VGA gain for now (26.5 dB) */
  1114. rc = r820t_write_reg_mask(priv, 0x0c, 0x0b, 0x9f);
  1115. if (rc < 0)
  1116. return rc;
  1117. }
  1118. return 0;
  1119. }
  1120. #endif
  1121. static int generic_set_freq(struct dvb_frontend *fe,
  1122. u32 freq /* in HZ */,
  1123. unsigned bw,
  1124. enum v4l2_tuner_type type,
  1125. v4l2_std_id std, u32 delsys)
  1126. {
  1127. struct r820t_priv *priv = fe->tuner_priv;
  1128. int rc;
  1129. u32 lo_freq;
  1130. tuner_dbg("should set frequency to %d kHz, bw %d MHz\n",
  1131. freq / 1000, bw);
  1132. rc = r820t_set_tv_standard(priv, bw, type, std, delsys);
  1133. if (rc < 0)
  1134. goto err;
  1135. if ((type == V4L2_TUNER_ANALOG_TV) && (std == V4L2_STD_SECAM_LC))
  1136. lo_freq = freq - priv->int_freq;
  1137. else
  1138. lo_freq = freq + priv->int_freq;
  1139. rc = r820t_set_mux(priv, lo_freq);
  1140. if (rc < 0)
  1141. goto err;
  1142. rc = r820t_set_pll(priv, type, lo_freq);
  1143. if (rc < 0 || !priv->has_lock)
  1144. goto err;
  1145. rc = r820t_sysfreq_sel(priv, freq, type, std, delsys);
  1146. if (rc < 0)
  1147. goto err;
  1148. tuner_dbg("%s: PLL locked on frequency %d Hz, gain=%d\n",
  1149. __func__, freq, r820t_read_gain(priv));
  1150. err:
  1151. if (rc < 0)
  1152. tuner_dbg("%s: failed=%d\n", __func__, rc);
  1153. return rc;
  1154. }
  1155. /*
  1156. * r820t standby logic
  1157. */
  1158. static int r820t_standby(struct r820t_priv *priv)
  1159. {
  1160. int rc;
  1161. /* If device was not initialized yet, don't need to standby */
  1162. if (!priv->init_done)
  1163. return 0;
  1164. rc = r820t_write_reg(priv, 0x06, 0xb1);
  1165. if (rc < 0)
  1166. return rc;
  1167. rc = r820t_write_reg(priv, 0x05, 0x03);
  1168. if (rc < 0)
  1169. return rc;
  1170. rc = r820t_write_reg(priv, 0x07, 0x3a);
  1171. if (rc < 0)
  1172. return rc;
  1173. rc = r820t_write_reg(priv, 0x08, 0x40);
  1174. if (rc < 0)
  1175. return rc;
  1176. rc = r820t_write_reg(priv, 0x09, 0xc0);
  1177. if (rc < 0)
  1178. return rc;
  1179. rc = r820t_write_reg(priv, 0x0a, 0x36);
  1180. if (rc < 0)
  1181. return rc;
  1182. rc = r820t_write_reg(priv, 0x0c, 0x35);
  1183. if (rc < 0)
  1184. return rc;
  1185. rc = r820t_write_reg(priv, 0x0f, 0x68);
  1186. if (rc < 0)
  1187. return rc;
  1188. rc = r820t_write_reg(priv, 0x11, 0x03);
  1189. if (rc < 0)
  1190. return rc;
  1191. rc = r820t_write_reg(priv, 0x17, 0xf4);
  1192. if (rc < 0)
  1193. return rc;
  1194. rc = r820t_write_reg(priv, 0x19, 0x0c);
  1195. /* Force initial calibration */
  1196. priv->type = -1;
  1197. return rc;
  1198. }
  1199. /*
  1200. * r820t device init logic
  1201. */
  1202. static int r820t_xtal_check(struct r820t_priv *priv)
  1203. {
  1204. int rc, i;
  1205. u8 data[3], val;
  1206. /* Initialize the shadow registers */
  1207. memcpy(priv->regs, r820t_init_array, sizeof(r820t_init_array));
  1208. /* cap 30pF & Drive Low */
  1209. rc = r820t_write_reg_mask(priv, 0x10, 0x0b, 0x0b);
  1210. if (rc < 0)
  1211. return rc;
  1212. /* set pll autotune = 128kHz */
  1213. rc = r820t_write_reg_mask(priv, 0x1a, 0x00, 0x0c);
  1214. if (rc < 0)
  1215. return rc;
  1216. /* set manual initial reg = 111111; */
  1217. rc = r820t_write_reg_mask(priv, 0x13, 0x7f, 0x7f);
  1218. if (rc < 0)
  1219. return rc;
  1220. /* set auto */
  1221. rc = r820t_write_reg_mask(priv, 0x13, 0x00, 0x40);
  1222. if (rc < 0)
  1223. return rc;
  1224. /* Try several xtal capacitor alternatives */
  1225. for (i = 0; i < ARRAY_SIZE(r820t_xtal_capacitor); i++) {
  1226. rc = r820t_write_reg_mask(priv, 0x10,
  1227. r820t_xtal_capacitor[i][0], 0x1b);
  1228. if (rc < 0)
  1229. return rc;
  1230. usleep_range(5000, 6000);
  1231. rc = r820t_read(priv, 0x00, data, sizeof(data));
  1232. if (rc < 0)
  1233. return rc;
  1234. if (!(data[2] & 0x40))
  1235. continue;
  1236. val = data[2] & 0x3f;
  1237. if (priv->cfg->xtal == 16000000 && (val > 29 || val < 23))
  1238. break;
  1239. if (val != 0x3f)
  1240. break;
  1241. }
  1242. if (i == ARRAY_SIZE(r820t_xtal_capacitor))
  1243. return -EINVAL;
  1244. return r820t_xtal_capacitor[i][1];
  1245. }
  1246. static int r820t_imr_prepare(struct r820t_priv *priv)
  1247. {
  1248. int rc;
  1249. /* Initialize the shadow registers */
  1250. memcpy(priv->regs, r820t_init_array, sizeof(r820t_init_array));
  1251. /* lna off (air-in off) */
  1252. rc = r820t_write_reg_mask(priv, 0x05, 0x20, 0x20);
  1253. if (rc < 0)
  1254. return rc;
  1255. /* mixer gain mode = manual */
  1256. rc = r820t_write_reg_mask(priv, 0x07, 0, 0x10);
  1257. if (rc < 0)
  1258. return rc;
  1259. /* filter corner = lowest */
  1260. rc = r820t_write_reg_mask(priv, 0x0a, 0x0f, 0x0f);
  1261. if (rc < 0)
  1262. return rc;
  1263. /* filter bw=+2cap, hp=5M */
  1264. rc = r820t_write_reg_mask(priv, 0x0b, 0x60, 0x6f);
  1265. if (rc < 0)
  1266. return rc;
  1267. /* adc=on, vga code mode, gain = 26.5dB */
  1268. rc = r820t_write_reg_mask(priv, 0x0c, 0x0b, 0x9f);
  1269. if (rc < 0)
  1270. return rc;
  1271. /* ring clk = on */
  1272. rc = r820t_write_reg_mask(priv, 0x0f, 0, 0x08);
  1273. if (rc < 0)
  1274. return rc;
  1275. /* ring power = on */
  1276. rc = r820t_write_reg_mask(priv, 0x18, 0x10, 0x10);
  1277. if (rc < 0)
  1278. return rc;
  1279. /* from ring = ring pll in */
  1280. rc = r820t_write_reg_mask(priv, 0x1c, 0x02, 0x02);
  1281. if (rc < 0)
  1282. return rc;
  1283. /* sw_pdect = det3 */
  1284. rc = r820t_write_reg_mask(priv, 0x1e, 0x80, 0x80);
  1285. if (rc < 0)
  1286. return rc;
  1287. /* Set filt_3dB */
  1288. rc = r820t_write_reg_mask(priv, 0x06, 0x20, 0x20);
  1289. return rc;
  1290. }
  1291. static int r820t_multi_read(struct r820t_priv *priv)
  1292. {
  1293. int rc, i;
  1294. u16 sum = 0;
  1295. u8 data[2], min = 255, max = 0;
  1296. usleep_range(5000, 6000);
  1297. for (i = 0; i < 6; i++) {
  1298. rc = r820t_read(priv, 0x00, data, sizeof(data));
  1299. if (rc < 0)
  1300. return rc;
  1301. sum += data[1];
  1302. if (data[1] < min)
  1303. min = data[1];
  1304. if (data[1] > max)
  1305. max = data[1];
  1306. }
  1307. rc = sum - max - min;
  1308. return rc;
  1309. }
  1310. static int r820t_imr_cross(struct r820t_priv *priv,
  1311. struct r820t_sect_type iq_point[3],
  1312. u8 *x_direct)
  1313. {
  1314. struct r820t_sect_type cross[5]; /* (0,0)(0,Q-1)(0,I-1)(Q-1,0)(I-1,0) */
  1315. struct r820t_sect_type tmp;
  1316. int i, rc;
  1317. u8 reg08, reg09;
  1318. reg08 = r820t_read_cache_reg(priv, 8) & 0xc0;
  1319. reg09 = r820t_read_cache_reg(priv, 9) & 0xc0;
  1320. tmp.gain_x = 0;
  1321. tmp.phase_y = 0;
  1322. tmp.value = 255;
  1323. for (i = 0; i < 5; i++) {
  1324. switch (i) {
  1325. case 0:
  1326. cross[i].gain_x = reg08;
  1327. cross[i].phase_y = reg09;
  1328. break;
  1329. case 1:
  1330. cross[i].gain_x = reg08; /* 0 */
  1331. cross[i].phase_y = reg09 + 1; /* Q-1 */
  1332. break;
  1333. case 2:
  1334. cross[i].gain_x = reg08; /* 0 */
  1335. cross[i].phase_y = (reg09 | 0x20) + 1; /* I-1 */
  1336. break;
  1337. case 3:
  1338. cross[i].gain_x = reg08 + 1; /* Q-1 */
  1339. cross[i].phase_y = reg09;
  1340. break;
  1341. default:
  1342. cross[i].gain_x = (reg08 | 0x20) + 1; /* I-1 */
  1343. cross[i].phase_y = reg09;
  1344. }
  1345. rc = r820t_write_reg(priv, 0x08, cross[i].gain_x);
  1346. if (rc < 0)
  1347. return rc;
  1348. rc = r820t_write_reg(priv, 0x09, cross[i].phase_y);
  1349. if (rc < 0)
  1350. return rc;
  1351. rc = r820t_multi_read(priv);
  1352. if (rc < 0)
  1353. return rc;
  1354. cross[i].value = rc;
  1355. if (cross[i].value < tmp.value)
  1356. tmp = cross[i];
  1357. }
  1358. if ((tmp.phase_y & 0x1f) == 1) { /* y-direction */
  1359. *x_direct = 0;
  1360. iq_point[0] = cross[0];
  1361. iq_point[1] = cross[1];
  1362. iq_point[2] = cross[2];
  1363. } else { /* (0,0) or x-direction */
  1364. *x_direct = 1;
  1365. iq_point[0] = cross[0];
  1366. iq_point[1] = cross[3];
  1367. iq_point[2] = cross[4];
  1368. }
  1369. return 0;
  1370. }
  1371. static void r820t_compre_cor(struct r820t_sect_type iq[3])
  1372. {
  1373. int i;
  1374. for (i = 3; i > 0; i--) {
  1375. if (iq[0].value > iq[i - 1].value)
  1376. swap(iq[0], iq[i - 1]);
  1377. }
  1378. }
  1379. static int r820t_compre_step(struct r820t_priv *priv,
  1380. struct r820t_sect_type iq[3], u8 reg)
  1381. {
  1382. int rc;
  1383. struct r820t_sect_type tmp;
  1384. /*
  1385. * Purpose: if (Gain<9 or Phase<9), Gain+1 or Phase+1 and compare
  1386. * with min value:
  1387. * new < min => update to min and continue
  1388. * new > min => Exit
  1389. */
  1390. /* min value already saved in iq[0] */
  1391. tmp.phase_y = iq[0].phase_y;
  1392. tmp.gain_x = iq[0].gain_x;
  1393. while (((tmp.gain_x & 0x1f) < IMR_TRIAL) &&
  1394. ((tmp.phase_y & 0x1f) < IMR_TRIAL)) {
  1395. if (reg == 0x08)
  1396. tmp.gain_x++;
  1397. else
  1398. tmp.phase_y++;
  1399. rc = r820t_write_reg(priv, 0x08, tmp.gain_x);
  1400. if (rc < 0)
  1401. return rc;
  1402. rc = r820t_write_reg(priv, 0x09, tmp.phase_y);
  1403. if (rc < 0)
  1404. return rc;
  1405. rc = r820t_multi_read(priv);
  1406. if (rc < 0)
  1407. return rc;
  1408. tmp.value = rc;
  1409. if (tmp.value <= iq[0].value) {
  1410. iq[0].gain_x = tmp.gain_x;
  1411. iq[0].phase_y = tmp.phase_y;
  1412. iq[0].value = tmp.value;
  1413. } else {
  1414. return 0;
  1415. }
  1416. }
  1417. return 0;
  1418. }
  1419. static int r820t_iq_tree(struct r820t_priv *priv,
  1420. struct r820t_sect_type iq[3],
  1421. u8 fix_val, u8 var_val, u8 fix_reg)
  1422. {
  1423. int rc, i;
  1424. u8 tmp, var_reg;
  1425. /*
  1426. * record IMC results by input gain/phase location then adjust
  1427. * gain or phase positive 1 step and negative 1 step,
  1428. * both record results
  1429. */
  1430. if (fix_reg == 0x08)
  1431. var_reg = 0x09;
  1432. else
  1433. var_reg = 0x08;
  1434. for (i = 0; i < 3; i++) {
  1435. rc = r820t_write_reg(priv, fix_reg, fix_val);
  1436. if (rc < 0)
  1437. return rc;
  1438. rc = r820t_write_reg(priv, var_reg, var_val);
  1439. if (rc < 0)
  1440. return rc;
  1441. rc = r820t_multi_read(priv);
  1442. if (rc < 0)
  1443. return rc;
  1444. iq[i].value = rc;
  1445. if (fix_reg == 0x08) {
  1446. iq[i].gain_x = fix_val;
  1447. iq[i].phase_y = var_val;
  1448. } else {
  1449. iq[i].phase_y = fix_val;
  1450. iq[i].gain_x = var_val;
  1451. }
  1452. if (i == 0) { /* try right-side point */
  1453. var_val++;
  1454. } else if (i == 1) { /* try left-side point */
  1455. /* if absolute location is 1, change I/Q direction */
  1456. if ((var_val & 0x1f) < 0x02) {
  1457. tmp = 2 - (var_val & 0x1f);
  1458. /* b[5]:I/Q selection. 0:Q-path, 1:I-path */
  1459. if (var_val & 0x20) {
  1460. var_val &= 0xc0;
  1461. var_val |= tmp;
  1462. } else {
  1463. var_val |= 0x20 | tmp;
  1464. }
  1465. } else {
  1466. var_val -= 2;
  1467. }
  1468. }
  1469. }
  1470. return 0;
  1471. }
  1472. static int r820t_section(struct r820t_priv *priv,
  1473. struct r820t_sect_type *iq_point)
  1474. {
  1475. int rc;
  1476. struct r820t_sect_type compare_iq[3], compare_bet[3];
  1477. /* Try X-1 column and save min result to compare_bet[0] */
  1478. if (!(iq_point->gain_x & 0x1f))
  1479. compare_iq[0].gain_x = ((iq_point->gain_x) & 0xdf) + 1; /* Q-path, Gain=1 */
  1480. else
  1481. compare_iq[0].gain_x = iq_point->gain_x - 1; /* left point */
  1482. compare_iq[0].phase_y = iq_point->phase_y;
  1483. /* y-direction */
  1484. rc = r820t_iq_tree(priv, compare_iq, compare_iq[0].gain_x,
  1485. compare_iq[0].phase_y, 0x08);
  1486. if (rc < 0)
  1487. return rc;
  1488. r820t_compre_cor(compare_iq);
  1489. compare_bet[0] = compare_iq[0];
  1490. /* Try X column and save min result to compare_bet[1] */
  1491. compare_iq[0].gain_x = iq_point->gain_x;
  1492. compare_iq[0].phase_y = iq_point->phase_y;
  1493. rc = r820t_iq_tree(priv, compare_iq, compare_iq[0].gain_x,
  1494. compare_iq[0].phase_y, 0x08);
  1495. if (rc < 0)
  1496. return rc;
  1497. r820t_compre_cor(compare_iq);
  1498. compare_bet[1] = compare_iq[0];
  1499. /* Try X+1 column and save min result to compare_bet[2] */
  1500. if ((iq_point->gain_x & 0x1f) == 0x00)
  1501. compare_iq[0].gain_x = ((iq_point->gain_x) | 0x20) + 1; /* I-path, Gain=1 */
  1502. else
  1503. compare_iq[0].gain_x = iq_point->gain_x + 1;
  1504. compare_iq[0].phase_y = iq_point->phase_y;
  1505. rc = r820t_iq_tree(priv, compare_iq, compare_iq[0].gain_x,
  1506. compare_iq[0].phase_y, 0x08);
  1507. if (rc < 0)
  1508. return rc;
  1509. r820t_compre_cor(compare_iq);
  1510. compare_bet[2] = compare_iq[0];
  1511. r820t_compre_cor(compare_bet);
  1512. *iq_point = compare_bet[0];
  1513. return 0;
  1514. }
  1515. static int r820t_vga_adjust(struct r820t_priv *priv)
  1516. {
  1517. int rc;
  1518. u8 vga_count;
  1519. /* increase vga power to let image significant */
  1520. for (vga_count = 12; vga_count < 16; vga_count++) {
  1521. rc = r820t_write_reg_mask(priv, 0x0c, vga_count, 0x0f);
  1522. if (rc < 0)
  1523. return rc;
  1524. usleep_range(10000, 11000);
  1525. rc = r820t_multi_read(priv);
  1526. if (rc < 0)
  1527. return rc;
  1528. if (rc > 40 * 4)
  1529. break;
  1530. }
  1531. return 0;
  1532. }
  1533. static int r820t_iq(struct r820t_priv *priv, struct r820t_sect_type *iq_pont)
  1534. {
  1535. struct r820t_sect_type compare_iq[3];
  1536. int rc;
  1537. u8 x_direction = 0; /* 1:x, 0:y */
  1538. u8 dir_reg, other_reg;
  1539. r820t_vga_adjust(priv);
  1540. rc = r820t_imr_cross(priv, compare_iq, &x_direction);
  1541. if (rc < 0)
  1542. return rc;
  1543. if (x_direction == 1) {
  1544. dir_reg = 0x08;
  1545. other_reg = 0x09;
  1546. } else {
  1547. dir_reg = 0x09;
  1548. other_reg = 0x08;
  1549. }
  1550. /* compare and find min of 3 points. determine i/q direction */
  1551. r820t_compre_cor(compare_iq);
  1552. /* increase step to find min value of this direction */
  1553. rc = r820t_compre_step(priv, compare_iq, dir_reg);
  1554. if (rc < 0)
  1555. return rc;
  1556. /* the other direction */
  1557. rc = r820t_iq_tree(priv, compare_iq, compare_iq[0].gain_x,
  1558. compare_iq[0].phase_y, dir_reg);
  1559. if (rc < 0)
  1560. return rc;
  1561. /* compare and find min of 3 points. determine i/q direction */
  1562. r820t_compre_cor(compare_iq);
  1563. /* increase step to find min value on this direction */
  1564. rc = r820t_compre_step(priv, compare_iq, other_reg);
  1565. if (rc < 0)
  1566. return rc;
  1567. /* check 3 points again */
  1568. rc = r820t_iq_tree(priv, compare_iq, compare_iq[0].gain_x,
  1569. compare_iq[0].phase_y, other_reg);
  1570. if (rc < 0)
  1571. return rc;
  1572. r820t_compre_cor(compare_iq);
  1573. /* section-9 check */
  1574. rc = r820t_section(priv, compare_iq);
  1575. *iq_pont = compare_iq[0];
  1576. /* reset gain/phase control setting */
  1577. rc = r820t_write_reg_mask(priv, 0x08, 0, 0x3f);
  1578. if (rc < 0)
  1579. return rc;
  1580. rc = r820t_write_reg_mask(priv, 0x09, 0, 0x3f);
  1581. return rc;
  1582. }
  1583. static int r820t_f_imr(struct r820t_priv *priv, struct r820t_sect_type *iq_pont)
  1584. {
  1585. int rc;
  1586. r820t_vga_adjust(priv);
  1587. /*
  1588. * search surrounding points from previous point
  1589. * try (x-1), (x), (x+1) columns, and find min IMR result point
  1590. */
  1591. rc = r820t_section(priv, iq_pont);
  1592. if (rc < 0)
  1593. return rc;
  1594. return 0;
  1595. }
  1596. static int r820t_imr(struct r820t_priv *priv, unsigned imr_mem, bool im_flag)
  1597. {
  1598. struct r820t_sect_type imr_point;
  1599. int rc;
  1600. u32 ring_vco, ring_freq, ring_ref;
  1601. u8 n_ring, n;
  1602. int reg18, reg19, reg1f;
  1603. if (priv->cfg->xtal > 24000000)
  1604. ring_ref = priv->cfg->xtal / 2000;
  1605. else
  1606. ring_ref = priv->cfg->xtal / 1000;
  1607. n_ring = 15;
  1608. for (n = 0; n < 16; n++) {
  1609. if ((16 + n) * 8 * ring_ref >= 3100000) {
  1610. n_ring = n;
  1611. break;
  1612. }
  1613. }
  1614. reg18 = r820t_read_cache_reg(priv, 0x18);
  1615. reg19 = r820t_read_cache_reg(priv, 0x19);
  1616. reg1f = r820t_read_cache_reg(priv, 0x1f);
  1617. reg18 &= 0xf0; /* set ring[3:0] */
  1618. reg18 |= n_ring;
  1619. ring_vco = (16 + n_ring) * 8 * ring_ref;
  1620. reg18 &= 0xdf; /* clear ring_se23 */
  1621. reg19 &= 0xfc; /* clear ring_seldiv */
  1622. reg1f &= 0xfc; /* clear ring_att */
  1623. switch (imr_mem) {
  1624. case 0:
  1625. ring_freq = ring_vco / 48;
  1626. reg18 |= 0x20; /* ring_se23 = 1 */
  1627. reg19 |= 0x03; /* ring_seldiv = 3 */
  1628. reg1f |= 0x02; /* ring_att 10 */
  1629. break;
  1630. case 1:
  1631. ring_freq = ring_vco / 16;
  1632. reg18 |= 0x00; /* ring_se23 = 0 */
  1633. reg19 |= 0x02; /* ring_seldiv = 2 */
  1634. reg1f |= 0x00; /* pw_ring 00 */
  1635. break;
  1636. case 2:
  1637. ring_freq = ring_vco / 8;
  1638. reg18 |= 0x00; /* ring_se23 = 0 */
  1639. reg19 |= 0x01; /* ring_seldiv = 1 */
  1640. reg1f |= 0x03; /* pw_ring 11 */
  1641. break;
  1642. case 3:
  1643. ring_freq = ring_vco / 6;
  1644. reg18 |= 0x20; /* ring_se23 = 1 */
  1645. reg19 |= 0x00; /* ring_seldiv = 0 */
  1646. reg1f |= 0x03; /* pw_ring 11 */
  1647. break;
  1648. case 4:
  1649. ring_freq = ring_vco / 4;
  1650. reg18 |= 0x00; /* ring_se23 = 0 */
  1651. reg19 |= 0x00; /* ring_seldiv = 0 */
  1652. reg1f |= 0x01; /* pw_ring 01 */
  1653. break;
  1654. default:
  1655. ring_freq = ring_vco / 4;
  1656. reg18 |= 0x00; /* ring_se23 = 0 */
  1657. reg19 |= 0x00; /* ring_seldiv = 0 */
  1658. reg1f |= 0x01; /* pw_ring 01 */
  1659. break;
  1660. }
  1661. /* write pw_ring, n_ring, ringdiv2 registers */
  1662. /* n_ring, ring_se23 */
  1663. rc = r820t_write_reg(priv, 0x18, reg18);
  1664. if (rc < 0)
  1665. return rc;
  1666. /* ring_sediv */
  1667. rc = r820t_write_reg(priv, 0x19, reg19);
  1668. if (rc < 0)
  1669. return rc;
  1670. /* pw_ring */
  1671. rc = r820t_write_reg(priv, 0x1f, reg1f);
  1672. if (rc < 0)
  1673. return rc;
  1674. /* mux input freq ~ rf_in freq */
  1675. rc = r820t_set_mux(priv, (ring_freq - 5300) * 1000);
  1676. if (rc < 0)
  1677. return rc;
  1678. rc = r820t_set_pll(priv, V4L2_TUNER_DIGITAL_TV,
  1679. (ring_freq - 5300) * 1000);
  1680. if (!priv->has_lock)
  1681. rc = -EINVAL;
  1682. if (rc < 0)
  1683. return rc;
  1684. if (im_flag) {
  1685. rc = r820t_iq(priv, &imr_point);
  1686. } else {
  1687. imr_point.gain_x = priv->imr_data[3].gain_x;
  1688. imr_point.phase_y = priv->imr_data[3].phase_y;
  1689. imr_point.value = priv->imr_data[3].value;
  1690. rc = r820t_f_imr(priv, &imr_point);
  1691. }
  1692. if (rc < 0)
  1693. return rc;
  1694. /* save IMR value */
  1695. switch (imr_mem) {
  1696. case 0:
  1697. priv->imr_data[0].gain_x = imr_point.gain_x;
  1698. priv->imr_data[0].phase_y = imr_point.phase_y;
  1699. priv->imr_data[0].value = imr_point.value;
  1700. break;
  1701. case 1:
  1702. priv->imr_data[1].gain_x = imr_point.gain_x;
  1703. priv->imr_data[1].phase_y = imr_point.phase_y;
  1704. priv->imr_data[1].value = imr_point.value;
  1705. break;
  1706. case 2:
  1707. priv->imr_data[2].gain_x = imr_point.gain_x;
  1708. priv->imr_data[2].phase_y = imr_point.phase_y;
  1709. priv->imr_data[2].value = imr_point.value;
  1710. break;
  1711. case 3:
  1712. priv->imr_data[3].gain_x = imr_point.gain_x;
  1713. priv->imr_data[3].phase_y = imr_point.phase_y;
  1714. priv->imr_data[3].value = imr_point.value;
  1715. break;
  1716. case 4:
  1717. priv->imr_data[4].gain_x = imr_point.gain_x;
  1718. priv->imr_data[4].phase_y = imr_point.phase_y;
  1719. priv->imr_data[4].value = imr_point.value;
  1720. break;
  1721. default:
  1722. priv->imr_data[4].gain_x = imr_point.gain_x;
  1723. priv->imr_data[4].phase_y = imr_point.phase_y;
  1724. priv->imr_data[4].value = imr_point.value;
  1725. break;
  1726. }
  1727. return 0;
  1728. }
  1729. static int r820t_imr_callibrate(struct r820t_priv *priv)
  1730. {
  1731. int rc, i;
  1732. int xtal_cap = 0;
  1733. if (priv->init_done)
  1734. return 0;
  1735. /* Detect Xtal capacitance */
  1736. if ((priv->cfg->rafael_chip == CHIP_R820T) ||
  1737. (priv->cfg->rafael_chip == CHIP_R828S) ||
  1738. (priv->cfg->rafael_chip == CHIP_R820C)) {
  1739. priv->xtal_cap_sel = XTAL_HIGH_CAP_0P;
  1740. } else {
  1741. /* Initialize registers */
  1742. rc = r820t_write(priv, 0x05,
  1743. r820t_init_array, sizeof(r820t_init_array));
  1744. if (rc < 0)
  1745. return rc;
  1746. for (i = 0; i < 3; i++) {
  1747. rc = r820t_xtal_check(priv);
  1748. if (rc < 0)
  1749. return rc;
  1750. if (!i || rc > xtal_cap)
  1751. xtal_cap = rc;
  1752. }
  1753. priv->xtal_cap_sel = xtal_cap;
  1754. }
  1755. /*
  1756. * Disables IMR calibration. That emulates the same behaviour
  1757. * as what is done by rtl-sdr userspace library. Useful for testing
  1758. */
  1759. if (no_imr_cal) {
  1760. priv->init_done = true;
  1761. return 0;
  1762. }
  1763. /* Initialize registers */
  1764. rc = r820t_write(priv, 0x05,
  1765. r820t_init_array, sizeof(r820t_init_array));
  1766. if (rc < 0)
  1767. return rc;
  1768. rc = r820t_imr_prepare(priv);
  1769. if (rc < 0)
  1770. return rc;
  1771. rc = r820t_imr(priv, 3, true);
  1772. if (rc < 0)
  1773. return rc;
  1774. rc = r820t_imr(priv, 1, false);
  1775. if (rc < 0)
  1776. return rc;
  1777. rc = r820t_imr(priv, 0, false);
  1778. if (rc < 0)
  1779. return rc;
  1780. rc = r820t_imr(priv, 2, false);
  1781. if (rc < 0)
  1782. return rc;
  1783. rc = r820t_imr(priv, 4, false);
  1784. if (rc < 0)
  1785. return rc;
  1786. priv->init_done = true;
  1787. priv->imr_done = true;
  1788. return 0;
  1789. }
  1790. #if 0
  1791. /* Not used, for now */
  1792. static int r820t_gpio(struct r820t_priv *priv, bool enable)
  1793. {
  1794. return r820t_write_reg_mask(priv, 0x0f, enable ? 1 : 0, 0x01);
  1795. }
  1796. #endif
  1797. /*
  1798. * r820t frontend operations and tuner attach code
  1799. *
  1800. * All driver locks and i2c control are only in this part of the code
  1801. */
  1802. static int r820t_init(struct dvb_frontend *fe)
  1803. {
  1804. struct r820t_priv *priv = fe->tuner_priv;
  1805. int rc;
  1806. tuner_dbg("%s:\n", __func__);
  1807. mutex_lock(&priv->lock);
  1808. if (fe->ops.i2c_gate_ctrl)
  1809. fe->ops.i2c_gate_ctrl(fe, 1);
  1810. rc = r820t_imr_callibrate(priv);
  1811. if (rc < 0)
  1812. goto err;
  1813. /* Initialize registers */
  1814. rc = r820t_write(priv, 0x05,
  1815. r820t_init_array, sizeof(r820t_init_array));
  1816. err:
  1817. if (fe->ops.i2c_gate_ctrl)
  1818. fe->ops.i2c_gate_ctrl(fe, 0);
  1819. mutex_unlock(&priv->lock);
  1820. if (rc < 0)
  1821. tuner_dbg("%s: failed=%d\n", __func__, rc);
  1822. return rc;
  1823. }
  1824. static int r820t_sleep(struct dvb_frontend *fe)
  1825. {
  1826. struct r820t_priv *priv = fe->tuner_priv;
  1827. int rc;
  1828. tuner_dbg("%s:\n", __func__);
  1829. mutex_lock(&priv->lock);
  1830. if (fe->ops.i2c_gate_ctrl)
  1831. fe->ops.i2c_gate_ctrl(fe, 1);
  1832. rc = r820t_standby(priv);
  1833. if (fe->ops.i2c_gate_ctrl)
  1834. fe->ops.i2c_gate_ctrl(fe, 0);
  1835. mutex_unlock(&priv->lock);
  1836. tuner_dbg("%s: failed=%d\n", __func__, rc);
  1837. return rc;
  1838. }
  1839. static int r820t_set_analog_freq(struct dvb_frontend *fe,
  1840. struct analog_parameters *p)
  1841. {
  1842. struct r820t_priv *priv = fe->tuner_priv;
  1843. unsigned bw;
  1844. int rc;
  1845. tuner_dbg("%s called\n", __func__);
  1846. /* if std is not defined, choose one */
  1847. if (!p->std)
  1848. p->std = V4L2_STD_MN;
  1849. if ((p->std == V4L2_STD_PAL_M) || (p->std == V4L2_STD_NTSC))
  1850. bw = 6;
  1851. else
  1852. bw = 8;
  1853. mutex_lock(&priv->lock);
  1854. if (fe->ops.i2c_gate_ctrl)
  1855. fe->ops.i2c_gate_ctrl(fe, 1);
  1856. rc = generic_set_freq(fe, 62500l * p->frequency, bw,
  1857. V4L2_TUNER_ANALOG_TV, p->std, SYS_UNDEFINED);
  1858. if (fe->ops.i2c_gate_ctrl)
  1859. fe->ops.i2c_gate_ctrl(fe, 0);
  1860. mutex_unlock(&priv->lock);
  1861. return rc;
  1862. }
  1863. static int r820t_set_params(struct dvb_frontend *fe)
  1864. {
  1865. struct r820t_priv *priv = fe->tuner_priv;
  1866. struct dtv_frontend_properties *c = &fe->dtv_property_cache;
  1867. int rc;
  1868. unsigned bw;
  1869. tuner_dbg("%s: delivery_system=%d frequency=%d bandwidth_hz=%d\n",
  1870. __func__, c->delivery_system, c->frequency, c->bandwidth_hz);
  1871. mutex_lock(&priv->lock);
  1872. if (fe->ops.i2c_gate_ctrl)
  1873. fe->ops.i2c_gate_ctrl(fe, 1);
  1874. bw = (c->bandwidth_hz + 500000) / 1000000;
  1875. if (!bw)
  1876. bw = 8;
  1877. rc = generic_set_freq(fe, c->frequency, bw,
  1878. V4L2_TUNER_DIGITAL_TV, 0, c->delivery_system);
  1879. if (fe->ops.i2c_gate_ctrl)
  1880. fe->ops.i2c_gate_ctrl(fe, 0);
  1881. mutex_unlock(&priv->lock);
  1882. if (rc)
  1883. tuner_dbg("%s: failed=%d\n", __func__, rc);
  1884. return rc;
  1885. }
  1886. static int r820t_signal(struct dvb_frontend *fe, u16 *strength)
  1887. {
  1888. struct r820t_priv *priv = fe->tuner_priv;
  1889. int rc = 0;
  1890. mutex_lock(&priv->lock);
  1891. if (fe->ops.i2c_gate_ctrl)
  1892. fe->ops.i2c_gate_ctrl(fe, 1);
  1893. if (priv->has_lock) {
  1894. rc = r820t_read_gain(priv);
  1895. if (rc < 0)
  1896. goto err;
  1897. /* A higher gain at LNA means a lower signal strength */
  1898. *strength = (45 - rc) << 4 | 0xff;
  1899. if (*strength == 0xff)
  1900. *strength = 0;
  1901. } else {
  1902. *strength = 0;
  1903. }
  1904. err:
  1905. if (fe->ops.i2c_gate_ctrl)
  1906. fe->ops.i2c_gate_ctrl(fe, 0);
  1907. mutex_unlock(&priv->lock);
  1908. tuner_dbg("%s: %s, gain=%d strength=%d\n",
  1909. __func__,
  1910. priv->has_lock ? "PLL locked" : "no signal",
  1911. rc, *strength);
  1912. return 0;
  1913. }
  1914. static int r820t_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
  1915. {
  1916. struct r820t_priv *priv = fe->tuner_priv;
  1917. tuner_dbg("%s:\n", __func__);
  1918. *frequency = priv->int_freq;
  1919. return 0;
  1920. }
  1921. static void r820t_release(struct dvb_frontend *fe)
  1922. {
  1923. struct r820t_priv *priv = fe->tuner_priv;
  1924. tuner_dbg("%s:\n", __func__);
  1925. mutex_lock(&r820t_list_mutex);
  1926. if (priv)
  1927. hybrid_tuner_release_state(priv);
  1928. mutex_unlock(&r820t_list_mutex);
  1929. fe->tuner_priv = NULL;
  1930. }
  1931. static const struct dvb_tuner_ops r820t_tuner_ops = {
  1932. .info = {
  1933. .name = "Rafael Micro R820T",
  1934. .frequency_min_hz = 42 * MHz,
  1935. .frequency_max_hz = 1002 * MHz,
  1936. },
  1937. .init = r820t_init,
  1938. .release = r820t_release,
  1939. .sleep = r820t_sleep,
  1940. .set_params = r820t_set_params,
  1941. .set_analog_params = r820t_set_analog_freq,
  1942. .get_if_frequency = r820t_get_if_frequency,
  1943. .get_rf_strength = r820t_signal,
  1944. };
  1945. struct dvb_frontend *r820t_attach(struct dvb_frontend *fe,
  1946. struct i2c_adapter *i2c,
  1947. const struct r820t_config *cfg)
  1948. {
  1949. struct r820t_priv *priv;
  1950. int rc = -ENODEV;
  1951. u8 data[5];
  1952. int instance;
  1953. mutex_lock(&r820t_list_mutex);
  1954. instance = hybrid_tuner_request_state(struct r820t_priv, priv,
  1955. hybrid_tuner_instance_list,
  1956. i2c, cfg->i2c_addr,
  1957. "r820t");
  1958. switch (instance) {
  1959. case 0:
  1960. /* memory allocation failure */
  1961. goto err_no_gate;
  1962. case 1:
  1963. /* new tuner instance */
  1964. priv->cfg = cfg;
  1965. mutex_init(&priv->lock);
  1966. fe->tuner_priv = priv;
  1967. break;
  1968. case 2:
  1969. /* existing tuner instance */
  1970. fe->tuner_priv = priv;
  1971. break;
  1972. }
  1973. if (fe->ops.i2c_gate_ctrl)
  1974. fe->ops.i2c_gate_ctrl(fe, 1);
  1975. /* check if the tuner is there */
  1976. rc = r820t_read(priv, 0x00, data, sizeof(data));
  1977. if (rc < 0)
  1978. goto err;
  1979. rc = r820t_sleep(fe);
  1980. if (rc < 0)
  1981. goto err;
  1982. tuner_info("Rafael Micro r820t successfully identified\n");
  1983. if (fe->ops.i2c_gate_ctrl)
  1984. fe->ops.i2c_gate_ctrl(fe, 0);
  1985. mutex_unlock(&r820t_list_mutex);
  1986. memcpy(&fe->ops.tuner_ops, &r820t_tuner_ops,
  1987. sizeof(struct dvb_tuner_ops));
  1988. return fe;
  1989. err:
  1990. if (fe->ops.i2c_gate_ctrl)
  1991. fe->ops.i2c_gate_ctrl(fe, 0);
  1992. err_no_gate:
  1993. mutex_unlock(&r820t_list_mutex);
  1994. pr_info("%s: failed=%d\n", __func__, rc);
  1995. r820t_release(fe);
  1996. return NULL;
  1997. }
  1998. EXPORT_SYMBOL_GPL(r820t_attach);
  1999. MODULE_DESCRIPTION("Rafael Micro r820t silicon tuner driver");
  2000. MODULE_AUTHOR("Mauro Carvalho Chehab");
  2001. MODULE_LICENSE("GPL v2");