qm1d1c0042.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Sharp QM1D1C0042 8PSK tuner driver
  4. *
  5. * Copyright (C) 2014 Akihiro Tsukada <tskd08@gmail.com>
  6. */
  7. /*
  8. * NOTICE:
  9. * As the disclosed information on the chip is very limited,
  10. * this driver lacks some features, including chip config like IF freq.
  11. * It assumes that users of this driver (such as a PCI bridge of
  12. * DTV receiver cards) know the relevant info and
  13. * configure the chip via I2C if necessary.
  14. *
  15. * Currently, PT3 driver is the only one that uses this driver,
  16. * and contains init/config code in its firmware.
  17. * Thus some part of the code might be dependent on PT3 specific config.
  18. */
  19. #include <linux/kernel.h>
  20. #include <linux/math64.h>
  21. #include "qm1d1c0042.h"
  22. #define QM1D1C0042_NUM_REGS 0x20
  23. #define QM1D1C0042_NUM_REG_ROWS 2
  24. static const u8
  25. reg_initval[QM1D1C0042_NUM_REG_ROWS][QM1D1C0042_NUM_REGS] = { {
  26. 0x48, 0x1c, 0xa0, 0x10, 0xbc, 0xc5, 0x20, 0x33,
  27. 0x06, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00,
  28. 0x00, 0xff, 0xf3, 0x00, 0x2a, 0x64, 0xa6, 0x86,
  29. 0x8c, 0xcf, 0xb8, 0xf1, 0xa8, 0xf2, 0x89, 0x00
  30. }, {
  31. 0x68, 0x1c, 0xc0, 0x10, 0xbc, 0xc1, 0x11, 0x33,
  32. 0x03, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00,
  33. 0x00, 0xff, 0xf3, 0x00, 0x3f, 0x25, 0x5c, 0xd6,
  34. 0x55, 0xcf, 0x95, 0xf6, 0x36, 0xf2, 0x09, 0x00
  35. }
  36. };
  37. static int reg_index;
  38. static const struct qm1d1c0042_config default_cfg = {
  39. .xtal_freq = 16000,
  40. .lpf = 1,
  41. .fast_srch = 0,
  42. .lpf_wait = 20,
  43. .fast_srch_wait = 4,
  44. .normal_srch_wait = 15,
  45. };
  46. struct qm1d1c0042_state {
  47. struct qm1d1c0042_config cfg;
  48. struct i2c_client *i2c;
  49. u8 regs[QM1D1C0042_NUM_REGS];
  50. };
  51. static struct qm1d1c0042_state *cfg_to_state(struct qm1d1c0042_config *c)
  52. {
  53. return container_of(c, struct qm1d1c0042_state, cfg);
  54. }
  55. static int reg_write(struct qm1d1c0042_state *state, u8 reg, u8 val)
  56. {
  57. u8 wbuf[2] = { reg, val };
  58. int ret;
  59. ret = i2c_master_send(state->i2c, wbuf, sizeof(wbuf));
  60. if (ret >= 0 && ret < sizeof(wbuf))
  61. ret = -EIO;
  62. return (ret == sizeof(wbuf)) ? 0 : ret;
  63. }
  64. static int reg_read(struct qm1d1c0042_state *state, u8 reg, u8 *val)
  65. {
  66. struct i2c_msg msgs[2] = {
  67. {
  68. .addr = state->i2c->addr,
  69. .flags = 0,
  70. .buf = &reg,
  71. .len = 1,
  72. },
  73. {
  74. .addr = state->i2c->addr,
  75. .flags = I2C_M_RD,
  76. .buf = val,
  77. .len = 1,
  78. },
  79. };
  80. int ret;
  81. ret = i2c_transfer(state->i2c->adapter, msgs, ARRAY_SIZE(msgs));
  82. if (ret >= 0 && ret < ARRAY_SIZE(msgs))
  83. ret = -EIO;
  84. return (ret == ARRAY_SIZE(msgs)) ? 0 : ret;
  85. }
  86. static int qm1d1c0042_set_srch_mode(struct qm1d1c0042_state *state, bool fast)
  87. {
  88. if (fast)
  89. state->regs[0x03] |= 0x01; /* set fast search mode */
  90. else
  91. state->regs[0x03] &= ~0x01 & 0xff;
  92. return reg_write(state, 0x03, state->regs[0x03]);
  93. }
  94. static int qm1d1c0042_wakeup(struct qm1d1c0042_state *state)
  95. {
  96. int ret;
  97. state->regs[0x01] |= 1 << 3; /* BB_Reg_enable */
  98. state->regs[0x01] &= (~(1 << 0)) & 0xff; /* NORMAL (wake-up) */
  99. state->regs[0x05] &= (~(1 << 3)) & 0xff; /* pfd_rst NORMAL */
  100. ret = reg_write(state, 0x01, state->regs[0x01]);
  101. if (ret == 0)
  102. ret = reg_write(state, 0x05, state->regs[0x05]);
  103. if (ret < 0)
  104. dev_warn(&state->i2c->dev, "(%s) failed. [adap%d-fe%d]\n",
  105. __func__, state->cfg.fe->dvb->num, state->cfg.fe->id);
  106. return ret;
  107. }
  108. /* tuner_ops */
  109. static int qm1d1c0042_set_config(struct dvb_frontend *fe, void *priv_cfg)
  110. {
  111. struct qm1d1c0042_state *state;
  112. struct qm1d1c0042_config *cfg;
  113. state = fe->tuner_priv;
  114. cfg = priv_cfg;
  115. if (cfg->fe)
  116. state->cfg.fe = cfg->fe;
  117. if (cfg->xtal_freq != QM1D1C0042_CFG_XTAL_DFLT)
  118. dev_warn(&state->i2c->dev,
  119. "(%s) changing xtal_freq not supported. ", __func__);
  120. state->cfg.xtal_freq = default_cfg.xtal_freq;
  121. state->cfg.lpf = cfg->lpf;
  122. state->cfg.fast_srch = cfg->fast_srch;
  123. if (cfg->lpf_wait != QM1D1C0042_CFG_WAIT_DFLT)
  124. state->cfg.lpf_wait = cfg->lpf_wait;
  125. else
  126. state->cfg.lpf_wait = default_cfg.lpf_wait;
  127. if (cfg->fast_srch_wait != QM1D1C0042_CFG_WAIT_DFLT)
  128. state->cfg.fast_srch_wait = cfg->fast_srch_wait;
  129. else
  130. state->cfg.fast_srch_wait = default_cfg.fast_srch_wait;
  131. if (cfg->normal_srch_wait != QM1D1C0042_CFG_WAIT_DFLT)
  132. state->cfg.normal_srch_wait = cfg->normal_srch_wait;
  133. else
  134. state->cfg.normal_srch_wait = default_cfg.normal_srch_wait;
  135. return 0;
  136. }
  137. /* divisor, vco_band parameters */
  138. /* {maxfreq, param1(band?), param2(div?) */
  139. static const u32 conv_table[9][3] = {
  140. { 2151000, 1, 7 },
  141. { 1950000, 1, 6 },
  142. { 1800000, 1, 5 },
  143. { 1600000, 1, 4 },
  144. { 1450000, 1, 3 },
  145. { 1250000, 1, 2 },
  146. { 1200000, 0, 7 },
  147. { 975000, 0, 6 },
  148. { 950000, 0, 0 }
  149. };
  150. static int qm1d1c0042_set_params(struct dvb_frontend *fe)
  151. {
  152. struct qm1d1c0042_state *state;
  153. u32 freq;
  154. int i, ret;
  155. u8 val, mask;
  156. u32 a, sd;
  157. s32 b;
  158. state = fe->tuner_priv;
  159. freq = fe->dtv_property_cache.frequency;
  160. state->regs[0x08] &= 0xf0;
  161. state->regs[0x08] |= 0x09;
  162. state->regs[0x13] &= 0x9f;
  163. state->regs[0x13] |= 0x20;
  164. /* div2/vco_band */
  165. val = state->regs[0x02] & 0x0f;
  166. for (i = 0; i < 8; i++)
  167. if (freq < conv_table[i][0] && freq >= conv_table[i + 1][0]) {
  168. val |= conv_table[i][1] << 7;
  169. val |= conv_table[i][2] << 4;
  170. break;
  171. }
  172. ret = reg_write(state, 0x02, val);
  173. if (ret < 0)
  174. return ret;
  175. a = DIV_ROUND_CLOSEST(freq, state->cfg.xtal_freq);
  176. state->regs[0x06] &= 0x40;
  177. state->regs[0x06] |= (a - 12) / 4;
  178. ret = reg_write(state, 0x06, state->regs[0x06]);
  179. if (ret < 0)
  180. return ret;
  181. state->regs[0x07] &= 0xf0;
  182. state->regs[0x07] |= (a - 4 * ((a - 12) / 4 + 1) - 5) & 0x0f;
  183. ret = reg_write(state, 0x07, state->regs[0x07]);
  184. if (ret < 0)
  185. return ret;
  186. /* LPF */
  187. val = state->regs[0x08];
  188. if (state->cfg.lpf) {
  189. /* LPF_CLK, LPF_FC */
  190. val &= 0xf0;
  191. val |= 0x02;
  192. }
  193. ret = reg_write(state, 0x08, val);
  194. if (ret < 0)
  195. return ret;
  196. /*
  197. * b = (freq / state->cfg.xtal_freq - a) << 20;
  198. * sd = b (b >= 0)
  199. * 1<<22 + b (b < 0)
  200. */
  201. b = (s32)div64_s64(((s64) freq) << 20, state->cfg.xtal_freq)
  202. - (((s64) a) << 20);
  203. if (b >= 0)
  204. sd = b;
  205. else
  206. sd = (1 << 22) + b;
  207. state->regs[0x09] &= 0xc0;
  208. state->regs[0x09] |= (sd >> 16) & 0x3f;
  209. state->regs[0x0a] = (sd >> 8) & 0xff;
  210. state->regs[0x0b] = sd & 0xff;
  211. ret = reg_write(state, 0x09, state->regs[0x09]);
  212. if (ret == 0)
  213. ret = reg_write(state, 0x0a, state->regs[0x0a]);
  214. if (ret == 0)
  215. ret = reg_write(state, 0x0b, state->regs[0x0b]);
  216. if (ret != 0)
  217. return ret;
  218. if (!state->cfg.lpf) {
  219. /* CSEL_Offset */
  220. ret = reg_write(state, 0x13, state->regs[0x13]);
  221. if (ret < 0)
  222. return ret;
  223. }
  224. /* VCO_TM, LPF_TM */
  225. mask = state->cfg.lpf ? 0x3f : 0x7f;
  226. val = state->regs[0x0c] & mask;
  227. ret = reg_write(state, 0x0c, val);
  228. if (ret < 0)
  229. return ret;
  230. usleep_range(2000, 3000);
  231. val = state->regs[0x0c] | ~mask;
  232. ret = reg_write(state, 0x0c, val);
  233. if (ret < 0)
  234. return ret;
  235. if (state->cfg.lpf)
  236. msleep(state->cfg.lpf_wait);
  237. else if (state->regs[0x03] & 0x01)
  238. msleep(state->cfg.fast_srch_wait);
  239. else
  240. msleep(state->cfg.normal_srch_wait);
  241. if (state->cfg.lpf) {
  242. /* LPF_FC */
  243. ret = reg_write(state, 0x08, 0x09);
  244. if (ret < 0)
  245. return ret;
  246. /* CSEL_Offset */
  247. ret = reg_write(state, 0x13, state->regs[0x13]);
  248. if (ret < 0)
  249. return ret;
  250. }
  251. return 0;
  252. }
  253. static int qm1d1c0042_sleep(struct dvb_frontend *fe)
  254. {
  255. struct qm1d1c0042_state *state;
  256. int ret;
  257. state = fe->tuner_priv;
  258. state->regs[0x01] &= (~(1 << 3)) & 0xff; /* BB_Reg_disable */
  259. state->regs[0x01] |= 1 << 0; /* STDBY */
  260. state->regs[0x05] |= 1 << 3; /* pfd_rst STANDBY */
  261. ret = reg_write(state, 0x05, state->regs[0x05]);
  262. if (ret == 0)
  263. ret = reg_write(state, 0x01, state->regs[0x01]);
  264. if (ret < 0)
  265. dev_warn(&state->i2c->dev, "(%s) failed. [adap%d-fe%d]\n",
  266. __func__, fe->dvb->num, fe->id);
  267. return ret;
  268. }
  269. static int qm1d1c0042_init(struct dvb_frontend *fe)
  270. {
  271. struct qm1d1c0042_state *state;
  272. u8 val;
  273. int i, ret;
  274. state = fe->tuner_priv;
  275. reg_write(state, 0x01, 0x0c);
  276. reg_write(state, 0x01, 0x0c);
  277. ret = reg_write(state, 0x01, 0x0c); /* soft reset on */
  278. if (ret < 0)
  279. goto failed;
  280. usleep_range(2000, 3000);
  281. ret = reg_write(state, 0x01, 0x1c); /* soft reset off */
  282. if (ret < 0)
  283. goto failed;
  284. /* check ID and choose initial registers corresponding ID */
  285. ret = reg_read(state, 0x00, &val);
  286. if (ret < 0)
  287. goto failed;
  288. for (reg_index = 0; reg_index < QM1D1C0042_NUM_REG_ROWS;
  289. reg_index++) {
  290. if (val == reg_initval[reg_index][0x00])
  291. break;
  292. }
  293. if (reg_index >= QM1D1C0042_NUM_REG_ROWS) {
  294. ret = -EINVAL;
  295. goto failed;
  296. }
  297. memcpy(state->regs, reg_initval[reg_index], QM1D1C0042_NUM_REGS);
  298. usleep_range(2000, 3000);
  299. state->regs[0x0c] |= 0x40;
  300. ret = reg_write(state, 0x0c, state->regs[0x0c]);
  301. if (ret < 0)
  302. goto failed;
  303. msleep(state->cfg.lpf_wait);
  304. /* set all writable registers */
  305. for (i = 1; i <= 0x0c ; i++) {
  306. ret = reg_write(state, i, state->regs[i]);
  307. if (ret < 0)
  308. goto failed;
  309. }
  310. for (i = 0x11; i < QM1D1C0042_NUM_REGS; i++) {
  311. ret = reg_write(state, i, state->regs[i]);
  312. if (ret < 0)
  313. goto failed;
  314. }
  315. ret = qm1d1c0042_wakeup(state);
  316. if (ret < 0)
  317. goto failed;
  318. ret = qm1d1c0042_set_srch_mode(state, state->cfg.fast_srch);
  319. if (ret < 0)
  320. goto failed;
  321. return ret;
  322. failed:
  323. dev_warn(&state->i2c->dev, "(%s) failed. [adap%d-fe%d]\n",
  324. __func__, fe->dvb->num, fe->id);
  325. return ret;
  326. }
  327. /* I2C driver functions */
  328. static const struct dvb_tuner_ops qm1d1c0042_ops = {
  329. .info = {
  330. .name = "Sharp QM1D1C0042",
  331. .frequency_min_hz = 950 * MHz,
  332. .frequency_max_hz = 2150 * MHz,
  333. },
  334. .init = qm1d1c0042_init,
  335. .sleep = qm1d1c0042_sleep,
  336. .set_config = qm1d1c0042_set_config,
  337. .set_params = qm1d1c0042_set_params,
  338. };
  339. static int qm1d1c0042_probe(struct i2c_client *client,
  340. const struct i2c_device_id *id)
  341. {
  342. struct qm1d1c0042_state *state;
  343. struct qm1d1c0042_config *cfg;
  344. struct dvb_frontend *fe;
  345. state = kzalloc(sizeof(*state), GFP_KERNEL);
  346. if (!state)
  347. return -ENOMEM;
  348. state->i2c = client;
  349. cfg = client->dev.platform_data;
  350. fe = cfg->fe;
  351. fe->tuner_priv = state;
  352. qm1d1c0042_set_config(fe, cfg);
  353. memcpy(&fe->ops.tuner_ops, &qm1d1c0042_ops, sizeof(qm1d1c0042_ops));
  354. i2c_set_clientdata(client, &state->cfg);
  355. dev_info(&client->dev, "Sharp QM1D1C0042 attached.\n");
  356. return 0;
  357. }
  358. static int qm1d1c0042_remove(struct i2c_client *client)
  359. {
  360. struct qm1d1c0042_state *state;
  361. state = cfg_to_state(i2c_get_clientdata(client));
  362. state->cfg.fe->tuner_priv = NULL;
  363. kfree(state);
  364. return 0;
  365. }
  366. static const struct i2c_device_id qm1d1c0042_id[] = {
  367. {"qm1d1c0042", 0},
  368. {}
  369. };
  370. MODULE_DEVICE_TABLE(i2c, qm1d1c0042_id);
  371. static struct i2c_driver qm1d1c0042_driver = {
  372. .driver = {
  373. .name = "qm1d1c0042",
  374. },
  375. .probe = qm1d1c0042_probe,
  376. .remove = qm1d1c0042_remove,
  377. .id_table = qm1d1c0042_id,
  378. };
  379. module_i2c_driver(qm1d1c0042_driver);
  380. MODULE_DESCRIPTION("Sharp QM1D1C0042 tuner");
  381. MODULE_AUTHOR("Akihiro TSUKADA");
  382. MODULE_LICENSE("GPL");