mxl5005s.c 126 KB

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  1. /*
  2. MaxLinear MXL5005S VSB/QAM/DVBT tuner driver
  3. Copyright (C) 2008 MaxLinear
  4. Copyright (C) 2006 Steven Toth <stoth@linuxtv.org>
  5. Functions:
  6. mxl5005s_reset()
  7. mxl5005s_writereg()
  8. mxl5005s_writeregs()
  9. mxl5005s_init()
  10. mxl5005s_reconfigure()
  11. mxl5005s_AssignTunerMode()
  12. mxl5005s_set_params()
  13. mxl5005s_get_frequency()
  14. mxl5005s_get_bandwidth()
  15. mxl5005s_release()
  16. mxl5005s_attach()
  17. Copyright (C) 2008 Realtek
  18. Copyright (C) 2008 Jan Hoogenraad
  19. Functions:
  20. mxl5005s_SetRfFreqHz()
  21. This program is free software; you can redistribute it and/or modify
  22. it under the terms of the GNU General Public License as published by
  23. the Free Software Foundation; either version 2 of the License, or
  24. (at your option) any later version.
  25. This program is distributed in the hope that it will be useful,
  26. but WITHOUT ANY WARRANTY; without even the implied warranty of
  27. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  28. GNU General Public License for more details.
  29. You should have received a copy of the GNU General Public License
  30. along with this program; if not, write to the Free Software
  31. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  32. */
  33. /*
  34. History of this driver (Steven Toth):
  35. I was given a public release of a linux driver that included
  36. support for the MaxLinear MXL5005S silicon tuner. Analysis of
  37. the tuner driver showed clearly three things.
  38. 1. The tuner driver didn't support the LinuxTV tuner API
  39. so the code Realtek added had to be removed.
  40. 2. A significant amount of the driver is reference driver code
  41. from MaxLinear, I felt it was important to identify and
  42. preserve this.
  43. 3. New code has to be added to interface correctly with the
  44. LinuxTV API, as a regular kernel module.
  45. Other than the reference driver enum's, I've clearly marked
  46. sections of the code and retained the copyright of the
  47. respective owners.
  48. */
  49. #include <linux/kernel.h>
  50. #include <linux/init.h>
  51. #include <linux/module.h>
  52. #include <linux/string.h>
  53. #include <linux/slab.h>
  54. #include <linux/delay.h>
  55. #include <media/dvb_frontend.h>
  56. #include "mxl5005s.h"
  57. static int debug;
  58. #define dprintk(level, arg...) do { \
  59. if (level <= debug) \
  60. printk(arg); \
  61. } while (0)
  62. #define TUNER_REGS_NUM 104
  63. #define INITCTRL_NUM 40
  64. #ifdef _MXL_PRODUCTION
  65. #define CHCTRL_NUM 39
  66. #else
  67. #define CHCTRL_NUM 36
  68. #endif
  69. #define MXLCTRL_NUM 189
  70. #define MASTER_CONTROL_ADDR 9
  71. /* Enumeration of Master Control Register State */
  72. enum master_control_state {
  73. MC_LOAD_START = 1,
  74. MC_POWER_DOWN,
  75. MC_SYNTH_RESET,
  76. MC_SEQ_OFF
  77. };
  78. /* Enumeration of MXL5005 Tuner Modulation Type */
  79. enum {
  80. MXL_DEFAULT_MODULATION = 0,
  81. MXL_DVBT,
  82. MXL_ATSC,
  83. MXL_QAM,
  84. MXL_ANALOG_CABLE,
  85. MXL_ANALOG_OTA
  86. };
  87. /* MXL5005 Tuner Register Struct */
  88. struct TunerReg {
  89. u16 Reg_Num; /* Tuner Register Address */
  90. u16 Reg_Val; /* Current sw programmed value waiting to be written */
  91. };
  92. enum {
  93. /* Initialization Control Names */
  94. DN_IQTN_AMP_CUT = 1, /* 1 */
  95. BB_MODE, /* 2 */
  96. BB_BUF, /* 3 */
  97. BB_BUF_OA, /* 4 */
  98. BB_ALPF_BANDSELECT, /* 5 */
  99. BB_IQSWAP, /* 6 */
  100. BB_DLPF_BANDSEL, /* 7 */
  101. RFSYN_CHP_GAIN, /* 8 */
  102. RFSYN_EN_CHP_HIGAIN, /* 9 */
  103. AGC_IF, /* 10 */
  104. AGC_RF, /* 11 */
  105. IF_DIVVAL, /* 12 */
  106. IF_VCO_BIAS, /* 13 */
  107. CHCAL_INT_MOD_IF, /* 14 */
  108. CHCAL_FRAC_MOD_IF, /* 15 */
  109. DRV_RES_SEL, /* 16 */
  110. I_DRIVER, /* 17 */
  111. EN_AAF, /* 18 */
  112. EN_3P, /* 19 */
  113. EN_AUX_3P, /* 20 */
  114. SEL_AAF_BAND, /* 21 */
  115. SEQ_ENCLK16_CLK_OUT, /* 22 */
  116. SEQ_SEL4_16B, /* 23 */
  117. XTAL_CAPSELECT, /* 24 */
  118. IF_SEL_DBL, /* 25 */
  119. RFSYN_R_DIV, /* 26 */
  120. SEQ_EXTSYNTHCALIF, /* 27 */
  121. SEQ_EXTDCCAL, /* 28 */
  122. AGC_EN_RSSI, /* 29 */
  123. RFA_ENCLKRFAGC, /* 30 */
  124. RFA_RSSI_REFH, /* 31 */
  125. RFA_RSSI_REF, /* 32 */
  126. RFA_RSSI_REFL, /* 33 */
  127. RFA_FLR, /* 34 */
  128. RFA_CEIL, /* 35 */
  129. SEQ_EXTIQFSMPULSE, /* 36 */
  130. OVERRIDE_1, /* 37 */
  131. BB_INITSTATE_DLPF_TUNE, /* 38 */
  132. TG_R_DIV, /* 39 */
  133. EN_CHP_LIN_B, /* 40 */
  134. /* Channel Change Control Names */
  135. DN_POLY = 51, /* 51 */
  136. DN_RFGAIN, /* 52 */
  137. DN_CAP_RFLPF, /* 53 */
  138. DN_EN_VHFUHFBAR, /* 54 */
  139. DN_GAIN_ADJUST, /* 55 */
  140. DN_IQTNBUF_AMP, /* 56 */
  141. DN_IQTNGNBFBIAS_BST, /* 57 */
  142. RFSYN_EN_OUTMUX, /* 58 */
  143. RFSYN_SEL_VCO_OUT, /* 59 */
  144. RFSYN_SEL_VCO_HI, /* 60 */
  145. RFSYN_SEL_DIVM, /* 61 */
  146. RFSYN_RF_DIV_BIAS, /* 62 */
  147. DN_SEL_FREQ, /* 63 */
  148. RFSYN_VCO_BIAS, /* 64 */
  149. CHCAL_INT_MOD_RF, /* 65 */
  150. CHCAL_FRAC_MOD_RF, /* 66 */
  151. RFSYN_LPF_R, /* 67 */
  152. CHCAL_EN_INT_RF, /* 68 */
  153. TG_LO_DIVVAL, /* 69 */
  154. TG_LO_SELVAL, /* 70 */
  155. TG_DIV_VAL, /* 71 */
  156. TG_VCO_BIAS, /* 72 */
  157. SEQ_EXTPOWERUP, /* 73 */
  158. OVERRIDE_2, /* 74 */
  159. OVERRIDE_3, /* 75 */
  160. OVERRIDE_4, /* 76 */
  161. SEQ_FSM_PULSE, /* 77 */
  162. GPIO_4B, /* 78 */
  163. GPIO_3B, /* 79 */
  164. GPIO_4, /* 80 */
  165. GPIO_3, /* 81 */
  166. GPIO_1B, /* 82 */
  167. DAC_A_ENABLE, /* 83 */
  168. DAC_B_ENABLE, /* 84 */
  169. DAC_DIN_A, /* 85 */
  170. DAC_DIN_B, /* 86 */
  171. #ifdef _MXL_PRODUCTION
  172. RFSYN_EN_DIV, /* 87 */
  173. RFSYN_DIVM, /* 88 */
  174. DN_BYPASS_AGC_I2C /* 89 */
  175. #endif
  176. };
  177. /*
  178. * The following context is source code provided by MaxLinear.
  179. * MaxLinear source code - Common_MXL.h (?)
  180. */
  181. /* Constants */
  182. #define MXL5005S_REG_WRITING_TABLE_LEN_MAX 104
  183. #define MXL5005S_LATCH_BYTE 0xfe
  184. /* Register address, MSB, and LSB */
  185. #define MXL5005S_BB_IQSWAP_ADDR 59
  186. #define MXL5005S_BB_IQSWAP_MSB 0
  187. #define MXL5005S_BB_IQSWAP_LSB 0
  188. #define MXL5005S_BB_DLPF_BANDSEL_ADDR 53
  189. #define MXL5005S_BB_DLPF_BANDSEL_MSB 4
  190. #define MXL5005S_BB_DLPF_BANDSEL_LSB 3
  191. /* Standard modes */
  192. enum {
  193. MXL5005S_STANDARD_DVBT,
  194. MXL5005S_STANDARD_ATSC,
  195. };
  196. #define MXL5005S_STANDARD_MODE_NUM 2
  197. /* Bandwidth modes */
  198. enum {
  199. MXL5005S_BANDWIDTH_6MHZ = 6000000,
  200. MXL5005S_BANDWIDTH_7MHZ = 7000000,
  201. MXL5005S_BANDWIDTH_8MHZ = 8000000,
  202. };
  203. #define MXL5005S_BANDWIDTH_MODE_NUM 3
  204. /* MXL5005 Tuner Control Struct */
  205. struct TunerControl {
  206. u16 Ctrl_Num; /* Control Number */
  207. u16 size; /* Number of bits to represent Value */
  208. u16 addr[25]; /* Array of Tuner Register Address for each bit pos */
  209. u16 bit[25]; /* Array of bit pos in Reg Addr for each bit pos */
  210. u16 val[25]; /* Binary representation of Value */
  211. };
  212. /* MXL5005 Tuner Struct */
  213. struct mxl5005s_state {
  214. u8 Mode; /* 0: Analog Mode ; 1: Digital Mode */
  215. u8 IF_Mode; /* for Analog Mode, 0: zero IF; 1: low IF */
  216. u32 Chan_Bandwidth; /* filter channel bandwidth (6, 7, 8) */
  217. u32 IF_OUT; /* Desired IF Out Frequency */
  218. u16 IF_OUT_LOAD; /* IF Out Load Resistor (200/300 Ohms) */
  219. u32 RF_IN; /* RF Input Frequency */
  220. u32 Fxtal; /* XTAL Frequency */
  221. u8 AGC_Mode; /* AGC Mode 0: Dual AGC; 1: Single AGC */
  222. u16 TOP; /* Value: take over point */
  223. u8 CLOCK_OUT; /* 0: turn off clk out; 1: turn on clock out */
  224. u8 DIV_OUT; /* 4MHz or 16MHz */
  225. u8 CAPSELECT; /* 0: disable On-Chip pulling cap; 1: enable */
  226. u8 EN_RSSI; /* 0: disable RSSI; 1: enable RSSI */
  227. /* Modulation Type; */
  228. /* 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */
  229. u8 Mod_Type;
  230. /* Tracking Filter Type */
  231. /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */
  232. u8 TF_Type;
  233. /* Calculated Settings */
  234. u32 RF_LO; /* Synth RF LO Frequency */
  235. u32 IF_LO; /* Synth IF LO Frequency */
  236. u32 TG_LO; /* Synth TG_LO Frequency */
  237. /* Pointers to ControlName Arrays */
  238. u16 Init_Ctrl_Num; /* Number of INIT Control Names */
  239. struct TunerControl
  240. Init_Ctrl[INITCTRL_NUM]; /* INIT Control Names Array Pointer */
  241. u16 CH_Ctrl_Num; /* Number of CH Control Names */
  242. struct TunerControl
  243. CH_Ctrl[CHCTRL_NUM]; /* CH Control Name Array Pointer */
  244. u16 MXL_Ctrl_Num; /* Number of MXL Control Names */
  245. struct TunerControl
  246. MXL_Ctrl[MXLCTRL_NUM]; /* MXL Control Name Array Pointer */
  247. /* Pointer to Tuner Register Array */
  248. u16 TunerRegs_Num; /* Number of Tuner Registers */
  249. struct TunerReg
  250. TunerRegs[TUNER_REGS_NUM]; /* Tuner Register Array Pointer */
  251. /* Linux driver framework specific */
  252. struct mxl5005s_config *config;
  253. struct dvb_frontend *frontend;
  254. struct i2c_adapter *i2c;
  255. /* Cache values */
  256. u32 current_mode;
  257. };
  258. static u16 MXL_GetMasterControl(u8 *MasterReg, int state);
  259. static u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value);
  260. static u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value);
  261. static void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit,
  262. u8 bitVal);
  263. static u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 *RegNum,
  264. u8 *RegVal, int *count);
  265. static u32 MXL_Ceiling(u32 value, u32 resolution);
  266. static u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal);
  267. static u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum,
  268. u32 value, u16 controlGroup);
  269. static u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val);
  270. static u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 *RegNum,
  271. u8 *RegVal, int *count);
  272. static u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq);
  273. static void MXL_SynthIFLO_Calc(struct dvb_frontend *fe);
  274. static void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe);
  275. static u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum,
  276. u8 *RegVal, int *count);
  277. static int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable,
  278. u8 *datatable, u8 len);
  279. static u16 MXL_IFSynthInit(struct dvb_frontend *fe);
  280. static int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type,
  281. u32 bandwidth);
  282. static int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type,
  283. u32 bandwidth);
  284. /* ----------------------------------------------------------------
  285. * Begin: Custom code salvaged from the Realtek driver.
  286. * Copyright (C) 2008 Realtek
  287. * Copyright (C) 2008 Jan Hoogenraad
  288. * This code is placed under the terms of the GNU General Public License
  289. *
  290. * Released by Realtek under GPLv2.
  291. * Thanks to Realtek for a lot of support we received !
  292. *
  293. * Revision: 080314 - original version
  294. */
  295. static int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz)
  296. {
  297. struct mxl5005s_state *state = fe->tuner_priv;
  298. unsigned char AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
  299. unsigned char ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
  300. int TableLen;
  301. u32 IfDivval = 0;
  302. unsigned char MasterControlByte;
  303. dprintk(1, "%s() freq=%ld\n", __func__, RfFreqHz);
  304. /* Set MxL5005S tuner RF frequency according to example code. */
  305. /* Tuner RF frequency setting stage 0 */
  306. MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET);
  307. AddrTable[0] = MASTER_CONTROL_ADDR;
  308. ByteTable[0] |= state->config->AgcMasterByte;
  309. mxl5005s_writeregs(fe, AddrTable, ByteTable, 1);
  310. /* Tuner RF frequency setting stage 1 */
  311. MXL_TuneRF(fe, RfFreqHz);
  312. MXL_ControlRead(fe, IF_DIVVAL, &IfDivval);
  313. MXL_ControlWrite(fe, SEQ_FSM_PULSE, 0);
  314. MXL_ControlWrite(fe, SEQ_EXTPOWERUP, 1);
  315. MXL_ControlWrite(fe, IF_DIVVAL, 8);
  316. MXL_GetCHRegister(fe, AddrTable, ByteTable, &TableLen);
  317. MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START);
  318. AddrTable[TableLen] = MASTER_CONTROL_ADDR ;
  319. ByteTable[TableLen] = MasterControlByte |
  320. state->config->AgcMasterByte;
  321. TableLen += 1;
  322. mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen);
  323. /* Wait 30 ms. */
  324. msleep(150);
  325. /* Tuner RF frequency setting stage 2 */
  326. MXL_ControlWrite(fe, SEQ_FSM_PULSE, 1);
  327. MXL_ControlWrite(fe, IF_DIVVAL, IfDivval);
  328. MXL_GetCHRegister_ZeroIF(fe, AddrTable, ByteTable, &TableLen);
  329. MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START);
  330. AddrTable[TableLen] = MASTER_CONTROL_ADDR ;
  331. ByteTable[TableLen] = MasterControlByte |
  332. state->config->AgcMasterByte ;
  333. TableLen += 1;
  334. mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen);
  335. msleep(100);
  336. return 0;
  337. }
  338. /* End: Custom code taken from the Realtek driver */
  339. /* ----------------------------------------------------------------
  340. * Begin: Reference driver code found in the Realtek driver.
  341. * Copyright (C) 2008 MaxLinear
  342. */
  343. static u16 MXL5005_RegisterInit(struct dvb_frontend *fe)
  344. {
  345. struct mxl5005s_state *state = fe->tuner_priv;
  346. state->TunerRegs_Num = TUNER_REGS_NUM ;
  347. state->TunerRegs[0].Reg_Num = 9 ;
  348. state->TunerRegs[0].Reg_Val = 0x40 ;
  349. state->TunerRegs[1].Reg_Num = 11 ;
  350. state->TunerRegs[1].Reg_Val = 0x19 ;
  351. state->TunerRegs[2].Reg_Num = 12 ;
  352. state->TunerRegs[2].Reg_Val = 0x60 ;
  353. state->TunerRegs[3].Reg_Num = 13 ;
  354. state->TunerRegs[3].Reg_Val = 0x00 ;
  355. state->TunerRegs[4].Reg_Num = 14 ;
  356. state->TunerRegs[4].Reg_Val = 0x00 ;
  357. state->TunerRegs[5].Reg_Num = 15 ;
  358. state->TunerRegs[5].Reg_Val = 0xC0 ;
  359. state->TunerRegs[6].Reg_Num = 16 ;
  360. state->TunerRegs[6].Reg_Val = 0x00 ;
  361. state->TunerRegs[7].Reg_Num = 17 ;
  362. state->TunerRegs[7].Reg_Val = 0x00 ;
  363. state->TunerRegs[8].Reg_Num = 18 ;
  364. state->TunerRegs[8].Reg_Val = 0x00 ;
  365. state->TunerRegs[9].Reg_Num = 19 ;
  366. state->TunerRegs[9].Reg_Val = 0x34 ;
  367. state->TunerRegs[10].Reg_Num = 21 ;
  368. state->TunerRegs[10].Reg_Val = 0x00 ;
  369. state->TunerRegs[11].Reg_Num = 22 ;
  370. state->TunerRegs[11].Reg_Val = 0x6B ;
  371. state->TunerRegs[12].Reg_Num = 23 ;
  372. state->TunerRegs[12].Reg_Val = 0x35 ;
  373. state->TunerRegs[13].Reg_Num = 24 ;
  374. state->TunerRegs[13].Reg_Val = 0x70 ;
  375. state->TunerRegs[14].Reg_Num = 25 ;
  376. state->TunerRegs[14].Reg_Val = 0x3E ;
  377. state->TunerRegs[15].Reg_Num = 26 ;
  378. state->TunerRegs[15].Reg_Val = 0x82 ;
  379. state->TunerRegs[16].Reg_Num = 31 ;
  380. state->TunerRegs[16].Reg_Val = 0x00 ;
  381. state->TunerRegs[17].Reg_Num = 32 ;
  382. state->TunerRegs[17].Reg_Val = 0x40 ;
  383. state->TunerRegs[18].Reg_Num = 33 ;
  384. state->TunerRegs[18].Reg_Val = 0x53 ;
  385. state->TunerRegs[19].Reg_Num = 34 ;
  386. state->TunerRegs[19].Reg_Val = 0x81 ;
  387. state->TunerRegs[20].Reg_Num = 35 ;
  388. state->TunerRegs[20].Reg_Val = 0xC9 ;
  389. state->TunerRegs[21].Reg_Num = 36 ;
  390. state->TunerRegs[21].Reg_Val = 0x01 ;
  391. state->TunerRegs[22].Reg_Num = 37 ;
  392. state->TunerRegs[22].Reg_Val = 0x00 ;
  393. state->TunerRegs[23].Reg_Num = 41 ;
  394. state->TunerRegs[23].Reg_Val = 0x00 ;
  395. state->TunerRegs[24].Reg_Num = 42 ;
  396. state->TunerRegs[24].Reg_Val = 0xF8 ;
  397. state->TunerRegs[25].Reg_Num = 43 ;
  398. state->TunerRegs[25].Reg_Val = 0x43 ;
  399. state->TunerRegs[26].Reg_Num = 44 ;
  400. state->TunerRegs[26].Reg_Val = 0x20 ;
  401. state->TunerRegs[27].Reg_Num = 45 ;
  402. state->TunerRegs[27].Reg_Val = 0x80 ;
  403. state->TunerRegs[28].Reg_Num = 46 ;
  404. state->TunerRegs[28].Reg_Val = 0x88 ;
  405. state->TunerRegs[29].Reg_Num = 47 ;
  406. state->TunerRegs[29].Reg_Val = 0x86 ;
  407. state->TunerRegs[30].Reg_Num = 48 ;
  408. state->TunerRegs[30].Reg_Val = 0x00 ;
  409. state->TunerRegs[31].Reg_Num = 49 ;
  410. state->TunerRegs[31].Reg_Val = 0x00 ;
  411. state->TunerRegs[32].Reg_Num = 53 ;
  412. state->TunerRegs[32].Reg_Val = 0x94 ;
  413. state->TunerRegs[33].Reg_Num = 54 ;
  414. state->TunerRegs[33].Reg_Val = 0xFA ;
  415. state->TunerRegs[34].Reg_Num = 55 ;
  416. state->TunerRegs[34].Reg_Val = 0x92 ;
  417. state->TunerRegs[35].Reg_Num = 56 ;
  418. state->TunerRegs[35].Reg_Val = 0x80 ;
  419. state->TunerRegs[36].Reg_Num = 57 ;
  420. state->TunerRegs[36].Reg_Val = 0x41 ;
  421. state->TunerRegs[37].Reg_Num = 58 ;
  422. state->TunerRegs[37].Reg_Val = 0xDB ;
  423. state->TunerRegs[38].Reg_Num = 59 ;
  424. state->TunerRegs[38].Reg_Val = 0x00 ;
  425. state->TunerRegs[39].Reg_Num = 60 ;
  426. state->TunerRegs[39].Reg_Val = 0x00 ;
  427. state->TunerRegs[40].Reg_Num = 61 ;
  428. state->TunerRegs[40].Reg_Val = 0x00 ;
  429. state->TunerRegs[41].Reg_Num = 62 ;
  430. state->TunerRegs[41].Reg_Val = 0x00 ;
  431. state->TunerRegs[42].Reg_Num = 65 ;
  432. state->TunerRegs[42].Reg_Val = 0xF8 ;
  433. state->TunerRegs[43].Reg_Num = 66 ;
  434. state->TunerRegs[43].Reg_Val = 0xE4 ;
  435. state->TunerRegs[44].Reg_Num = 67 ;
  436. state->TunerRegs[44].Reg_Val = 0x90 ;
  437. state->TunerRegs[45].Reg_Num = 68 ;
  438. state->TunerRegs[45].Reg_Val = 0xC0 ;
  439. state->TunerRegs[46].Reg_Num = 69 ;
  440. state->TunerRegs[46].Reg_Val = 0x01 ;
  441. state->TunerRegs[47].Reg_Num = 70 ;
  442. state->TunerRegs[47].Reg_Val = 0x50 ;
  443. state->TunerRegs[48].Reg_Num = 71 ;
  444. state->TunerRegs[48].Reg_Val = 0x06 ;
  445. state->TunerRegs[49].Reg_Num = 72 ;
  446. state->TunerRegs[49].Reg_Val = 0x00 ;
  447. state->TunerRegs[50].Reg_Num = 73 ;
  448. state->TunerRegs[50].Reg_Val = 0x20 ;
  449. state->TunerRegs[51].Reg_Num = 76 ;
  450. state->TunerRegs[51].Reg_Val = 0xBB ;
  451. state->TunerRegs[52].Reg_Num = 77 ;
  452. state->TunerRegs[52].Reg_Val = 0x13 ;
  453. state->TunerRegs[53].Reg_Num = 81 ;
  454. state->TunerRegs[53].Reg_Val = 0x04 ;
  455. state->TunerRegs[54].Reg_Num = 82 ;
  456. state->TunerRegs[54].Reg_Val = 0x75 ;
  457. state->TunerRegs[55].Reg_Num = 83 ;
  458. state->TunerRegs[55].Reg_Val = 0x00 ;
  459. state->TunerRegs[56].Reg_Num = 84 ;
  460. state->TunerRegs[56].Reg_Val = 0x00 ;
  461. state->TunerRegs[57].Reg_Num = 85 ;
  462. state->TunerRegs[57].Reg_Val = 0x00 ;
  463. state->TunerRegs[58].Reg_Num = 91 ;
  464. state->TunerRegs[58].Reg_Val = 0x70 ;
  465. state->TunerRegs[59].Reg_Num = 92 ;
  466. state->TunerRegs[59].Reg_Val = 0x00 ;
  467. state->TunerRegs[60].Reg_Num = 93 ;
  468. state->TunerRegs[60].Reg_Val = 0x00 ;
  469. state->TunerRegs[61].Reg_Num = 94 ;
  470. state->TunerRegs[61].Reg_Val = 0x00 ;
  471. state->TunerRegs[62].Reg_Num = 95 ;
  472. state->TunerRegs[62].Reg_Val = 0x0C ;
  473. state->TunerRegs[63].Reg_Num = 96 ;
  474. state->TunerRegs[63].Reg_Val = 0x00 ;
  475. state->TunerRegs[64].Reg_Num = 97 ;
  476. state->TunerRegs[64].Reg_Val = 0x00 ;
  477. state->TunerRegs[65].Reg_Num = 98 ;
  478. state->TunerRegs[65].Reg_Val = 0xE2 ;
  479. state->TunerRegs[66].Reg_Num = 99 ;
  480. state->TunerRegs[66].Reg_Val = 0x00 ;
  481. state->TunerRegs[67].Reg_Num = 100 ;
  482. state->TunerRegs[67].Reg_Val = 0x00 ;
  483. state->TunerRegs[68].Reg_Num = 101 ;
  484. state->TunerRegs[68].Reg_Val = 0x12 ;
  485. state->TunerRegs[69].Reg_Num = 102 ;
  486. state->TunerRegs[69].Reg_Val = 0x80 ;
  487. state->TunerRegs[70].Reg_Num = 103 ;
  488. state->TunerRegs[70].Reg_Val = 0x32 ;
  489. state->TunerRegs[71].Reg_Num = 104 ;
  490. state->TunerRegs[71].Reg_Val = 0xB4 ;
  491. state->TunerRegs[72].Reg_Num = 105 ;
  492. state->TunerRegs[72].Reg_Val = 0x60 ;
  493. state->TunerRegs[73].Reg_Num = 106 ;
  494. state->TunerRegs[73].Reg_Val = 0x83 ;
  495. state->TunerRegs[74].Reg_Num = 107 ;
  496. state->TunerRegs[74].Reg_Val = 0x84 ;
  497. state->TunerRegs[75].Reg_Num = 108 ;
  498. state->TunerRegs[75].Reg_Val = 0x9C ;
  499. state->TunerRegs[76].Reg_Num = 109 ;
  500. state->TunerRegs[76].Reg_Val = 0x02 ;
  501. state->TunerRegs[77].Reg_Num = 110 ;
  502. state->TunerRegs[77].Reg_Val = 0x81 ;
  503. state->TunerRegs[78].Reg_Num = 111 ;
  504. state->TunerRegs[78].Reg_Val = 0xC0 ;
  505. state->TunerRegs[79].Reg_Num = 112 ;
  506. state->TunerRegs[79].Reg_Val = 0x10 ;
  507. state->TunerRegs[80].Reg_Num = 131 ;
  508. state->TunerRegs[80].Reg_Val = 0x8A ;
  509. state->TunerRegs[81].Reg_Num = 132 ;
  510. state->TunerRegs[81].Reg_Val = 0x10 ;
  511. state->TunerRegs[82].Reg_Num = 133 ;
  512. state->TunerRegs[82].Reg_Val = 0x24 ;
  513. state->TunerRegs[83].Reg_Num = 134 ;
  514. state->TunerRegs[83].Reg_Val = 0x00 ;
  515. state->TunerRegs[84].Reg_Num = 135 ;
  516. state->TunerRegs[84].Reg_Val = 0x00 ;
  517. state->TunerRegs[85].Reg_Num = 136 ;
  518. state->TunerRegs[85].Reg_Val = 0x7E ;
  519. state->TunerRegs[86].Reg_Num = 137 ;
  520. state->TunerRegs[86].Reg_Val = 0x40 ;
  521. state->TunerRegs[87].Reg_Num = 138 ;
  522. state->TunerRegs[87].Reg_Val = 0x38 ;
  523. state->TunerRegs[88].Reg_Num = 146 ;
  524. state->TunerRegs[88].Reg_Val = 0xF6 ;
  525. state->TunerRegs[89].Reg_Num = 147 ;
  526. state->TunerRegs[89].Reg_Val = 0x1A ;
  527. state->TunerRegs[90].Reg_Num = 148 ;
  528. state->TunerRegs[90].Reg_Val = 0x62 ;
  529. state->TunerRegs[91].Reg_Num = 149 ;
  530. state->TunerRegs[91].Reg_Val = 0x33 ;
  531. state->TunerRegs[92].Reg_Num = 150 ;
  532. state->TunerRegs[92].Reg_Val = 0x80 ;
  533. state->TunerRegs[93].Reg_Num = 156 ;
  534. state->TunerRegs[93].Reg_Val = 0x56 ;
  535. state->TunerRegs[94].Reg_Num = 157 ;
  536. state->TunerRegs[94].Reg_Val = 0x17 ;
  537. state->TunerRegs[95].Reg_Num = 158 ;
  538. state->TunerRegs[95].Reg_Val = 0xA9 ;
  539. state->TunerRegs[96].Reg_Num = 159 ;
  540. state->TunerRegs[96].Reg_Val = 0x00 ;
  541. state->TunerRegs[97].Reg_Num = 160 ;
  542. state->TunerRegs[97].Reg_Val = 0x00 ;
  543. state->TunerRegs[98].Reg_Num = 161 ;
  544. state->TunerRegs[98].Reg_Val = 0x00 ;
  545. state->TunerRegs[99].Reg_Num = 162 ;
  546. state->TunerRegs[99].Reg_Val = 0x40 ;
  547. state->TunerRegs[100].Reg_Num = 166 ;
  548. state->TunerRegs[100].Reg_Val = 0xAE ;
  549. state->TunerRegs[101].Reg_Num = 167 ;
  550. state->TunerRegs[101].Reg_Val = 0x1B ;
  551. state->TunerRegs[102].Reg_Num = 168 ;
  552. state->TunerRegs[102].Reg_Val = 0xF2 ;
  553. state->TunerRegs[103].Reg_Num = 195 ;
  554. state->TunerRegs[103].Reg_Val = 0x00 ;
  555. return 0 ;
  556. }
  557. static u16 MXL5005_ControlInit(struct dvb_frontend *fe)
  558. {
  559. struct mxl5005s_state *state = fe->tuner_priv;
  560. state->Init_Ctrl_Num = INITCTRL_NUM;
  561. state->Init_Ctrl[0].Ctrl_Num = DN_IQTN_AMP_CUT ;
  562. state->Init_Ctrl[0].size = 1 ;
  563. state->Init_Ctrl[0].addr[0] = 73;
  564. state->Init_Ctrl[0].bit[0] = 7;
  565. state->Init_Ctrl[0].val[0] = 0;
  566. state->Init_Ctrl[1].Ctrl_Num = BB_MODE ;
  567. state->Init_Ctrl[1].size = 1 ;
  568. state->Init_Ctrl[1].addr[0] = 53;
  569. state->Init_Ctrl[1].bit[0] = 2;
  570. state->Init_Ctrl[1].val[0] = 1;
  571. state->Init_Ctrl[2].Ctrl_Num = BB_BUF ;
  572. state->Init_Ctrl[2].size = 2 ;
  573. state->Init_Ctrl[2].addr[0] = 53;
  574. state->Init_Ctrl[2].bit[0] = 1;
  575. state->Init_Ctrl[2].val[0] = 0;
  576. state->Init_Ctrl[2].addr[1] = 57;
  577. state->Init_Ctrl[2].bit[1] = 0;
  578. state->Init_Ctrl[2].val[1] = 1;
  579. state->Init_Ctrl[3].Ctrl_Num = BB_BUF_OA ;
  580. state->Init_Ctrl[3].size = 1 ;
  581. state->Init_Ctrl[3].addr[0] = 53;
  582. state->Init_Ctrl[3].bit[0] = 0;
  583. state->Init_Ctrl[3].val[0] = 0;
  584. state->Init_Ctrl[4].Ctrl_Num = BB_ALPF_BANDSELECT ;
  585. state->Init_Ctrl[4].size = 3 ;
  586. state->Init_Ctrl[4].addr[0] = 53;
  587. state->Init_Ctrl[4].bit[0] = 5;
  588. state->Init_Ctrl[4].val[0] = 0;
  589. state->Init_Ctrl[4].addr[1] = 53;
  590. state->Init_Ctrl[4].bit[1] = 6;
  591. state->Init_Ctrl[4].val[1] = 0;
  592. state->Init_Ctrl[4].addr[2] = 53;
  593. state->Init_Ctrl[4].bit[2] = 7;
  594. state->Init_Ctrl[4].val[2] = 1;
  595. state->Init_Ctrl[5].Ctrl_Num = BB_IQSWAP ;
  596. state->Init_Ctrl[5].size = 1 ;
  597. state->Init_Ctrl[5].addr[0] = 59;
  598. state->Init_Ctrl[5].bit[0] = 0;
  599. state->Init_Ctrl[5].val[0] = 0;
  600. state->Init_Ctrl[6].Ctrl_Num = BB_DLPF_BANDSEL ;
  601. state->Init_Ctrl[6].size = 2 ;
  602. state->Init_Ctrl[6].addr[0] = 53;
  603. state->Init_Ctrl[6].bit[0] = 3;
  604. state->Init_Ctrl[6].val[0] = 0;
  605. state->Init_Ctrl[6].addr[1] = 53;
  606. state->Init_Ctrl[6].bit[1] = 4;
  607. state->Init_Ctrl[6].val[1] = 1;
  608. state->Init_Ctrl[7].Ctrl_Num = RFSYN_CHP_GAIN ;
  609. state->Init_Ctrl[7].size = 4 ;
  610. state->Init_Ctrl[7].addr[0] = 22;
  611. state->Init_Ctrl[7].bit[0] = 4;
  612. state->Init_Ctrl[7].val[0] = 0;
  613. state->Init_Ctrl[7].addr[1] = 22;
  614. state->Init_Ctrl[7].bit[1] = 5;
  615. state->Init_Ctrl[7].val[1] = 1;
  616. state->Init_Ctrl[7].addr[2] = 22;
  617. state->Init_Ctrl[7].bit[2] = 6;
  618. state->Init_Ctrl[7].val[2] = 1;
  619. state->Init_Ctrl[7].addr[3] = 22;
  620. state->Init_Ctrl[7].bit[3] = 7;
  621. state->Init_Ctrl[7].val[3] = 0;
  622. state->Init_Ctrl[8].Ctrl_Num = RFSYN_EN_CHP_HIGAIN ;
  623. state->Init_Ctrl[8].size = 1 ;
  624. state->Init_Ctrl[8].addr[0] = 22;
  625. state->Init_Ctrl[8].bit[0] = 2;
  626. state->Init_Ctrl[8].val[0] = 0;
  627. state->Init_Ctrl[9].Ctrl_Num = AGC_IF ;
  628. state->Init_Ctrl[9].size = 4 ;
  629. state->Init_Ctrl[9].addr[0] = 76;
  630. state->Init_Ctrl[9].bit[0] = 0;
  631. state->Init_Ctrl[9].val[0] = 1;
  632. state->Init_Ctrl[9].addr[1] = 76;
  633. state->Init_Ctrl[9].bit[1] = 1;
  634. state->Init_Ctrl[9].val[1] = 1;
  635. state->Init_Ctrl[9].addr[2] = 76;
  636. state->Init_Ctrl[9].bit[2] = 2;
  637. state->Init_Ctrl[9].val[2] = 0;
  638. state->Init_Ctrl[9].addr[3] = 76;
  639. state->Init_Ctrl[9].bit[3] = 3;
  640. state->Init_Ctrl[9].val[3] = 1;
  641. state->Init_Ctrl[10].Ctrl_Num = AGC_RF ;
  642. state->Init_Ctrl[10].size = 4 ;
  643. state->Init_Ctrl[10].addr[0] = 76;
  644. state->Init_Ctrl[10].bit[0] = 4;
  645. state->Init_Ctrl[10].val[0] = 1;
  646. state->Init_Ctrl[10].addr[1] = 76;
  647. state->Init_Ctrl[10].bit[1] = 5;
  648. state->Init_Ctrl[10].val[1] = 1;
  649. state->Init_Ctrl[10].addr[2] = 76;
  650. state->Init_Ctrl[10].bit[2] = 6;
  651. state->Init_Ctrl[10].val[2] = 0;
  652. state->Init_Ctrl[10].addr[3] = 76;
  653. state->Init_Ctrl[10].bit[3] = 7;
  654. state->Init_Ctrl[10].val[3] = 1;
  655. state->Init_Ctrl[11].Ctrl_Num = IF_DIVVAL ;
  656. state->Init_Ctrl[11].size = 5 ;
  657. state->Init_Ctrl[11].addr[0] = 43;
  658. state->Init_Ctrl[11].bit[0] = 3;
  659. state->Init_Ctrl[11].val[0] = 0;
  660. state->Init_Ctrl[11].addr[1] = 43;
  661. state->Init_Ctrl[11].bit[1] = 4;
  662. state->Init_Ctrl[11].val[1] = 0;
  663. state->Init_Ctrl[11].addr[2] = 43;
  664. state->Init_Ctrl[11].bit[2] = 5;
  665. state->Init_Ctrl[11].val[2] = 0;
  666. state->Init_Ctrl[11].addr[3] = 43;
  667. state->Init_Ctrl[11].bit[3] = 6;
  668. state->Init_Ctrl[11].val[3] = 1;
  669. state->Init_Ctrl[11].addr[4] = 43;
  670. state->Init_Ctrl[11].bit[4] = 7;
  671. state->Init_Ctrl[11].val[4] = 0;
  672. state->Init_Ctrl[12].Ctrl_Num = IF_VCO_BIAS ;
  673. state->Init_Ctrl[12].size = 6 ;
  674. state->Init_Ctrl[12].addr[0] = 44;
  675. state->Init_Ctrl[12].bit[0] = 2;
  676. state->Init_Ctrl[12].val[0] = 0;
  677. state->Init_Ctrl[12].addr[1] = 44;
  678. state->Init_Ctrl[12].bit[1] = 3;
  679. state->Init_Ctrl[12].val[1] = 0;
  680. state->Init_Ctrl[12].addr[2] = 44;
  681. state->Init_Ctrl[12].bit[2] = 4;
  682. state->Init_Ctrl[12].val[2] = 0;
  683. state->Init_Ctrl[12].addr[3] = 44;
  684. state->Init_Ctrl[12].bit[3] = 5;
  685. state->Init_Ctrl[12].val[3] = 1;
  686. state->Init_Ctrl[12].addr[4] = 44;
  687. state->Init_Ctrl[12].bit[4] = 6;
  688. state->Init_Ctrl[12].val[4] = 0;
  689. state->Init_Ctrl[12].addr[5] = 44;
  690. state->Init_Ctrl[12].bit[5] = 7;
  691. state->Init_Ctrl[12].val[5] = 0;
  692. state->Init_Ctrl[13].Ctrl_Num = CHCAL_INT_MOD_IF ;
  693. state->Init_Ctrl[13].size = 7 ;
  694. state->Init_Ctrl[13].addr[0] = 11;
  695. state->Init_Ctrl[13].bit[0] = 0;
  696. state->Init_Ctrl[13].val[0] = 1;
  697. state->Init_Ctrl[13].addr[1] = 11;
  698. state->Init_Ctrl[13].bit[1] = 1;
  699. state->Init_Ctrl[13].val[1] = 0;
  700. state->Init_Ctrl[13].addr[2] = 11;
  701. state->Init_Ctrl[13].bit[2] = 2;
  702. state->Init_Ctrl[13].val[2] = 0;
  703. state->Init_Ctrl[13].addr[3] = 11;
  704. state->Init_Ctrl[13].bit[3] = 3;
  705. state->Init_Ctrl[13].val[3] = 1;
  706. state->Init_Ctrl[13].addr[4] = 11;
  707. state->Init_Ctrl[13].bit[4] = 4;
  708. state->Init_Ctrl[13].val[4] = 1;
  709. state->Init_Ctrl[13].addr[5] = 11;
  710. state->Init_Ctrl[13].bit[5] = 5;
  711. state->Init_Ctrl[13].val[5] = 0;
  712. state->Init_Ctrl[13].addr[6] = 11;
  713. state->Init_Ctrl[13].bit[6] = 6;
  714. state->Init_Ctrl[13].val[6] = 0;
  715. state->Init_Ctrl[14].Ctrl_Num = CHCAL_FRAC_MOD_IF ;
  716. state->Init_Ctrl[14].size = 16 ;
  717. state->Init_Ctrl[14].addr[0] = 13;
  718. state->Init_Ctrl[14].bit[0] = 0;
  719. state->Init_Ctrl[14].val[0] = 0;
  720. state->Init_Ctrl[14].addr[1] = 13;
  721. state->Init_Ctrl[14].bit[1] = 1;
  722. state->Init_Ctrl[14].val[1] = 0;
  723. state->Init_Ctrl[14].addr[2] = 13;
  724. state->Init_Ctrl[14].bit[2] = 2;
  725. state->Init_Ctrl[14].val[2] = 0;
  726. state->Init_Ctrl[14].addr[3] = 13;
  727. state->Init_Ctrl[14].bit[3] = 3;
  728. state->Init_Ctrl[14].val[3] = 0;
  729. state->Init_Ctrl[14].addr[4] = 13;
  730. state->Init_Ctrl[14].bit[4] = 4;
  731. state->Init_Ctrl[14].val[4] = 0;
  732. state->Init_Ctrl[14].addr[5] = 13;
  733. state->Init_Ctrl[14].bit[5] = 5;
  734. state->Init_Ctrl[14].val[5] = 0;
  735. state->Init_Ctrl[14].addr[6] = 13;
  736. state->Init_Ctrl[14].bit[6] = 6;
  737. state->Init_Ctrl[14].val[6] = 0;
  738. state->Init_Ctrl[14].addr[7] = 13;
  739. state->Init_Ctrl[14].bit[7] = 7;
  740. state->Init_Ctrl[14].val[7] = 0;
  741. state->Init_Ctrl[14].addr[8] = 12;
  742. state->Init_Ctrl[14].bit[8] = 0;
  743. state->Init_Ctrl[14].val[8] = 0;
  744. state->Init_Ctrl[14].addr[9] = 12;
  745. state->Init_Ctrl[14].bit[9] = 1;
  746. state->Init_Ctrl[14].val[9] = 0;
  747. state->Init_Ctrl[14].addr[10] = 12;
  748. state->Init_Ctrl[14].bit[10] = 2;
  749. state->Init_Ctrl[14].val[10] = 0;
  750. state->Init_Ctrl[14].addr[11] = 12;
  751. state->Init_Ctrl[14].bit[11] = 3;
  752. state->Init_Ctrl[14].val[11] = 0;
  753. state->Init_Ctrl[14].addr[12] = 12;
  754. state->Init_Ctrl[14].bit[12] = 4;
  755. state->Init_Ctrl[14].val[12] = 0;
  756. state->Init_Ctrl[14].addr[13] = 12;
  757. state->Init_Ctrl[14].bit[13] = 5;
  758. state->Init_Ctrl[14].val[13] = 1;
  759. state->Init_Ctrl[14].addr[14] = 12;
  760. state->Init_Ctrl[14].bit[14] = 6;
  761. state->Init_Ctrl[14].val[14] = 1;
  762. state->Init_Ctrl[14].addr[15] = 12;
  763. state->Init_Ctrl[14].bit[15] = 7;
  764. state->Init_Ctrl[14].val[15] = 0;
  765. state->Init_Ctrl[15].Ctrl_Num = DRV_RES_SEL ;
  766. state->Init_Ctrl[15].size = 3 ;
  767. state->Init_Ctrl[15].addr[0] = 147;
  768. state->Init_Ctrl[15].bit[0] = 2;
  769. state->Init_Ctrl[15].val[0] = 0;
  770. state->Init_Ctrl[15].addr[1] = 147;
  771. state->Init_Ctrl[15].bit[1] = 3;
  772. state->Init_Ctrl[15].val[1] = 1;
  773. state->Init_Ctrl[15].addr[2] = 147;
  774. state->Init_Ctrl[15].bit[2] = 4;
  775. state->Init_Ctrl[15].val[2] = 1;
  776. state->Init_Ctrl[16].Ctrl_Num = I_DRIVER ;
  777. state->Init_Ctrl[16].size = 2 ;
  778. state->Init_Ctrl[16].addr[0] = 147;
  779. state->Init_Ctrl[16].bit[0] = 0;
  780. state->Init_Ctrl[16].val[0] = 0;
  781. state->Init_Ctrl[16].addr[1] = 147;
  782. state->Init_Ctrl[16].bit[1] = 1;
  783. state->Init_Ctrl[16].val[1] = 1;
  784. state->Init_Ctrl[17].Ctrl_Num = EN_AAF ;
  785. state->Init_Ctrl[17].size = 1 ;
  786. state->Init_Ctrl[17].addr[0] = 147;
  787. state->Init_Ctrl[17].bit[0] = 7;
  788. state->Init_Ctrl[17].val[0] = 0;
  789. state->Init_Ctrl[18].Ctrl_Num = EN_3P ;
  790. state->Init_Ctrl[18].size = 1 ;
  791. state->Init_Ctrl[18].addr[0] = 147;
  792. state->Init_Ctrl[18].bit[0] = 6;
  793. state->Init_Ctrl[18].val[0] = 0;
  794. state->Init_Ctrl[19].Ctrl_Num = EN_AUX_3P ;
  795. state->Init_Ctrl[19].size = 1 ;
  796. state->Init_Ctrl[19].addr[0] = 156;
  797. state->Init_Ctrl[19].bit[0] = 0;
  798. state->Init_Ctrl[19].val[0] = 0;
  799. state->Init_Ctrl[20].Ctrl_Num = SEL_AAF_BAND ;
  800. state->Init_Ctrl[20].size = 1 ;
  801. state->Init_Ctrl[20].addr[0] = 147;
  802. state->Init_Ctrl[20].bit[0] = 5;
  803. state->Init_Ctrl[20].val[0] = 0;
  804. state->Init_Ctrl[21].Ctrl_Num = SEQ_ENCLK16_CLK_OUT ;
  805. state->Init_Ctrl[21].size = 1 ;
  806. state->Init_Ctrl[21].addr[0] = 137;
  807. state->Init_Ctrl[21].bit[0] = 4;
  808. state->Init_Ctrl[21].val[0] = 0;
  809. state->Init_Ctrl[22].Ctrl_Num = SEQ_SEL4_16B ;
  810. state->Init_Ctrl[22].size = 1 ;
  811. state->Init_Ctrl[22].addr[0] = 137;
  812. state->Init_Ctrl[22].bit[0] = 7;
  813. state->Init_Ctrl[22].val[0] = 0;
  814. state->Init_Ctrl[23].Ctrl_Num = XTAL_CAPSELECT ;
  815. state->Init_Ctrl[23].size = 1 ;
  816. state->Init_Ctrl[23].addr[0] = 91;
  817. state->Init_Ctrl[23].bit[0] = 5;
  818. state->Init_Ctrl[23].val[0] = 1;
  819. state->Init_Ctrl[24].Ctrl_Num = IF_SEL_DBL ;
  820. state->Init_Ctrl[24].size = 1 ;
  821. state->Init_Ctrl[24].addr[0] = 43;
  822. state->Init_Ctrl[24].bit[0] = 0;
  823. state->Init_Ctrl[24].val[0] = 1;
  824. state->Init_Ctrl[25].Ctrl_Num = RFSYN_R_DIV ;
  825. state->Init_Ctrl[25].size = 2 ;
  826. state->Init_Ctrl[25].addr[0] = 22;
  827. state->Init_Ctrl[25].bit[0] = 0;
  828. state->Init_Ctrl[25].val[0] = 1;
  829. state->Init_Ctrl[25].addr[1] = 22;
  830. state->Init_Ctrl[25].bit[1] = 1;
  831. state->Init_Ctrl[25].val[1] = 1;
  832. state->Init_Ctrl[26].Ctrl_Num = SEQ_EXTSYNTHCALIF ;
  833. state->Init_Ctrl[26].size = 1 ;
  834. state->Init_Ctrl[26].addr[0] = 134;
  835. state->Init_Ctrl[26].bit[0] = 2;
  836. state->Init_Ctrl[26].val[0] = 0;
  837. state->Init_Ctrl[27].Ctrl_Num = SEQ_EXTDCCAL ;
  838. state->Init_Ctrl[27].size = 1 ;
  839. state->Init_Ctrl[27].addr[0] = 137;
  840. state->Init_Ctrl[27].bit[0] = 3;
  841. state->Init_Ctrl[27].val[0] = 0;
  842. state->Init_Ctrl[28].Ctrl_Num = AGC_EN_RSSI ;
  843. state->Init_Ctrl[28].size = 1 ;
  844. state->Init_Ctrl[28].addr[0] = 77;
  845. state->Init_Ctrl[28].bit[0] = 7;
  846. state->Init_Ctrl[28].val[0] = 0;
  847. state->Init_Ctrl[29].Ctrl_Num = RFA_ENCLKRFAGC ;
  848. state->Init_Ctrl[29].size = 1 ;
  849. state->Init_Ctrl[29].addr[0] = 166;
  850. state->Init_Ctrl[29].bit[0] = 7;
  851. state->Init_Ctrl[29].val[0] = 1;
  852. state->Init_Ctrl[30].Ctrl_Num = RFA_RSSI_REFH ;
  853. state->Init_Ctrl[30].size = 3 ;
  854. state->Init_Ctrl[30].addr[0] = 166;
  855. state->Init_Ctrl[30].bit[0] = 0;
  856. state->Init_Ctrl[30].val[0] = 0;
  857. state->Init_Ctrl[30].addr[1] = 166;
  858. state->Init_Ctrl[30].bit[1] = 1;
  859. state->Init_Ctrl[30].val[1] = 1;
  860. state->Init_Ctrl[30].addr[2] = 166;
  861. state->Init_Ctrl[30].bit[2] = 2;
  862. state->Init_Ctrl[30].val[2] = 1;
  863. state->Init_Ctrl[31].Ctrl_Num = RFA_RSSI_REF ;
  864. state->Init_Ctrl[31].size = 3 ;
  865. state->Init_Ctrl[31].addr[0] = 166;
  866. state->Init_Ctrl[31].bit[0] = 3;
  867. state->Init_Ctrl[31].val[0] = 1;
  868. state->Init_Ctrl[31].addr[1] = 166;
  869. state->Init_Ctrl[31].bit[1] = 4;
  870. state->Init_Ctrl[31].val[1] = 0;
  871. state->Init_Ctrl[31].addr[2] = 166;
  872. state->Init_Ctrl[31].bit[2] = 5;
  873. state->Init_Ctrl[31].val[2] = 1;
  874. state->Init_Ctrl[32].Ctrl_Num = RFA_RSSI_REFL ;
  875. state->Init_Ctrl[32].size = 3 ;
  876. state->Init_Ctrl[32].addr[0] = 167;
  877. state->Init_Ctrl[32].bit[0] = 0;
  878. state->Init_Ctrl[32].val[0] = 1;
  879. state->Init_Ctrl[32].addr[1] = 167;
  880. state->Init_Ctrl[32].bit[1] = 1;
  881. state->Init_Ctrl[32].val[1] = 1;
  882. state->Init_Ctrl[32].addr[2] = 167;
  883. state->Init_Ctrl[32].bit[2] = 2;
  884. state->Init_Ctrl[32].val[2] = 0;
  885. state->Init_Ctrl[33].Ctrl_Num = RFA_FLR ;
  886. state->Init_Ctrl[33].size = 4 ;
  887. state->Init_Ctrl[33].addr[0] = 168;
  888. state->Init_Ctrl[33].bit[0] = 0;
  889. state->Init_Ctrl[33].val[0] = 0;
  890. state->Init_Ctrl[33].addr[1] = 168;
  891. state->Init_Ctrl[33].bit[1] = 1;
  892. state->Init_Ctrl[33].val[1] = 1;
  893. state->Init_Ctrl[33].addr[2] = 168;
  894. state->Init_Ctrl[33].bit[2] = 2;
  895. state->Init_Ctrl[33].val[2] = 0;
  896. state->Init_Ctrl[33].addr[3] = 168;
  897. state->Init_Ctrl[33].bit[3] = 3;
  898. state->Init_Ctrl[33].val[3] = 0;
  899. state->Init_Ctrl[34].Ctrl_Num = RFA_CEIL ;
  900. state->Init_Ctrl[34].size = 4 ;
  901. state->Init_Ctrl[34].addr[0] = 168;
  902. state->Init_Ctrl[34].bit[0] = 4;
  903. state->Init_Ctrl[34].val[0] = 1;
  904. state->Init_Ctrl[34].addr[1] = 168;
  905. state->Init_Ctrl[34].bit[1] = 5;
  906. state->Init_Ctrl[34].val[1] = 1;
  907. state->Init_Ctrl[34].addr[2] = 168;
  908. state->Init_Ctrl[34].bit[2] = 6;
  909. state->Init_Ctrl[34].val[2] = 1;
  910. state->Init_Ctrl[34].addr[3] = 168;
  911. state->Init_Ctrl[34].bit[3] = 7;
  912. state->Init_Ctrl[34].val[3] = 1;
  913. state->Init_Ctrl[35].Ctrl_Num = SEQ_EXTIQFSMPULSE ;
  914. state->Init_Ctrl[35].size = 1 ;
  915. state->Init_Ctrl[35].addr[0] = 135;
  916. state->Init_Ctrl[35].bit[0] = 0;
  917. state->Init_Ctrl[35].val[0] = 0;
  918. state->Init_Ctrl[36].Ctrl_Num = OVERRIDE_1 ;
  919. state->Init_Ctrl[36].size = 1 ;
  920. state->Init_Ctrl[36].addr[0] = 56;
  921. state->Init_Ctrl[36].bit[0] = 3;
  922. state->Init_Ctrl[36].val[0] = 0;
  923. state->Init_Ctrl[37].Ctrl_Num = BB_INITSTATE_DLPF_TUNE ;
  924. state->Init_Ctrl[37].size = 7 ;
  925. state->Init_Ctrl[37].addr[0] = 59;
  926. state->Init_Ctrl[37].bit[0] = 1;
  927. state->Init_Ctrl[37].val[0] = 0;
  928. state->Init_Ctrl[37].addr[1] = 59;
  929. state->Init_Ctrl[37].bit[1] = 2;
  930. state->Init_Ctrl[37].val[1] = 0;
  931. state->Init_Ctrl[37].addr[2] = 59;
  932. state->Init_Ctrl[37].bit[2] = 3;
  933. state->Init_Ctrl[37].val[2] = 0;
  934. state->Init_Ctrl[37].addr[3] = 59;
  935. state->Init_Ctrl[37].bit[3] = 4;
  936. state->Init_Ctrl[37].val[3] = 0;
  937. state->Init_Ctrl[37].addr[4] = 59;
  938. state->Init_Ctrl[37].bit[4] = 5;
  939. state->Init_Ctrl[37].val[4] = 0;
  940. state->Init_Ctrl[37].addr[5] = 59;
  941. state->Init_Ctrl[37].bit[5] = 6;
  942. state->Init_Ctrl[37].val[5] = 0;
  943. state->Init_Ctrl[37].addr[6] = 59;
  944. state->Init_Ctrl[37].bit[6] = 7;
  945. state->Init_Ctrl[37].val[6] = 0;
  946. state->Init_Ctrl[38].Ctrl_Num = TG_R_DIV ;
  947. state->Init_Ctrl[38].size = 6 ;
  948. state->Init_Ctrl[38].addr[0] = 32;
  949. state->Init_Ctrl[38].bit[0] = 2;
  950. state->Init_Ctrl[38].val[0] = 0;
  951. state->Init_Ctrl[38].addr[1] = 32;
  952. state->Init_Ctrl[38].bit[1] = 3;
  953. state->Init_Ctrl[38].val[1] = 0;
  954. state->Init_Ctrl[38].addr[2] = 32;
  955. state->Init_Ctrl[38].bit[2] = 4;
  956. state->Init_Ctrl[38].val[2] = 0;
  957. state->Init_Ctrl[38].addr[3] = 32;
  958. state->Init_Ctrl[38].bit[3] = 5;
  959. state->Init_Ctrl[38].val[3] = 0;
  960. state->Init_Ctrl[38].addr[4] = 32;
  961. state->Init_Ctrl[38].bit[4] = 6;
  962. state->Init_Ctrl[38].val[4] = 1;
  963. state->Init_Ctrl[38].addr[5] = 32;
  964. state->Init_Ctrl[38].bit[5] = 7;
  965. state->Init_Ctrl[38].val[5] = 0;
  966. state->Init_Ctrl[39].Ctrl_Num = EN_CHP_LIN_B ;
  967. state->Init_Ctrl[39].size = 1 ;
  968. state->Init_Ctrl[39].addr[0] = 25;
  969. state->Init_Ctrl[39].bit[0] = 3;
  970. state->Init_Ctrl[39].val[0] = 1;
  971. state->CH_Ctrl_Num = CHCTRL_NUM ;
  972. state->CH_Ctrl[0].Ctrl_Num = DN_POLY ;
  973. state->CH_Ctrl[0].size = 2 ;
  974. state->CH_Ctrl[0].addr[0] = 68;
  975. state->CH_Ctrl[0].bit[0] = 6;
  976. state->CH_Ctrl[0].val[0] = 1;
  977. state->CH_Ctrl[0].addr[1] = 68;
  978. state->CH_Ctrl[0].bit[1] = 7;
  979. state->CH_Ctrl[0].val[1] = 1;
  980. state->CH_Ctrl[1].Ctrl_Num = DN_RFGAIN ;
  981. state->CH_Ctrl[1].size = 2 ;
  982. state->CH_Ctrl[1].addr[0] = 70;
  983. state->CH_Ctrl[1].bit[0] = 6;
  984. state->CH_Ctrl[1].val[0] = 1;
  985. state->CH_Ctrl[1].addr[1] = 70;
  986. state->CH_Ctrl[1].bit[1] = 7;
  987. state->CH_Ctrl[1].val[1] = 0;
  988. state->CH_Ctrl[2].Ctrl_Num = DN_CAP_RFLPF ;
  989. state->CH_Ctrl[2].size = 9 ;
  990. state->CH_Ctrl[2].addr[0] = 69;
  991. state->CH_Ctrl[2].bit[0] = 5;
  992. state->CH_Ctrl[2].val[0] = 0;
  993. state->CH_Ctrl[2].addr[1] = 69;
  994. state->CH_Ctrl[2].bit[1] = 6;
  995. state->CH_Ctrl[2].val[1] = 0;
  996. state->CH_Ctrl[2].addr[2] = 69;
  997. state->CH_Ctrl[2].bit[2] = 7;
  998. state->CH_Ctrl[2].val[2] = 0;
  999. state->CH_Ctrl[2].addr[3] = 68;
  1000. state->CH_Ctrl[2].bit[3] = 0;
  1001. state->CH_Ctrl[2].val[3] = 0;
  1002. state->CH_Ctrl[2].addr[4] = 68;
  1003. state->CH_Ctrl[2].bit[4] = 1;
  1004. state->CH_Ctrl[2].val[4] = 0;
  1005. state->CH_Ctrl[2].addr[5] = 68;
  1006. state->CH_Ctrl[2].bit[5] = 2;
  1007. state->CH_Ctrl[2].val[5] = 0;
  1008. state->CH_Ctrl[2].addr[6] = 68;
  1009. state->CH_Ctrl[2].bit[6] = 3;
  1010. state->CH_Ctrl[2].val[6] = 0;
  1011. state->CH_Ctrl[2].addr[7] = 68;
  1012. state->CH_Ctrl[2].bit[7] = 4;
  1013. state->CH_Ctrl[2].val[7] = 0;
  1014. state->CH_Ctrl[2].addr[8] = 68;
  1015. state->CH_Ctrl[2].bit[8] = 5;
  1016. state->CH_Ctrl[2].val[8] = 0;
  1017. state->CH_Ctrl[3].Ctrl_Num = DN_EN_VHFUHFBAR ;
  1018. state->CH_Ctrl[3].size = 1 ;
  1019. state->CH_Ctrl[3].addr[0] = 70;
  1020. state->CH_Ctrl[3].bit[0] = 5;
  1021. state->CH_Ctrl[3].val[0] = 0;
  1022. state->CH_Ctrl[4].Ctrl_Num = DN_GAIN_ADJUST ;
  1023. state->CH_Ctrl[4].size = 3 ;
  1024. state->CH_Ctrl[4].addr[0] = 73;
  1025. state->CH_Ctrl[4].bit[0] = 4;
  1026. state->CH_Ctrl[4].val[0] = 0;
  1027. state->CH_Ctrl[4].addr[1] = 73;
  1028. state->CH_Ctrl[4].bit[1] = 5;
  1029. state->CH_Ctrl[4].val[1] = 1;
  1030. state->CH_Ctrl[4].addr[2] = 73;
  1031. state->CH_Ctrl[4].bit[2] = 6;
  1032. state->CH_Ctrl[4].val[2] = 0;
  1033. state->CH_Ctrl[5].Ctrl_Num = DN_IQTNBUF_AMP ;
  1034. state->CH_Ctrl[5].size = 4 ;
  1035. state->CH_Ctrl[5].addr[0] = 70;
  1036. state->CH_Ctrl[5].bit[0] = 0;
  1037. state->CH_Ctrl[5].val[0] = 0;
  1038. state->CH_Ctrl[5].addr[1] = 70;
  1039. state->CH_Ctrl[5].bit[1] = 1;
  1040. state->CH_Ctrl[5].val[1] = 0;
  1041. state->CH_Ctrl[5].addr[2] = 70;
  1042. state->CH_Ctrl[5].bit[2] = 2;
  1043. state->CH_Ctrl[5].val[2] = 0;
  1044. state->CH_Ctrl[5].addr[3] = 70;
  1045. state->CH_Ctrl[5].bit[3] = 3;
  1046. state->CH_Ctrl[5].val[3] = 0;
  1047. state->CH_Ctrl[6].Ctrl_Num = DN_IQTNGNBFBIAS_BST ;
  1048. state->CH_Ctrl[6].size = 1 ;
  1049. state->CH_Ctrl[6].addr[0] = 70;
  1050. state->CH_Ctrl[6].bit[0] = 4;
  1051. state->CH_Ctrl[6].val[0] = 1;
  1052. state->CH_Ctrl[7].Ctrl_Num = RFSYN_EN_OUTMUX ;
  1053. state->CH_Ctrl[7].size = 1 ;
  1054. state->CH_Ctrl[7].addr[0] = 111;
  1055. state->CH_Ctrl[7].bit[0] = 4;
  1056. state->CH_Ctrl[7].val[0] = 0;
  1057. state->CH_Ctrl[8].Ctrl_Num = RFSYN_SEL_VCO_OUT ;
  1058. state->CH_Ctrl[8].size = 1 ;
  1059. state->CH_Ctrl[8].addr[0] = 111;
  1060. state->CH_Ctrl[8].bit[0] = 7;
  1061. state->CH_Ctrl[8].val[0] = 1;
  1062. state->CH_Ctrl[9].Ctrl_Num = RFSYN_SEL_VCO_HI ;
  1063. state->CH_Ctrl[9].size = 1 ;
  1064. state->CH_Ctrl[9].addr[0] = 111;
  1065. state->CH_Ctrl[9].bit[0] = 6;
  1066. state->CH_Ctrl[9].val[0] = 1;
  1067. state->CH_Ctrl[10].Ctrl_Num = RFSYN_SEL_DIVM ;
  1068. state->CH_Ctrl[10].size = 1 ;
  1069. state->CH_Ctrl[10].addr[0] = 111;
  1070. state->CH_Ctrl[10].bit[0] = 5;
  1071. state->CH_Ctrl[10].val[0] = 0;
  1072. state->CH_Ctrl[11].Ctrl_Num = RFSYN_RF_DIV_BIAS ;
  1073. state->CH_Ctrl[11].size = 2 ;
  1074. state->CH_Ctrl[11].addr[0] = 110;
  1075. state->CH_Ctrl[11].bit[0] = 0;
  1076. state->CH_Ctrl[11].val[0] = 1;
  1077. state->CH_Ctrl[11].addr[1] = 110;
  1078. state->CH_Ctrl[11].bit[1] = 1;
  1079. state->CH_Ctrl[11].val[1] = 0;
  1080. state->CH_Ctrl[12].Ctrl_Num = DN_SEL_FREQ ;
  1081. state->CH_Ctrl[12].size = 3 ;
  1082. state->CH_Ctrl[12].addr[0] = 69;
  1083. state->CH_Ctrl[12].bit[0] = 2;
  1084. state->CH_Ctrl[12].val[0] = 0;
  1085. state->CH_Ctrl[12].addr[1] = 69;
  1086. state->CH_Ctrl[12].bit[1] = 3;
  1087. state->CH_Ctrl[12].val[1] = 0;
  1088. state->CH_Ctrl[12].addr[2] = 69;
  1089. state->CH_Ctrl[12].bit[2] = 4;
  1090. state->CH_Ctrl[12].val[2] = 0;
  1091. state->CH_Ctrl[13].Ctrl_Num = RFSYN_VCO_BIAS ;
  1092. state->CH_Ctrl[13].size = 6 ;
  1093. state->CH_Ctrl[13].addr[0] = 110;
  1094. state->CH_Ctrl[13].bit[0] = 2;
  1095. state->CH_Ctrl[13].val[0] = 0;
  1096. state->CH_Ctrl[13].addr[1] = 110;
  1097. state->CH_Ctrl[13].bit[1] = 3;
  1098. state->CH_Ctrl[13].val[1] = 0;
  1099. state->CH_Ctrl[13].addr[2] = 110;
  1100. state->CH_Ctrl[13].bit[2] = 4;
  1101. state->CH_Ctrl[13].val[2] = 0;
  1102. state->CH_Ctrl[13].addr[3] = 110;
  1103. state->CH_Ctrl[13].bit[3] = 5;
  1104. state->CH_Ctrl[13].val[3] = 0;
  1105. state->CH_Ctrl[13].addr[4] = 110;
  1106. state->CH_Ctrl[13].bit[4] = 6;
  1107. state->CH_Ctrl[13].val[4] = 0;
  1108. state->CH_Ctrl[13].addr[5] = 110;
  1109. state->CH_Ctrl[13].bit[5] = 7;
  1110. state->CH_Ctrl[13].val[5] = 1;
  1111. state->CH_Ctrl[14].Ctrl_Num = CHCAL_INT_MOD_RF ;
  1112. state->CH_Ctrl[14].size = 7 ;
  1113. state->CH_Ctrl[14].addr[0] = 14;
  1114. state->CH_Ctrl[14].bit[0] = 0;
  1115. state->CH_Ctrl[14].val[0] = 0;
  1116. state->CH_Ctrl[14].addr[1] = 14;
  1117. state->CH_Ctrl[14].bit[1] = 1;
  1118. state->CH_Ctrl[14].val[1] = 0;
  1119. state->CH_Ctrl[14].addr[2] = 14;
  1120. state->CH_Ctrl[14].bit[2] = 2;
  1121. state->CH_Ctrl[14].val[2] = 0;
  1122. state->CH_Ctrl[14].addr[3] = 14;
  1123. state->CH_Ctrl[14].bit[3] = 3;
  1124. state->CH_Ctrl[14].val[3] = 0;
  1125. state->CH_Ctrl[14].addr[4] = 14;
  1126. state->CH_Ctrl[14].bit[4] = 4;
  1127. state->CH_Ctrl[14].val[4] = 0;
  1128. state->CH_Ctrl[14].addr[5] = 14;
  1129. state->CH_Ctrl[14].bit[5] = 5;
  1130. state->CH_Ctrl[14].val[5] = 0;
  1131. state->CH_Ctrl[14].addr[6] = 14;
  1132. state->CH_Ctrl[14].bit[6] = 6;
  1133. state->CH_Ctrl[14].val[6] = 0;
  1134. state->CH_Ctrl[15].Ctrl_Num = CHCAL_FRAC_MOD_RF ;
  1135. state->CH_Ctrl[15].size = 18 ;
  1136. state->CH_Ctrl[15].addr[0] = 17;
  1137. state->CH_Ctrl[15].bit[0] = 6;
  1138. state->CH_Ctrl[15].val[0] = 0;
  1139. state->CH_Ctrl[15].addr[1] = 17;
  1140. state->CH_Ctrl[15].bit[1] = 7;
  1141. state->CH_Ctrl[15].val[1] = 0;
  1142. state->CH_Ctrl[15].addr[2] = 16;
  1143. state->CH_Ctrl[15].bit[2] = 0;
  1144. state->CH_Ctrl[15].val[2] = 0;
  1145. state->CH_Ctrl[15].addr[3] = 16;
  1146. state->CH_Ctrl[15].bit[3] = 1;
  1147. state->CH_Ctrl[15].val[3] = 0;
  1148. state->CH_Ctrl[15].addr[4] = 16;
  1149. state->CH_Ctrl[15].bit[4] = 2;
  1150. state->CH_Ctrl[15].val[4] = 0;
  1151. state->CH_Ctrl[15].addr[5] = 16;
  1152. state->CH_Ctrl[15].bit[5] = 3;
  1153. state->CH_Ctrl[15].val[5] = 0;
  1154. state->CH_Ctrl[15].addr[6] = 16;
  1155. state->CH_Ctrl[15].bit[6] = 4;
  1156. state->CH_Ctrl[15].val[6] = 0;
  1157. state->CH_Ctrl[15].addr[7] = 16;
  1158. state->CH_Ctrl[15].bit[7] = 5;
  1159. state->CH_Ctrl[15].val[7] = 0;
  1160. state->CH_Ctrl[15].addr[8] = 16;
  1161. state->CH_Ctrl[15].bit[8] = 6;
  1162. state->CH_Ctrl[15].val[8] = 0;
  1163. state->CH_Ctrl[15].addr[9] = 16;
  1164. state->CH_Ctrl[15].bit[9] = 7;
  1165. state->CH_Ctrl[15].val[9] = 0;
  1166. state->CH_Ctrl[15].addr[10] = 15;
  1167. state->CH_Ctrl[15].bit[10] = 0;
  1168. state->CH_Ctrl[15].val[10] = 0;
  1169. state->CH_Ctrl[15].addr[11] = 15;
  1170. state->CH_Ctrl[15].bit[11] = 1;
  1171. state->CH_Ctrl[15].val[11] = 0;
  1172. state->CH_Ctrl[15].addr[12] = 15;
  1173. state->CH_Ctrl[15].bit[12] = 2;
  1174. state->CH_Ctrl[15].val[12] = 0;
  1175. state->CH_Ctrl[15].addr[13] = 15;
  1176. state->CH_Ctrl[15].bit[13] = 3;
  1177. state->CH_Ctrl[15].val[13] = 0;
  1178. state->CH_Ctrl[15].addr[14] = 15;
  1179. state->CH_Ctrl[15].bit[14] = 4;
  1180. state->CH_Ctrl[15].val[14] = 0;
  1181. state->CH_Ctrl[15].addr[15] = 15;
  1182. state->CH_Ctrl[15].bit[15] = 5;
  1183. state->CH_Ctrl[15].val[15] = 0;
  1184. state->CH_Ctrl[15].addr[16] = 15;
  1185. state->CH_Ctrl[15].bit[16] = 6;
  1186. state->CH_Ctrl[15].val[16] = 1;
  1187. state->CH_Ctrl[15].addr[17] = 15;
  1188. state->CH_Ctrl[15].bit[17] = 7;
  1189. state->CH_Ctrl[15].val[17] = 1;
  1190. state->CH_Ctrl[16].Ctrl_Num = RFSYN_LPF_R ;
  1191. state->CH_Ctrl[16].size = 5 ;
  1192. state->CH_Ctrl[16].addr[0] = 112;
  1193. state->CH_Ctrl[16].bit[0] = 0;
  1194. state->CH_Ctrl[16].val[0] = 0;
  1195. state->CH_Ctrl[16].addr[1] = 112;
  1196. state->CH_Ctrl[16].bit[1] = 1;
  1197. state->CH_Ctrl[16].val[1] = 0;
  1198. state->CH_Ctrl[16].addr[2] = 112;
  1199. state->CH_Ctrl[16].bit[2] = 2;
  1200. state->CH_Ctrl[16].val[2] = 0;
  1201. state->CH_Ctrl[16].addr[3] = 112;
  1202. state->CH_Ctrl[16].bit[3] = 3;
  1203. state->CH_Ctrl[16].val[3] = 0;
  1204. state->CH_Ctrl[16].addr[4] = 112;
  1205. state->CH_Ctrl[16].bit[4] = 4;
  1206. state->CH_Ctrl[16].val[4] = 1;
  1207. state->CH_Ctrl[17].Ctrl_Num = CHCAL_EN_INT_RF ;
  1208. state->CH_Ctrl[17].size = 1 ;
  1209. state->CH_Ctrl[17].addr[0] = 14;
  1210. state->CH_Ctrl[17].bit[0] = 7;
  1211. state->CH_Ctrl[17].val[0] = 0;
  1212. state->CH_Ctrl[18].Ctrl_Num = TG_LO_DIVVAL ;
  1213. state->CH_Ctrl[18].size = 4 ;
  1214. state->CH_Ctrl[18].addr[0] = 107;
  1215. state->CH_Ctrl[18].bit[0] = 3;
  1216. state->CH_Ctrl[18].val[0] = 0;
  1217. state->CH_Ctrl[18].addr[1] = 107;
  1218. state->CH_Ctrl[18].bit[1] = 4;
  1219. state->CH_Ctrl[18].val[1] = 0;
  1220. state->CH_Ctrl[18].addr[2] = 107;
  1221. state->CH_Ctrl[18].bit[2] = 5;
  1222. state->CH_Ctrl[18].val[2] = 0;
  1223. state->CH_Ctrl[18].addr[3] = 107;
  1224. state->CH_Ctrl[18].bit[3] = 6;
  1225. state->CH_Ctrl[18].val[3] = 0;
  1226. state->CH_Ctrl[19].Ctrl_Num = TG_LO_SELVAL ;
  1227. state->CH_Ctrl[19].size = 3 ;
  1228. state->CH_Ctrl[19].addr[0] = 107;
  1229. state->CH_Ctrl[19].bit[0] = 7;
  1230. state->CH_Ctrl[19].val[0] = 1;
  1231. state->CH_Ctrl[19].addr[1] = 106;
  1232. state->CH_Ctrl[19].bit[1] = 0;
  1233. state->CH_Ctrl[19].val[1] = 1;
  1234. state->CH_Ctrl[19].addr[2] = 106;
  1235. state->CH_Ctrl[19].bit[2] = 1;
  1236. state->CH_Ctrl[19].val[2] = 1;
  1237. state->CH_Ctrl[20].Ctrl_Num = TG_DIV_VAL ;
  1238. state->CH_Ctrl[20].size = 11 ;
  1239. state->CH_Ctrl[20].addr[0] = 109;
  1240. state->CH_Ctrl[20].bit[0] = 2;
  1241. state->CH_Ctrl[20].val[0] = 0;
  1242. state->CH_Ctrl[20].addr[1] = 109;
  1243. state->CH_Ctrl[20].bit[1] = 3;
  1244. state->CH_Ctrl[20].val[1] = 0;
  1245. state->CH_Ctrl[20].addr[2] = 109;
  1246. state->CH_Ctrl[20].bit[2] = 4;
  1247. state->CH_Ctrl[20].val[2] = 0;
  1248. state->CH_Ctrl[20].addr[3] = 109;
  1249. state->CH_Ctrl[20].bit[3] = 5;
  1250. state->CH_Ctrl[20].val[3] = 0;
  1251. state->CH_Ctrl[20].addr[4] = 109;
  1252. state->CH_Ctrl[20].bit[4] = 6;
  1253. state->CH_Ctrl[20].val[4] = 0;
  1254. state->CH_Ctrl[20].addr[5] = 109;
  1255. state->CH_Ctrl[20].bit[5] = 7;
  1256. state->CH_Ctrl[20].val[5] = 0;
  1257. state->CH_Ctrl[20].addr[6] = 108;
  1258. state->CH_Ctrl[20].bit[6] = 0;
  1259. state->CH_Ctrl[20].val[6] = 0;
  1260. state->CH_Ctrl[20].addr[7] = 108;
  1261. state->CH_Ctrl[20].bit[7] = 1;
  1262. state->CH_Ctrl[20].val[7] = 0;
  1263. state->CH_Ctrl[20].addr[8] = 108;
  1264. state->CH_Ctrl[20].bit[8] = 2;
  1265. state->CH_Ctrl[20].val[8] = 1;
  1266. state->CH_Ctrl[20].addr[9] = 108;
  1267. state->CH_Ctrl[20].bit[9] = 3;
  1268. state->CH_Ctrl[20].val[9] = 1;
  1269. state->CH_Ctrl[20].addr[10] = 108;
  1270. state->CH_Ctrl[20].bit[10] = 4;
  1271. state->CH_Ctrl[20].val[10] = 1;
  1272. state->CH_Ctrl[21].Ctrl_Num = TG_VCO_BIAS ;
  1273. state->CH_Ctrl[21].size = 6 ;
  1274. state->CH_Ctrl[21].addr[0] = 106;
  1275. state->CH_Ctrl[21].bit[0] = 2;
  1276. state->CH_Ctrl[21].val[0] = 0;
  1277. state->CH_Ctrl[21].addr[1] = 106;
  1278. state->CH_Ctrl[21].bit[1] = 3;
  1279. state->CH_Ctrl[21].val[1] = 0;
  1280. state->CH_Ctrl[21].addr[2] = 106;
  1281. state->CH_Ctrl[21].bit[2] = 4;
  1282. state->CH_Ctrl[21].val[2] = 0;
  1283. state->CH_Ctrl[21].addr[3] = 106;
  1284. state->CH_Ctrl[21].bit[3] = 5;
  1285. state->CH_Ctrl[21].val[3] = 0;
  1286. state->CH_Ctrl[21].addr[4] = 106;
  1287. state->CH_Ctrl[21].bit[4] = 6;
  1288. state->CH_Ctrl[21].val[4] = 0;
  1289. state->CH_Ctrl[21].addr[5] = 106;
  1290. state->CH_Ctrl[21].bit[5] = 7;
  1291. state->CH_Ctrl[21].val[5] = 1;
  1292. state->CH_Ctrl[22].Ctrl_Num = SEQ_EXTPOWERUP ;
  1293. state->CH_Ctrl[22].size = 1 ;
  1294. state->CH_Ctrl[22].addr[0] = 138;
  1295. state->CH_Ctrl[22].bit[0] = 4;
  1296. state->CH_Ctrl[22].val[0] = 1;
  1297. state->CH_Ctrl[23].Ctrl_Num = OVERRIDE_2 ;
  1298. state->CH_Ctrl[23].size = 1 ;
  1299. state->CH_Ctrl[23].addr[0] = 17;
  1300. state->CH_Ctrl[23].bit[0] = 5;
  1301. state->CH_Ctrl[23].val[0] = 0;
  1302. state->CH_Ctrl[24].Ctrl_Num = OVERRIDE_3 ;
  1303. state->CH_Ctrl[24].size = 1 ;
  1304. state->CH_Ctrl[24].addr[0] = 111;
  1305. state->CH_Ctrl[24].bit[0] = 3;
  1306. state->CH_Ctrl[24].val[0] = 0;
  1307. state->CH_Ctrl[25].Ctrl_Num = OVERRIDE_4 ;
  1308. state->CH_Ctrl[25].size = 1 ;
  1309. state->CH_Ctrl[25].addr[0] = 112;
  1310. state->CH_Ctrl[25].bit[0] = 7;
  1311. state->CH_Ctrl[25].val[0] = 0;
  1312. state->CH_Ctrl[26].Ctrl_Num = SEQ_FSM_PULSE ;
  1313. state->CH_Ctrl[26].size = 1 ;
  1314. state->CH_Ctrl[26].addr[0] = 136;
  1315. state->CH_Ctrl[26].bit[0] = 7;
  1316. state->CH_Ctrl[26].val[0] = 0;
  1317. state->CH_Ctrl[27].Ctrl_Num = GPIO_4B ;
  1318. state->CH_Ctrl[27].size = 1 ;
  1319. state->CH_Ctrl[27].addr[0] = 149;
  1320. state->CH_Ctrl[27].bit[0] = 7;
  1321. state->CH_Ctrl[27].val[0] = 0;
  1322. state->CH_Ctrl[28].Ctrl_Num = GPIO_3B ;
  1323. state->CH_Ctrl[28].size = 1 ;
  1324. state->CH_Ctrl[28].addr[0] = 149;
  1325. state->CH_Ctrl[28].bit[0] = 6;
  1326. state->CH_Ctrl[28].val[0] = 0;
  1327. state->CH_Ctrl[29].Ctrl_Num = GPIO_4 ;
  1328. state->CH_Ctrl[29].size = 1 ;
  1329. state->CH_Ctrl[29].addr[0] = 149;
  1330. state->CH_Ctrl[29].bit[0] = 5;
  1331. state->CH_Ctrl[29].val[0] = 1;
  1332. state->CH_Ctrl[30].Ctrl_Num = GPIO_3 ;
  1333. state->CH_Ctrl[30].size = 1 ;
  1334. state->CH_Ctrl[30].addr[0] = 149;
  1335. state->CH_Ctrl[30].bit[0] = 4;
  1336. state->CH_Ctrl[30].val[0] = 1;
  1337. state->CH_Ctrl[31].Ctrl_Num = GPIO_1B ;
  1338. state->CH_Ctrl[31].size = 1 ;
  1339. state->CH_Ctrl[31].addr[0] = 149;
  1340. state->CH_Ctrl[31].bit[0] = 3;
  1341. state->CH_Ctrl[31].val[0] = 0;
  1342. state->CH_Ctrl[32].Ctrl_Num = DAC_A_ENABLE ;
  1343. state->CH_Ctrl[32].size = 1 ;
  1344. state->CH_Ctrl[32].addr[0] = 93;
  1345. state->CH_Ctrl[32].bit[0] = 1;
  1346. state->CH_Ctrl[32].val[0] = 0;
  1347. state->CH_Ctrl[33].Ctrl_Num = DAC_B_ENABLE ;
  1348. state->CH_Ctrl[33].size = 1 ;
  1349. state->CH_Ctrl[33].addr[0] = 93;
  1350. state->CH_Ctrl[33].bit[0] = 0;
  1351. state->CH_Ctrl[33].val[0] = 0;
  1352. state->CH_Ctrl[34].Ctrl_Num = DAC_DIN_A ;
  1353. state->CH_Ctrl[34].size = 6 ;
  1354. state->CH_Ctrl[34].addr[0] = 92;
  1355. state->CH_Ctrl[34].bit[0] = 2;
  1356. state->CH_Ctrl[34].val[0] = 0;
  1357. state->CH_Ctrl[34].addr[1] = 92;
  1358. state->CH_Ctrl[34].bit[1] = 3;
  1359. state->CH_Ctrl[34].val[1] = 0;
  1360. state->CH_Ctrl[34].addr[2] = 92;
  1361. state->CH_Ctrl[34].bit[2] = 4;
  1362. state->CH_Ctrl[34].val[2] = 0;
  1363. state->CH_Ctrl[34].addr[3] = 92;
  1364. state->CH_Ctrl[34].bit[3] = 5;
  1365. state->CH_Ctrl[34].val[3] = 0;
  1366. state->CH_Ctrl[34].addr[4] = 92;
  1367. state->CH_Ctrl[34].bit[4] = 6;
  1368. state->CH_Ctrl[34].val[4] = 0;
  1369. state->CH_Ctrl[34].addr[5] = 92;
  1370. state->CH_Ctrl[34].bit[5] = 7;
  1371. state->CH_Ctrl[34].val[5] = 0;
  1372. state->CH_Ctrl[35].Ctrl_Num = DAC_DIN_B ;
  1373. state->CH_Ctrl[35].size = 6 ;
  1374. state->CH_Ctrl[35].addr[0] = 93;
  1375. state->CH_Ctrl[35].bit[0] = 2;
  1376. state->CH_Ctrl[35].val[0] = 0;
  1377. state->CH_Ctrl[35].addr[1] = 93;
  1378. state->CH_Ctrl[35].bit[1] = 3;
  1379. state->CH_Ctrl[35].val[1] = 0;
  1380. state->CH_Ctrl[35].addr[2] = 93;
  1381. state->CH_Ctrl[35].bit[2] = 4;
  1382. state->CH_Ctrl[35].val[2] = 0;
  1383. state->CH_Ctrl[35].addr[3] = 93;
  1384. state->CH_Ctrl[35].bit[3] = 5;
  1385. state->CH_Ctrl[35].val[3] = 0;
  1386. state->CH_Ctrl[35].addr[4] = 93;
  1387. state->CH_Ctrl[35].bit[4] = 6;
  1388. state->CH_Ctrl[35].val[4] = 0;
  1389. state->CH_Ctrl[35].addr[5] = 93;
  1390. state->CH_Ctrl[35].bit[5] = 7;
  1391. state->CH_Ctrl[35].val[5] = 0;
  1392. #ifdef _MXL_PRODUCTION
  1393. state->CH_Ctrl[36].Ctrl_Num = RFSYN_EN_DIV ;
  1394. state->CH_Ctrl[36].size = 1 ;
  1395. state->CH_Ctrl[36].addr[0] = 109;
  1396. state->CH_Ctrl[36].bit[0] = 1;
  1397. state->CH_Ctrl[36].val[0] = 1;
  1398. state->CH_Ctrl[37].Ctrl_Num = RFSYN_DIVM ;
  1399. state->CH_Ctrl[37].size = 2 ;
  1400. state->CH_Ctrl[37].addr[0] = 112;
  1401. state->CH_Ctrl[37].bit[0] = 5;
  1402. state->CH_Ctrl[37].val[0] = 0;
  1403. state->CH_Ctrl[37].addr[1] = 112;
  1404. state->CH_Ctrl[37].bit[1] = 6;
  1405. state->CH_Ctrl[37].val[1] = 0;
  1406. state->CH_Ctrl[38].Ctrl_Num = DN_BYPASS_AGC_I2C ;
  1407. state->CH_Ctrl[38].size = 1 ;
  1408. state->CH_Ctrl[38].addr[0] = 65;
  1409. state->CH_Ctrl[38].bit[0] = 1;
  1410. state->CH_Ctrl[38].val[0] = 0;
  1411. #endif
  1412. return 0 ;
  1413. }
  1414. static void InitTunerControls(struct dvb_frontend *fe)
  1415. {
  1416. MXL5005_RegisterInit(fe);
  1417. MXL5005_ControlInit(fe);
  1418. #ifdef _MXL_INTERNAL
  1419. MXL5005_MXLControlInit(fe);
  1420. #endif
  1421. }
  1422. static u16 MXL5005_TunerConfig(struct dvb_frontend *fe,
  1423. u8 Mode, /* 0: Analog Mode ; 1: Digital Mode */
  1424. u8 IF_mode, /* for Analog Mode, 0: zero IF; 1: low IF */
  1425. u32 Bandwidth, /* filter channel bandwidth (6, 7, 8) */
  1426. u32 IF_out, /* Desired IF Out Frequency */
  1427. u32 Fxtal, /* XTAL Frequency */
  1428. u8 AGC_Mode, /* AGC Mode - Dual AGC: 0, Single AGC: 1 */
  1429. u16 TOP, /* 0: Dual AGC; Value: take over point */
  1430. u16 IF_OUT_LOAD, /* IF Out Load Resistor (200 / 300 Ohms) */
  1431. u8 CLOCK_OUT, /* 0: turn off clk out; 1: turn on clock out */
  1432. u8 DIV_OUT, /* 0: Div-1; 1: Div-4 */
  1433. u8 CAPSELECT, /* 0: disable On-Chip pulling cap; 1: enable */
  1434. u8 EN_RSSI, /* 0: disable RSSI; 1: enable RSSI */
  1435. /* Modulation Type; */
  1436. /* 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */
  1437. u8 Mod_Type,
  1438. /* Tracking Filter */
  1439. /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */
  1440. u8 TF_Type
  1441. )
  1442. {
  1443. struct mxl5005s_state *state = fe->tuner_priv;
  1444. state->Mode = Mode;
  1445. state->IF_Mode = IF_mode;
  1446. state->Chan_Bandwidth = Bandwidth;
  1447. state->IF_OUT = IF_out;
  1448. state->Fxtal = Fxtal;
  1449. state->AGC_Mode = AGC_Mode;
  1450. state->TOP = TOP;
  1451. state->IF_OUT_LOAD = IF_OUT_LOAD;
  1452. state->CLOCK_OUT = CLOCK_OUT;
  1453. state->DIV_OUT = DIV_OUT;
  1454. state->CAPSELECT = CAPSELECT;
  1455. state->EN_RSSI = EN_RSSI;
  1456. state->Mod_Type = Mod_Type;
  1457. state->TF_Type = TF_Type;
  1458. /* Initialize all the controls and registers */
  1459. InitTunerControls(fe);
  1460. /* Synthesizer LO frequency calculation */
  1461. MXL_SynthIFLO_Calc(fe);
  1462. return 0;
  1463. }
  1464. static void MXL_SynthIFLO_Calc(struct dvb_frontend *fe)
  1465. {
  1466. struct mxl5005s_state *state = fe->tuner_priv;
  1467. if (state->Mode == 1) /* Digital Mode */
  1468. state->IF_LO = state->IF_OUT;
  1469. else /* Analog Mode */ {
  1470. if (state->IF_Mode == 0) /* Analog Zero IF mode */
  1471. state->IF_LO = state->IF_OUT + 400000;
  1472. else /* Analog Low IF mode */
  1473. state->IF_LO = state->IF_OUT + state->Chan_Bandwidth/2;
  1474. }
  1475. }
  1476. static void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe)
  1477. {
  1478. struct mxl5005s_state *state = fe->tuner_priv;
  1479. if (state->Mode == 1) /* Digital Mode */ {
  1480. /* remove 20.48MHz setting for 2.6.10 */
  1481. state->RF_LO = state->RF_IN;
  1482. /* change for 2.6.6 */
  1483. state->TG_LO = state->RF_IN - 750000;
  1484. } else /* Analog Mode */ {
  1485. if (state->IF_Mode == 0) /* Analog Zero IF mode */ {
  1486. state->RF_LO = state->RF_IN - 400000;
  1487. state->TG_LO = state->RF_IN - 1750000;
  1488. } else /* Analog Low IF mode */ {
  1489. state->RF_LO = state->RF_IN - state->Chan_Bandwidth/2;
  1490. state->TG_LO = state->RF_IN -
  1491. state->Chan_Bandwidth + 500000;
  1492. }
  1493. }
  1494. }
  1495. static u16 MXL_OverwriteICDefault(struct dvb_frontend *fe)
  1496. {
  1497. u16 status = 0;
  1498. status += MXL_ControlWrite(fe, OVERRIDE_1, 1);
  1499. status += MXL_ControlWrite(fe, OVERRIDE_2, 1);
  1500. status += MXL_ControlWrite(fe, OVERRIDE_3, 1);
  1501. status += MXL_ControlWrite(fe, OVERRIDE_4, 1);
  1502. return status;
  1503. }
  1504. static u16 MXL_BlockInit(struct dvb_frontend *fe)
  1505. {
  1506. struct mxl5005s_state *state = fe->tuner_priv;
  1507. u16 status = 0;
  1508. status += MXL_OverwriteICDefault(fe);
  1509. /* Downconverter Control Dig Ana */
  1510. status += MXL_ControlWrite(fe, DN_IQTN_AMP_CUT, state->Mode ? 1 : 0);
  1511. /* Filter Control Dig Ana */
  1512. status += MXL_ControlWrite(fe, BB_MODE, state->Mode ? 0 : 1);
  1513. status += MXL_ControlWrite(fe, BB_BUF, state->Mode ? 3 : 2);
  1514. status += MXL_ControlWrite(fe, BB_BUF_OA, state->Mode ? 1 : 0);
  1515. status += MXL_ControlWrite(fe, BB_IQSWAP, state->Mode ? 0 : 1);
  1516. status += MXL_ControlWrite(fe, BB_INITSTATE_DLPF_TUNE, 0);
  1517. /* Initialize Low-Pass Filter */
  1518. if (state->Mode) { /* Digital Mode */
  1519. switch (state->Chan_Bandwidth) {
  1520. case 8000000:
  1521. status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 0);
  1522. break;
  1523. case 7000000:
  1524. status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 2);
  1525. break;
  1526. case 6000000:
  1527. status += MXL_ControlWrite(fe,
  1528. BB_DLPF_BANDSEL, 3);
  1529. break;
  1530. }
  1531. } else { /* Analog Mode */
  1532. switch (state->Chan_Bandwidth) {
  1533. case 8000000: /* Low Zero */
  1534. status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT,
  1535. (state->IF_Mode ? 0 : 3));
  1536. break;
  1537. case 7000000:
  1538. status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT,
  1539. (state->IF_Mode ? 1 : 4));
  1540. break;
  1541. case 6000000:
  1542. status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT,
  1543. (state->IF_Mode ? 2 : 5));
  1544. break;
  1545. }
  1546. }
  1547. /* Charge Pump Control Dig Ana */
  1548. status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, state->Mode ? 5 : 8);
  1549. status += MXL_ControlWrite(fe,
  1550. RFSYN_EN_CHP_HIGAIN, state->Mode ? 1 : 1);
  1551. status += MXL_ControlWrite(fe, EN_CHP_LIN_B, state->Mode ? 0 : 0);
  1552. /* AGC TOP Control */
  1553. if (state->AGC_Mode == 0) /* Dual AGC */ {
  1554. status += MXL_ControlWrite(fe, AGC_IF, 15);
  1555. status += MXL_ControlWrite(fe, AGC_RF, 15);
  1556. } else /* Single AGC Mode Dig Ana */
  1557. status += MXL_ControlWrite(fe, AGC_RF, state->Mode ? 15 : 12);
  1558. if (state->TOP == 55) /* TOP == 5.5 */
  1559. status += MXL_ControlWrite(fe, AGC_IF, 0x0);
  1560. if (state->TOP == 72) /* TOP == 7.2 */
  1561. status += MXL_ControlWrite(fe, AGC_IF, 0x1);
  1562. if (state->TOP == 92) /* TOP == 9.2 */
  1563. status += MXL_ControlWrite(fe, AGC_IF, 0x2);
  1564. if (state->TOP == 110) /* TOP == 11.0 */
  1565. status += MXL_ControlWrite(fe, AGC_IF, 0x3);
  1566. if (state->TOP == 129) /* TOP == 12.9 */
  1567. status += MXL_ControlWrite(fe, AGC_IF, 0x4);
  1568. if (state->TOP == 147) /* TOP == 14.7 */
  1569. status += MXL_ControlWrite(fe, AGC_IF, 0x5);
  1570. if (state->TOP == 168) /* TOP == 16.8 */
  1571. status += MXL_ControlWrite(fe, AGC_IF, 0x6);
  1572. if (state->TOP == 194) /* TOP == 19.4 */
  1573. status += MXL_ControlWrite(fe, AGC_IF, 0x7);
  1574. if (state->TOP == 212) /* TOP == 21.2 */
  1575. status += MXL_ControlWrite(fe, AGC_IF, 0x9);
  1576. if (state->TOP == 232) /* TOP == 23.2 */
  1577. status += MXL_ControlWrite(fe, AGC_IF, 0xA);
  1578. if (state->TOP == 252) /* TOP == 25.2 */
  1579. status += MXL_ControlWrite(fe, AGC_IF, 0xB);
  1580. if (state->TOP == 271) /* TOP == 27.1 */
  1581. status += MXL_ControlWrite(fe, AGC_IF, 0xC);
  1582. if (state->TOP == 292) /* TOP == 29.2 */
  1583. status += MXL_ControlWrite(fe, AGC_IF, 0xD);
  1584. if (state->TOP == 317) /* TOP == 31.7 */
  1585. status += MXL_ControlWrite(fe, AGC_IF, 0xE);
  1586. if (state->TOP == 349) /* TOP == 34.9 */
  1587. status += MXL_ControlWrite(fe, AGC_IF, 0xF);
  1588. /* IF Synthesizer Control */
  1589. status += MXL_IFSynthInit(fe);
  1590. /* IF UpConverter Control */
  1591. if (state->IF_OUT_LOAD == 200) {
  1592. status += MXL_ControlWrite(fe, DRV_RES_SEL, 6);
  1593. status += MXL_ControlWrite(fe, I_DRIVER, 2);
  1594. }
  1595. if (state->IF_OUT_LOAD == 300) {
  1596. status += MXL_ControlWrite(fe, DRV_RES_SEL, 4);
  1597. status += MXL_ControlWrite(fe, I_DRIVER, 1);
  1598. }
  1599. /* Anti-Alias Filtering Control
  1600. * initialise Anti-Aliasing Filter
  1601. */
  1602. if (state->Mode) { /* Digital Mode */
  1603. if (state->IF_OUT >= 4000000UL && state->IF_OUT <= 6280000UL) {
  1604. status += MXL_ControlWrite(fe, EN_AAF, 1);
  1605. status += MXL_ControlWrite(fe, EN_3P, 1);
  1606. status += MXL_ControlWrite(fe, EN_AUX_3P, 1);
  1607. status += MXL_ControlWrite(fe, SEL_AAF_BAND, 0);
  1608. }
  1609. if ((state->IF_OUT == 36125000UL) ||
  1610. (state->IF_OUT == 36150000UL)) {
  1611. status += MXL_ControlWrite(fe, EN_AAF, 1);
  1612. status += MXL_ControlWrite(fe, EN_3P, 1);
  1613. status += MXL_ControlWrite(fe, EN_AUX_3P, 1);
  1614. status += MXL_ControlWrite(fe, SEL_AAF_BAND, 1);
  1615. }
  1616. if (state->IF_OUT > 36150000UL) {
  1617. status += MXL_ControlWrite(fe, EN_AAF, 0);
  1618. status += MXL_ControlWrite(fe, EN_3P, 1);
  1619. status += MXL_ControlWrite(fe, EN_AUX_3P, 1);
  1620. status += MXL_ControlWrite(fe, SEL_AAF_BAND, 1);
  1621. }
  1622. } else { /* Analog Mode */
  1623. if (state->IF_OUT >= 4000000UL && state->IF_OUT <= 5000000UL) {
  1624. status += MXL_ControlWrite(fe, EN_AAF, 1);
  1625. status += MXL_ControlWrite(fe, EN_3P, 1);
  1626. status += MXL_ControlWrite(fe, EN_AUX_3P, 1);
  1627. status += MXL_ControlWrite(fe, SEL_AAF_BAND, 0);
  1628. }
  1629. if (state->IF_OUT > 5000000UL) {
  1630. status += MXL_ControlWrite(fe, EN_AAF, 0);
  1631. status += MXL_ControlWrite(fe, EN_3P, 0);
  1632. status += MXL_ControlWrite(fe, EN_AUX_3P, 0);
  1633. status += MXL_ControlWrite(fe, SEL_AAF_BAND, 0);
  1634. }
  1635. }
  1636. /* Demod Clock Out */
  1637. if (state->CLOCK_OUT)
  1638. status += MXL_ControlWrite(fe, SEQ_ENCLK16_CLK_OUT, 1);
  1639. else
  1640. status += MXL_ControlWrite(fe, SEQ_ENCLK16_CLK_OUT, 0);
  1641. if (state->DIV_OUT == 1)
  1642. status += MXL_ControlWrite(fe, SEQ_SEL4_16B, 1);
  1643. if (state->DIV_OUT == 0)
  1644. status += MXL_ControlWrite(fe, SEQ_SEL4_16B, 0);
  1645. /* Crystal Control */
  1646. if (state->CAPSELECT)
  1647. status += MXL_ControlWrite(fe, XTAL_CAPSELECT, 1);
  1648. else
  1649. status += MXL_ControlWrite(fe, XTAL_CAPSELECT, 0);
  1650. if (state->Fxtal >= 12000000UL && state->Fxtal <= 16000000UL)
  1651. status += MXL_ControlWrite(fe, IF_SEL_DBL, 1);
  1652. if (state->Fxtal > 16000000UL && state->Fxtal <= 32000000UL)
  1653. status += MXL_ControlWrite(fe, IF_SEL_DBL, 0);
  1654. if (state->Fxtal >= 12000000UL && state->Fxtal <= 22000000UL)
  1655. status += MXL_ControlWrite(fe, RFSYN_R_DIV, 3);
  1656. if (state->Fxtal > 22000000UL && state->Fxtal <= 32000000UL)
  1657. status += MXL_ControlWrite(fe, RFSYN_R_DIV, 0);
  1658. /* Misc Controls */
  1659. if (state->Mode == 0 && state->IF_Mode == 1) /* Analog LowIF mode */
  1660. status += MXL_ControlWrite(fe, SEQ_EXTIQFSMPULSE, 0);
  1661. else
  1662. status += MXL_ControlWrite(fe, SEQ_EXTIQFSMPULSE, 1);
  1663. /* status += MXL_ControlRead(fe, IF_DIVVAL, &IF_DIVVAL_Val); */
  1664. /* Set TG_R_DIV */
  1665. status += MXL_ControlWrite(fe, TG_R_DIV,
  1666. MXL_Ceiling(state->Fxtal, 1000000));
  1667. /* Apply Default value to BB_INITSTATE_DLPF_TUNE */
  1668. /* RSSI Control */
  1669. if (state->EN_RSSI) {
  1670. status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
  1671. status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
  1672. status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1);
  1673. status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
  1674. /* RSSI reference point */
  1675. status += MXL_ControlWrite(fe, RFA_RSSI_REF, 2);
  1676. status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 3);
  1677. status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 1);
  1678. /* TOP point */
  1679. status += MXL_ControlWrite(fe, RFA_FLR, 0);
  1680. status += MXL_ControlWrite(fe, RFA_CEIL, 12);
  1681. }
  1682. /* Modulation type bit settings
  1683. * Override the control values preset
  1684. */
  1685. if (state->Mod_Type == MXL_DVBT) /* DVB-T Mode */ {
  1686. state->AGC_Mode = 1; /* Single AGC Mode */
  1687. /* Enable RSSI */
  1688. status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
  1689. status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
  1690. status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1);
  1691. status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
  1692. /* RSSI reference point */
  1693. status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3);
  1694. status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5);
  1695. status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 1);
  1696. /* TOP point */
  1697. status += MXL_ControlWrite(fe, RFA_FLR, 2);
  1698. status += MXL_ControlWrite(fe, RFA_CEIL, 13);
  1699. if (state->IF_OUT <= 6280000UL) /* Low IF */
  1700. status += MXL_ControlWrite(fe, BB_IQSWAP, 0);
  1701. else /* High IF */
  1702. status += MXL_ControlWrite(fe, BB_IQSWAP, 1);
  1703. }
  1704. if (state->Mod_Type == MXL_ATSC) /* ATSC Mode */ {
  1705. state->AGC_Mode = 1; /* Single AGC Mode */
  1706. /* Enable RSSI */
  1707. status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
  1708. status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
  1709. status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1);
  1710. status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
  1711. /* RSSI reference point */
  1712. status += MXL_ControlWrite(fe, RFA_RSSI_REF, 2);
  1713. status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 4);
  1714. status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 1);
  1715. /* TOP point */
  1716. status += MXL_ControlWrite(fe, RFA_FLR, 2);
  1717. status += MXL_ControlWrite(fe, RFA_CEIL, 13);
  1718. status += MXL_ControlWrite(fe, BB_INITSTATE_DLPF_TUNE, 1);
  1719. /* Low Zero */
  1720. status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 5);
  1721. if (state->IF_OUT <= 6280000UL) /* Low IF */
  1722. status += MXL_ControlWrite(fe, BB_IQSWAP, 0);
  1723. else /* High IF */
  1724. status += MXL_ControlWrite(fe, BB_IQSWAP, 1);
  1725. }
  1726. if (state->Mod_Type == MXL_QAM) /* QAM Mode */ {
  1727. state->Mode = MXL_DIGITAL_MODE;
  1728. /* state->AGC_Mode = 1; */ /* Single AGC Mode */
  1729. /* Disable RSSI */ /* change here for v2.6.5 */
  1730. status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
  1731. status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
  1732. status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0);
  1733. status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
  1734. /* RSSI reference point */
  1735. status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5);
  1736. status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3);
  1737. status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 2);
  1738. /* change here for v2.6.5 */
  1739. status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3);
  1740. if (state->IF_OUT <= 6280000UL) /* Low IF */
  1741. status += MXL_ControlWrite(fe, BB_IQSWAP, 0);
  1742. else /* High IF */
  1743. status += MXL_ControlWrite(fe, BB_IQSWAP, 1);
  1744. status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 2);
  1745. }
  1746. if (state->Mod_Type == MXL_ANALOG_CABLE) {
  1747. /* Analog Cable Mode */
  1748. /* state->Mode = MXL_DIGITAL_MODE; */
  1749. state->AGC_Mode = 1; /* Single AGC Mode */
  1750. /* Disable RSSI */
  1751. status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
  1752. status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
  1753. status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0);
  1754. status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
  1755. /* change for 2.6.3 */
  1756. status += MXL_ControlWrite(fe, AGC_IF, 1);
  1757. status += MXL_ControlWrite(fe, AGC_RF, 15);
  1758. status += MXL_ControlWrite(fe, BB_IQSWAP, 1);
  1759. }
  1760. if (state->Mod_Type == MXL_ANALOG_OTA) {
  1761. /* Analog OTA Terrestrial mode add for 2.6.7 */
  1762. /* state->Mode = MXL_ANALOG_MODE; */
  1763. /* Enable RSSI */
  1764. status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
  1765. status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
  1766. status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1);
  1767. status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
  1768. /* RSSI reference point */
  1769. status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5);
  1770. status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3);
  1771. status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 2);
  1772. status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3);
  1773. status += MXL_ControlWrite(fe, BB_IQSWAP, 1);
  1774. }
  1775. /* RSSI disable */
  1776. if (state->EN_RSSI == 0) {
  1777. status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
  1778. status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
  1779. status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0);
  1780. status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
  1781. }
  1782. return status;
  1783. }
  1784. static u16 MXL_IFSynthInit(struct dvb_frontend *fe)
  1785. {
  1786. struct mxl5005s_state *state = fe->tuner_priv;
  1787. u16 status = 0 ;
  1788. u32 Fref = 0 ;
  1789. u32 Kdbl, intModVal ;
  1790. u32 fracModVal ;
  1791. Kdbl = 2 ;
  1792. if (state->Fxtal >= 12000000UL && state->Fxtal <= 16000000UL)
  1793. Kdbl = 2 ;
  1794. if (state->Fxtal > 16000000UL && state->Fxtal <= 32000000UL)
  1795. Kdbl = 1 ;
  1796. /* IF Synthesizer Control */
  1797. if (state->Mode == 0 && state->IF_Mode == 1) /* Analog Low IF mode */ {
  1798. if (state->IF_LO == 41000000UL) {
  1799. status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
  1800. status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
  1801. Fref = 328000000UL ;
  1802. }
  1803. if (state->IF_LO == 47000000UL) {
  1804. status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
  1805. status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
  1806. Fref = 376000000UL ;
  1807. }
  1808. if (state->IF_LO == 54000000UL) {
  1809. status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10);
  1810. status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
  1811. Fref = 324000000UL ;
  1812. }
  1813. if (state->IF_LO == 60000000UL) {
  1814. status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10);
  1815. status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
  1816. Fref = 360000000UL ;
  1817. }
  1818. if (state->IF_LO == 39250000UL) {
  1819. status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
  1820. status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
  1821. Fref = 314000000UL ;
  1822. }
  1823. if (state->IF_LO == 39650000UL) {
  1824. status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
  1825. status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
  1826. Fref = 317200000UL ;
  1827. }
  1828. if (state->IF_LO == 40150000UL) {
  1829. status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
  1830. status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
  1831. Fref = 321200000UL ;
  1832. }
  1833. if (state->IF_LO == 40650000UL) {
  1834. status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
  1835. status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
  1836. Fref = 325200000UL ;
  1837. }
  1838. }
  1839. if (state->Mode || (state->Mode == 0 && state->IF_Mode == 0)) {
  1840. if (state->IF_LO == 57000000UL) {
  1841. status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10);
  1842. status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
  1843. Fref = 342000000UL ;
  1844. }
  1845. if (state->IF_LO == 44000000UL) {
  1846. status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
  1847. status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
  1848. Fref = 352000000UL ;
  1849. }
  1850. if (state->IF_LO == 43750000UL) {
  1851. status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
  1852. status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
  1853. Fref = 350000000UL ;
  1854. }
  1855. if (state->IF_LO == 36650000UL) {
  1856. status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04);
  1857. status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
  1858. Fref = 366500000UL ;
  1859. }
  1860. if (state->IF_LO == 36150000UL) {
  1861. status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04);
  1862. status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
  1863. Fref = 361500000UL ;
  1864. }
  1865. if (state->IF_LO == 36000000UL) {
  1866. status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04);
  1867. status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
  1868. Fref = 360000000UL ;
  1869. }
  1870. if (state->IF_LO == 35250000UL) {
  1871. status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04);
  1872. status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
  1873. Fref = 352500000UL ;
  1874. }
  1875. if (state->IF_LO == 34750000UL) {
  1876. status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04);
  1877. status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
  1878. Fref = 347500000UL ;
  1879. }
  1880. if (state->IF_LO == 6280000UL) {
  1881. status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07);
  1882. status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
  1883. Fref = 376800000UL ;
  1884. }
  1885. if (state->IF_LO == 5000000UL) {
  1886. status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09);
  1887. status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
  1888. Fref = 360000000UL ;
  1889. }
  1890. if (state->IF_LO == 4500000UL) {
  1891. status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06);
  1892. status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
  1893. Fref = 360000000UL ;
  1894. }
  1895. if (state->IF_LO == 4570000UL) {
  1896. status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06);
  1897. status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
  1898. Fref = 365600000UL ;
  1899. }
  1900. if (state->IF_LO == 4000000UL) {
  1901. status += MXL_ControlWrite(fe, IF_DIVVAL, 0x05);
  1902. status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
  1903. Fref = 360000000UL ;
  1904. }
  1905. if (state->IF_LO == 57400000UL) {
  1906. status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10);
  1907. status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
  1908. Fref = 344400000UL ;
  1909. }
  1910. if (state->IF_LO == 44400000UL) {
  1911. status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
  1912. status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
  1913. Fref = 355200000UL ;
  1914. }
  1915. if (state->IF_LO == 44150000UL) {
  1916. status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
  1917. status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
  1918. Fref = 353200000UL ;
  1919. }
  1920. if (state->IF_LO == 37050000UL) {
  1921. status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04);
  1922. status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
  1923. Fref = 370500000UL ;
  1924. }
  1925. if (state->IF_LO == 36550000UL) {
  1926. status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04);
  1927. status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
  1928. Fref = 365500000UL ;
  1929. }
  1930. if (state->IF_LO == 36125000UL) {
  1931. status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04);
  1932. status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
  1933. Fref = 361250000UL ;
  1934. }
  1935. if (state->IF_LO == 6000000UL) {
  1936. status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07);
  1937. status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
  1938. Fref = 360000000UL ;
  1939. }
  1940. if (state->IF_LO == 5400000UL) {
  1941. status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07);
  1942. status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
  1943. Fref = 324000000UL ;
  1944. }
  1945. if (state->IF_LO == 5380000UL) {
  1946. status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07);
  1947. status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
  1948. Fref = 322800000UL ;
  1949. }
  1950. if (state->IF_LO == 5200000UL) {
  1951. status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09);
  1952. status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
  1953. Fref = 374400000UL ;
  1954. }
  1955. if (state->IF_LO == 4900000UL) {
  1956. status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09);
  1957. status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
  1958. Fref = 352800000UL ;
  1959. }
  1960. if (state->IF_LO == 4400000UL) {
  1961. status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06);
  1962. status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
  1963. Fref = 352000000UL ;
  1964. }
  1965. if (state->IF_LO == 4063000UL) /* add for 2.6.8 */ {
  1966. status += MXL_ControlWrite(fe, IF_DIVVAL, 0x05);
  1967. status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
  1968. Fref = 365670000UL ;
  1969. }
  1970. }
  1971. /* CHCAL_INT_MOD_IF */
  1972. /* CHCAL_FRAC_MOD_IF */
  1973. intModVal = Fref / (state->Fxtal * Kdbl/2);
  1974. status += MXL_ControlWrite(fe, CHCAL_INT_MOD_IF, intModVal);
  1975. fracModVal = (2<<15)*(Fref/1000 - (state->Fxtal/1000 * Kdbl/2) *
  1976. intModVal);
  1977. fracModVal = fracModVal / ((state->Fxtal * Kdbl/2)/1000);
  1978. status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_IF, fracModVal);
  1979. return status ;
  1980. }
  1981. static u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq)
  1982. {
  1983. struct mxl5005s_state *state = fe->tuner_priv;
  1984. u16 status = 0;
  1985. u32 divider_val, E3, E4, E5, E5A;
  1986. u32 Fmax, Fmin, FmaxBin, FminBin;
  1987. u32 Kdbl_RF = 2;
  1988. u32 tg_divval;
  1989. u32 tg_lo;
  1990. u32 Fref_TG;
  1991. u32 Fvco;
  1992. state->RF_IN = RF_Freq;
  1993. MXL_SynthRFTGLO_Calc(fe);
  1994. if (state->Fxtal >= 12000000UL && state->Fxtal <= 22000000UL)
  1995. Kdbl_RF = 2;
  1996. if (state->Fxtal > 22000000 && state->Fxtal <= 32000000)
  1997. Kdbl_RF = 1;
  1998. /* Downconverter Controls
  1999. * Look-Up Table Implementation for:
  2000. * DN_POLY
  2001. * DN_RFGAIN
  2002. * DN_CAP_RFLPF
  2003. * DN_EN_VHFUHFBAR
  2004. * DN_GAIN_ADJUST
  2005. * Change the boundary reference from RF_IN to RF_LO
  2006. */
  2007. if (state->RF_LO < 40000000UL)
  2008. return -1;
  2009. if (state->RF_LO >= 40000000UL && state->RF_LO <= 75000000UL) {
  2010. status += MXL_ControlWrite(fe, DN_POLY, 2);
  2011. status += MXL_ControlWrite(fe, DN_RFGAIN, 3);
  2012. status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 423);
  2013. status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1);
  2014. status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 1);
  2015. }
  2016. if (state->RF_LO > 75000000UL && state->RF_LO <= 100000000UL) {
  2017. status += MXL_ControlWrite(fe, DN_POLY, 3);
  2018. status += MXL_ControlWrite(fe, DN_RFGAIN, 3);
  2019. status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 222);
  2020. status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1);
  2021. status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 1);
  2022. }
  2023. if (state->RF_LO > 100000000UL && state->RF_LO <= 150000000UL) {
  2024. status += MXL_ControlWrite(fe, DN_POLY, 3);
  2025. status += MXL_ControlWrite(fe, DN_RFGAIN, 3);
  2026. status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 147);
  2027. status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1);
  2028. status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 2);
  2029. }
  2030. if (state->RF_LO > 150000000UL && state->RF_LO <= 200000000UL) {
  2031. status += MXL_ControlWrite(fe, DN_POLY, 3);
  2032. status += MXL_ControlWrite(fe, DN_RFGAIN, 3);
  2033. status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 9);
  2034. status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1);
  2035. status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 2);
  2036. }
  2037. if (state->RF_LO > 200000000UL && state->RF_LO <= 300000000UL) {
  2038. status += MXL_ControlWrite(fe, DN_POLY, 3);
  2039. status += MXL_ControlWrite(fe, DN_RFGAIN, 3);
  2040. status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 0);
  2041. status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1);
  2042. status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 3);
  2043. }
  2044. if (state->RF_LO > 300000000UL && state->RF_LO <= 650000000UL) {
  2045. status += MXL_ControlWrite(fe, DN_POLY, 3);
  2046. status += MXL_ControlWrite(fe, DN_RFGAIN, 1);
  2047. status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 0);
  2048. status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 0);
  2049. status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 3);
  2050. }
  2051. if (state->RF_LO > 650000000UL && state->RF_LO <= 900000000UL) {
  2052. status += MXL_ControlWrite(fe, DN_POLY, 3);
  2053. status += MXL_ControlWrite(fe, DN_RFGAIN, 2);
  2054. status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 0);
  2055. status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 0);
  2056. status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 3);
  2057. }
  2058. if (state->RF_LO > 900000000UL)
  2059. return -1;
  2060. /* DN_IQTNBUF_AMP */
  2061. /* DN_IQTNGNBFBIAS_BST */
  2062. if (state->RF_LO >= 40000000UL && state->RF_LO <= 75000000UL) {
  2063. status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
  2064. status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
  2065. }
  2066. if (state->RF_LO > 75000000UL && state->RF_LO <= 100000000UL) {
  2067. status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
  2068. status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
  2069. }
  2070. if (state->RF_LO > 100000000UL && state->RF_LO <= 150000000UL) {
  2071. status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
  2072. status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
  2073. }
  2074. if (state->RF_LO > 150000000UL && state->RF_LO <= 200000000UL) {
  2075. status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
  2076. status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
  2077. }
  2078. if (state->RF_LO > 200000000UL && state->RF_LO <= 300000000UL) {
  2079. status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
  2080. status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
  2081. }
  2082. if (state->RF_LO > 300000000UL && state->RF_LO <= 400000000UL) {
  2083. status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
  2084. status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
  2085. }
  2086. if (state->RF_LO > 400000000UL && state->RF_LO <= 450000000UL) {
  2087. status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
  2088. status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
  2089. }
  2090. if (state->RF_LO > 450000000UL && state->RF_LO <= 500000000UL) {
  2091. status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
  2092. status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
  2093. }
  2094. if (state->RF_LO > 500000000UL && state->RF_LO <= 550000000UL) {
  2095. status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
  2096. status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
  2097. }
  2098. if (state->RF_LO > 550000000UL && state->RF_LO <= 600000000UL) {
  2099. status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
  2100. status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
  2101. }
  2102. if (state->RF_LO > 600000000UL && state->RF_LO <= 650000000UL) {
  2103. status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
  2104. status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
  2105. }
  2106. if (state->RF_LO > 650000000UL && state->RF_LO <= 700000000UL) {
  2107. status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
  2108. status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
  2109. }
  2110. if (state->RF_LO > 700000000UL && state->RF_LO <= 750000000UL) {
  2111. status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
  2112. status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
  2113. }
  2114. if (state->RF_LO > 750000000UL && state->RF_LO <= 800000000UL) {
  2115. status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
  2116. status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
  2117. }
  2118. if (state->RF_LO > 800000000UL && state->RF_LO <= 850000000UL) {
  2119. status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 10);
  2120. status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 1);
  2121. }
  2122. if (state->RF_LO > 850000000UL && state->RF_LO <= 900000000UL) {
  2123. status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 10);
  2124. status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 1);
  2125. }
  2126. /*
  2127. * Set RF Synth and LO Path Control
  2128. *
  2129. * Look-Up table implementation for:
  2130. * RFSYN_EN_OUTMUX
  2131. * RFSYN_SEL_VCO_OUT
  2132. * RFSYN_SEL_VCO_HI
  2133. * RFSYN_SEL_DIVM
  2134. * RFSYN_RF_DIV_BIAS
  2135. * DN_SEL_FREQ
  2136. *
  2137. * Set divider_val, Fmax, Fmix to use in Equations
  2138. */
  2139. FminBin = 28000000UL ;
  2140. FmaxBin = 42500000UL ;
  2141. if (state->RF_LO >= 40000000UL && state->RF_LO <= FmaxBin) {
  2142. status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1);
  2143. status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0);
  2144. status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
  2145. status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
  2146. status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
  2147. status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1);
  2148. divider_val = 64 ;
  2149. Fmax = FmaxBin ;
  2150. Fmin = FminBin ;
  2151. }
  2152. FminBin = 42500000UL ;
  2153. FmaxBin = 56000000UL ;
  2154. if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
  2155. status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1);
  2156. status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0);
  2157. status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
  2158. status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
  2159. status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
  2160. status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1);
  2161. divider_val = 64 ;
  2162. Fmax = FmaxBin ;
  2163. Fmin = FminBin ;
  2164. }
  2165. FminBin = 56000000UL ;
  2166. FmaxBin = 85000000UL ;
  2167. if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
  2168. status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
  2169. status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
  2170. status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
  2171. status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
  2172. status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
  2173. status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1);
  2174. divider_val = 32 ;
  2175. Fmax = FmaxBin ;
  2176. Fmin = FminBin ;
  2177. }
  2178. FminBin = 85000000UL ;
  2179. FmaxBin = 112000000UL ;
  2180. if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
  2181. status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
  2182. status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
  2183. status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
  2184. status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
  2185. status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
  2186. status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1);
  2187. divider_val = 32 ;
  2188. Fmax = FmaxBin ;
  2189. Fmin = FminBin ;
  2190. }
  2191. FminBin = 112000000UL ;
  2192. FmaxBin = 170000000UL ;
  2193. if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
  2194. status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
  2195. status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
  2196. status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
  2197. status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
  2198. status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
  2199. status += MXL_ControlWrite(fe, DN_SEL_FREQ, 2);
  2200. divider_val = 16 ;
  2201. Fmax = FmaxBin ;
  2202. Fmin = FminBin ;
  2203. }
  2204. FminBin = 170000000UL ;
  2205. FmaxBin = 225000000UL ;
  2206. if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
  2207. status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
  2208. status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
  2209. status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
  2210. status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
  2211. status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
  2212. status += MXL_ControlWrite(fe, DN_SEL_FREQ, 2);
  2213. divider_val = 16 ;
  2214. Fmax = FmaxBin ;
  2215. Fmin = FminBin ;
  2216. }
  2217. FminBin = 225000000UL ;
  2218. FmaxBin = 300000000UL ;
  2219. if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
  2220. status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
  2221. status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
  2222. status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
  2223. status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
  2224. status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
  2225. status += MXL_ControlWrite(fe, DN_SEL_FREQ, 4);
  2226. divider_val = 8 ;
  2227. Fmax = 340000000UL ;
  2228. Fmin = FminBin ;
  2229. }
  2230. FminBin = 300000000UL ;
  2231. FmaxBin = 340000000UL ;
  2232. if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
  2233. status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1);
  2234. status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0);
  2235. status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
  2236. status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
  2237. status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
  2238. status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
  2239. divider_val = 8 ;
  2240. Fmax = FmaxBin ;
  2241. Fmin = 225000000UL ;
  2242. }
  2243. FminBin = 340000000UL ;
  2244. FmaxBin = 450000000UL ;
  2245. if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
  2246. status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1);
  2247. status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0);
  2248. status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
  2249. status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
  2250. status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 2);
  2251. status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
  2252. divider_val = 8 ;
  2253. Fmax = FmaxBin ;
  2254. Fmin = FminBin ;
  2255. }
  2256. FminBin = 450000000UL ;
  2257. FmaxBin = 680000000UL ;
  2258. if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
  2259. status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
  2260. status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
  2261. status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
  2262. status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 1);
  2263. status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
  2264. status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
  2265. divider_val = 4 ;
  2266. Fmax = FmaxBin ;
  2267. Fmin = FminBin ;
  2268. }
  2269. FminBin = 680000000UL ;
  2270. FmaxBin = 900000000UL ;
  2271. if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
  2272. status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
  2273. status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
  2274. status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
  2275. status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 1);
  2276. status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
  2277. status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
  2278. divider_val = 4 ;
  2279. Fmax = FmaxBin ;
  2280. Fmin = FminBin ;
  2281. }
  2282. /* CHCAL_INT_MOD_RF
  2283. * CHCAL_FRAC_MOD_RF
  2284. * RFSYN_LPF_R
  2285. * CHCAL_EN_INT_RF
  2286. */
  2287. /* Equation E3 RFSYN_VCO_BIAS */
  2288. E3 = (((Fmax-state->RF_LO)/1000)*32)/((Fmax-Fmin)/1000) + 8 ;
  2289. status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, E3);
  2290. /* Equation E4 CHCAL_INT_MOD_RF */
  2291. E4 = (state->RF_LO*divider_val/1000)/(2*state->Fxtal*Kdbl_RF/1000);
  2292. MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, E4);
  2293. /* Equation E5 CHCAL_FRAC_MOD_RF CHCAL_EN_INT_RF */
  2294. E5 = ((2<<17)*(state->RF_LO/10000*divider_val -
  2295. (E4*(2*state->Fxtal*Kdbl_RF)/10000))) /
  2296. (2*state->Fxtal*Kdbl_RF/10000);
  2297. status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, E5);
  2298. /* Equation E5A RFSYN_LPF_R */
  2299. E5A = (((Fmax - state->RF_LO)/1000)*4/((Fmax-Fmin)/1000)) + 1 ;
  2300. status += MXL_ControlWrite(fe, RFSYN_LPF_R, E5A);
  2301. /* Euqation E5B CHCAL_EN_INIT_RF */
  2302. status += MXL_ControlWrite(fe, CHCAL_EN_INT_RF, ((E5 == 0) ? 1 : 0));
  2303. /*if (E5 == 0)
  2304. * status += MXL_ControlWrite(fe, CHCAL_EN_INT_RF, 1);
  2305. *else
  2306. * status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, E5);
  2307. */
  2308. /*
  2309. * Set TG Synth
  2310. *
  2311. * Look-Up table implementation for:
  2312. * TG_LO_DIVVAL
  2313. * TG_LO_SELVAL
  2314. *
  2315. * Set divider_val, Fmax, Fmix to use in Equations
  2316. */
  2317. if (state->TG_LO < 33000000UL)
  2318. return -1;
  2319. FminBin = 33000000UL ;
  2320. FmaxBin = 50000000UL ;
  2321. if (state->TG_LO >= FminBin && state->TG_LO <= FmaxBin) {
  2322. status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x6);
  2323. status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x0);
  2324. divider_val = 36 ;
  2325. Fmax = FmaxBin ;
  2326. Fmin = FminBin ;
  2327. }
  2328. FminBin = 50000000UL ;
  2329. FmaxBin = 67000000UL ;
  2330. if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
  2331. status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x1);
  2332. status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x0);
  2333. divider_val = 24 ;
  2334. Fmax = FmaxBin ;
  2335. Fmin = FminBin ;
  2336. }
  2337. FminBin = 67000000UL ;
  2338. FmaxBin = 100000000UL ;
  2339. if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
  2340. status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0xC);
  2341. status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x2);
  2342. divider_val = 18 ;
  2343. Fmax = FmaxBin ;
  2344. Fmin = FminBin ;
  2345. }
  2346. FminBin = 100000000UL ;
  2347. FmaxBin = 150000000UL ;
  2348. if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
  2349. status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x8);
  2350. status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x2);
  2351. divider_val = 12 ;
  2352. Fmax = FmaxBin ;
  2353. Fmin = FminBin ;
  2354. }
  2355. FminBin = 150000000UL ;
  2356. FmaxBin = 200000000UL ;
  2357. if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
  2358. status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x0);
  2359. status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x2);
  2360. divider_val = 8 ;
  2361. Fmax = FmaxBin ;
  2362. Fmin = FminBin ;
  2363. }
  2364. FminBin = 200000000UL ;
  2365. FmaxBin = 300000000UL ;
  2366. if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
  2367. status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x8);
  2368. status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x3);
  2369. divider_val = 6 ;
  2370. Fmax = FmaxBin ;
  2371. Fmin = FminBin ;
  2372. }
  2373. FminBin = 300000000UL ;
  2374. FmaxBin = 400000000UL ;
  2375. if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
  2376. status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x0);
  2377. status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x3);
  2378. divider_val = 4 ;
  2379. Fmax = FmaxBin ;
  2380. Fmin = FminBin ;
  2381. }
  2382. FminBin = 400000000UL ;
  2383. FmaxBin = 600000000UL ;
  2384. if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
  2385. status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x8);
  2386. status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x7);
  2387. divider_val = 3 ;
  2388. Fmax = FmaxBin ;
  2389. Fmin = FminBin ;
  2390. }
  2391. FminBin = 600000000UL ;
  2392. FmaxBin = 900000000UL ;
  2393. if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
  2394. status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x0);
  2395. status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x7);
  2396. divider_val = 2 ;
  2397. }
  2398. /* TG_DIV_VAL */
  2399. tg_divval = (state->TG_LO*divider_val/100000) *
  2400. (MXL_Ceiling(state->Fxtal, 1000000) * 100) /
  2401. (state->Fxtal/1000);
  2402. status += MXL_ControlWrite(fe, TG_DIV_VAL, tg_divval);
  2403. if (state->TG_LO > 600000000UL)
  2404. status += MXL_ControlWrite(fe, TG_DIV_VAL, tg_divval + 1);
  2405. Fmax = 1800000000UL ;
  2406. Fmin = 1200000000UL ;
  2407. /* prevent overflow of 32 bit unsigned integer, use
  2408. * following equation. Edit for v2.6.4
  2409. */
  2410. /* Fref_TF = Fref_TG * 1000 */
  2411. Fref_TG = (state->Fxtal/1000) / MXL_Ceiling(state->Fxtal, 1000000);
  2412. /* Fvco = Fvco/10 */
  2413. Fvco = (state->TG_LO/10000) * divider_val * Fref_TG;
  2414. tg_lo = (((Fmax/10 - Fvco)/100)*32) / ((Fmax-Fmin)/1000)+8;
  2415. /* below equation is same as above but much harder to debug.
  2416. *
  2417. * static u32 MXL_GetXtalInt(u32 Xtal_Freq)
  2418. * {
  2419. * if ((Xtal_Freq % 1000000) == 0)
  2420. * return (Xtal_Freq / 10000);
  2421. * else
  2422. * return (((Xtal_Freq / 1000000) + 1)*100);
  2423. * }
  2424. *
  2425. * u32 Xtal_Int = MXL_GetXtalInt(state->Fxtal);
  2426. * tg_lo = ( ((Fmax/10000 * Xtal_Int)/100) -
  2427. * ((state->TG_LO/10000)*divider_val *
  2428. * (state->Fxtal/10000)/100) )*32/((Fmax-Fmin)/10000 *
  2429. * Xtal_Int/100) + 8;
  2430. */
  2431. status += MXL_ControlWrite(fe, TG_VCO_BIAS , tg_lo);
  2432. /* add for 2.6.5 Special setting for QAM */
  2433. if (state->Mod_Type == MXL_QAM) {
  2434. if (state->config->qam_gain != 0)
  2435. status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN,
  2436. state->config->qam_gain);
  2437. else if (state->RF_IN < 680000000)
  2438. status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3);
  2439. else
  2440. status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 2);
  2441. }
  2442. /* Off Chip Tracking Filter Control */
  2443. if (state->TF_Type == MXL_TF_OFF) {
  2444. /* Tracking Filter Off State; turn off all the banks */
  2445. status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
  2446. status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
  2447. status += MXL_SetGPIO(fe, 3, 1); /* Bank1 Off */
  2448. status += MXL_SetGPIO(fe, 1, 1); /* Bank2 Off */
  2449. status += MXL_SetGPIO(fe, 4, 1); /* Bank3 Off */
  2450. }
  2451. if (state->TF_Type == MXL_TF_C) /* Tracking Filter type C */ {
  2452. status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
  2453. status += MXL_ControlWrite(fe, DAC_DIN_A, 0);
  2454. if (state->RF_IN >= 43000000 && state->RF_IN < 150000000) {
  2455. status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
  2456. status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
  2457. status += MXL_SetGPIO(fe, 3, 0);
  2458. status += MXL_SetGPIO(fe, 1, 1);
  2459. status += MXL_SetGPIO(fe, 4, 1);
  2460. }
  2461. if (state->RF_IN >= 150000000 && state->RF_IN < 280000000) {
  2462. status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
  2463. status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
  2464. status += MXL_SetGPIO(fe, 3, 1);
  2465. status += MXL_SetGPIO(fe, 1, 0);
  2466. status += MXL_SetGPIO(fe, 4, 1);
  2467. }
  2468. if (state->RF_IN >= 280000000 && state->RF_IN < 360000000) {
  2469. status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
  2470. status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
  2471. status += MXL_SetGPIO(fe, 3, 1);
  2472. status += MXL_SetGPIO(fe, 1, 0);
  2473. status += MXL_SetGPIO(fe, 4, 0);
  2474. }
  2475. if (state->RF_IN >= 360000000 && state->RF_IN < 560000000) {
  2476. status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
  2477. status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
  2478. status += MXL_SetGPIO(fe, 3, 1);
  2479. status += MXL_SetGPIO(fe, 1, 1);
  2480. status += MXL_SetGPIO(fe, 4, 0);
  2481. }
  2482. if (state->RF_IN >= 560000000 && state->RF_IN < 580000000) {
  2483. status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
  2484. status += MXL_ControlWrite(fe, DAC_DIN_B, 29);
  2485. status += MXL_SetGPIO(fe, 3, 1);
  2486. status += MXL_SetGPIO(fe, 1, 1);
  2487. status += MXL_SetGPIO(fe, 4, 0);
  2488. }
  2489. if (state->RF_IN >= 580000000 && state->RF_IN < 630000000) {
  2490. status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
  2491. status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
  2492. status += MXL_SetGPIO(fe, 3, 1);
  2493. status += MXL_SetGPIO(fe, 1, 1);
  2494. status += MXL_SetGPIO(fe, 4, 0);
  2495. }
  2496. if (state->RF_IN >= 630000000 && state->RF_IN < 700000000) {
  2497. status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
  2498. status += MXL_ControlWrite(fe, DAC_DIN_B, 16);
  2499. status += MXL_SetGPIO(fe, 3, 1);
  2500. status += MXL_SetGPIO(fe, 1, 1);
  2501. status += MXL_SetGPIO(fe, 4, 1);
  2502. }
  2503. if (state->RF_IN >= 700000000 && state->RF_IN < 760000000) {
  2504. status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
  2505. status += MXL_ControlWrite(fe, DAC_DIN_B, 7);
  2506. status += MXL_SetGPIO(fe, 3, 1);
  2507. status += MXL_SetGPIO(fe, 1, 1);
  2508. status += MXL_SetGPIO(fe, 4, 1);
  2509. }
  2510. if (state->RF_IN >= 760000000 && state->RF_IN <= 900000000) {
  2511. status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
  2512. status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
  2513. status += MXL_SetGPIO(fe, 3, 1);
  2514. status += MXL_SetGPIO(fe, 1, 1);
  2515. status += MXL_SetGPIO(fe, 4, 1);
  2516. }
  2517. }
  2518. if (state->TF_Type == MXL_TF_C_H) {
  2519. /* Tracking Filter type C-H for Hauppauge only */
  2520. status += MXL_ControlWrite(fe, DAC_DIN_A, 0);
  2521. if (state->RF_IN >= 43000000 && state->RF_IN < 150000000) {
  2522. status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
  2523. status += MXL_SetGPIO(fe, 4, 0);
  2524. status += MXL_SetGPIO(fe, 3, 1);
  2525. status += MXL_SetGPIO(fe, 1, 1);
  2526. }
  2527. if (state->RF_IN >= 150000000 && state->RF_IN < 280000000) {
  2528. status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
  2529. status += MXL_SetGPIO(fe, 4, 1);
  2530. status += MXL_SetGPIO(fe, 3, 0);
  2531. status += MXL_SetGPIO(fe, 1, 1);
  2532. }
  2533. if (state->RF_IN >= 280000000 && state->RF_IN < 360000000) {
  2534. status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
  2535. status += MXL_SetGPIO(fe, 4, 1);
  2536. status += MXL_SetGPIO(fe, 3, 0);
  2537. status += MXL_SetGPIO(fe, 1, 0);
  2538. }
  2539. if (state->RF_IN >= 360000000 && state->RF_IN < 560000000) {
  2540. status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
  2541. status += MXL_SetGPIO(fe, 4, 1);
  2542. status += MXL_SetGPIO(fe, 3, 1);
  2543. status += MXL_SetGPIO(fe, 1, 0);
  2544. }
  2545. if (state->RF_IN >= 560000000 && state->RF_IN < 580000000) {
  2546. status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
  2547. status += MXL_SetGPIO(fe, 4, 1);
  2548. status += MXL_SetGPIO(fe, 3, 1);
  2549. status += MXL_SetGPIO(fe, 1, 0);
  2550. }
  2551. if (state->RF_IN >= 580000000 && state->RF_IN < 630000000) {
  2552. status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
  2553. status += MXL_SetGPIO(fe, 4, 1);
  2554. status += MXL_SetGPIO(fe, 3, 1);
  2555. status += MXL_SetGPIO(fe, 1, 0);
  2556. }
  2557. if (state->RF_IN >= 630000000 && state->RF_IN < 700000000) {
  2558. status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
  2559. status += MXL_SetGPIO(fe, 4, 1);
  2560. status += MXL_SetGPIO(fe, 3, 1);
  2561. status += MXL_SetGPIO(fe, 1, 1);
  2562. }
  2563. if (state->RF_IN >= 700000000 && state->RF_IN < 760000000) {
  2564. status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
  2565. status += MXL_SetGPIO(fe, 4, 1);
  2566. status += MXL_SetGPIO(fe, 3, 1);
  2567. status += MXL_SetGPIO(fe, 1, 1);
  2568. }
  2569. if (state->RF_IN >= 760000000 && state->RF_IN <= 900000000) {
  2570. status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
  2571. status += MXL_SetGPIO(fe, 4, 1);
  2572. status += MXL_SetGPIO(fe, 3, 1);
  2573. status += MXL_SetGPIO(fe, 1, 1);
  2574. }
  2575. }
  2576. if (state->TF_Type == MXL_TF_D) { /* Tracking Filter type D */
  2577. status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
  2578. if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) {
  2579. status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
  2580. status += MXL_SetGPIO(fe, 4, 0);
  2581. status += MXL_SetGPIO(fe, 1, 1);
  2582. status += MXL_SetGPIO(fe, 3, 1);
  2583. }
  2584. if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) {
  2585. status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
  2586. status += MXL_SetGPIO(fe, 4, 0);
  2587. status += MXL_SetGPIO(fe, 1, 0);
  2588. status += MXL_SetGPIO(fe, 3, 1);
  2589. }
  2590. if (state->RF_IN >= 250000000 && state->RF_IN < 310000000) {
  2591. status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
  2592. status += MXL_SetGPIO(fe, 4, 1);
  2593. status += MXL_SetGPIO(fe, 1, 0);
  2594. status += MXL_SetGPIO(fe, 3, 1);
  2595. }
  2596. if (state->RF_IN >= 310000000 && state->RF_IN < 360000000) {
  2597. status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
  2598. status += MXL_SetGPIO(fe, 4, 1);
  2599. status += MXL_SetGPIO(fe, 1, 0);
  2600. status += MXL_SetGPIO(fe, 3, 0);
  2601. }
  2602. if (state->RF_IN >= 360000000 && state->RF_IN < 470000000) {
  2603. status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
  2604. status += MXL_SetGPIO(fe, 4, 1);
  2605. status += MXL_SetGPIO(fe, 1, 1);
  2606. status += MXL_SetGPIO(fe, 3, 0);
  2607. }
  2608. if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) {
  2609. status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
  2610. status += MXL_SetGPIO(fe, 4, 1);
  2611. status += MXL_SetGPIO(fe, 1, 1);
  2612. status += MXL_SetGPIO(fe, 3, 0);
  2613. }
  2614. if (state->RF_IN >= 640000000 && state->RF_IN <= 900000000) {
  2615. status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
  2616. status += MXL_SetGPIO(fe, 4, 1);
  2617. status += MXL_SetGPIO(fe, 1, 1);
  2618. status += MXL_SetGPIO(fe, 3, 1);
  2619. }
  2620. }
  2621. if (state->TF_Type == MXL_TF_D_L) {
  2622. /* Tracking Filter type D-L for Lumanate ONLY change 2.6.3 */
  2623. status += MXL_ControlWrite(fe, DAC_DIN_A, 0);
  2624. /* if UHF and terrestrial => Turn off Tracking Filter */
  2625. if (state->RF_IN >= 471000000 &&
  2626. (state->RF_IN - 471000000)%6000000 != 0) {
  2627. /* Turn off all the banks */
  2628. status += MXL_SetGPIO(fe, 3, 1);
  2629. status += MXL_SetGPIO(fe, 1, 1);
  2630. status += MXL_SetGPIO(fe, 4, 1);
  2631. status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
  2632. status += MXL_ControlWrite(fe, AGC_IF, 10);
  2633. } else {
  2634. /* if VHF or cable => Turn on Tracking Filter */
  2635. if (state->RF_IN >= 43000000 &&
  2636. state->RF_IN < 140000000) {
  2637. status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
  2638. status += MXL_SetGPIO(fe, 4, 1);
  2639. status += MXL_SetGPIO(fe, 1, 1);
  2640. status += MXL_SetGPIO(fe, 3, 0);
  2641. }
  2642. if (state->RF_IN >= 140000000 &&
  2643. state->RF_IN < 240000000) {
  2644. status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
  2645. status += MXL_SetGPIO(fe, 4, 1);
  2646. status += MXL_SetGPIO(fe, 1, 0);
  2647. status += MXL_SetGPIO(fe, 3, 0);
  2648. }
  2649. if (state->RF_IN >= 240000000 &&
  2650. state->RF_IN < 340000000) {
  2651. status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
  2652. status += MXL_SetGPIO(fe, 4, 0);
  2653. status += MXL_SetGPIO(fe, 1, 1);
  2654. status += MXL_SetGPIO(fe, 3, 0);
  2655. }
  2656. if (state->RF_IN >= 340000000 &&
  2657. state->RF_IN < 430000000) {
  2658. status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
  2659. status += MXL_SetGPIO(fe, 4, 0);
  2660. status += MXL_SetGPIO(fe, 1, 0);
  2661. status += MXL_SetGPIO(fe, 3, 1);
  2662. }
  2663. if (state->RF_IN >= 430000000 &&
  2664. state->RF_IN < 470000000) {
  2665. status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
  2666. status += MXL_SetGPIO(fe, 4, 1);
  2667. status += MXL_SetGPIO(fe, 1, 0);
  2668. status += MXL_SetGPIO(fe, 3, 1);
  2669. }
  2670. if (state->RF_IN >= 470000000 &&
  2671. state->RF_IN < 570000000) {
  2672. status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
  2673. status += MXL_SetGPIO(fe, 4, 0);
  2674. status += MXL_SetGPIO(fe, 1, 0);
  2675. status += MXL_SetGPIO(fe, 3, 1);
  2676. }
  2677. if (state->RF_IN >= 570000000 &&
  2678. state->RF_IN < 620000000) {
  2679. status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
  2680. status += MXL_SetGPIO(fe, 4, 0);
  2681. status += MXL_SetGPIO(fe, 1, 1);
  2682. status += MXL_SetGPIO(fe, 3, 1);
  2683. }
  2684. if (state->RF_IN >= 620000000 &&
  2685. state->RF_IN < 760000000) {
  2686. status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
  2687. status += MXL_SetGPIO(fe, 4, 0);
  2688. status += MXL_SetGPIO(fe, 1, 1);
  2689. status += MXL_SetGPIO(fe, 3, 1);
  2690. }
  2691. if (state->RF_IN >= 760000000 &&
  2692. state->RF_IN <= 900000000) {
  2693. status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
  2694. status += MXL_SetGPIO(fe, 4, 1);
  2695. status += MXL_SetGPIO(fe, 1, 1);
  2696. status += MXL_SetGPIO(fe, 3, 1);
  2697. }
  2698. }
  2699. }
  2700. if (state->TF_Type == MXL_TF_E) /* Tracking Filter type E */ {
  2701. status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
  2702. if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) {
  2703. status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
  2704. status += MXL_SetGPIO(fe, 4, 0);
  2705. status += MXL_SetGPIO(fe, 1, 1);
  2706. status += MXL_SetGPIO(fe, 3, 1);
  2707. }
  2708. if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) {
  2709. status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
  2710. status += MXL_SetGPIO(fe, 4, 0);
  2711. status += MXL_SetGPIO(fe, 1, 0);
  2712. status += MXL_SetGPIO(fe, 3, 1);
  2713. }
  2714. if (state->RF_IN >= 250000000 && state->RF_IN < 310000000) {
  2715. status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
  2716. status += MXL_SetGPIO(fe, 4, 1);
  2717. status += MXL_SetGPIO(fe, 1, 0);
  2718. status += MXL_SetGPIO(fe, 3, 1);
  2719. }
  2720. if (state->RF_IN >= 310000000 && state->RF_IN < 360000000) {
  2721. status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
  2722. status += MXL_SetGPIO(fe, 4, 1);
  2723. status += MXL_SetGPIO(fe, 1, 0);
  2724. status += MXL_SetGPIO(fe, 3, 0);
  2725. }
  2726. if (state->RF_IN >= 360000000 && state->RF_IN < 470000000) {
  2727. status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
  2728. status += MXL_SetGPIO(fe, 4, 1);
  2729. status += MXL_SetGPIO(fe, 1, 1);
  2730. status += MXL_SetGPIO(fe, 3, 0);
  2731. }
  2732. if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) {
  2733. status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
  2734. status += MXL_SetGPIO(fe, 4, 1);
  2735. status += MXL_SetGPIO(fe, 1, 1);
  2736. status += MXL_SetGPIO(fe, 3, 0);
  2737. }
  2738. if (state->RF_IN >= 640000000 && state->RF_IN <= 900000000) {
  2739. status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
  2740. status += MXL_SetGPIO(fe, 4, 1);
  2741. status += MXL_SetGPIO(fe, 1, 1);
  2742. status += MXL_SetGPIO(fe, 3, 1);
  2743. }
  2744. }
  2745. if (state->TF_Type == MXL_TF_F) {
  2746. /* Tracking Filter type F */
  2747. status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
  2748. if (state->RF_IN >= 43000000 && state->RF_IN < 160000000) {
  2749. status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
  2750. status += MXL_SetGPIO(fe, 4, 0);
  2751. status += MXL_SetGPIO(fe, 1, 1);
  2752. status += MXL_SetGPIO(fe, 3, 1);
  2753. }
  2754. if (state->RF_IN >= 160000000 && state->RF_IN < 210000000) {
  2755. status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
  2756. status += MXL_SetGPIO(fe, 4, 0);
  2757. status += MXL_SetGPIO(fe, 1, 0);
  2758. status += MXL_SetGPIO(fe, 3, 1);
  2759. }
  2760. if (state->RF_IN >= 210000000 && state->RF_IN < 300000000) {
  2761. status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
  2762. status += MXL_SetGPIO(fe, 4, 1);
  2763. status += MXL_SetGPIO(fe, 1, 0);
  2764. status += MXL_SetGPIO(fe, 3, 1);
  2765. }
  2766. if (state->RF_IN >= 300000000 && state->RF_IN < 390000000) {
  2767. status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
  2768. status += MXL_SetGPIO(fe, 4, 1);
  2769. status += MXL_SetGPIO(fe, 1, 0);
  2770. status += MXL_SetGPIO(fe, 3, 0);
  2771. }
  2772. if (state->RF_IN >= 390000000 && state->RF_IN < 515000000) {
  2773. status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
  2774. status += MXL_SetGPIO(fe, 4, 1);
  2775. status += MXL_SetGPIO(fe, 1, 1);
  2776. status += MXL_SetGPIO(fe, 3, 0);
  2777. }
  2778. if (state->RF_IN >= 515000000 && state->RF_IN < 650000000) {
  2779. status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
  2780. status += MXL_SetGPIO(fe, 4, 1);
  2781. status += MXL_SetGPIO(fe, 1, 1);
  2782. status += MXL_SetGPIO(fe, 3, 0);
  2783. }
  2784. if (state->RF_IN >= 650000000 && state->RF_IN <= 900000000) {
  2785. status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
  2786. status += MXL_SetGPIO(fe, 4, 1);
  2787. status += MXL_SetGPIO(fe, 1, 1);
  2788. status += MXL_SetGPIO(fe, 3, 1);
  2789. }
  2790. }
  2791. if (state->TF_Type == MXL_TF_E_2) {
  2792. /* Tracking Filter type E_2 */
  2793. status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
  2794. if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) {
  2795. status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
  2796. status += MXL_SetGPIO(fe, 4, 0);
  2797. status += MXL_SetGPIO(fe, 1, 1);
  2798. status += MXL_SetGPIO(fe, 3, 1);
  2799. }
  2800. if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) {
  2801. status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
  2802. status += MXL_SetGPIO(fe, 4, 0);
  2803. status += MXL_SetGPIO(fe, 1, 0);
  2804. status += MXL_SetGPIO(fe, 3, 1);
  2805. }
  2806. if (state->RF_IN >= 250000000 && state->RF_IN < 350000000) {
  2807. status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
  2808. status += MXL_SetGPIO(fe, 4, 1);
  2809. status += MXL_SetGPIO(fe, 1, 0);
  2810. status += MXL_SetGPIO(fe, 3, 1);
  2811. }
  2812. if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) {
  2813. status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
  2814. status += MXL_SetGPIO(fe, 4, 1);
  2815. status += MXL_SetGPIO(fe, 1, 0);
  2816. status += MXL_SetGPIO(fe, 3, 0);
  2817. }
  2818. if (state->RF_IN >= 400000000 && state->RF_IN < 570000000) {
  2819. status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
  2820. status += MXL_SetGPIO(fe, 4, 1);
  2821. status += MXL_SetGPIO(fe, 1, 1);
  2822. status += MXL_SetGPIO(fe, 3, 0);
  2823. }
  2824. if (state->RF_IN >= 570000000 && state->RF_IN < 770000000) {
  2825. status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
  2826. status += MXL_SetGPIO(fe, 4, 1);
  2827. status += MXL_SetGPIO(fe, 1, 1);
  2828. status += MXL_SetGPIO(fe, 3, 0);
  2829. }
  2830. if (state->RF_IN >= 770000000 && state->RF_IN <= 900000000) {
  2831. status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
  2832. status += MXL_SetGPIO(fe, 4, 1);
  2833. status += MXL_SetGPIO(fe, 1, 1);
  2834. status += MXL_SetGPIO(fe, 3, 1);
  2835. }
  2836. }
  2837. if (state->TF_Type == MXL_TF_G) {
  2838. /* Tracking Filter type G add for v2.6.8 */
  2839. status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
  2840. if (state->RF_IN >= 50000000 && state->RF_IN < 190000000) {
  2841. status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
  2842. status += MXL_SetGPIO(fe, 4, 0);
  2843. status += MXL_SetGPIO(fe, 1, 1);
  2844. status += MXL_SetGPIO(fe, 3, 1);
  2845. }
  2846. if (state->RF_IN >= 190000000 && state->RF_IN < 280000000) {
  2847. status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
  2848. status += MXL_SetGPIO(fe, 4, 0);
  2849. status += MXL_SetGPIO(fe, 1, 0);
  2850. status += MXL_SetGPIO(fe, 3, 1);
  2851. }
  2852. if (state->RF_IN >= 280000000 && state->RF_IN < 350000000) {
  2853. status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
  2854. status += MXL_SetGPIO(fe, 4, 1);
  2855. status += MXL_SetGPIO(fe, 1, 0);
  2856. status += MXL_SetGPIO(fe, 3, 1);
  2857. }
  2858. if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) {
  2859. status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
  2860. status += MXL_SetGPIO(fe, 4, 1);
  2861. status += MXL_SetGPIO(fe, 1, 0);
  2862. status += MXL_SetGPIO(fe, 3, 0);
  2863. }
  2864. if (state->RF_IN >= 400000000 && state->RF_IN < 470000000) {
  2865. status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
  2866. status += MXL_SetGPIO(fe, 4, 1);
  2867. status += MXL_SetGPIO(fe, 1, 0);
  2868. status += MXL_SetGPIO(fe, 3, 1);
  2869. }
  2870. if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) {
  2871. status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
  2872. status += MXL_SetGPIO(fe, 4, 1);
  2873. status += MXL_SetGPIO(fe, 1, 1);
  2874. status += MXL_SetGPIO(fe, 3, 0);
  2875. }
  2876. if (state->RF_IN >= 640000000 && state->RF_IN < 820000000) {
  2877. status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
  2878. status += MXL_SetGPIO(fe, 4, 1);
  2879. status += MXL_SetGPIO(fe, 1, 1);
  2880. status += MXL_SetGPIO(fe, 3, 0);
  2881. }
  2882. if (state->RF_IN >= 820000000 && state->RF_IN <= 900000000) {
  2883. status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
  2884. status += MXL_SetGPIO(fe, 4, 1);
  2885. status += MXL_SetGPIO(fe, 1, 1);
  2886. status += MXL_SetGPIO(fe, 3, 1);
  2887. }
  2888. }
  2889. if (state->TF_Type == MXL_TF_E_NA) {
  2890. /* Tracking Filter type E-NA for Empia ONLY change for 2.6.8 */
  2891. status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
  2892. /* if UHF and terrestrial=> Turn off Tracking Filter */
  2893. if (state->RF_IN >= 471000000 &&
  2894. (state->RF_IN - 471000000)%6000000 != 0) {
  2895. /* Turn off all the banks */
  2896. status += MXL_SetGPIO(fe, 3, 1);
  2897. status += MXL_SetGPIO(fe, 1, 1);
  2898. status += MXL_SetGPIO(fe, 4, 1);
  2899. status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
  2900. /* 2.6.12 Turn on RSSI */
  2901. status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
  2902. status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
  2903. status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1);
  2904. status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
  2905. /* RSSI reference point */
  2906. status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5);
  2907. status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3);
  2908. status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 2);
  2909. /* following parameter is from analog OTA mode,
  2910. * can be change to seek better performance */
  2911. status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3);
  2912. } else {
  2913. /* if VHF or Cable => Turn on Tracking Filter */
  2914. /* 2.6.12 Turn off RSSI */
  2915. status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0);
  2916. /* change back from above condition */
  2917. status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 5);
  2918. if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) {
  2919. status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
  2920. status += MXL_SetGPIO(fe, 4, 0);
  2921. status += MXL_SetGPIO(fe, 1, 1);
  2922. status += MXL_SetGPIO(fe, 3, 1);
  2923. }
  2924. if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) {
  2925. status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
  2926. status += MXL_SetGPIO(fe, 4, 0);
  2927. status += MXL_SetGPIO(fe, 1, 0);
  2928. status += MXL_SetGPIO(fe, 3, 1);
  2929. }
  2930. if (state->RF_IN >= 250000000 && state->RF_IN < 350000000) {
  2931. status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
  2932. status += MXL_SetGPIO(fe, 4, 1);
  2933. status += MXL_SetGPIO(fe, 1, 0);
  2934. status += MXL_SetGPIO(fe, 3, 1);
  2935. }
  2936. if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) {
  2937. status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
  2938. status += MXL_SetGPIO(fe, 4, 1);
  2939. status += MXL_SetGPIO(fe, 1, 0);
  2940. status += MXL_SetGPIO(fe, 3, 0);
  2941. }
  2942. if (state->RF_IN >= 400000000 && state->RF_IN < 570000000) {
  2943. status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
  2944. status += MXL_SetGPIO(fe, 4, 1);
  2945. status += MXL_SetGPIO(fe, 1, 1);
  2946. status += MXL_SetGPIO(fe, 3, 0);
  2947. }
  2948. if (state->RF_IN >= 570000000 && state->RF_IN < 770000000) {
  2949. status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
  2950. status += MXL_SetGPIO(fe, 4, 1);
  2951. status += MXL_SetGPIO(fe, 1, 1);
  2952. status += MXL_SetGPIO(fe, 3, 0);
  2953. }
  2954. if (state->RF_IN >= 770000000 && state->RF_IN <= 900000000) {
  2955. status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
  2956. status += MXL_SetGPIO(fe, 4, 1);
  2957. status += MXL_SetGPIO(fe, 1, 1);
  2958. status += MXL_SetGPIO(fe, 3, 1);
  2959. }
  2960. }
  2961. }
  2962. return status ;
  2963. }
  2964. static u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val)
  2965. {
  2966. u16 status = 0;
  2967. if (GPIO_Num == 1)
  2968. status += MXL_ControlWrite(fe, GPIO_1B, GPIO_Val ? 0 : 1);
  2969. /* GPIO2 is not available */
  2970. if (GPIO_Num == 3) {
  2971. if (GPIO_Val == 1) {
  2972. status += MXL_ControlWrite(fe, GPIO_3, 0);
  2973. status += MXL_ControlWrite(fe, GPIO_3B, 0);
  2974. }
  2975. if (GPIO_Val == 0) {
  2976. status += MXL_ControlWrite(fe, GPIO_3, 1);
  2977. status += MXL_ControlWrite(fe, GPIO_3B, 1);
  2978. }
  2979. if (GPIO_Val == 3) { /* tri-state */
  2980. status += MXL_ControlWrite(fe, GPIO_3, 0);
  2981. status += MXL_ControlWrite(fe, GPIO_3B, 1);
  2982. }
  2983. }
  2984. if (GPIO_Num == 4) {
  2985. if (GPIO_Val == 1) {
  2986. status += MXL_ControlWrite(fe, GPIO_4, 0);
  2987. status += MXL_ControlWrite(fe, GPIO_4B, 0);
  2988. }
  2989. if (GPIO_Val == 0) {
  2990. status += MXL_ControlWrite(fe, GPIO_4, 1);
  2991. status += MXL_ControlWrite(fe, GPIO_4B, 1);
  2992. }
  2993. if (GPIO_Val == 3) { /* tri-state */
  2994. status += MXL_ControlWrite(fe, GPIO_4, 0);
  2995. status += MXL_ControlWrite(fe, GPIO_4B, 1);
  2996. }
  2997. }
  2998. return status;
  2999. }
  3000. static u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value)
  3001. {
  3002. u16 status = 0;
  3003. /* Will write ALL Matching Control Name */
  3004. /* Write Matching INIT Control */
  3005. status += MXL_ControlWrite_Group(fe, ControlNum, value, 1);
  3006. /* Write Matching CH Control */
  3007. status += MXL_ControlWrite_Group(fe, ControlNum, value, 2);
  3008. #ifdef _MXL_INTERNAL
  3009. /* Write Matching MXL Control */
  3010. status += MXL_ControlWrite_Group(fe, ControlNum, value, 3);
  3011. #endif
  3012. return status;
  3013. }
  3014. static u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum,
  3015. u32 value, u16 controlGroup)
  3016. {
  3017. struct mxl5005s_state *state = fe->tuner_priv;
  3018. u16 i, j, k;
  3019. u32 highLimit;
  3020. u32 ctrlVal;
  3021. if (controlGroup == 1) /* Initial Control */ {
  3022. for (i = 0; i < state->Init_Ctrl_Num; i++) {
  3023. if (controlNum == state->Init_Ctrl[i].Ctrl_Num) {
  3024. highLimit = 1 << state->Init_Ctrl[i].size;
  3025. if (value < highLimit) {
  3026. for (j = 0; j < state->Init_Ctrl[i].size; j++) {
  3027. state->Init_Ctrl[i].val[j] = (u8)((value >> j) & 0x01);
  3028. MXL_RegWriteBit(fe, (u8)(state->Init_Ctrl[i].addr[j]),
  3029. (u8)(state->Init_Ctrl[i].bit[j]),
  3030. (u8)((value>>j) & 0x01));
  3031. }
  3032. ctrlVal = 0;
  3033. for (k = 0; k < state->Init_Ctrl[i].size; k++)
  3034. ctrlVal += state->Init_Ctrl[i].val[k] * (1 << k);
  3035. } else
  3036. return -1;
  3037. }
  3038. }
  3039. }
  3040. if (controlGroup == 2) /* Chan change Control */ {
  3041. for (i = 0; i < state->CH_Ctrl_Num; i++) {
  3042. if (controlNum == state->CH_Ctrl[i].Ctrl_Num) {
  3043. highLimit = 1 << state->CH_Ctrl[i].size;
  3044. if (value < highLimit) {
  3045. for (j = 0; j < state->CH_Ctrl[i].size; j++) {
  3046. state->CH_Ctrl[i].val[j] = (u8)((value >> j) & 0x01);
  3047. MXL_RegWriteBit(fe, (u8)(state->CH_Ctrl[i].addr[j]),
  3048. (u8)(state->CH_Ctrl[i].bit[j]),
  3049. (u8)((value>>j) & 0x01));
  3050. }
  3051. ctrlVal = 0;
  3052. for (k = 0; k < state->CH_Ctrl[i].size; k++)
  3053. ctrlVal += state->CH_Ctrl[i].val[k] * (1 << k);
  3054. } else
  3055. return -1;
  3056. }
  3057. }
  3058. }
  3059. #ifdef _MXL_INTERNAL
  3060. if (controlGroup == 3) /* Maxlinear Control */ {
  3061. for (i = 0; i < state->MXL_Ctrl_Num; i++) {
  3062. if (controlNum == state->MXL_Ctrl[i].Ctrl_Num) {
  3063. highLimit = (1 << state->MXL_Ctrl[i].size);
  3064. if (value < highLimit) {
  3065. for (j = 0; j < state->MXL_Ctrl[i].size; j++) {
  3066. state->MXL_Ctrl[i].val[j] = (u8)((value >> j) & 0x01);
  3067. MXL_RegWriteBit(fe, (u8)(state->MXL_Ctrl[i].addr[j]),
  3068. (u8)(state->MXL_Ctrl[i].bit[j]),
  3069. (u8)((value>>j) & 0x01));
  3070. }
  3071. ctrlVal = 0;
  3072. for (k = 0; k < state->MXL_Ctrl[i].size; k++)
  3073. ctrlVal += state->
  3074. MXL_Ctrl[i].val[k] *
  3075. (1 << k);
  3076. } else
  3077. return -1;
  3078. }
  3079. }
  3080. }
  3081. #endif
  3082. return 0 ; /* successful return */
  3083. }
  3084. static u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal)
  3085. {
  3086. struct mxl5005s_state *state = fe->tuner_priv;
  3087. int i ;
  3088. for (i = 0; i < 104; i++) {
  3089. if (RegNum == state->TunerRegs[i].Reg_Num) {
  3090. *RegVal = (u8)(state->TunerRegs[i].Reg_Val);
  3091. return 0;
  3092. }
  3093. }
  3094. return 1;
  3095. }
  3096. static u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value)
  3097. {
  3098. struct mxl5005s_state *state = fe->tuner_priv;
  3099. u32 ctrlVal ;
  3100. u16 i, k ;
  3101. for (i = 0; i < state->Init_Ctrl_Num ; i++) {
  3102. if (controlNum == state->Init_Ctrl[i].Ctrl_Num) {
  3103. ctrlVal = 0;
  3104. for (k = 0; k < state->Init_Ctrl[i].size; k++)
  3105. ctrlVal += state->Init_Ctrl[i].val[k] * (1<<k);
  3106. *value = ctrlVal;
  3107. return 0;
  3108. }
  3109. }
  3110. for (i = 0; i < state->CH_Ctrl_Num ; i++) {
  3111. if (controlNum == state->CH_Ctrl[i].Ctrl_Num) {
  3112. ctrlVal = 0;
  3113. for (k = 0; k < state->CH_Ctrl[i].size; k++)
  3114. ctrlVal += state->CH_Ctrl[i].val[k] * (1 << k);
  3115. *value = ctrlVal;
  3116. return 0;
  3117. }
  3118. }
  3119. #ifdef _MXL_INTERNAL
  3120. for (i = 0; i < state->MXL_Ctrl_Num ; i++) {
  3121. if (controlNum == state->MXL_Ctrl[i].Ctrl_Num) {
  3122. ctrlVal = 0;
  3123. for (k = 0; k < state->MXL_Ctrl[i].size; k++)
  3124. ctrlVal += state->MXL_Ctrl[i].val[k] * (1<<k);
  3125. *value = ctrlVal;
  3126. return 0;
  3127. }
  3128. }
  3129. #endif
  3130. return 1;
  3131. }
  3132. static void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit,
  3133. u8 bitVal)
  3134. {
  3135. struct mxl5005s_state *state = fe->tuner_priv;
  3136. int i ;
  3137. const u8 AND_MAP[8] = {
  3138. 0xFE, 0xFD, 0xFB, 0xF7,
  3139. 0xEF, 0xDF, 0xBF, 0x7F } ;
  3140. const u8 OR_MAP[8] = {
  3141. 0x01, 0x02, 0x04, 0x08,
  3142. 0x10, 0x20, 0x40, 0x80 } ;
  3143. for (i = 0; i < state->TunerRegs_Num; i++) {
  3144. if (state->TunerRegs[i].Reg_Num == address) {
  3145. if (bitVal)
  3146. state->TunerRegs[i].Reg_Val |= OR_MAP[bit];
  3147. else
  3148. state->TunerRegs[i].Reg_Val &= AND_MAP[bit];
  3149. break ;
  3150. }
  3151. }
  3152. }
  3153. static u32 MXL_Ceiling(u32 value, u32 resolution)
  3154. {
  3155. return value / resolution + (value % resolution > 0 ? 1 : 0);
  3156. }
  3157. /* Retrieve the Initialization Registers */
  3158. static u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 *RegNum,
  3159. u8 *RegVal, int *count)
  3160. {
  3161. u16 status = 0;
  3162. int i ;
  3163. static const u8 RegAddr[] = {
  3164. 11, 12, 13, 22, 32, 43, 44, 53, 56, 59, 73,
  3165. 76, 77, 91, 134, 135, 137, 147,
  3166. 156, 166, 167, 168, 25
  3167. };
  3168. *count = ARRAY_SIZE(RegAddr);
  3169. status += MXL_BlockInit(fe);
  3170. for (i = 0 ; i < *count; i++) {
  3171. RegNum[i] = RegAddr[i];
  3172. status += MXL_RegRead(fe, RegNum[i], &RegVal[i]);
  3173. }
  3174. return status;
  3175. }
  3176. static u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal,
  3177. int *count)
  3178. {
  3179. u16 status = 0;
  3180. int i ;
  3181. /* add 77, 166, 167, 168 register for 2.6.12 */
  3182. #ifdef _MXL_PRODUCTION
  3183. static const u8 RegAddr[] = {
  3184. 14, 15, 16, 17, 22, 43, 65, 68, 69, 70, 73, 92, 93, 106,
  3185. 107, 108, 109, 110, 111, 112, 136, 138, 149, 77, 166, 167, 168
  3186. };
  3187. #else
  3188. static const u8 RegAddr[] = {
  3189. 14, 15, 16, 17, 22, 43, 68, 69, 70, 73, 92, 93, 106,
  3190. 107, 108, 109, 110, 111, 112, 136, 138, 149, 77, 166, 167, 168
  3191. };
  3192. /*
  3193. u8 RegAddr[171];
  3194. for (i = 0; i <= 170; i++)
  3195. RegAddr[i] = i;
  3196. */
  3197. #endif
  3198. *count = ARRAY_SIZE(RegAddr);
  3199. for (i = 0 ; i < *count; i++) {
  3200. RegNum[i] = RegAddr[i];
  3201. status += MXL_RegRead(fe, RegNum[i], &RegVal[i]);
  3202. }
  3203. return status;
  3204. }
  3205. static u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum,
  3206. u8 *RegVal, int *count)
  3207. {
  3208. u16 status = 0;
  3209. int i;
  3210. u8 RegAddr[] = {43, 136};
  3211. *count = ARRAY_SIZE(RegAddr);
  3212. for (i = 0; i < *count; i++) {
  3213. RegNum[i] = RegAddr[i];
  3214. status += MXL_RegRead(fe, RegNum[i], &RegVal[i]);
  3215. }
  3216. return status;
  3217. }
  3218. static u16 MXL_GetMasterControl(u8 *MasterReg, int state)
  3219. {
  3220. if (state == 1) /* Load_Start */
  3221. *MasterReg = 0xF3;
  3222. if (state == 2) /* Power_Down */
  3223. *MasterReg = 0x41;
  3224. if (state == 3) /* Synth_Reset */
  3225. *MasterReg = 0xB1;
  3226. if (state == 4) /* Seq_Off */
  3227. *MasterReg = 0xF1;
  3228. return 0;
  3229. }
  3230. #ifdef _MXL_PRODUCTION
  3231. static u16 MXL_VCORange_Test(struct dvb_frontend *fe, int VCO_Range)
  3232. {
  3233. struct mxl5005s_state *state = fe->tuner_priv;
  3234. u16 status = 0 ;
  3235. if (VCO_Range == 1) {
  3236. status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1);
  3237. status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
  3238. status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
  3239. status += MXL_ControlWrite(fe, RFSYN_DIVM, 1);
  3240. status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
  3241. status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
  3242. status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
  3243. if (state->Mode == 0 && state->IF_Mode == 1) {
  3244. /* Analog Low IF Mode */
  3245. status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
  3246. status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
  3247. status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56);
  3248. status += MXL_ControlWrite(fe,
  3249. CHCAL_FRAC_MOD_RF, 180224);
  3250. }
  3251. if (state->Mode == 0 && state->IF_Mode == 0) {
  3252. /* Analog Zero IF Mode */
  3253. status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
  3254. status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
  3255. status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56);
  3256. status += MXL_ControlWrite(fe,
  3257. CHCAL_FRAC_MOD_RF, 222822);
  3258. }
  3259. if (state->Mode == 1) /* Digital Mode */ {
  3260. status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
  3261. status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
  3262. status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56);
  3263. status += MXL_ControlWrite(fe,
  3264. CHCAL_FRAC_MOD_RF, 229376);
  3265. }
  3266. }
  3267. if (VCO_Range == 2) {
  3268. status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1);
  3269. status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
  3270. status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
  3271. status += MXL_ControlWrite(fe, RFSYN_DIVM, 1);
  3272. status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
  3273. status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
  3274. status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
  3275. status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
  3276. status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
  3277. status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 41);
  3278. if (state->Mode == 0 && state->IF_Mode == 1) {
  3279. /* Analog Low IF Mode */
  3280. status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
  3281. status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
  3282. status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42);
  3283. status += MXL_ControlWrite(fe,
  3284. CHCAL_FRAC_MOD_RF, 206438);
  3285. }
  3286. if (state->Mode == 0 && state->IF_Mode == 0) {
  3287. /* Analog Zero IF Mode */
  3288. status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
  3289. status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
  3290. status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42);
  3291. status += MXL_ControlWrite(fe,
  3292. CHCAL_FRAC_MOD_RF, 206438);
  3293. }
  3294. if (state->Mode == 1) /* Digital Mode */ {
  3295. status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
  3296. status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
  3297. status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 41);
  3298. status += MXL_ControlWrite(fe,
  3299. CHCAL_FRAC_MOD_RF, 16384);
  3300. }
  3301. }
  3302. if (VCO_Range == 3) {
  3303. status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1);
  3304. status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
  3305. status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
  3306. status += MXL_ControlWrite(fe, RFSYN_DIVM, 1);
  3307. status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
  3308. status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
  3309. status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
  3310. status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
  3311. status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
  3312. status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42);
  3313. if (state->Mode == 0 && state->IF_Mode == 1) {
  3314. /* Analog Low IF Mode */
  3315. status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
  3316. status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
  3317. status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 44);
  3318. status += MXL_ControlWrite(fe,
  3319. CHCAL_FRAC_MOD_RF, 173670);
  3320. }
  3321. if (state->Mode == 0 && state->IF_Mode == 0) {
  3322. /* Analog Zero IF Mode */
  3323. status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
  3324. status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
  3325. status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 44);
  3326. status += MXL_ControlWrite(fe,
  3327. CHCAL_FRAC_MOD_RF, 173670);
  3328. }
  3329. if (state->Mode == 1) /* Digital Mode */ {
  3330. status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
  3331. status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
  3332. status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42);
  3333. status += MXL_ControlWrite(fe,
  3334. CHCAL_FRAC_MOD_RF, 245760);
  3335. }
  3336. }
  3337. if (VCO_Range == 4) {
  3338. status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1);
  3339. status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
  3340. status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
  3341. status += MXL_ControlWrite(fe, RFSYN_DIVM, 1);
  3342. status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
  3343. status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
  3344. status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
  3345. status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
  3346. status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
  3347. status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27);
  3348. if (state->Mode == 0 && state->IF_Mode == 1) {
  3349. /* Analog Low IF Mode */
  3350. status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
  3351. status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
  3352. status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27);
  3353. status += MXL_ControlWrite(fe,
  3354. CHCAL_FRAC_MOD_RF, 206438);
  3355. }
  3356. if (state->Mode == 0 && state->IF_Mode == 0) {
  3357. /* Analog Zero IF Mode */
  3358. status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
  3359. status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
  3360. status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27);
  3361. status += MXL_ControlWrite(fe,
  3362. CHCAL_FRAC_MOD_RF, 206438);
  3363. }
  3364. if (state->Mode == 1) /* Digital Mode */ {
  3365. status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
  3366. status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
  3367. status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27);
  3368. status += MXL_ControlWrite(fe,
  3369. CHCAL_FRAC_MOD_RF, 212992);
  3370. }
  3371. }
  3372. return status;
  3373. }
  3374. static u16 MXL_Hystersis_Test(struct dvb_frontend *fe, int Hystersis)
  3375. {
  3376. struct mxl5005s_state *state = fe->tuner_priv;
  3377. u16 status = 0;
  3378. if (Hystersis == 1)
  3379. status += MXL_ControlWrite(fe, DN_BYPASS_AGC_I2C, 1);
  3380. return status;
  3381. }
  3382. #endif
  3383. /* End: Reference driver code found in the Realtek driver that
  3384. * is copyright MaxLinear */
  3385. /* ----------------------------------------------------------------
  3386. * Begin: Everything after here is new code to adapt the
  3387. * proprietary Realtek driver into a Linux API tuner.
  3388. * Copyright (C) 2008 Steven Toth <stoth@linuxtv.org>
  3389. */
  3390. static int mxl5005s_reset(struct dvb_frontend *fe)
  3391. {
  3392. struct mxl5005s_state *state = fe->tuner_priv;
  3393. int ret = 0;
  3394. u8 buf[2] = { 0xff, 0x00 };
  3395. struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0,
  3396. .buf = buf, .len = 2 };
  3397. dprintk(2, "%s()\n", __func__);
  3398. if (fe->ops.i2c_gate_ctrl)
  3399. fe->ops.i2c_gate_ctrl(fe, 1);
  3400. if (i2c_transfer(state->i2c, &msg, 1) != 1) {
  3401. printk(KERN_WARNING "mxl5005s I2C reset failed\n");
  3402. ret = -EREMOTEIO;
  3403. }
  3404. if (fe->ops.i2c_gate_ctrl)
  3405. fe->ops.i2c_gate_ctrl(fe, 0);
  3406. return ret;
  3407. }
  3408. /* Write a single byte to a single reg, latch the value if required by
  3409. * following the transaction with the latch byte.
  3410. */
  3411. static int mxl5005s_writereg(struct dvb_frontend *fe, u8 reg, u8 val, int latch)
  3412. {
  3413. struct mxl5005s_state *state = fe->tuner_priv;
  3414. u8 buf[3] = { reg, val, MXL5005S_LATCH_BYTE };
  3415. struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0,
  3416. .buf = buf, .len = 3 };
  3417. if (latch == 0)
  3418. msg.len = 2;
  3419. dprintk(2, "%s(0x%x, 0x%x, 0x%x)\n", __func__, reg, val, msg.addr);
  3420. if (i2c_transfer(state->i2c, &msg, 1) != 1) {
  3421. printk(KERN_WARNING "mxl5005s I2C write failed\n");
  3422. return -EREMOTEIO;
  3423. }
  3424. return 0;
  3425. }
  3426. static int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable,
  3427. u8 *datatable, u8 len)
  3428. {
  3429. int ret = 0, i;
  3430. if (fe->ops.i2c_gate_ctrl)
  3431. fe->ops.i2c_gate_ctrl(fe, 1);
  3432. for (i = 0 ; i < len-1; i++) {
  3433. ret = mxl5005s_writereg(fe, addrtable[i], datatable[i], 0);
  3434. if (ret < 0)
  3435. break;
  3436. }
  3437. ret = mxl5005s_writereg(fe, addrtable[i], datatable[i], 1);
  3438. if (fe->ops.i2c_gate_ctrl)
  3439. fe->ops.i2c_gate_ctrl(fe, 0);
  3440. return ret;
  3441. }
  3442. static int mxl5005s_init(struct dvb_frontend *fe)
  3443. {
  3444. struct mxl5005s_state *state = fe->tuner_priv;
  3445. dprintk(1, "%s()\n", __func__);
  3446. state->current_mode = MXL_QAM;
  3447. return mxl5005s_reconfigure(fe, MXL_QAM, MXL5005S_BANDWIDTH_6MHZ);
  3448. }
  3449. static int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type,
  3450. u32 bandwidth)
  3451. {
  3452. struct mxl5005s_state *state = fe->tuner_priv;
  3453. u8 AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
  3454. u8 ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
  3455. int TableLen;
  3456. dprintk(1, "%s(type=%d, bw=%d)\n", __func__, mod_type, bandwidth);
  3457. mxl5005s_reset(fe);
  3458. /* Tuner initialization stage 0 */
  3459. MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET);
  3460. AddrTable[0] = MASTER_CONTROL_ADDR;
  3461. ByteTable[0] |= state->config->AgcMasterByte;
  3462. mxl5005s_writeregs(fe, AddrTable, ByteTable, 1);
  3463. mxl5005s_AssignTunerMode(fe, mod_type, bandwidth);
  3464. /* Tuner initialization stage 1 */
  3465. MXL_GetInitRegister(fe, AddrTable, ByteTable, &TableLen);
  3466. mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen);
  3467. return 0;
  3468. }
  3469. static int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type,
  3470. u32 bandwidth)
  3471. {
  3472. struct mxl5005s_state *state = fe->tuner_priv;
  3473. struct mxl5005s_config *c = state->config;
  3474. InitTunerControls(fe);
  3475. /* Set MxL5005S parameters. */
  3476. MXL5005_TunerConfig(
  3477. fe,
  3478. c->mod_mode,
  3479. c->if_mode,
  3480. bandwidth,
  3481. c->if_freq,
  3482. c->xtal_freq,
  3483. c->agc_mode,
  3484. c->top,
  3485. c->output_load,
  3486. c->clock_out,
  3487. c->div_out,
  3488. c->cap_select,
  3489. c->rssi_enable,
  3490. mod_type,
  3491. c->tracking_filter);
  3492. return 0;
  3493. }
  3494. static int mxl5005s_set_params(struct dvb_frontend *fe)
  3495. {
  3496. struct mxl5005s_state *state = fe->tuner_priv;
  3497. struct dtv_frontend_properties *c = &fe->dtv_property_cache;
  3498. u32 delsys = c->delivery_system;
  3499. u32 bw = c->bandwidth_hz;
  3500. u32 req_mode, req_bw = 0;
  3501. int ret;
  3502. dprintk(1, "%s()\n", __func__);
  3503. switch (delsys) {
  3504. case SYS_ATSC:
  3505. req_mode = MXL_ATSC;
  3506. req_bw = MXL5005S_BANDWIDTH_6MHZ;
  3507. break;
  3508. case SYS_DVBC_ANNEX_B:
  3509. req_mode = MXL_QAM;
  3510. req_bw = MXL5005S_BANDWIDTH_6MHZ;
  3511. break;
  3512. default: /* Assume DVB-T */
  3513. req_mode = MXL_DVBT;
  3514. switch (bw) {
  3515. case 6000000:
  3516. req_bw = MXL5005S_BANDWIDTH_6MHZ;
  3517. break;
  3518. case 7000000:
  3519. req_bw = MXL5005S_BANDWIDTH_7MHZ;
  3520. break;
  3521. case 8000000:
  3522. case 0:
  3523. req_bw = MXL5005S_BANDWIDTH_8MHZ;
  3524. break;
  3525. default:
  3526. return -EINVAL;
  3527. }
  3528. }
  3529. /* Change tuner for new modulation type if reqd */
  3530. if (req_mode != state->current_mode ||
  3531. req_bw != state->Chan_Bandwidth) {
  3532. state->current_mode = req_mode;
  3533. ret = mxl5005s_reconfigure(fe, req_mode, req_bw);
  3534. } else
  3535. ret = 0;
  3536. if (ret == 0) {
  3537. dprintk(1, "%s() freq=%d\n", __func__, c->frequency);
  3538. ret = mxl5005s_SetRfFreqHz(fe, c->frequency);
  3539. }
  3540. return ret;
  3541. }
  3542. static int mxl5005s_get_frequency(struct dvb_frontend *fe, u32 *frequency)
  3543. {
  3544. struct mxl5005s_state *state = fe->tuner_priv;
  3545. dprintk(1, "%s()\n", __func__);
  3546. *frequency = state->RF_IN;
  3547. return 0;
  3548. }
  3549. static int mxl5005s_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
  3550. {
  3551. struct mxl5005s_state *state = fe->tuner_priv;
  3552. dprintk(1, "%s()\n", __func__);
  3553. *bandwidth = state->Chan_Bandwidth;
  3554. return 0;
  3555. }
  3556. static int mxl5005s_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
  3557. {
  3558. struct mxl5005s_state *state = fe->tuner_priv;
  3559. dprintk(1, "%s()\n", __func__);
  3560. *frequency = state->IF_OUT;
  3561. return 0;
  3562. }
  3563. static void mxl5005s_release(struct dvb_frontend *fe)
  3564. {
  3565. dprintk(1, "%s()\n", __func__);
  3566. kfree(fe->tuner_priv);
  3567. fe->tuner_priv = NULL;
  3568. }
  3569. static const struct dvb_tuner_ops mxl5005s_tuner_ops = {
  3570. .info = {
  3571. .name = "MaxLinear MXL5005S",
  3572. .frequency_min_hz = 48 * MHz,
  3573. .frequency_max_hz = 860 * MHz,
  3574. .frequency_step_hz = 50 * kHz,
  3575. },
  3576. .release = mxl5005s_release,
  3577. .init = mxl5005s_init,
  3578. .set_params = mxl5005s_set_params,
  3579. .get_frequency = mxl5005s_get_frequency,
  3580. .get_bandwidth = mxl5005s_get_bandwidth,
  3581. .get_if_frequency = mxl5005s_get_if_frequency,
  3582. };
  3583. struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe,
  3584. struct i2c_adapter *i2c,
  3585. struct mxl5005s_config *config)
  3586. {
  3587. struct mxl5005s_state *state = NULL;
  3588. dprintk(1, "%s()\n", __func__);
  3589. state = kzalloc(sizeof(struct mxl5005s_state), GFP_KERNEL);
  3590. if (state == NULL)
  3591. return NULL;
  3592. state->frontend = fe;
  3593. state->config = config;
  3594. state->i2c = i2c;
  3595. printk(KERN_INFO "MXL5005S: Attached at address 0x%02x\n",
  3596. config->i2c_address);
  3597. memcpy(&fe->ops.tuner_ops, &mxl5005s_tuner_ops,
  3598. sizeof(struct dvb_tuner_ops));
  3599. fe->tuner_priv = state;
  3600. return fe;
  3601. }
  3602. EXPORT_SYMBOL(mxl5005s_attach);
  3603. MODULE_DESCRIPTION("MaxLinear MXL5005S silicon tuner driver");
  3604. MODULE_AUTHOR("Steven Toth");
  3605. MODULE_LICENSE("GPL");