mt2063.c 65 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Driver for mt2063 Micronas tuner
  4. *
  5. * Copyright (c) 2011 Mauro Carvalho Chehab
  6. *
  7. * This driver came from a driver originally written by:
  8. * Henry Wang <Henry.wang@AzureWave.com>
  9. * Made publicly available by Terratec, at:
  10. * http://linux.terratec.de/files/TERRATEC_H7/20110323_TERRATEC_H7_Linux.tar.gz
  11. */
  12. #include <linux/init.h>
  13. #include <linux/kernel.h>
  14. #include <linux/module.h>
  15. #include <linux/string.h>
  16. #include <linux/videodev2.h>
  17. #include <linux/gcd.h>
  18. #include "mt2063.h"
  19. static unsigned int debug;
  20. module_param(debug, int, 0644);
  21. MODULE_PARM_DESC(debug, "Set Verbosity level");
  22. #define dprintk(level, fmt, arg...) do { \
  23. if (debug >= level) \
  24. printk(KERN_DEBUG "mt2063 %s: " fmt, __func__, ## arg); \
  25. } while (0)
  26. /* positive error codes used internally */
  27. /* Info: Unavoidable LO-related spur may be present in the output */
  28. #define MT2063_SPUR_PRESENT_ERR (0x00800000)
  29. /* Info: Mask of bits used for # of LO-related spurs that were avoided during tuning */
  30. #define MT2063_SPUR_CNT_MASK (0x001f0000)
  31. #define MT2063_SPUR_SHIFT (16)
  32. /* Info: Upconverter frequency is out of range (may be reason for MT_UPC_UNLOCK) */
  33. #define MT2063_UPC_RANGE (0x04000000)
  34. /* Info: Downconverter frequency is out of range (may be reason for MT_DPC_UNLOCK) */
  35. #define MT2063_DNC_RANGE (0x08000000)
  36. /*
  37. * Constant defining the version of the following structure
  38. * and therefore the API for this code.
  39. *
  40. * When compiling the tuner driver, the preprocessor will
  41. * check against this version number to make sure that
  42. * it matches the version that the tuner driver knows about.
  43. */
  44. /* DECT Frequency Avoidance */
  45. #define MT2063_DECT_AVOID_US_FREQS 0x00000001
  46. #define MT2063_DECT_AVOID_EURO_FREQS 0x00000002
  47. #define MT2063_EXCLUDE_US_DECT_FREQUENCIES(s) (((s) & MT2063_DECT_AVOID_US_FREQS) != 0)
  48. #define MT2063_EXCLUDE_EURO_DECT_FREQUENCIES(s) (((s) & MT2063_DECT_AVOID_EURO_FREQS) != 0)
  49. enum MT2063_DECT_Avoid_Type {
  50. MT2063_NO_DECT_AVOIDANCE = 0, /* Do not create DECT exclusion zones. */
  51. MT2063_AVOID_US_DECT = MT2063_DECT_AVOID_US_FREQS, /* Avoid US DECT frequencies. */
  52. MT2063_AVOID_EURO_DECT = MT2063_DECT_AVOID_EURO_FREQS, /* Avoid European DECT frequencies. */
  53. MT2063_AVOID_BOTH /* Avoid both regions. Not typically used. */
  54. };
  55. #define MT2063_MAX_ZONES 48
  56. struct MT2063_ExclZone_t {
  57. u32 min_;
  58. u32 max_;
  59. struct MT2063_ExclZone_t *next_;
  60. };
  61. /*
  62. * Structure of data needed for Spur Avoidance
  63. */
  64. struct MT2063_AvoidSpursData_t {
  65. u32 f_ref;
  66. u32 f_in;
  67. u32 f_LO1;
  68. u32 f_if1_Center;
  69. u32 f_if1_Request;
  70. u32 f_if1_bw;
  71. u32 f_LO2;
  72. u32 f_out;
  73. u32 f_out_bw;
  74. u32 f_LO1_Step;
  75. u32 f_LO2_Step;
  76. u32 f_LO1_FracN_Avoid;
  77. u32 f_LO2_FracN_Avoid;
  78. u32 f_zif_bw;
  79. u32 f_min_LO_Separation;
  80. u32 maxH1;
  81. u32 maxH2;
  82. enum MT2063_DECT_Avoid_Type avoidDECT;
  83. u32 bSpurPresent;
  84. u32 bSpurAvoided;
  85. u32 nSpursFound;
  86. u32 nZones;
  87. struct MT2063_ExclZone_t *freeZones;
  88. struct MT2063_ExclZone_t *usedZones;
  89. struct MT2063_ExclZone_t MT2063_ExclZones[MT2063_MAX_ZONES];
  90. };
  91. /*
  92. * Parameter for function MT2063_SetPowerMask that specifies the power down
  93. * of various sections of the MT2063.
  94. */
  95. enum MT2063_Mask_Bits {
  96. MT2063_REG_SD = 0x0040, /* Shutdown regulator */
  97. MT2063_SRO_SD = 0x0020, /* Shutdown SRO */
  98. MT2063_AFC_SD = 0x0010, /* Shutdown AFC A/D */
  99. MT2063_PD_SD = 0x0002, /* Enable power detector shutdown */
  100. MT2063_PDADC_SD = 0x0001, /* Enable power detector A/D shutdown */
  101. MT2063_VCO_SD = 0x8000, /* Enable VCO shutdown */
  102. MT2063_LTX_SD = 0x4000, /* Enable LTX shutdown */
  103. MT2063_LT1_SD = 0x2000, /* Enable LT1 shutdown */
  104. MT2063_LNA_SD = 0x1000, /* Enable LNA shutdown */
  105. MT2063_UPC_SD = 0x0800, /* Enable upconverter shutdown */
  106. MT2063_DNC_SD = 0x0400, /* Enable downconverter shutdown */
  107. MT2063_VGA_SD = 0x0200, /* Enable VGA shutdown */
  108. MT2063_AMP_SD = 0x0100, /* Enable AMP shutdown */
  109. MT2063_ALL_SD = 0xFF73, /* All shutdown bits for this tuner */
  110. MT2063_NONE_SD = 0x0000 /* No shutdown bits */
  111. };
  112. /*
  113. * Possible values for MT2063_DNC_OUTPUT
  114. */
  115. enum MT2063_DNC_Output_Enable {
  116. MT2063_DNC_NONE = 0,
  117. MT2063_DNC_1,
  118. MT2063_DNC_2,
  119. MT2063_DNC_BOTH
  120. };
  121. /*
  122. * Two-wire serial bus subaddresses of the tuner registers.
  123. * Also known as the tuner's register addresses.
  124. */
  125. enum MT2063_Register_Offsets {
  126. MT2063_REG_PART_REV = 0, /* 0x00: Part/Rev Code */
  127. MT2063_REG_LO1CQ_1, /* 0x01: LO1C Queued Byte 1 */
  128. MT2063_REG_LO1CQ_2, /* 0x02: LO1C Queued Byte 2 */
  129. MT2063_REG_LO2CQ_1, /* 0x03: LO2C Queued Byte 1 */
  130. MT2063_REG_LO2CQ_2, /* 0x04: LO2C Queued Byte 2 */
  131. MT2063_REG_LO2CQ_3, /* 0x05: LO2C Queued Byte 3 */
  132. MT2063_REG_RSVD_06, /* 0x06: Reserved */
  133. MT2063_REG_LO_STATUS, /* 0x07: LO Status */
  134. MT2063_REG_FIFFC, /* 0x08: FIFF Center */
  135. MT2063_REG_CLEARTUNE, /* 0x09: ClearTune Filter */
  136. MT2063_REG_ADC_OUT, /* 0x0A: ADC_OUT */
  137. MT2063_REG_LO1C_1, /* 0x0B: LO1C Byte 1 */
  138. MT2063_REG_LO1C_2, /* 0x0C: LO1C Byte 2 */
  139. MT2063_REG_LO2C_1, /* 0x0D: LO2C Byte 1 */
  140. MT2063_REG_LO2C_2, /* 0x0E: LO2C Byte 2 */
  141. MT2063_REG_LO2C_3, /* 0x0F: LO2C Byte 3 */
  142. MT2063_REG_RSVD_10, /* 0x10: Reserved */
  143. MT2063_REG_PWR_1, /* 0x11: PWR Byte 1 */
  144. MT2063_REG_PWR_2, /* 0x12: PWR Byte 2 */
  145. MT2063_REG_TEMP_STATUS, /* 0x13: Temp Status */
  146. MT2063_REG_XO_STATUS, /* 0x14: Crystal Status */
  147. MT2063_REG_RF_STATUS, /* 0x15: RF Attn Status */
  148. MT2063_REG_FIF_STATUS, /* 0x16: FIF Attn Status */
  149. MT2063_REG_LNA_OV, /* 0x17: LNA Attn Override */
  150. MT2063_REG_RF_OV, /* 0x18: RF Attn Override */
  151. MT2063_REG_FIF_OV, /* 0x19: FIF Attn Override */
  152. MT2063_REG_LNA_TGT, /* 0x1A: Reserved */
  153. MT2063_REG_PD1_TGT, /* 0x1B: Pwr Det 1 Target */
  154. MT2063_REG_PD2_TGT, /* 0x1C: Pwr Det 2 Target */
  155. MT2063_REG_RSVD_1D, /* 0x1D: Reserved */
  156. MT2063_REG_RSVD_1E, /* 0x1E: Reserved */
  157. MT2063_REG_RSVD_1F, /* 0x1F: Reserved */
  158. MT2063_REG_RSVD_20, /* 0x20: Reserved */
  159. MT2063_REG_BYP_CTRL, /* 0x21: Bypass Control */
  160. MT2063_REG_RSVD_22, /* 0x22: Reserved */
  161. MT2063_REG_RSVD_23, /* 0x23: Reserved */
  162. MT2063_REG_RSVD_24, /* 0x24: Reserved */
  163. MT2063_REG_RSVD_25, /* 0x25: Reserved */
  164. MT2063_REG_RSVD_26, /* 0x26: Reserved */
  165. MT2063_REG_RSVD_27, /* 0x27: Reserved */
  166. MT2063_REG_FIFF_CTRL, /* 0x28: FIFF Control */
  167. MT2063_REG_FIFF_OFFSET, /* 0x29: FIFF Offset */
  168. MT2063_REG_CTUNE_CTRL, /* 0x2A: Reserved */
  169. MT2063_REG_CTUNE_OV, /* 0x2B: Reserved */
  170. MT2063_REG_CTRL_2C, /* 0x2C: Reserved */
  171. MT2063_REG_FIFF_CTRL2, /* 0x2D: Fiff Control */
  172. MT2063_REG_RSVD_2E, /* 0x2E: Reserved */
  173. MT2063_REG_DNC_GAIN, /* 0x2F: DNC Control */
  174. MT2063_REG_VGA_GAIN, /* 0x30: VGA Gain Ctrl */
  175. MT2063_REG_RSVD_31, /* 0x31: Reserved */
  176. MT2063_REG_TEMP_SEL, /* 0x32: Temperature Selection */
  177. MT2063_REG_RSVD_33, /* 0x33: Reserved */
  178. MT2063_REG_RSVD_34, /* 0x34: Reserved */
  179. MT2063_REG_RSVD_35, /* 0x35: Reserved */
  180. MT2063_REG_RSVD_36, /* 0x36: Reserved */
  181. MT2063_REG_RSVD_37, /* 0x37: Reserved */
  182. MT2063_REG_RSVD_38, /* 0x38: Reserved */
  183. MT2063_REG_RSVD_39, /* 0x39: Reserved */
  184. MT2063_REG_RSVD_3A, /* 0x3A: Reserved */
  185. MT2063_REG_RSVD_3B, /* 0x3B: Reserved */
  186. MT2063_REG_RSVD_3C, /* 0x3C: Reserved */
  187. MT2063_REG_END_REGS
  188. };
  189. struct mt2063_state {
  190. struct i2c_adapter *i2c;
  191. bool init;
  192. const struct mt2063_config *config;
  193. struct dvb_tuner_ops ops;
  194. struct dvb_frontend *frontend;
  195. u32 frequency;
  196. u32 srate;
  197. u32 bandwidth;
  198. u32 reference;
  199. u32 tuner_id;
  200. struct MT2063_AvoidSpursData_t AS_Data;
  201. u32 f_IF1_actual;
  202. u32 rcvr_mode;
  203. u32 ctfilt_sw;
  204. u32 CTFiltMax[31];
  205. u32 num_regs;
  206. u8 reg[MT2063_REG_END_REGS];
  207. };
  208. /*
  209. * mt2063_write - Write data into the I2C bus
  210. */
  211. static int mt2063_write(struct mt2063_state *state, u8 reg, u8 *data, u32 len)
  212. {
  213. struct dvb_frontend *fe = state->frontend;
  214. int ret;
  215. u8 buf[60];
  216. struct i2c_msg msg = {
  217. .addr = state->config->tuner_address,
  218. .flags = 0,
  219. .buf = buf,
  220. .len = len + 1
  221. };
  222. dprintk(2, "\n");
  223. msg.buf[0] = reg;
  224. memcpy(msg.buf + 1, data, len);
  225. if (fe->ops.i2c_gate_ctrl)
  226. fe->ops.i2c_gate_ctrl(fe, 1);
  227. ret = i2c_transfer(state->i2c, &msg, 1);
  228. if (fe->ops.i2c_gate_ctrl)
  229. fe->ops.i2c_gate_ctrl(fe, 0);
  230. if (ret < 0)
  231. printk(KERN_ERR "%s error ret=%d\n", __func__, ret);
  232. return ret;
  233. }
  234. /*
  235. * mt2063_write - Write register data into the I2C bus, caching the value
  236. */
  237. static int mt2063_setreg(struct mt2063_state *state, u8 reg, u8 val)
  238. {
  239. int status;
  240. dprintk(2, "\n");
  241. if (reg >= MT2063_REG_END_REGS)
  242. return -ERANGE;
  243. status = mt2063_write(state, reg, &val, 1);
  244. if (status < 0)
  245. return status;
  246. state->reg[reg] = val;
  247. return 0;
  248. }
  249. /*
  250. * mt2063_read - Read data from the I2C bus
  251. */
  252. static int mt2063_read(struct mt2063_state *state,
  253. u8 subAddress, u8 *pData, u32 cnt)
  254. {
  255. int status = 0; /* Status to be returned */
  256. struct dvb_frontend *fe = state->frontend;
  257. u32 i = 0;
  258. dprintk(2, "addr 0x%02x, cnt %d\n", subAddress, cnt);
  259. if (fe->ops.i2c_gate_ctrl)
  260. fe->ops.i2c_gate_ctrl(fe, 1);
  261. for (i = 0; i < cnt; i++) {
  262. u8 b0[] = { subAddress + i };
  263. struct i2c_msg msg[] = {
  264. {
  265. .addr = state->config->tuner_address,
  266. .flags = 0,
  267. .buf = b0,
  268. .len = 1
  269. }, {
  270. .addr = state->config->tuner_address,
  271. .flags = I2C_M_RD,
  272. .buf = pData + i,
  273. .len = 1
  274. }
  275. };
  276. status = i2c_transfer(state->i2c, msg, 2);
  277. dprintk(2, "addr 0x%02x, ret = %d, val = 0x%02x\n",
  278. subAddress + i, status, *(pData + i));
  279. if (status < 0)
  280. break;
  281. }
  282. if (fe->ops.i2c_gate_ctrl)
  283. fe->ops.i2c_gate_ctrl(fe, 0);
  284. if (status < 0)
  285. printk(KERN_ERR "Can't read from address 0x%02x,\n",
  286. subAddress + i);
  287. return status;
  288. }
  289. /*
  290. * FIXME: Is this really needed?
  291. */
  292. static int MT2063_Sleep(struct dvb_frontend *fe)
  293. {
  294. /*
  295. * ToDo: Add code here to implement a OS blocking
  296. */
  297. msleep(100);
  298. return 0;
  299. }
  300. /*
  301. * Microtune spur avoidance
  302. */
  303. /* Implement ceiling, floor functions. */
  304. #define ceil(n, d) (((n) < 0) ? (-((-(n))/(d))) : (n)/(d) + ((n)%(d) != 0))
  305. #define floor(n, d) (((n) < 0) ? (-((-(n))/(d))) - ((n)%(d) != 0) : (n)/(d))
  306. struct MT2063_FIFZone_t {
  307. s32 min_;
  308. s32 max_;
  309. };
  310. static struct MT2063_ExclZone_t *InsertNode(struct MT2063_AvoidSpursData_t
  311. *pAS_Info,
  312. struct MT2063_ExclZone_t *pPrevNode)
  313. {
  314. struct MT2063_ExclZone_t *pNode;
  315. dprintk(2, "\n");
  316. /* Check for a node in the free list */
  317. if (pAS_Info->freeZones != NULL) {
  318. /* Use one from the free list */
  319. pNode = pAS_Info->freeZones;
  320. pAS_Info->freeZones = pNode->next_;
  321. } else {
  322. /* Grab a node from the array */
  323. pNode = &pAS_Info->MT2063_ExclZones[pAS_Info->nZones];
  324. }
  325. if (pPrevNode != NULL) {
  326. pNode->next_ = pPrevNode->next_;
  327. pPrevNode->next_ = pNode;
  328. } else { /* insert at the beginning of the list */
  329. pNode->next_ = pAS_Info->usedZones;
  330. pAS_Info->usedZones = pNode;
  331. }
  332. pAS_Info->nZones++;
  333. return pNode;
  334. }
  335. static struct MT2063_ExclZone_t *RemoveNode(struct MT2063_AvoidSpursData_t
  336. *pAS_Info,
  337. struct MT2063_ExclZone_t *pPrevNode,
  338. struct MT2063_ExclZone_t
  339. *pNodeToRemove)
  340. {
  341. struct MT2063_ExclZone_t *pNext = pNodeToRemove->next_;
  342. dprintk(2, "\n");
  343. /* Make previous node point to the subsequent node */
  344. if (pPrevNode != NULL)
  345. pPrevNode->next_ = pNext;
  346. /* Add pNodeToRemove to the beginning of the freeZones */
  347. pNodeToRemove->next_ = pAS_Info->freeZones;
  348. pAS_Info->freeZones = pNodeToRemove;
  349. /* Decrement node count */
  350. pAS_Info->nZones--;
  351. return pNext;
  352. }
  353. /*
  354. * MT_AddExclZone()
  355. *
  356. * Add (and merge) an exclusion zone into the list.
  357. * If the range (f_min, f_max) is totally outside the
  358. * 1st IF BW, ignore the entry.
  359. * If the range (f_min, f_max) is negative, ignore the entry.
  360. */
  361. static void MT2063_AddExclZone(struct MT2063_AvoidSpursData_t *pAS_Info,
  362. u32 f_min, u32 f_max)
  363. {
  364. struct MT2063_ExclZone_t *pNode = pAS_Info->usedZones;
  365. struct MT2063_ExclZone_t *pPrev = NULL;
  366. struct MT2063_ExclZone_t *pNext = NULL;
  367. dprintk(2, "\n");
  368. /* Check to see if this overlaps the 1st IF filter */
  369. if ((f_max > (pAS_Info->f_if1_Center - (pAS_Info->f_if1_bw / 2)))
  370. && (f_min < (pAS_Info->f_if1_Center + (pAS_Info->f_if1_bw / 2)))
  371. && (f_min < f_max)) {
  372. /*
  373. * 1 2 3 4 5 6
  374. *
  375. * New entry: |---| |--| |--| |-| |---| |--|
  376. * or or or or or
  377. * Existing: |--| |--| |--| |---| |-| |--|
  378. */
  379. /* Check for our place in the list */
  380. while ((pNode != NULL) && (pNode->max_ < f_min)) {
  381. pPrev = pNode;
  382. pNode = pNode->next_;
  383. }
  384. if ((pNode != NULL) && (pNode->min_ < f_max)) {
  385. /* Combine me with pNode */
  386. if (f_min < pNode->min_)
  387. pNode->min_ = f_min;
  388. if (f_max > pNode->max_)
  389. pNode->max_ = f_max;
  390. } else {
  391. pNode = InsertNode(pAS_Info, pPrev);
  392. pNode->min_ = f_min;
  393. pNode->max_ = f_max;
  394. }
  395. /* Look for merging possibilities */
  396. pNext = pNode->next_;
  397. while ((pNext != NULL) && (pNext->min_ < pNode->max_)) {
  398. if (pNext->max_ > pNode->max_)
  399. pNode->max_ = pNext->max_;
  400. /* Remove pNext, return ptr to pNext->next */
  401. pNext = RemoveNode(pAS_Info, pNode, pNext);
  402. }
  403. }
  404. }
  405. /*
  406. * Reset all exclusion zones.
  407. * Add zones to protect the PLL FracN regions near zero
  408. */
  409. static void MT2063_ResetExclZones(struct MT2063_AvoidSpursData_t *pAS_Info)
  410. {
  411. u32 center;
  412. dprintk(2, "\n");
  413. pAS_Info->nZones = 0; /* this clears the used list */
  414. pAS_Info->usedZones = NULL; /* reset ptr */
  415. pAS_Info->freeZones = NULL; /* reset ptr */
  416. center =
  417. pAS_Info->f_ref *
  418. ((pAS_Info->f_if1_Center - pAS_Info->f_if1_bw / 2 +
  419. pAS_Info->f_in) / pAS_Info->f_ref) - pAS_Info->f_in;
  420. while (center <
  421. pAS_Info->f_if1_Center + pAS_Info->f_if1_bw / 2 +
  422. pAS_Info->f_LO1_FracN_Avoid) {
  423. /* Exclude LO1 FracN */
  424. MT2063_AddExclZone(pAS_Info,
  425. center - pAS_Info->f_LO1_FracN_Avoid,
  426. center - 1);
  427. MT2063_AddExclZone(pAS_Info, center + 1,
  428. center + pAS_Info->f_LO1_FracN_Avoid);
  429. center += pAS_Info->f_ref;
  430. }
  431. center =
  432. pAS_Info->f_ref *
  433. ((pAS_Info->f_if1_Center - pAS_Info->f_if1_bw / 2 -
  434. pAS_Info->f_out) / pAS_Info->f_ref) + pAS_Info->f_out;
  435. while (center <
  436. pAS_Info->f_if1_Center + pAS_Info->f_if1_bw / 2 +
  437. pAS_Info->f_LO2_FracN_Avoid) {
  438. /* Exclude LO2 FracN */
  439. MT2063_AddExclZone(pAS_Info,
  440. center - pAS_Info->f_LO2_FracN_Avoid,
  441. center - 1);
  442. MT2063_AddExclZone(pAS_Info, center + 1,
  443. center + pAS_Info->f_LO2_FracN_Avoid);
  444. center += pAS_Info->f_ref;
  445. }
  446. if (MT2063_EXCLUDE_US_DECT_FREQUENCIES(pAS_Info->avoidDECT)) {
  447. /* Exclude LO1 values that conflict with DECT channels */
  448. MT2063_AddExclZone(pAS_Info, 1920836000 - pAS_Info->f_in, 1922236000 - pAS_Info->f_in); /* Ctr = 1921.536 */
  449. MT2063_AddExclZone(pAS_Info, 1922564000 - pAS_Info->f_in, 1923964000 - pAS_Info->f_in); /* Ctr = 1923.264 */
  450. MT2063_AddExclZone(pAS_Info, 1924292000 - pAS_Info->f_in, 1925692000 - pAS_Info->f_in); /* Ctr = 1924.992 */
  451. MT2063_AddExclZone(pAS_Info, 1926020000 - pAS_Info->f_in, 1927420000 - pAS_Info->f_in); /* Ctr = 1926.720 */
  452. MT2063_AddExclZone(pAS_Info, 1927748000 - pAS_Info->f_in, 1929148000 - pAS_Info->f_in); /* Ctr = 1928.448 */
  453. }
  454. if (MT2063_EXCLUDE_EURO_DECT_FREQUENCIES(pAS_Info->avoidDECT)) {
  455. MT2063_AddExclZone(pAS_Info, 1896644000 - pAS_Info->f_in, 1898044000 - pAS_Info->f_in); /* Ctr = 1897.344 */
  456. MT2063_AddExclZone(pAS_Info, 1894916000 - pAS_Info->f_in, 1896316000 - pAS_Info->f_in); /* Ctr = 1895.616 */
  457. MT2063_AddExclZone(pAS_Info, 1893188000 - pAS_Info->f_in, 1894588000 - pAS_Info->f_in); /* Ctr = 1893.888 */
  458. MT2063_AddExclZone(pAS_Info, 1891460000 - pAS_Info->f_in, 1892860000 - pAS_Info->f_in); /* Ctr = 1892.16 */
  459. MT2063_AddExclZone(pAS_Info, 1889732000 - pAS_Info->f_in, 1891132000 - pAS_Info->f_in); /* Ctr = 1890.432 */
  460. MT2063_AddExclZone(pAS_Info, 1888004000 - pAS_Info->f_in, 1889404000 - pAS_Info->f_in); /* Ctr = 1888.704 */
  461. MT2063_AddExclZone(pAS_Info, 1886276000 - pAS_Info->f_in, 1887676000 - pAS_Info->f_in); /* Ctr = 1886.976 */
  462. MT2063_AddExclZone(pAS_Info, 1884548000 - pAS_Info->f_in, 1885948000 - pAS_Info->f_in); /* Ctr = 1885.248 */
  463. MT2063_AddExclZone(pAS_Info, 1882820000 - pAS_Info->f_in, 1884220000 - pAS_Info->f_in); /* Ctr = 1883.52 */
  464. MT2063_AddExclZone(pAS_Info, 1881092000 - pAS_Info->f_in, 1882492000 - pAS_Info->f_in); /* Ctr = 1881.792 */
  465. }
  466. }
  467. /*
  468. * MT_ChooseFirstIF - Choose the best available 1st IF
  469. * If f_Desired is not excluded, choose that first.
  470. * Otherwise, return the value closest to f_Center that is
  471. * not excluded
  472. */
  473. static u32 MT2063_ChooseFirstIF(struct MT2063_AvoidSpursData_t *pAS_Info)
  474. {
  475. /*
  476. * Update "f_Desired" to be the nearest "combinational-multiple" of
  477. * "f_LO1_Step".
  478. * The resulting number, F_LO1 must be a multiple of f_LO1_Step.
  479. * And F_LO1 is the arithmetic sum of f_in + f_Center.
  480. * Neither f_in, nor f_Center must be a multiple of f_LO1_Step.
  481. * However, the sum must be.
  482. */
  483. const u32 f_Desired =
  484. pAS_Info->f_LO1_Step *
  485. ((pAS_Info->f_if1_Request + pAS_Info->f_in +
  486. pAS_Info->f_LO1_Step / 2) / pAS_Info->f_LO1_Step) -
  487. pAS_Info->f_in;
  488. const u32 f_Step =
  489. (pAS_Info->f_LO1_Step >
  490. pAS_Info->f_LO2_Step) ? pAS_Info->f_LO1_Step : pAS_Info->
  491. f_LO2_Step;
  492. u32 f_Center;
  493. s32 i;
  494. s32 j = 0;
  495. u32 bDesiredExcluded = 0;
  496. u32 bZeroExcluded = 0;
  497. s32 tmpMin, tmpMax;
  498. s32 bestDiff;
  499. struct MT2063_ExclZone_t *pNode = pAS_Info->usedZones;
  500. struct MT2063_FIFZone_t zones[MT2063_MAX_ZONES];
  501. dprintk(2, "\n");
  502. if (pAS_Info->nZones == 0)
  503. return f_Desired;
  504. /*
  505. * f_Center needs to be an integer multiple of f_Step away
  506. * from f_Desired
  507. */
  508. if (pAS_Info->f_if1_Center > f_Desired)
  509. f_Center =
  510. f_Desired +
  511. f_Step *
  512. ((pAS_Info->f_if1_Center - f_Desired +
  513. f_Step / 2) / f_Step);
  514. else
  515. f_Center =
  516. f_Desired -
  517. f_Step *
  518. ((f_Desired - pAS_Info->f_if1_Center +
  519. f_Step / 2) / f_Step);
  520. /*
  521. * Take MT_ExclZones, center around f_Center and change the
  522. * resolution to f_Step
  523. */
  524. while (pNode != NULL) {
  525. /* floor function */
  526. tmpMin =
  527. floor((s32) (pNode->min_ - f_Center), (s32) f_Step);
  528. /* ceil function */
  529. tmpMax =
  530. ceil((s32) (pNode->max_ - f_Center), (s32) f_Step);
  531. if ((pNode->min_ < f_Desired) && (pNode->max_ > f_Desired))
  532. bDesiredExcluded = 1;
  533. if ((tmpMin < 0) && (tmpMax > 0))
  534. bZeroExcluded = 1;
  535. /* See if this zone overlaps the previous */
  536. if ((j > 0) && (tmpMin < zones[j - 1].max_))
  537. zones[j - 1].max_ = tmpMax;
  538. else {
  539. /* Add new zone */
  540. zones[j].min_ = tmpMin;
  541. zones[j].max_ = tmpMax;
  542. j++;
  543. }
  544. pNode = pNode->next_;
  545. }
  546. /*
  547. * If the desired is okay, return with it
  548. */
  549. if (bDesiredExcluded == 0)
  550. return f_Desired;
  551. /*
  552. * If the desired is excluded and the center is okay, return with it
  553. */
  554. if (bZeroExcluded == 0)
  555. return f_Center;
  556. /* Find the value closest to 0 (f_Center) */
  557. bestDiff = zones[0].min_;
  558. for (i = 0; i < j; i++) {
  559. if (abs(zones[i].min_) < abs(bestDiff))
  560. bestDiff = zones[i].min_;
  561. if (abs(zones[i].max_) < abs(bestDiff))
  562. bestDiff = zones[i].max_;
  563. }
  564. if (bestDiff < 0)
  565. return f_Center - ((u32) (-bestDiff) * f_Step);
  566. return f_Center + (bestDiff * f_Step);
  567. }
  568. /**
  569. * IsSpurInBand() - Checks to see if a spur will be present within the IF's
  570. * bandwidth. (fIFOut +/- fIFBW, -fIFOut +/- fIFBW)
  571. *
  572. * ma mb mc md
  573. * <--+-+-+-------------------+-------------------+-+-+-->
  574. * | ^ 0 ^ |
  575. * ^ b=-fIFOut+fIFBW/2 -b=+fIFOut-fIFBW/2 ^
  576. * a=-fIFOut-fIFBW/2 -a=+fIFOut+fIFBW/2
  577. *
  578. * Note that some equations are doubled to prevent round-off
  579. * problems when calculating fIFBW/2
  580. *
  581. * @pAS_Info: Avoid Spurs information block
  582. * @fm: If spur, amount f_IF1 has to move negative
  583. * @fp: If spur, amount f_IF1 has to move positive
  584. *
  585. * Returns 1 if an LO spur would be present, otherwise 0.
  586. */
  587. static u32 IsSpurInBand(struct MT2063_AvoidSpursData_t *pAS_Info,
  588. u32 *fm, u32 * fp)
  589. {
  590. /*
  591. ** Calculate LO frequency settings.
  592. */
  593. u32 n, n0;
  594. const u32 f_LO1 = pAS_Info->f_LO1;
  595. const u32 f_LO2 = pAS_Info->f_LO2;
  596. const u32 d = pAS_Info->f_out + pAS_Info->f_out_bw / 2;
  597. const u32 c = d - pAS_Info->f_out_bw;
  598. const u32 f = pAS_Info->f_zif_bw / 2;
  599. const u32 f_Scale = (f_LO1 / (UINT_MAX / 2 / pAS_Info->maxH1)) + 1;
  600. s32 f_nsLO1, f_nsLO2;
  601. s32 f_Spur;
  602. u32 ma, mb, mc, md, me, mf;
  603. u32 lo_gcd, gd_Scale, gc_Scale, gf_Scale, hgds, hgfs, hgcs;
  604. dprintk(2, "\n");
  605. *fm = 0;
  606. /*
  607. ** For each edge (d, c & f), calculate a scale, based on the gcd
  608. ** of f_LO1, f_LO2 and the edge value. Use the larger of this
  609. ** gcd-based scale factor or f_Scale.
  610. */
  611. lo_gcd = gcd(f_LO1, f_LO2);
  612. gd_Scale = max((u32) gcd(lo_gcd, d), f_Scale);
  613. hgds = gd_Scale / 2;
  614. gc_Scale = max((u32) gcd(lo_gcd, c), f_Scale);
  615. hgcs = gc_Scale / 2;
  616. gf_Scale = max((u32) gcd(lo_gcd, f), f_Scale);
  617. hgfs = gf_Scale / 2;
  618. n0 = DIV_ROUND_UP(f_LO2 - d, f_LO1 - f_LO2);
  619. /* Check out all multiples of LO1 from n0 to m_maxLOSpurHarmonic */
  620. for (n = n0; n <= pAS_Info->maxH1; ++n) {
  621. md = (n * ((f_LO1 + hgds) / gd_Scale) -
  622. ((d + hgds) / gd_Scale)) / ((f_LO2 + hgds) / gd_Scale);
  623. /* If # fLO2 harmonics > m_maxLOSpurHarmonic, then no spurs present */
  624. if (md >= pAS_Info->maxH1)
  625. break;
  626. ma = (n * ((f_LO1 + hgds) / gd_Scale) +
  627. ((d + hgds) / gd_Scale)) / ((f_LO2 + hgds) / gd_Scale);
  628. /* If no spurs between +/- (f_out + f_IFBW/2), then try next harmonic */
  629. if (md == ma)
  630. continue;
  631. mc = (n * ((f_LO1 + hgcs) / gc_Scale) -
  632. ((c + hgcs) / gc_Scale)) / ((f_LO2 + hgcs) / gc_Scale);
  633. if (mc != md) {
  634. f_nsLO1 = (s32) (n * (f_LO1 / gc_Scale));
  635. f_nsLO2 = (s32) (mc * (f_LO2 / gc_Scale));
  636. f_Spur =
  637. (gc_Scale * (f_nsLO1 - f_nsLO2)) +
  638. n * (f_LO1 % gc_Scale) - mc * (f_LO2 % gc_Scale);
  639. *fp = ((f_Spur - (s32) c) / (mc - n)) + 1;
  640. *fm = (((s32) d - f_Spur) / (mc - n)) + 1;
  641. return 1;
  642. }
  643. /* Location of Zero-IF-spur to be checked */
  644. me = (n * ((f_LO1 + hgfs) / gf_Scale) +
  645. ((f + hgfs) / gf_Scale)) / ((f_LO2 + hgfs) / gf_Scale);
  646. mf = (n * ((f_LO1 + hgfs) / gf_Scale) -
  647. ((f + hgfs) / gf_Scale)) / ((f_LO2 + hgfs) / gf_Scale);
  648. if (me != mf) {
  649. f_nsLO1 = n * (f_LO1 / gf_Scale);
  650. f_nsLO2 = me * (f_LO2 / gf_Scale);
  651. f_Spur =
  652. (gf_Scale * (f_nsLO1 - f_nsLO2)) +
  653. n * (f_LO1 % gf_Scale) - me * (f_LO2 % gf_Scale);
  654. *fp = ((f_Spur + (s32) f) / (me - n)) + 1;
  655. *fm = (((s32) f - f_Spur) / (me - n)) + 1;
  656. return 1;
  657. }
  658. mb = (n * ((f_LO1 + hgcs) / gc_Scale) +
  659. ((c + hgcs) / gc_Scale)) / ((f_LO2 + hgcs) / gc_Scale);
  660. if (ma != mb) {
  661. f_nsLO1 = n * (f_LO1 / gc_Scale);
  662. f_nsLO2 = ma * (f_LO2 / gc_Scale);
  663. f_Spur =
  664. (gc_Scale * (f_nsLO1 - f_nsLO2)) +
  665. n * (f_LO1 % gc_Scale) - ma * (f_LO2 % gc_Scale);
  666. *fp = (((s32) d + f_Spur) / (ma - n)) + 1;
  667. *fm = (-(f_Spur + (s32) c) / (ma - n)) + 1;
  668. return 1;
  669. }
  670. }
  671. /* No spurs found */
  672. return 0;
  673. }
  674. /*
  675. * MT_AvoidSpurs() - Main entry point to avoid spurs.
  676. * Checks for existing spurs in present LO1, LO2 freqs
  677. * and if present, chooses spur-free LO1, LO2 combination
  678. * that tunes the same input/output frequencies.
  679. */
  680. static u32 MT2063_AvoidSpurs(struct MT2063_AvoidSpursData_t *pAS_Info)
  681. {
  682. int status = 0;
  683. u32 fm, fp; /* restricted range on LO's */
  684. pAS_Info->bSpurAvoided = 0;
  685. pAS_Info->nSpursFound = 0;
  686. dprintk(2, "\n");
  687. if (pAS_Info->maxH1 == 0)
  688. return 0;
  689. /*
  690. * Avoid LO Generated Spurs
  691. *
  692. * Make sure that have no LO-related spurs within the IF output
  693. * bandwidth.
  694. *
  695. * If there is an LO spur in this band, start at the current IF1 frequency
  696. * and work out until we find a spur-free frequency or run up against the
  697. * 1st IF SAW band edge. Use temporary copies of fLO1 and fLO2 so that they
  698. * will be unchanged if a spur-free setting is not found.
  699. */
  700. pAS_Info->bSpurPresent = IsSpurInBand(pAS_Info, &fm, &fp);
  701. if (pAS_Info->bSpurPresent) {
  702. u32 zfIF1 = pAS_Info->f_LO1 - pAS_Info->f_in; /* current attempt at a 1st IF */
  703. u32 zfLO1 = pAS_Info->f_LO1; /* current attempt at an LO1 freq */
  704. u32 zfLO2 = pAS_Info->f_LO2; /* current attempt at an LO2 freq */
  705. u32 delta_IF1;
  706. u32 new_IF1;
  707. /*
  708. ** Spur was found, attempt to find a spur-free 1st IF
  709. */
  710. do {
  711. pAS_Info->nSpursFound++;
  712. /* Raise f_IF1_upper, if needed */
  713. MT2063_AddExclZone(pAS_Info, zfIF1 - fm, zfIF1 + fp);
  714. /* Choose next IF1 that is closest to f_IF1_CENTER */
  715. new_IF1 = MT2063_ChooseFirstIF(pAS_Info);
  716. if (new_IF1 > zfIF1) {
  717. pAS_Info->f_LO1 += (new_IF1 - zfIF1);
  718. pAS_Info->f_LO2 += (new_IF1 - zfIF1);
  719. } else {
  720. pAS_Info->f_LO1 -= (zfIF1 - new_IF1);
  721. pAS_Info->f_LO2 -= (zfIF1 - new_IF1);
  722. }
  723. zfIF1 = new_IF1;
  724. if (zfIF1 > pAS_Info->f_if1_Center)
  725. delta_IF1 = zfIF1 - pAS_Info->f_if1_Center;
  726. else
  727. delta_IF1 = pAS_Info->f_if1_Center - zfIF1;
  728. pAS_Info->bSpurPresent = IsSpurInBand(pAS_Info, &fm, &fp);
  729. /*
  730. * Continue while the new 1st IF is still within the 1st IF bandwidth
  731. * and there is a spur in the band (again)
  732. */
  733. } while ((2 * delta_IF1 + pAS_Info->f_out_bw <= pAS_Info->f_if1_bw) && pAS_Info->bSpurPresent);
  734. /*
  735. * Use the LO-spur free values found. If the search went all
  736. * the way to the 1st IF band edge and always found spurs, just
  737. * leave the original choice. It's as "good" as any other.
  738. */
  739. if (pAS_Info->bSpurPresent == 1) {
  740. status |= MT2063_SPUR_PRESENT_ERR;
  741. pAS_Info->f_LO1 = zfLO1;
  742. pAS_Info->f_LO2 = zfLO2;
  743. } else
  744. pAS_Info->bSpurAvoided = 1;
  745. }
  746. status |=
  747. ((pAS_Info->
  748. nSpursFound << MT2063_SPUR_SHIFT) & MT2063_SPUR_CNT_MASK);
  749. return status;
  750. }
  751. /*
  752. * Constants used by the tuning algorithm
  753. */
  754. #define MT2063_REF_FREQ (16000000UL) /* Reference oscillator Frequency (in Hz) */
  755. #define MT2063_IF1_BW (22000000UL) /* The IF1 filter bandwidth (in Hz) */
  756. #define MT2063_TUNE_STEP_SIZE (50000UL) /* Tune in steps of 50 kHz */
  757. #define MT2063_SPUR_STEP_HZ (250000UL) /* Step size (in Hz) to move IF1 when avoiding spurs */
  758. #define MT2063_ZIF_BW (2000000UL) /* Zero-IF spur-free bandwidth (in Hz) */
  759. #define MT2063_MAX_HARMONICS_1 (15UL) /* Highest intra-tuner LO Spur Harmonic to be avoided */
  760. #define MT2063_MAX_HARMONICS_2 (5UL) /* Highest inter-tuner LO Spur Harmonic to be avoided */
  761. #define MT2063_MIN_LO_SEP (1000000UL) /* Minimum inter-tuner LO frequency separation */
  762. #define MT2063_LO1_FRACN_AVOID (0UL) /* LO1 FracN numerator avoid region (in Hz) */
  763. #define MT2063_LO2_FRACN_AVOID (199999UL) /* LO2 FracN numerator avoid region (in Hz) */
  764. #define MT2063_MIN_FIN_FREQ (44000000UL) /* Minimum input frequency (in Hz) */
  765. #define MT2063_MAX_FIN_FREQ (1100000000UL) /* Maximum input frequency (in Hz) */
  766. #define MT2063_MIN_FOUT_FREQ (36000000UL) /* Minimum output frequency (in Hz) */
  767. #define MT2063_MAX_FOUT_FREQ (57000000UL) /* Maximum output frequency (in Hz) */
  768. #define MT2063_MIN_DNC_FREQ (1293000000UL) /* Minimum LO2 frequency (in Hz) */
  769. #define MT2063_MAX_DNC_FREQ (1614000000UL) /* Maximum LO2 frequency (in Hz) */
  770. #define MT2063_MIN_UPC_FREQ (1396000000UL) /* Minimum LO1 frequency (in Hz) */
  771. #define MT2063_MAX_UPC_FREQ (2750000000UL) /* Maximum LO1 frequency (in Hz) */
  772. /*
  773. * Define the supported Part/Rev codes for the MT2063
  774. */
  775. #define MT2063_B0 (0x9B)
  776. #define MT2063_B1 (0x9C)
  777. #define MT2063_B2 (0x9D)
  778. #define MT2063_B3 (0x9E)
  779. /**
  780. * mt2063_lockStatus - Checks to see if LO1 and LO2 are locked
  781. *
  782. * @state: struct mt2063_state pointer
  783. *
  784. * This function returns 0, if no lock, 1 if locked and a value < 1 if error
  785. */
  786. static int mt2063_lockStatus(struct mt2063_state *state)
  787. {
  788. const u32 nMaxWait = 100; /* wait a maximum of 100 msec */
  789. const u32 nPollRate = 2; /* poll status bits every 2 ms */
  790. const u32 nMaxLoops = nMaxWait / nPollRate;
  791. const u8 LO1LK = 0x80;
  792. u8 LO2LK = 0x08;
  793. int status;
  794. u32 nDelays = 0;
  795. dprintk(2, "\n");
  796. /* LO2 Lock bit was in a different place for B0 version */
  797. if (state->tuner_id == MT2063_B0)
  798. LO2LK = 0x40;
  799. do {
  800. status = mt2063_read(state, MT2063_REG_LO_STATUS,
  801. &state->reg[MT2063_REG_LO_STATUS], 1);
  802. if (status < 0)
  803. return status;
  804. if ((state->reg[MT2063_REG_LO_STATUS] & (LO1LK | LO2LK)) ==
  805. (LO1LK | LO2LK)) {
  806. return TUNER_STATUS_LOCKED | TUNER_STATUS_STEREO;
  807. }
  808. msleep(nPollRate); /* Wait between retries */
  809. } while (++nDelays < nMaxLoops);
  810. /*
  811. * Got no lock or partial lock
  812. */
  813. return 0;
  814. }
  815. /*
  816. * Constants for setting receiver modes.
  817. * (6 modes defined at this time, enumerated by mt2063_delivery_sys)
  818. * (DNC1GC & DNC2GC are the values, which are used, when the specific
  819. * DNC Output is selected, the other is always off)
  820. *
  821. * enum mt2063_delivery_sys
  822. * -------------+----------------------------------------------
  823. * Mode 0 : | MT2063_CABLE_QAM
  824. * Mode 1 : | MT2063_CABLE_ANALOG
  825. * Mode 2 : | MT2063_OFFAIR_COFDM
  826. * Mode 3 : | MT2063_OFFAIR_COFDM_SAWLESS
  827. * Mode 4 : | MT2063_OFFAIR_ANALOG
  828. * Mode 5 : | MT2063_OFFAIR_8VSB
  829. * --------------+----------------------------------------------
  830. *
  831. * |<---------- Mode -------------->|
  832. * Reg Field | 0 | 1 | 2 | 3 | 4 | 5 |
  833. * ------------+-----+-----+-----+-----+-----+-----+
  834. * RFAGCen | OFF | OFF | OFF | OFF | OFF | OFF
  835. * LNARin | 0 | 0 | 3 | 3 | 3 | 3
  836. * FIFFQen | 1 | 1 | 1 | 1 | 1 | 1
  837. * FIFFq | 0 | 0 | 0 | 0 | 0 | 0
  838. * DNC1gc | 0 | 0 | 0 | 0 | 0 | 0
  839. * DNC2gc | 0 | 0 | 0 | 0 | 0 | 0
  840. * GCU Auto | 1 | 1 | 1 | 1 | 1 | 1
  841. * LNA max Atn | 31 | 31 | 31 | 31 | 31 | 31
  842. * LNA Target | 44 | 43 | 43 | 43 | 43 | 43
  843. * ign RF Ovl | 0 | 0 | 0 | 0 | 0 | 0
  844. * RF max Atn | 31 | 31 | 31 | 31 | 31 | 31
  845. * PD1 Target | 36 | 36 | 38 | 38 | 36 | 38
  846. * ign FIF Ovl | 0 | 0 | 0 | 0 | 0 | 0
  847. * FIF max Atn | 5 | 5 | 5 | 5 | 5 | 5
  848. * PD2 Target | 40 | 33 | 42 | 42 | 33 | 42
  849. */
  850. enum mt2063_delivery_sys {
  851. MT2063_CABLE_QAM = 0,
  852. MT2063_CABLE_ANALOG,
  853. MT2063_OFFAIR_COFDM,
  854. MT2063_OFFAIR_COFDM_SAWLESS,
  855. MT2063_OFFAIR_ANALOG,
  856. MT2063_OFFAIR_8VSB,
  857. MT2063_NUM_RCVR_MODES
  858. };
  859. static const char *mt2063_mode_name[] = {
  860. [MT2063_CABLE_QAM] = "digital cable",
  861. [MT2063_CABLE_ANALOG] = "analog cable",
  862. [MT2063_OFFAIR_COFDM] = "digital offair",
  863. [MT2063_OFFAIR_COFDM_SAWLESS] = "digital offair without SAW",
  864. [MT2063_OFFAIR_ANALOG] = "analog offair",
  865. [MT2063_OFFAIR_8VSB] = "analog offair 8vsb",
  866. };
  867. static const u8 RFAGCEN[] = { 0, 0, 0, 0, 0, 0 };
  868. static const u8 LNARIN[] = { 0, 0, 3, 3, 3, 3 };
  869. static const u8 FIFFQEN[] = { 1, 1, 1, 1, 1, 1 };
  870. static const u8 FIFFQ[] = { 0, 0, 0, 0, 0, 0 };
  871. static const u8 DNC1GC[] = { 0, 0, 0, 0, 0, 0 };
  872. static const u8 DNC2GC[] = { 0, 0, 0, 0, 0, 0 };
  873. static const u8 ACLNAMAX[] = { 31, 31, 31, 31, 31, 31 };
  874. static const u8 LNATGT[] = { 44, 43, 43, 43, 43, 43 };
  875. static const u8 RFOVDIS[] = { 0, 0, 0, 0, 0, 0 };
  876. static const u8 ACRFMAX[] = { 31, 31, 31, 31, 31, 31 };
  877. static const u8 PD1TGT[] = { 36, 36, 38, 38, 36, 38 };
  878. static const u8 FIFOVDIS[] = { 0, 0, 0, 0, 0, 0 };
  879. static const u8 ACFIFMAX[] = { 29, 29, 29, 29, 29, 29 };
  880. static const u8 PD2TGT[] = { 40, 33, 38, 42, 30, 38 };
  881. /*
  882. * mt2063_set_dnc_output_enable()
  883. */
  884. static u32 mt2063_get_dnc_output_enable(struct mt2063_state *state,
  885. enum MT2063_DNC_Output_Enable *pValue)
  886. {
  887. dprintk(2, "\n");
  888. if ((state->reg[MT2063_REG_DNC_GAIN] & 0x03) == 0x03) { /* if DNC1 is off */
  889. if ((state->reg[MT2063_REG_VGA_GAIN] & 0x03) == 0x03) /* if DNC2 is off */
  890. *pValue = MT2063_DNC_NONE;
  891. else
  892. *pValue = MT2063_DNC_2;
  893. } else { /* DNC1 is on */
  894. if ((state->reg[MT2063_REG_VGA_GAIN] & 0x03) == 0x03) /* if DNC2 is off */
  895. *pValue = MT2063_DNC_1;
  896. else
  897. *pValue = MT2063_DNC_BOTH;
  898. }
  899. return 0;
  900. }
  901. /*
  902. * mt2063_set_dnc_output_enable()
  903. */
  904. static u32 mt2063_set_dnc_output_enable(struct mt2063_state *state,
  905. enum MT2063_DNC_Output_Enable nValue)
  906. {
  907. int status = 0; /* Status to be returned */
  908. u8 val = 0;
  909. dprintk(2, "\n");
  910. /* selects, which DNC output is used */
  911. switch (nValue) {
  912. case MT2063_DNC_NONE:
  913. val = (state->reg[MT2063_REG_DNC_GAIN] & 0xFC) | 0x03; /* Set DNC1GC=3 */
  914. if (state->reg[MT2063_REG_DNC_GAIN] !=
  915. val)
  916. status |=
  917. mt2063_setreg(state,
  918. MT2063_REG_DNC_GAIN,
  919. val);
  920. val = (state->reg[MT2063_REG_VGA_GAIN] & 0xFC) | 0x03; /* Set DNC2GC=3 */
  921. if (state->reg[MT2063_REG_VGA_GAIN] !=
  922. val)
  923. status |=
  924. mt2063_setreg(state,
  925. MT2063_REG_VGA_GAIN,
  926. val);
  927. val = (state->reg[MT2063_REG_RSVD_20] & ~0x40); /* Set PD2MUX=0 */
  928. if (state->reg[MT2063_REG_RSVD_20] !=
  929. val)
  930. status |=
  931. mt2063_setreg(state,
  932. MT2063_REG_RSVD_20,
  933. val);
  934. break;
  935. case MT2063_DNC_1:
  936. val = (state->reg[MT2063_REG_DNC_GAIN] & 0xFC) | (DNC1GC[state->rcvr_mode] & 0x03); /* Set DNC1GC=x */
  937. if (state->reg[MT2063_REG_DNC_GAIN] !=
  938. val)
  939. status |=
  940. mt2063_setreg(state,
  941. MT2063_REG_DNC_GAIN,
  942. val);
  943. val = (state->reg[MT2063_REG_VGA_GAIN] & 0xFC) | 0x03; /* Set DNC2GC=3 */
  944. if (state->reg[MT2063_REG_VGA_GAIN] !=
  945. val)
  946. status |=
  947. mt2063_setreg(state,
  948. MT2063_REG_VGA_GAIN,
  949. val);
  950. val = (state->reg[MT2063_REG_RSVD_20] & ~0x40); /* Set PD2MUX=0 */
  951. if (state->reg[MT2063_REG_RSVD_20] !=
  952. val)
  953. status |=
  954. mt2063_setreg(state,
  955. MT2063_REG_RSVD_20,
  956. val);
  957. break;
  958. case MT2063_DNC_2:
  959. val = (state->reg[MT2063_REG_DNC_GAIN] & 0xFC) | 0x03; /* Set DNC1GC=3 */
  960. if (state->reg[MT2063_REG_DNC_GAIN] !=
  961. val)
  962. status |=
  963. mt2063_setreg(state,
  964. MT2063_REG_DNC_GAIN,
  965. val);
  966. val = (state->reg[MT2063_REG_VGA_GAIN] & 0xFC) | (DNC2GC[state->rcvr_mode] & 0x03); /* Set DNC2GC=x */
  967. if (state->reg[MT2063_REG_VGA_GAIN] !=
  968. val)
  969. status |=
  970. mt2063_setreg(state,
  971. MT2063_REG_VGA_GAIN,
  972. val);
  973. val = (state->reg[MT2063_REG_RSVD_20] | 0x40); /* Set PD2MUX=1 */
  974. if (state->reg[MT2063_REG_RSVD_20] !=
  975. val)
  976. status |=
  977. mt2063_setreg(state,
  978. MT2063_REG_RSVD_20,
  979. val);
  980. break;
  981. case MT2063_DNC_BOTH:
  982. val = (state->reg[MT2063_REG_DNC_GAIN] & 0xFC) | (DNC1GC[state->rcvr_mode] & 0x03); /* Set DNC1GC=x */
  983. if (state->reg[MT2063_REG_DNC_GAIN] !=
  984. val)
  985. status |=
  986. mt2063_setreg(state,
  987. MT2063_REG_DNC_GAIN,
  988. val);
  989. val = (state->reg[MT2063_REG_VGA_GAIN] & 0xFC) | (DNC2GC[state->rcvr_mode] & 0x03); /* Set DNC2GC=x */
  990. if (state->reg[MT2063_REG_VGA_GAIN] !=
  991. val)
  992. status |=
  993. mt2063_setreg(state,
  994. MT2063_REG_VGA_GAIN,
  995. val);
  996. val = (state->reg[MT2063_REG_RSVD_20] | 0x40); /* Set PD2MUX=1 */
  997. if (state->reg[MT2063_REG_RSVD_20] !=
  998. val)
  999. status |=
  1000. mt2063_setreg(state,
  1001. MT2063_REG_RSVD_20,
  1002. val);
  1003. break;
  1004. default:
  1005. break;
  1006. }
  1007. return status;
  1008. }
  1009. /*
  1010. * MT2063_SetReceiverMode() - Set the MT2063 receiver mode, according with
  1011. * the selected enum mt2063_delivery_sys type.
  1012. *
  1013. * (DNC1GC & DNC2GC are the values, which are used, when the specific
  1014. * DNC Output is selected, the other is always off)
  1015. *
  1016. * @state: ptr to mt2063_state structure
  1017. * @Mode: desired receiver delivery system
  1018. *
  1019. * Note: Register cache must be valid for it to work
  1020. */
  1021. static u32 MT2063_SetReceiverMode(struct mt2063_state *state,
  1022. enum mt2063_delivery_sys Mode)
  1023. {
  1024. int status = 0; /* Status to be returned */
  1025. u8 val;
  1026. u32 longval;
  1027. dprintk(2, "\n");
  1028. if (Mode >= MT2063_NUM_RCVR_MODES)
  1029. status = -ERANGE;
  1030. /* RFAGCen */
  1031. if (status >= 0) {
  1032. val =
  1033. (state->
  1034. reg[MT2063_REG_PD1_TGT] & ~0x40) | (RFAGCEN[Mode]
  1035. ? 0x40 :
  1036. 0x00);
  1037. if (state->reg[MT2063_REG_PD1_TGT] != val)
  1038. status |= mt2063_setreg(state, MT2063_REG_PD1_TGT, val);
  1039. }
  1040. /* LNARin */
  1041. if (status >= 0) {
  1042. u8 val = (state->reg[MT2063_REG_CTRL_2C] & ~0x03) |
  1043. (LNARIN[Mode] & 0x03);
  1044. if (state->reg[MT2063_REG_CTRL_2C] != val)
  1045. status |= mt2063_setreg(state, MT2063_REG_CTRL_2C, val);
  1046. }
  1047. /* FIFFQEN and FIFFQ */
  1048. if (status >= 0) {
  1049. val =
  1050. (state->
  1051. reg[MT2063_REG_FIFF_CTRL2] & ~0xF0) |
  1052. (FIFFQEN[Mode] << 7) | (FIFFQ[Mode] << 4);
  1053. if (state->reg[MT2063_REG_FIFF_CTRL2] != val) {
  1054. status |=
  1055. mt2063_setreg(state, MT2063_REG_FIFF_CTRL2, val);
  1056. /* trigger FIFF calibration, needed after changing FIFFQ */
  1057. val =
  1058. (state->reg[MT2063_REG_FIFF_CTRL] | 0x01);
  1059. status |=
  1060. mt2063_setreg(state, MT2063_REG_FIFF_CTRL, val);
  1061. val =
  1062. (state->
  1063. reg[MT2063_REG_FIFF_CTRL] & ~0x01);
  1064. status |=
  1065. mt2063_setreg(state, MT2063_REG_FIFF_CTRL, val);
  1066. }
  1067. }
  1068. /* DNC1GC & DNC2GC */
  1069. status |= mt2063_get_dnc_output_enable(state, &longval);
  1070. status |= mt2063_set_dnc_output_enable(state, longval);
  1071. /* acLNAmax */
  1072. if (status >= 0) {
  1073. u8 val = (state->reg[MT2063_REG_LNA_OV] & ~0x1F) |
  1074. (ACLNAMAX[Mode] & 0x1F);
  1075. if (state->reg[MT2063_REG_LNA_OV] != val)
  1076. status |= mt2063_setreg(state, MT2063_REG_LNA_OV, val);
  1077. }
  1078. /* LNATGT */
  1079. if (status >= 0) {
  1080. u8 val = (state->reg[MT2063_REG_LNA_TGT] & ~0x3F) |
  1081. (LNATGT[Mode] & 0x3F);
  1082. if (state->reg[MT2063_REG_LNA_TGT] != val)
  1083. status |= mt2063_setreg(state, MT2063_REG_LNA_TGT, val);
  1084. }
  1085. /* ACRF */
  1086. if (status >= 0) {
  1087. u8 val = (state->reg[MT2063_REG_RF_OV] & ~0x1F) |
  1088. (ACRFMAX[Mode] & 0x1F);
  1089. if (state->reg[MT2063_REG_RF_OV] != val)
  1090. status |= mt2063_setreg(state, MT2063_REG_RF_OV, val);
  1091. }
  1092. /* PD1TGT */
  1093. if (status >= 0) {
  1094. u8 val = (state->reg[MT2063_REG_PD1_TGT] & ~0x3F) |
  1095. (PD1TGT[Mode] & 0x3F);
  1096. if (state->reg[MT2063_REG_PD1_TGT] != val)
  1097. status |= mt2063_setreg(state, MT2063_REG_PD1_TGT, val);
  1098. }
  1099. /* FIFATN */
  1100. if (status >= 0) {
  1101. u8 val = ACFIFMAX[Mode];
  1102. if (state->reg[MT2063_REG_PART_REV] != MT2063_B3 && val > 5)
  1103. val = 5;
  1104. val = (state->reg[MT2063_REG_FIF_OV] & ~0x1F) |
  1105. (val & 0x1F);
  1106. if (state->reg[MT2063_REG_FIF_OV] != val)
  1107. status |= mt2063_setreg(state, MT2063_REG_FIF_OV, val);
  1108. }
  1109. /* PD2TGT */
  1110. if (status >= 0) {
  1111. u8 val = (state->reg[MT2063_REG_PD2_TGT] & ~0x3F) |
  1112. (PD2TGT[Mode] & 0x3F);
  1113. if (state->reg[MT2063_REG_PD2_TGT] != val)
  1114. status |= mt2063_setreg(state, MT2063_REG_PD2_TGT, val);
  1115. }
  1116. /* Ignore ATN Overload */
  1117. if (status >= 0) {
  1118. val = (state->reg[MT2063_REG_LNA_TGT] & ~0x80) |
  1119. (RFOVDIS[Mode] ? 0x80 : 0x00);
  1120. if (state->reg[MT2063_REG_LNA_TGT] != val)
  1121. status |= mt2063_setreg(state, MT2063_REG_LNA_TGT, val);
  1122. }
  1123. /* Ignore FIF Overload */
  1124. if (status >= 0) {
  1125. val = (state->reg[MT2063_REG_PD1_TGT] & ~0x80) |
  1126. (FIFOVDIS[Mode] ? 0x80 : 0x00);
  1127. if (state->reg[MT2063_REG_PD1_TGT] != val)
  1128. status |= mt2063_setreg(state, MT2063_REG_PD1_TGT, val);
  1129. }
  1130. if (status >= 0) {
  1131. state->rcvr_mode = Mode;
  1132. dprintk(1, "mt2063 mode changed to %s\n",
  1133. mt2063_mode_name[state->rcvr_mode]);
  1134. }
  1135. return status;
  1136. }
  1137. /*
  1138. * MT2063_ClearPowerMaskBits () - Clears the power-down mask bits for various
  1139. * sections of the MT2063
  1140. *
  1141. * @Bits: Mask bits to be cleared.
  1142. *
  1143. * See definition of MT2063_Mask_Bits type for description
  1144. * of each of the power bits.
  1145. */
  1146. static u32 MT2063_ClearPowerMaskBits(struct mt2063_state *state,
  1147. enum MT2063_Mask_Bits Bits)
  1148. {
  1149. int status = 0;
  1150. dprintk(2, "\n");
  1151. Bits = (enum MT2063_Mask_Bits)(Bits & MT2063_ALL_SD); /* Only valid bits for this tuner */
  1152. if ((Bits & 0xFF00) != 0) {
  1153. state->reg[MT2063_REG_PWR_2] &= ~(u8) (Bits >> 8);
  1154. status |=
  1155. mt2063_write(state,
  1156. MT2063_REG_PWR_2,
  1157. &state->reg[MT2063_REG_PWR_2], 1);
  1158. }
  1159. if ((Bits & 0xFF) != 0) {
  1160. state->reg[MT2063_REG_PWR_1] &= ~(u8) (Bits & 0xFF);
  1161. status |=
  1162. mt2063_write(state,
  1163. MT2063_REG_PWR_1,
  1164. &state->reg[MT2063_REG_PWR_1], 1);
  1165. }
  1166. return status;
  1167. }
  1168. /*
  1169. * MT2063_SoftwareShutdown() - Enables or disables software shutdown function.
  1170. * When Shutdown is 1, any section whose power
  1171. * mask is set will be shutdown.
  1172. */
  1173. static u32 MT2063_SoftwareShutdown(struct mt2063_state *state, u8 Shutdown)
  1174. {
  1175. int status;
  1176. dprintk(2, "\n");
  1177. if (Shutdown == 1)
  1178. state->reg[MT2063_REG_PWR_1] |= 0x04;
  1179. else
  1180. state->reg[MT2063_REG_PWR_1] &= ~0x04;
  1181. status = mt2063_write(state,
  1182. MT2063_REG_PWR_1,
  1183. &state->reg[MT2063_REG_PWR_1], 1);
  1184. if (Shutdown != 1) {
  1185. state->reg[MT2063_REG_BYP_CTRL] =
  1186. (state->reg[MT2063_REG_BYP_CTRL] & 0x9F) | 0x40;
  1187. status |=
  1188. mt2063_write(state,
  1189. MT2063_REG_BYP_CTRL,
  1190. &state->reg[MT2063_REG_BYP_CTRL],
  1191. 1);
  1192. state->reg[MT2063_REG_BYP_CTRL] =
  1193. (state->reg[MT2063_REG_BYP_CTRL] & 0x9F);
  1194. status |=
  1195. mt2063_write(state,
  1196. MT2063_REG_BYP_CTRL,
  1197. &state->reg[MT2063_REG_BYP_CTRL],
  1198. 1);
  1199. }
  1200. return status;
  1201. }
  1202. static u32 MT2063_Round_fLO(u32 f_LO, u32 f_LO_Step, u32 f_ref)
  1203. {
  1204. return f_ref * (f_LO / f_ref)
  1205. + f_LO_Step * (((f_LO % f_ref) + (f_LO_Step / 2)) / f_LO_Step);
  1206. }
  1207. /**
  1208. * fLO_FractionalTerm() - Calculates the portion contributed by FracN / denom.
  1209. * This function preserves maximum precision without
  1210. * risk of overflow. It accurately calculates
  1211. * f_ref * num / denom to within 1 HZ with fixed math.
  1212. *
  1213. * @f_ref: SRO frequency.
  1214. * @num: Fractional portion of the multiplier
  1215. * @denom: denominator portion of the ratio
  1216. *
  1217. * This calculation handles f_ref as two separate 14-bit fields.
  1218. * Therefore, a maximum value of 2^28-1 may safely be used for f_ref.
  1219. * This is the genesis of the magic number "14" and the magic mask value of
  1220. * 0x03FFF.
  1221. *
  1222. * This routine successfully handles denom values up to and including 2^18.
  1223. * Returns: f_ref * num / denom
  1224. */
  1225. static u32 MT2063_fLO_FractionalTerm(u32 f_ref, u32 num, u32 denom)
  1226. {
  1227. u32 t1 = (f_ref >> 14) * num;
  1228. u32 term1 = t1 / denom;
  1229. u32 loss = t1 % denom;
  1230. u32 term2 =
  1231. (((f_ref & 0x00003FFF) * num + (loss << 14)) + (denom / 2)) / denom;
  1232. return (term1 << 14) + term2;
  1233. }
  1234. /*
  1235. * CalcLO1Mult()- Calculates Integer divider value and the numerator
  1236. * value for a FracN PLL.
  1237. *
  1238. * This function assumes that the f_LO and f_Ref are
  1239. * evenly divisible by f_LO_Step.
  1240. *
  1241. * @Div: OUTPUT: Whole number portion of the multiplier
  1242. * @FracN: OUTPUT: Fractional portion of the multiplier
  1243. * @f_LO: desired LO frequency.
  1244. * @f_LO_Step: Minimum step size for the LO (in Hz).
  1245. * @f_Ref: SRO frequency.
  1246. * @f_Avoid: Range of PLL frequencies to avoid near integer multiples
  1247. * of f_Ref (in Hz).
  1248. *
  1249. * Returns: Recalculated LO frequency.
  1250. */
  1251. static u32 MT2063_CalcLO1Mult(u32 *Div,
  1252. u32 *FracN,
  1253. u32 f_LO,
  1254. u32 f_LO_Step, u32 f_Ref)
  1255. {
  1256. /* Calculate the whole number portion of the divider */
  1257. *Div = f_LO / f_Ref;
  1258. /* Calculate the numerator value (round to nearest f_LO_Step) */
  1259. *FracN =
  1260. (64 * (((f_LO % f_Ref) + (f_LO_Step / 2)) / f_LO_Step) +
  1261. (f_Ref / f_LO_Step / 2)) / (f_Ref / f_LO_Step);
  1262. return (f_Ref * (*Div)) + MT2063_fLO_FractionalTerm(f_Ref, *FracN, 64);
  1263. }
  1264. /**
  1265. * CalcLO2Mult() - Calculates Integer divider value and the numerator
  1266. * value for a FracN PLL.
  1267. *
  1268. * This function assumes that the f_LO and f_Ref are
  1269. * evenly divisible by f_LO_Step.
  1270. *
  1271. * @Div: OUTPUT: Whole number portion of the multiplier
  1272. * @FracN: OUTPUT: Fractional portion of the multiplier
  1273. * @f_LO: desired LO frequency.
  1274. * @f_LO_Step: Minimum step size for the LO (in Hz).
  1275. * @f_Ref: SRO frequency.
  1276. *
  1277. * Returns: Recalculated LO frequency.
  1278. */
  1279. static u32 MT2063_CalcLO2Mult(u32 *Div,
  1280. u32 *FracN,
  1281. u32 f_LO,
  1282. u32 f_LO_Step, u32 f_Ref)
  1283. {
  1284. /* Calculate the whole number portion of the divider */
  1285. *Div = f_LO / f_Ref;
  1286. /* Calculate the numerator value (round to nearest f_LO_Step) */
  1287. *FracN =
  1288. (8191 * (((f_LO % f_Ref) + (f_LO_Step / 2)) / f_LO_Step) +
  1289. (f_Ref / f_LO_Step / 2)) / (f_Ref / f_LO_Step);
  1290. return (f_Ref * (*Div)) + MT2063_fLO_FractionalTerm(f_Ref, *FracN,
  1291. 8191);
  1292. }
  1293. /*
  1294. * FindClearTuneFilter() - Calculate the corrrect ClearTune filter to be
  1295. * used for a given input frequency.
  1296. *
  1297. * @state: ptr to tuner data structure
  1298. * @f_in: RF input center frequency (in Hz).
  1299. *
  1300. * Returns: ClearTune filter number (0-31)
  1301. */
  1302. static u32 FindClearTuneFilter(struct mt2063_state *state, u32 f_in)
  1303. {
  1304. u32 RFBand;
  1305. u32 idx; /* index loop */
  1306. /*
  1307. ** Find RF Band setting
  1308. */
  1309. RFBand = 31; /* def when f_in > all */
  1310. for (idx = 0; idx < 31; ++idx) {
  1311. if (state->CTFiltMax[idx] >= f_in) {
  1312. RFBand = idx;
  1313. break;
  1314. }
  1315. }
  1316. return RFBand;
  1317. }
  1318. /*
  1319. * MT2063_Tune() - Change the tuner's tuned frequency to RFin.
  1320. */
  1321. static u32 MT2063_Tune(struct mt2063_state *state, u32 f_in)
  1322. { /* RF input center frequency */
  1323. int status = 0;
  1324. u32 LO1; /* 1st LO register value */
  1325. u32 Num1; /* Numerator for LO1 reg. value */
  1326. u32 f_IF1; /* 1st IF requested */
  1327. u32 LO2; /* 2nd LO register value */
  1328. u32 Num2; /* Numerator for LO2 reg. value */
  1329. u32 ofLO1, ofLO2; /* last time's LO frequencies */
  1330. u8 fiffc = 0x80; /* FIFF center freq from tuner */
  1331. u32 fiffof; /* Offset from FIFF center freq */
  1332. const u8 LO1LK = 0x80; /* Mask for LO1 Lock bit */
  1333. u8 LO2LK = 0x08; /* Mask for LO2 Lock bit */
  1334. u8 val;
  1335. u32 RFBand;
  1336. dprintk(2, "\n");
  1337. /* Check the input and output frequency ranges */
  1338. if ((f_in < MT2063_MIN_FIN_FREQ) || (f_in > MT2063_MAX_FIN_FREQ))
  1339. return -EINVAL;
  1340. if ((state->AS_Data.f_out < MT2063_MIN_FOUT_FREQ)
  1341. || (state->AS_Data.f_out > MT2063_MAX_FOUT_FREQ))
  1342. return -EINVAL;
  1343. /*
  1344. * Save original LO1 and LO2 register values
  1345. */
  1346. ofLO1 = state->AS_Data.f_LO1;
  1347. ofLO2 = state->AS_Data.f_LO2;
  1348. /*
  1349. * Find and set RF Band setting
  1350. */
  1351. if (state->ctfilt_sw == 1) {
  1352. val = (state->reg[MT2063_REG_CTUNE_CTRL] | 0x08);
  1353. if (state->reg[MT2063_REG_CTUNE_CTRL] != val) {
  1354. status |=
  1355. mt2063_setreg(state, MT2063_REG_CTUNE_CTRL, val);
  1356. }
  1357. val = state->reg[MT2063_REG_CTUNE_OV];
  1358. RFBand = FindClearTuneFilter(state, f_in);
  1359. state->reg[MT2063_REG_CTUNE_OV] =
  1360. (u8) ((state->reg[MT2063_REG_CTUNE_OV] & ~0x1F)
  1361. | RFBand);
  1362. if (state->reg[MT2063_REG_CTUNE_OV] != val) {
  1363. status |=
  1364. mt2063_setreg(state, MT2063_REG_CTUNE_OV, val);
  1365. }
  1366. }
  1367. /*
  1368. * Read the FIFF Center Frequency from the tuner
  1369. */
  1370. if (status >= 0) {
  1371. status |=
  1372. mt2063_read(state,
  1373. MT2063_REG_FIFFC,
  1374. &state->reg[MT2063_REG_FIFFC], 1);
  1375. fiffc = state->reg[MT2063_REG_FIFFC];
  1376. }
  1377. /*
  1378. * Assign in the requested values
  1379. */
  1380. state->AS_Data.f_in = f_in;
  1381. /* Request a 1st IF such that LO1 is on a step size */
  1382. state->AS_Data.f_if1_Request =
  1383. MT2063_Round_fLO(state->AS_Data.f_if1_Request + f_in,
  1384. state->AS_Data.f_LO1_Step,
  1385. state->AS_Data.f_ref) - f_in;
  1386. /*
  1387. * Calculate frequency settings. f_IF1_FREQ + f_in is the
  1388. * desired LO1 frequency
  1389. */
  1390. MT2063_ResetExclZones(&state->AS_Data);
  1391. f_IF1 = MT2063_ChooseFirstIF(&state->AS_Data);
  1392. state->AS_Data.f_LO1 =
  1393. MT2063_Round_fLO(f_IF1 + f_in, state->AS_Data.f_LO1_Step,
  1394. state->AS_Data.f_ref);
  1395. state->AS_Data.f_LO2 =
  1396. MT2063_Round_fLO(state->AS_Data.f_LO1 - state->AS_Data.f_out - f_in,
  1397. state->AS_Data.f_LO2_Step, state->AS_Data.f_ref);
  1398. /*
  1399. * Check for any LO spurs in the output bandwidth and adjust
  1400. * the LO settings to avoid them if needed
  1401. */
  1402. status |= MT2063_AvoidSpurs(&state->AS_Data);
  1403. /*
  1404. * MT_AvoidSpurs spurs may have changed the LO1 & LO2 values.
  1405. * Recalculate the LO frequencies and the values to be placed
  1406. * in the tuning registers.
  1407. */
  1408. state->AS_Data.f_LO1 =
  1409. MT2063_CalcLO1Mult(&LO1, &Num1, state->AS_Data.f_LO1,
  1410. state->AS_Data.f_LO1_Step, state->AS_Data.f_ref);
  1411. state->AS_Data.f_LO2 =
  1412. MT2063_Round_fLO(state->AS_Data.f_LO1 - state->AS_Data.f_out - f_in,
  1413. state->AS_Data.f_LO2_Step, state->AS_Data.f_ref);
  1414. state->AS_Data.f_LO2 =
  1415. MT2063_CalcLO2Mult(&LO2, &Num2, state->AS_Data.f_LO2,
  1416. state->AS_Data.f_LO2_Step, state->AS_Data.f_ref);
  1417. /*
  1418. * Check the upconverter and downconverter frequency ranges
  1419. */
  1420. if ((state->AS_Data.f_LO1 < MT2063_MIN_UPC_FREQ)
  1421. || (state->AS_Data.f_LO1 > MT2063_MAX_UPC_FREQ))
  1422. status |= MT2063_UPC_RANGE;
  1423. if ((state->AS_Data.f_LO2 < MT2063_MIN_DNC_FREQ)
  1424. || (state->AS_Data.f_LO2 > MT2063_MAX_DNC_FREQ))
  1425. status |= MT2063_DNC_RANGE;
  1426. /* LO2 Lock bit was in a different place for B0 version */
  1427. if (state->tuner_id == MT2063_B0)
  1428. LO2LK = 0x40;
  1429. /*
  1430. * If we have the same LO frequencies and we're already locked,
  1431. * then skip re-programming the LO registers.
  1432. */
  1433. if ((ofLO1 != state->AS_Data.f_LO1)
  1434. || (ofLO2 != state->AS_Data.f_LO2)
  1435. || ((state->reg[MT2063_REG_LO_STATUS] & (LO1LK | LO2LK)) !=
  1436. (LO1LK | LO2LK))) {
  1437. /*
  1438. * Calculate the FIFFOF register value
  1439. *
  1440. * IF1_Actual
  1441. * FIFFOF = ------------ - 8 * FIFFC - 4992
  1442. * f_ref/64
  1443. */
  1444. fiffof =
  1445. (state->AS_Data.f_LO1 -
  1446. f_in) / (state->AS_Data.f_ref / 64) - 8 * (u32) fiffc -
  1447. 4992;
  1448. if (fiffof > 0xFF)
  1449. fiffof = 0xFF;
  1450. /*
  1451. * Place all of the calculated values into the local tuner
  1452. * register fields.
  1453. */
  1454. if (status >= 0) {
  1455. state->reg[MT2063_REG_LO1CQ_1] = (u8) (LO1 & 0xFF); /* DIV1q */
  1456. state->reg[MT2063_REG_LO1CQ_2] = (u8) (Num1 & 0x3F); /* NUM1q */
  1457. state->reg[MT2063_REG_LO2CQ_1] = (u8) (((LO2 & 0x7F) << 1) /* DIV2q */
  1458. |(Num2 >> 12)); /* NUM2q (hi) */
  1459. state->reg[MT2063_REG_LO2CQ_2] = (u8) ((Num2 & 0x0FF0) >> 4); /* NUM2q (mid) */
  1460. state->reg[MT2063_REG_LO2CQ_3] = (u8) (0xE0 | (Num2 & 0x000F)); /* NUM2q (lo) */
  1461. /*
  1462. * Now write out the computed register values
  1463. * IMPORTANT: There is a required order for writing
  1464. * (0x05 must follow all the others).
  1465. */
  1466. status |= mt2063_write(state, MT2063_REG_LO1CQ_1, &state->reg[MT2063_REG_LO1CQ_1], 5); /* 0x01 - 0x05 */
  1467. if (state->tuner_id == MT2063_B0) {
  1468. /* Re-write the one-shot bits to trigger the tune operation */
  1469. status |= mt2063_write(state, MT2063_REG_LO2CQ_3, &state->reg[MT2063_REG_LO2CQ_3], 1); /* 0x05 */
  1470. }
  1471. /* Write out the FIFF offset only if it's changing */
  1472. if (state->reg[MT2063_REG_FIFF_OFFSET] !=
  1473. (u8) fiffof) {
  1474. state->reg[MT2063_REG_FIFF_OFFSET] =
  1475. (u8) fiffof;
  1476. status |=
  1477. mt2063_write(state,
  1478. MT2063_REG_FIFF_OFFSET,
  1479. &state->
  1480. reg[MT2063_REG_FIFF_OFFSET],
  1481. 1);
  1482. }
  1483. }
  1484. /*
  1485. * Check for LO's locking
  1486. */
  1487. if (status < 0)
  1488. return status;
  1489. status = mt2063_lockStatus(state);
  1490. if (status < 0)
  1491. return status;
  1492. if (!status)
  1493. return -EINVAL; /* Couldn't lock */
  1494. /*
  1495. * If we locked OK, assign calculated data to mt2063_state structure
  1496. */
  1497. state->f_IF1_actual = state->AS_Data.f_LO1 - f_in;
  1498. }
  1499. return status;
  1500. }
  1501. static const u8 MT2063B0_defaults[] = {
  1502. /* Reg, Value */
  1503. 0x19, 0x05,
  1504. 0x1B, 0x1D,
  1505. 0x1C, 0x1F,
  1506. 0x1D, 0x0F,
  1507. 0x1E, 0x3F,
  1508. 0x1F, 0x0F,
  1509. 0x20, 0x3F,
  1510. 0x22, 0x21,
  1511. 0x23, 0x3F,
  1512. 0x24, 0x20,
  1513. 0x25, 0x3F,
  1514. 0x27, 0xEE,
  1515. 0x2C, 0x27, /* bit at 0x20 is cleared below */
  1516. 0x30, 0x03,
  1517. 0x2C, 0x07, /* bit at 0x20 is cleared here */
  1518. 0x2D, 0x87,
  1519. 0x2E, 0xAA,
  1520. 0x28, 0xE1, /* Set the FIFCrst bit here */
  1521. 0x28, 0xE0, /* Clear the FIFCrst bit here */
  1522. 0x00
  1523. };
  1524. /* writing 0x05 0xf0 sw-resets all registers, so we write only needed changes */
  1525. static const u8 MT2063B1_defaults[] = {
  1526. /* Reg, Value */
  1527. 0x05, 0xF0,
  1528. 0x11, 0x10, /* New Enable AFCsd */
  1529. 0x19, 0x05,
  1530. 0x1A, 0x6C,
  1531. 0x1B, 0x24,
  1532. 0x1C, 0x28,
  1533. 0x1D, 0x8F,
  1534. 0x1E, 0x14,
  1535. 0x1F, 0x8F,
  1536. 0x20, 0x57,
  1537. 0x22, 0x21, /* New - ver 1.03 */
  1538. 0x23, 0x3C, /* New - ver 1.10 */
  1539. 0x24, 0x20, /* New - ver 1.03 */
  1540. 0x2C, 0x24, /* bit at 0x20 is cleared below */
  1541. 0x2D, 0x87, /* FIFFQ=0 */
  1542. 0x2F, 0xF3,
  1543. 0x30, 0x0C, /* New - ver 1.11 */
  1544. 0x31, 0x1B, /* New - ver 1.11 */
  1545. 0x2C, 0x04, /* bit at 0x20 is cleared here */
  1546. 0x28, 0xE1, /* Set the FIFCrst bit here */
  1547. 0x28, 0xE0, /* Clear the FIFCrst bit here */
  1548. 0x00
  1549. };
  1550. /* writing 0x05 0xf0 sw-resets all registers, so we write only needed changes */
  1551. static const u8 MT2063B3_defaults[] = {
  1552. /* Reg, Value */
  1553. 0x05, 0xF0,
  1554. 0x19, 0x3D,
  1555. 0x2C, 0x24, /* bit at 0x20 is cleared below */
  1556. 0x2C, 0x04, /* bit at 0x20 is cleared here */
  1557. 0x28, 0xE1, /* Set the FIFCrst bit here */
  1558. 0x28, 0xE0, /* Clear the FIFCrst bit here */
  1559. 0x00
  1560. };
  1561. static int mt2063_init(struct dvb_frontend *fe)
  1562. {
  1563. int status;
  1564. struct mt2063_state *state = fe->tuner_priv;
  1565. u8 all_resets = 0xF0; /* reset/load bits */
  1566. const u8 *def = NULL;
  1567. char *step;
  1568. u32 FCRUN;
  1569. s32 maxReads;
  1570. u32 fcu_osc;
  1571. u32 i;
  1572. dprintk(2, "\n");
  1573. state->rcvr_mode = MT2063_CABLE_QAM;
  1574. /* Read the Part/Rev code from the tuner */
  1575. status = mt2063_read(state, MT2063_REG_PART_REV,
  1576. &state->reg[MT2063_REG_PART_REV], 1);
  1577. if (status < 0) {
  1578. printk(KERN_ERR "Can't read mt2063 part ID\n");
  1579. return status;
  1580. }
  1581. /* Check the part/rev code */
  1582. switch (state->reg[MT2063_REG_PART_REV]) {
  1583. case MT2063_B0:
  1584. step = "B0";
  1585. break;
  1586. case MT2063_B1:
  1587. step = "B1";
  1588. break;
  1589. case MT2063_B2:
  1590. step = "B2";
  1591. break;
  1592. case MT2063_B3:
  1593. step = "B3";
  1594. break;
  1595. default:
  1596. printk(KERN_ERR "mt2063: Unknown mt2063 device ID (0x%02x)\n",
  1597. state->reg[MT2063_REG_PART_REV]);
  1598. return -ENODEV; /* Wrong tuner Part/Rev code */
  1599. }
  1600. /* Check the 2nd byte of the Part/Rev code from the tuner */
  1601. status = mt2063_read(state, MT2063_REG_RSVD_3B,
  1602. &state->reg[MT2063_REG_RSVD_3B], 1);
  1603. /* b7 != 0 ==> NOT MT2063 */
  1604. if (status < 0 || ((state->reg[MT2063_REG_RSVD_3B] & 0x80) != 0x00)) {
  1605. printk(KERN_ERR "mt2063: Unknown part ID (0x%02x%02x)\n",
  1606. state->reg[MT2063_REG_PART_REV],
  1607. state->reg[MT2063_REG_RSVD_3B]);
  1608. return -ENODEV; /* Wrong tuner Part/Rev code */
  1609. }
  1610. printk(KERN_INFO "mt2063: detected a mt2063 %s\n", step);
  1611. /* Reset the tuner */
  1612. status = mt2063_write(state, MT2063_REG_LO2CQ_3, &all_resets, 1);
  1613. if (status < 0)
  1614. return status;
  1615. /* change all of the default values that vary from the HW reset values */
  1616. /* def = (state->reg[PART_REV] == MT2063_B0) ? MT2063B0_defaults : MT2063B1_defaults; */
  1617. switch (state->reg[MT2063_REG_PART_REV]) {
  1618. case MT2063_B3:
  1619. def = MT2063B3_defaults;
  1620. break;
  1621. case MT2063_B1:
  1622. def = MT2063B1_defaults;
  1623. break;
  1624. case MT2063_B0:
  1625. def = MT2063B0_defaults;
  1626. break;
  1627. default:
  1628. return -ENODEV;
  1629. break;
  1630. }
  1631. while (status >= 0 && *def) {
  1632. u8 reg = *def++;
  1633. u8 val = *def++;
  1634. status = mt2063_write(state, reg, &val, 1);
  1635. }
  1636. if (status < 0)
  1637. return status;
  1638. /* Wait for FIFF location to complete. */
  1639. FCRUN = 1;
  1640. maxReads = 10;
  1641. while (status >= 0 && (FCRUN != 0) && (maxReads-- > 0)) {
  1642. msleep(2);
  1643. status = mt2063_read(state,
  1644. MT2063_REG_XO_STATUS,
  1645. &state->
  1646. reg[MT2063_REG_XO_STATUS], 1);
  1647. FCRUN = (state->reg[MT2063_REG_XO_STATUS] & 0x40) >> 6;
  1648. }
  1649. if (FCRUN != 0 || status < 0)
  1650. return -ENODEV;
  1651. status = mt2063_read(state,
  1652. MT2063_REG_FIFFC,
  1653. &state->reg[MT2063_REG_FIFFC], 1);
  1654. if (status < 0)
  1655. return status;
  1656. /* Read back all the registers from the tuner */
  1657. status = mt2063_read(state,
  1658. MT2063_REG_PART_REV,
  1659. state->reg, MT2063_REG_END_REGS);
  1660. if (status < 0)
  1661. return status;
  1662. /* Initialize the tuner state. */
  1663. state->tuner_id = state->reg[MT2063_REG_PART_REV];
  1664. state->AS_Data.f_ref = MT2063_REF_FREQ;
  1665. state->AS_Data.f_if1_Center = (state->AS_Data.f_ref / 8) *
  1666. ((u32) state->reg[MT2063_REG_FIFFC] + 640);
  1667. state->AS_Data.f_if1_bw = MT2063_IF1_BW;
  1668. state->AS_Data.f_out = 43750000UL;
  1669. state->AS_Data.f_out_bw = 6750000UL;
  1670. state->AS_Data.f_zif_bw = MT2063_ZIF_BW;
  1671. state->AS_Data.f_LO1_Step = state->AS_Data.f_ref / 64;
  1672. state->AS_Data.f_LO2_Step = MT2063_TUNE_STEP_SIZE;
  1673. state->AS_Data.maxH1 = MT2063_MAX_HARMONICS_1;
  1674. state->AS_Data.maxH2 = MT2063_MAX_HARMONICS_2;
  1675. state->AS_Data.f_min_LO_Separation = MT2063_MIN_LO_SEP;
  1676. state->AS_Data.f_if1_Request = state->AS_Data.f_if1_Center;
  1677. state->AS_Data.f_LO1 = 2181000000UL;
  1678. state->AS_Data.f_LO2 = 1486249786UL;
  1679. state->f_IF1_actual = state->AS_Data.f_if1_Center;
  1680. state->AS_Data.f_in = state->AS_Data.f_LO1 - state->f_IF1_actual;
  1681. state->AS_Data.f_LO1_FracN_Avoid = MT2063_LO1_FRACN_AVOID;
  1682. state->AS_Data.f_LO2_FracN_Avoid = MT2063_LO2_FRACN_AVOID;
  1683. state->num_regs = MT2063_REG_END_REGS;
  1684. state->AS_Data.avoidDECT = MT2063_AVOID_BOTH;
  1685. state->ctfilt_sw = 0;
  1686. state->CTFiltMax[0] = 69230000;
  1687. state->CTFiltMax[1] = 105770000;
  1688. state->CTFiltMax[2] = 140350000;
  1689. state->CTFiltMax[3] = 177110000;
  1690. state->CTFiltMax[4] = 212860000;
  1691. state->CTFiltMax[5] = 241130000;
  1692. state->CTFiltMax[6] = 274370000;
  1693. state->CTFiltMax[7] = 309820000;
  1694. state->CTFiltMax[8] = 342450000;
  1695. state->CTFiltMax[9] = 378870000;
  1696. state->CTFiltMax[10] = 416210000;
  1697. state->CTFiltMax[11] = 456500000;
  1698. state->CTFiltMax[12] = 495790000;
  1699. state->CTFiltMax[13] = 534530000;
  1700. state->CTFiltMax[14] = 572610000;
  1701. state->CTFiltMax[15] = 598970000;
  1702. state->CTFiltMax[16] = 635910000;
  1703. state->CTFiltMax[17] = 672130000;
  1704. state->CTFiltMax[18] = 714840000;
  1705. state->CTFiltMax[19] = 739660000;
  1706. state->CTFiltMax[20] = 770410000;
  1707. state->CTFiltMax[21] = 814660000;
  1708. state->CTFiltMax[22] = 846950000;
  1709. state->CTFiltMax[23] = 867820000;
  1710. state->CTFiltMax[24] = 915980000;
  1711. state->CTFiltMax[25] = 947450000;
  1712. state->CTFiltMax[26] = 983110000;
  1713. state->CTFiltMax[27] = 1021630000;
  1714. state->CTFiltMax[28] = 1061870000;
  1715. state->CTFiltMax[29] = 1098330000;
  1716. state->CTFiltMax[30] = 1138990000;
  1717. /*
  1718. ** Fetch the FCU osc value and use it and the fRef value to
  1719. ** scale all of the Band Max values
  1720. */
  1721. state->reg[MT2063_REG_CTUNE_CTRL] = 0x0A;
  1722. status = mt2063_write(state, MT2063_REG_CTUNE_CTRL,
  1723. &state->reg[MT2063_REG_CTUNE_CTRL], 1);
  1724. if (status < 0)
  1725. return status;
  1726. /* Read the ClearTune filter calibration value */
  1727. status = mt2063_read(state, MT2063_REG_FIFFC,
  1728. &state->reg[MT2063_REG_FIFFC], 1);
  1729. if (status < 0)
  1730. return status;
  1731. fcu_osc = state->reg[MT2063_REG_FIFFC];
  1732. state->reg[MT2063_REG_CTUNE_CTRL] = 0x00;
  1733. status = mt2063_write(state, MT2063_REG_CTUNE_CTRL,
  1734. &state->reg[MT2063_REG_CTUNE_CTRL], 1);
  1735. if (status < 0)
  1736. return status;
  1737. /* Adjust each of the values in the ClearTune filter cross-over table */
  1738. for (i = 0; i < 31; i++)
  1739. state->CTFiltMax[i] = (state->CTFiltMax[i] / 768) * (fcu_osc + 640);
  1740. status = MT2063_SoftwareShutdown(state, 1);
  1741. if (status < 0)
  1742. return status;
  1743. status = MT2063_ClearPowerMaskBits(state, MT2063_ALL_SD);
  1744. if (status < 0)
  1745. return status;
  1746. state->init = true;
  1747. return 0;
  1748. }
  1749. static int mt2063_get_status(struct dvb_frontend *fe, u32 *tuner_status)
  1750. {
  1751. struct mt2063_state *state = fe->tuner_priv;
  1752. int status;
  1753. dprintk(2, "\n");
  1754. if (!state->init)
  1755. return -ENODEV;
  1756. *tuner_status = 0;
  1757. status = mt2063_lockStatus(state);
  1758. if (status < 0)
  1759. return status;
  1760. if (status)
  1761. *tuner_status = TUNER_STATUS_LOCKED;
  1762. dprintk(1, "Tuner status: %d", *tuner_status);
  1763. return 0;
  1764. }
  1765. static void mt2063_release(struct dvb_frontend *fe)
  1766. {
  1767. struct mt2063_state *state = fe->tuner_priv;
  1768. dprintk(2, "\n");
  1769. fe->tuner_priv = NULL;
  1770. kfree(state);
  1771. }
  1772. static int mt2063_set_analog_params(struct dvb_frontend *fe,
  1773. struct analog_parameters *params)
  1774. {
  1775. struct mt2063_state *state = fe->tuner_priv;
  1776. s32 pict_car;
  1777. s32 pict2chanb_vsb;
  1778. s32 ch_bw;
  1779. s32 if_mid;
  1780. s32 rcvr_mode;
  1781. int status;
  1782. dprintk(2, "\n");
  1783. if (!state->init) {
  1784. status = mt2063_init(fe);
  1785. if (status < 0)
  1786. return status;
  1787. }
  1788. switch (params->mode) {
  1789. case V4L2_TUNER_RADIO:
  1790. pict_car = 38900000;
  1791. ch_bw = 8000000;
  1792. pict2chanb_vsb = -(ch_bw / 2);
  1793. rcvr_mode = MT2063_OFFAIR_ANALOG;
  1794. break;
  1795. case V4L2_TUNER_ANALOG_TV:
  1796. rcvr_mode = MT2063_CABLE_ANALOG;
  1797. if (params->std & ~V4L2_STD_MN) {
  1798. pict_car = 38900000;
  1799. ch_bw = 6000000;
  1800. pict2chanb_vsb = -1250000;
  1801. } else if (params->std & V4L2_STD_PAL_G) {
  1802. pict_car = 38900000;
  1803. ch_bw = 7000000;
  1804. pict2chanb_vsb = -1250000;
  1805. } else { /* PAL/SECAM standards */
  1806. pict_car = 38900000;
  1807. ch_bw = 8000000;
  1808. pict2chanb_vsb = -1250000;
  1809. }
  1810. break;
  1811. default:
  1812. return -EINVAL;
  1813. }
  1814. if_mid = pict_car - (pict2chanb_vsb + (ch_bw / 2));
  1815. state->AS_Data.f_LO2_Step = 125000; /* FIXME: probably 5000 for FM */
  1816. state->AS_Data.f_out = if_mid;
  1817. state->AS_Data.f_out_bw = ch_bw + 750000;
  1818. status = MT2063_SetReceiverMode(state, rcvr_mode);
  1819. if (status < 0)
  1820. return status;
  1821. dprintk(1, "Tuning to frequency: %d, bandwidth %d, foffset %d\n",
  1822. params->frequency, ch_bw, pict2chanb_vsb);
  1823. status = MT2063_Tune(state, (params->frequency + (pict2chanb_vsb + (ch_bw / 2))));
  1824. if (status < 0)
  1825. return status;
  1826. state->frequency = params->frequency;
  1827. return 0;
  1828. }
  1829. /*
  1830. * As defined on EN 300 429, the DVB-C roll-off factor is 0.15.
  1831. * So, the amount of the needed bandwidth is given by:
  1832. * Bw = Symbol_rate * (1 + 0.15)
  1833. * As such, the maximum symbol rate supported by 6 MHz is given by:
  1834. * max_symbol_rate = 6 MHz / 1.15 = 5217391 Bauds
  1835. */
  1836. #define MAX_SYMBOL_RATE_6MHz 5217391
  1837. static int mt2063_set_params(struct dvb_frontend *fe)
  1838. {
  1839. struct dtv_frontend_properties *c = &fe->dtv_property_cache;
  1840. struct mt2063_state *state = fe->tuner_priv;
  1841. int status;
  1842. s32 pict_car;
  1843. s32 pict2chanb_vsb;
  1844. s32 ch_bw;
  1845. s32 if_mid;
  1846. s32 rcvr_mode;
  1847. if (!state->init) {
  1848. status = mt2063_init(fe);
  1849. if (status < 0)
  1850. return status;
  1851. }
  1852. dprintk(2, "\n");
  1853. if (c->bandwidth_hz == 0)
  1854. return -EINVAL;
  1855. if (c->bandwidth_hz <= 6000000)
  1856. ch_bw = 6000000;
  1857. else if (c->bandwidth_hz <= 7000000)
  1858. ch_bw = 7000000;
  1859. else
  1860. ch_bw = 8000000;
  1861. switch (c->delivery_system) {
  1862. case SYS_DVBT:
  1863. rcvr_mode = MT2063_OFFAIR_COFDM;
  1864. pict_car = 36125000;
  1865. pict2chanb_vsb = -(ch_bw / 2);
  1866. break;
  1867. case SYS_DVBC_ANNEX_A:
  1868. case SYS_DVBC_ANNEX_C:
  1869. rcvr_mode = MT2063_CABLE_QAM;
  1870. pict_car = 36125000;
  1871. pict2chanb_vsb = -(ch_bw / 2);
  1872. break;
  1873. default:
  1874. return -EINVAL;
  1875. }
  1876. if_mid = pict_car - (pict2chanb_vsb + (ch_bw / 2));
  1877. state->AS_Data.f_LO2_Step = 125000; /* FIXME: probably 5000 for FM */
  1878. state->AS_Data.f_out = if_mid;
  1879. state->AS_Data.f_out_bw = ch_bw + 750000;
  1880. status = MT2063_SetReceiverMode(state, rcvr_mode);
  1881. if (status < 0)
  1882. return status;
  1883. dprintk(1, "Tuning to frequency: %d, bandwidth %d, foffset %d\n",
  1884. c->frequency, ch_bw, pict2chanb_vsb);
  1885. status = MT2063_Tune(state, (c->frequency + (pict2chanb_vsb + (ch_bw / 2))));
  1886. if (status < 0)
  1887. return status;
  1888. state->frequency = c->frequency;
  1889. return 0;
  1890. }
  1891. static int mt2063_get_if_frequency(struct dvb_frontend *fe, u32 *freq)
  1892. {
  1893. struct mt2063_state *state = fe->tuner_priv;
  1894. dprintk(2, "\n");
  1895. if (!state->init)
  1896. return -ENODEV;
  1897. *freq = state->AS_Data.f_out;
  1898. dprintk(1, "IF frequency: %d\n", *freq);
  1899. return 0;
  1900. }
  1901. static int mt2063_get_bandwidth(struct dvb_frontend *fe, u32 *bw)
  1902. {
  1903. struct mt2063_state *state = fe->tuner_priv;
  1904. dprintk(2, "\n");
  1905. if (!state->init)
  1906. return -ENODEV;
  1907. *bw = state->AS_Data.f_out_bw - 750000;
  1908. dprintk(1, "bandwidth: %d\n", *bw);
  1909. return 0;
  1910. }
  1911. static const struct dvb_tuner_ops mt2063_ops = {
  1912. .info = {
  1913. .name = "MT2063 Silicon Tuner",
  1914. .frequency_min_hz = 45 * MHz,
  1915. .frequency_max_hz = 865 * MHz,
  1916. },
  1917. .init = mt2063_init,
  1918. .sleep = MT2063_Sleep,
  1919. .get_status = mt2063_get_status,
  1920. .set_analog_params = mt2063_set_analog_params,
  1921. .set_params = mt2063_set_params,
  1922. .get_if_frequency = mt2063_get_if_frequency,
  1923. .get_bandwidth = mt2063_get_bandwidth,
  1924. .release = mt2063_release,
  1925. };
  1926. struct dvb_frontend *mt2063_attach(struct dvb_frontend *fe,
  1927. struct mt2063_config *config,
  1928. struct i2c_adapter *i2c)
  1929. {
  1930. struct mt2063_state *state = NULL;
  1931. dprintk(2, "\n");
  1932. state = kzalloc(sizeof(struct mt2063_state), GFP_KERNEL);
  1933. if (!state)
  1934. return NULL;
  1935. state->config = config;
  1936. state->i2c = i2c;
  1937. state->frontend = fe;
  1938. state->reference = config->refclock / 1000; /* kHz */
  1939. fe->tuner_priv = state;
  1940. fe->ops.tuner_ops = mt2063_ops;
  1941. printk(KERN_INFO "%s: Attaching MT2063\n", __func__);
  1942. return fe;
  1943. }
  1944. EXPORT_SYMBOL_GPL(mt2063_attach);
  1945. #if 0
  1946. /*
  1947. * Ancillary routines visible outside mt2063
  1948. * FIXME: Remove them in favor of using standard tuner callbacks
  1949. */
  1950. static int tuner_MT2063_SoftwareShutdown(struct dvb_frontend *fe)
  1951. {
  1952. struct mt2063_state *state = fe->tuner_priv;
  1953. int err = 0;
  1954. dprintk(2, "\n");
  1955. err = MT2063_SoftwareShutdown(state, 1);
  1956. if (err < 0)
  1957. printk(KERN_ERR "%s: Couldn't shutdown\n", __func__);
  1958. return err;
  1959. }
  1960. static int tuner_MT2063_ClearPowerMaskBits(struct dvb_frontend *fe)
  1961. {
  1962. struct mt2063_state *state = fe->tuner_priv;
  1963. int err = 0;
  1964. dprintk(2, "\n");
  1965. err = MT2063_ClearPowerMaskBits(state, MT2063_ALL_SD);
  1966. if (err < 0)
  1967. printk(KERN_ERR "%s: Invalid parameter\n", __func__);
  1968. return err;
  1969. }
  1970. #endif
  1971. MODULE_AUTHOR("Mauro Carvalho Chehab");
  1972. MODULE_DESCRIPTION("MT2063 Silicon tuner");
  1973. MODULE_LICENSE("GPL");