mt2060_priv.h 3.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * Driver for Microtune MT2060 "Single chip dual conversion broadband tuner"
  4. *
  5. * Copyright (c) 2006 Olivier DANET <odanet@caramail.com>
  6. */
  7. #ifndef MT2060_PRIV_H
  8. #define MT2060_PRIV_H
  9. // Uncomment the #define below to enable spurs checking. The results where quite unconvincing.
  10. // #define MT2060_SPURCHECK
  11. /* This driver is based on the information available in the datasheet of the
  12. "Comtech SDVBT-3K6M" tuner ( K1000737843.pdf ) which features the MT2060 register map :
  13. I2C Address : 0x60
  14. Reg.No | B7 | B6 | B5 | B4 | B3 | B2 | B1 | B0 | ( defaults )
  15. --------------------------------------------------------------------------------
  16. 00 | [ PART ] | [ REV ] | R = 0x63
  17. 01 | [ LNABAND ] | [ NUM1(5:2) ] | RW = 0x3F
  18. 02 | [ DIV1 ] | RW = 0x74
  19. 03 | FM1CA | FM1SS | [ NUM1(1:0) ] | [ NUM2(3:0) ] | RW = 0x00
  20. 04 | NUM2(11:4) ] | RW = 0x08
  21. 05 | [ DIV2 ] |NUM2(12)| RW = 0x93
  22. 06 | L1LK | [ TAD1 ] | L2LK | [ TAD2 ] | R
  23. 07 | [ FMF ] | R
  24. 08 | ? | FMCAL | ? | ? | ? | ? | ? | TEMP | R
  25. 09 | 0 | 0 | [ FMGC ] | 0 | GP02 | GP01 | 0 | RW = 0x20
  26. 0A | ??
  27. 0B | 0 | 0 | 1 | 1 | 0 | 0 | [ VGAG ] | RW = 0x30
  28. 0C | V1CSE | 1 | 1 | 1 | 1 | 1 | 1 | 1 | RW = 0xFF
  29. 0D | 1 | 0 | [ V1CS ] | RW = 0xB0
  30. 0E | ??
  31. 0F | ??
  32. 10 | ??
  33. 11 | [ LOTO ] | 0 | 0 | 1 | 0 | RW = 0x42
  34. PART : Part code : 6 for MT2060
  35. REV : Revision code : 3 for current revision
  36. LNABAND : Input frequency range : ( See code for details )
  37. NUM1 / DIV1 / NUM2 / DIV2 : Frequencies programming ( See code for details )
  38. FM1CA : Calibration Start Bit
  39. FM1SS : Calibration Single Step bit
  40. L1LK : LO1 Lock Detect
  41. TAD1 : Tune Line ADC ( ? )
  42. L2LK : LO2 Lock Detect
  43. TAD2 : Tune Line ADC ( ? )
  44. FMF : Estimated first IF Center frequency Offset ( ? )
  45. FM1CAL : Calibration done bit
  46. TEMP : On chip temperature sensor
  47. FMCG : Mixer 1 Cap Gain ( ? )
  48. GP01 / GP02 : Programmable digital outputs. Unconnected pins ?
  49. V1CSE : LO1 VCO Automatic Capacitor Select Enable ( ? )
  50. V1CS : LO1 Capacitor Selection Value ( ? )
  51. LOTO : LO Timeout ( ? )
  52. VGAG : Tuner Output gain
  53. */
  54. #define I2C_ADDRESS 0x60
  55. #define REG_PART_REV 0
  56. #define REG_LO1C1 1
  57. #define REG_LO1C2 2
  58. #define REG_LO2C1 3
  59. #define REG_LO2C2 4
  60. #define REG_LO2C3 5
  61. #define REG_LO_STATUS 6
  62. #define REG_FM_FREQ 7
  63. #define REG_MISC_STAT 8
  64. #define REG_MISC_CTRL 9
  65. #define REG_RESERVED_A 0x0A
  66. #define REG_VGAG 0x0B
  67. #define REG_LO1B1 0x0C
  68. #define REG_LO1B2 0x0D
  69. #define REG_LOTO 0x11
  70. #define PART_REV 0x63 // The current driver works only with PART=6 and REV=3 chips
  71. struct mt2060_priv {
  72. struct mt2060_config *cfg;
  73. struct i2c_adapter *i2c;
  74. struct i2c_client *client;
  75. struct mt2060_config config;
  76. u8 i2c_max_regs;
  77. u32 frequency;
  78. u16 if1_freq;
  79. u8 fmfreq;
  80. /*
  81. * Use REG_MISC_CTRL register for sleep. That drops sleep power usage
  82. * about 0.9W (huge!). Register bit meanings are unknown, so let it be
  83. * disabled by default to avoid possible regression. Convert driver to
  84. * i2c model in order to enable it.
  85. */
  86. bool sleep;
  87. };
  88. #endif