msi001.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Mirics MSi001 silicon tuner driver
  4. *
  5. * Copyright (C) 2013 Antti Palosaari <crope@iki.fi>
  6. * Copyright (C) 2014 Antti Palosaari <crope@iki.fi>
  7. */
  8. #include <linux/module.h>
  9. #include <linux/gcd.h>
  10. #include <media/v4l2-device.h>
  11. #include <media/v4l2-ctrls.h>
  12. static const struct v4l2_frequency_band bands[] = {
  13. {
  14. .type = V4L2_TUNER_RF,
  15. .index = 0,
  16. .capability = V4L2_TUNER_CAP_1HZ | V4L2_TUNER_CAP_FREQ_BANDS,
  17. .rangelow = 49000000,
  18. .rangehigh = 263000000,
  19. }, {
  20. .type = V4L2_TUNER_RF,
  21. .index = 1,
  22. .capability = V4L2_TUNER_CAP_1HZ | V4L2_TUNER_CAP_FREQ_BANDS,
  23. .rangelow = 390000000,
  24. .rangehigh = 960000000,
  25. },
  26. };
  27. struct msi001_dev {
  28. struct spi_device *spi;
  29. struct v4l2_subdev sd;
  30. /* Controls */
  31. struct v4l2_ctrl_handler hdl;
  32. struct v4l2_ctrl *bandwidth_auto;
  33. struct v4l2_ctrl *bandwidth;
  34. struct v4l2_ctrl *lna_gain;
  35. struct v4l2_ctrl *mixer_gain;
  36. struct v4l2_ctrl *if_gain;
  37. unsigned int f_tuner;
  38. };
  39. static inline struct msi001_dev *sd_to_msi001_dev(struct v4l2_subdev *sd)
  40. {
  41. return container_of(sd, struct msi001_dev, sd);
  42. }
  43. static int msi001_wreg(struct msi001_dev *dev, u32 data)
  44. {
  45. /* Register format: 4 bits addr + 20 bits value */
  46. return spi_write(dev->spi, &data, 3);
  47. };
  48. static int msi001_set_gain(struct msi001_dev *dev, int lna_gain, int mixer_gain,
  49. int if_gain)
  50. {
  51. struct spi_device *spi = dev->spi;
  52. int ret;
  53. u32 reg;
  54. dev_dbg(&spi->dev, "lna=%d mixer=%d if=%d\n",
  55. lna_gain, mixer_gain, if_gain);
  56. reg = 1 << 0;
  57. reg |= (59 - if_gain) << 4;
  58. reg |= 0 << 10;
  59. reg |= (1 - mixer_gain) << 12;
  60. reg |= (1 - lna_gain) << 13;
  61. reg |= 4 << 14;
  62. reg |= 0 << 17;
  63. ret = msi001_wreg(dev, reg);
  64. if (ret)
  65. goto err;
  66. return 0;
  67. err:
  68. dev_dbg(&spi->dev, "failed %d\n", ret);
  69. return ret;
  70. };
  71. static int msi001_set_tuner(struct msi001_dev *dev)
  72. {
  73. struct spi_device *spi = dev->spi;
  74. int ret, i;
  75. unsigned int uitmp, div_n, k, k_thresh, k_frac, div_lo, f_if1;
  76. u32 reg;
  77. u64 f_vco;
  78. u8 mode, filter_mode;
  79. static const struct {
  80. u32 rf;
  81. u8 mode;
  82. u8 div_lo;
  83. } band_lut[] = {
  84. { 50000000, 0xe1, 16}, /* AM_MODE2, antenna 2 */
  85. {108000000, 0x42, 32}, /* VHF_MODE */
  86. {330000000, 0x44, 16}, /* B3_MODE */
  87. {960000000, 0x48, 4}, /* B45_MODE */
  88. { ~0U, 0x50, 2}, /* BL_MODE */
  89. };
  90. static const struct {
  91. u32 freq;
  92. u8 filter_mode;
  93. } if_freq_lut[] = {
  94. { 0, 0x03}, /* Zero IF */
  95. { 450000, 0x02}, /* 450 kHz IF */
  96. {1620000, 0x01}, /* 1.62 MHz IF */
  97. {2048000, 0x00}, /* 2.048 MHz IF */
  98. };
  99. static const struct {
  100. u32 freq;
  101. u8 val;
  102. } bandwidth_lut[] = {
  103. { 200000, 0x00}, /* 200 kHz */
  104. { 300000, 0x01}, /* 300 kHz */
  105. { 600000, 0x02}, /* 600 kHz */
  106. {1536000, 0x03}, /* 1.536 MHz */
  107. {5000000, 0x04}, /* 5 MHz */
  108. {6000000, 0x05}, /* 6 MHz */
  109. {7000000, 0x06}, /* 7 MHz */
  110. {8000000, 0x07}, /* 8 MHz */
  111. };
  112. unsigned int f_rf = dev->f_tuner;
  113. /*
  114. * bandwidth (Hz)
  115. * 200000, 300000, 600000, 1536000, 5000000, 6000000, 7000000, 8000000
  116. */
  117. unsigned int bandwidth;
  118. /*
  119. * intermediate frequency (Hz)
  120. * 0, 450000, 1620000, 2048000
  121. */
  122. unsigned int f_if = 0;
  123. #define F_REF 24000000
  124. #define DIV_PRE_N 4
  125. #define F_VCO_STEP div_lo
  126. dev_dbg(&spi->dev, "f_rf=%d f_if=%d\n", f_rf, f_if);
  127. for (i = 0; i < ARRAY_SIZE(band_lut); i++) {
  128. if (f_rf <= band_lut[i].rf) {
  129. mode = band_lut[i].mode;
  130. div_lo = band_lut[i].div_lo;
  131. break;
  132. }
  133. }
  134. if (i == ARRAY_SIZE(band_lut)) {
  135. ret = -EINVAL;
  136. goto err;
  137. }
  138. /* AM_MODE is upconverted */
  139. if ((mode >> 0) & 0x1)
  140. f_if1 = 5 * F_REF;
  141. else
  142. f_if1 = 0;
  143. for (i = 0; i < ARRAY_SIZE(if_freq_lut); i++) {
  144. if (f_if == if_freq_lut[i].freq) {
  145. filter_mode = if_freq_lut[i].filter_mode;
  146. break;
  147. }
  148. }
  149. if (i == ARRAY_SIZE(if_freq_lut)) {
  150. ret = -EINVAL;
  151. goto err;
  152. }
  153. /* filters */
  154. bandwidth = dev->bandwidth->val;
  155. bandwidth = clamp(bandwidth, 200000U, 8000000U);
  156. for (i = 0; i < ARRAY_SIZE(bandwidth_lut); i++) {
  157. if (bandwidth <= bandwidth_lut[i].freq) {
  158. bandwidth = bandwidth_lut[i].val;
  159. break;
  160. }
  161. }
  162. if (i == ARRAY_SIZE(bandwidth_lut)) {
  163. ret = -EINVAL;
  164. goto err;
  165. }
  166. dev->bandwidth->val = bandwidth_lut[i].freq;
  167. dev_dbg(&spi->dev, "bandwidth selected=%d\n", bandwidth_lut[i].freq);
  168. /*
  169. * Fractional-N synthesizer
  170. *
  171. * +---------------------------------------+
  172. * v |
  173. * Fref +----+ +-------+ +----+ +------+ +---+
  174. * ------> | PD | --> | VCO | ------> | /4 | --> | /N.F | <-- | K |
  175. * +----+ +-------+ +----+ +------+ +---+
  176. * |
  177. * |
  178. * v
  179. * +-------+ Fout
  180. * | /Rout | ------>
  181. * +-------+
  182. */
  183. /* Calculate PLL integer and fractional control word. */
  184. f_vco = (u64) (f_rf + f_if + f_if1) * div_lo;
  185. div_n = div_u64_rem(f_vco, DIV_PRE_N * F_REF, &k);
  186. k_thresh = (DIV_PRE_N * F_REF) / F_VCO_STEP;
  187. k_frac = div_u64((u64) k * k_thresh, (DIV_PRE_N * F_REF));
  188. /* Find out greatest common divisor and divide to smaller. */
  189. uitmp = gcd(k_thresh, k_frac);
  190. k_thresh /= uitmp;
  191. k_frac /= uitmp;
  192. /* Force divide to reg max. Resolution will be reduced. */
  193. uitmp = DIV_ROUND_UP(k_thresh, 4095);
  194. k_thresh = DIV_ROUND_CLOSEST(k_thresh, uitmp);
  195. k_frac = DIV_ROUND_CLOSEST(k_frac, uitmp);
  196. /* Calculate real RF set. */
  197. uitmp = (unsigned int) F_REF * DIV_PRE_N * div_n;
  198. uitmp += (unsigned int) F_REF * DIV_PRE_N * k_frac / k_thresh;
  199. uitmp /= div_lo;
  200. dev_dbg(&spi->dev,
  201. "f_rf=%u:%u f_vco=%llu div_n=%u k_thresh=%u k_frac=%u div_lo=%u\n",
  202. f_rf, uitmp, f_vco, div_n, k_thresh, k_frac, div_lo);
  203. ret = msi001_wreg(dev, 0x00000e);
  204. if (ret)
  205. goto err;
  206. ret = msi001_wreg(dev, 0x000003);
  207. if (ret)
  208. goto err;
  209. reg = 0 << 0;
  210. reg |= mode << 4;
  211. reg |= filter_mode << 12;
  212. reg |= bandwidth << 14;
  213. reg |= 0x02 << 17;
  214. reg |= 0x00 << 20;
  215. ret = msi001_wreg(dev, reg);
  216. if (ret)
  217. goto err;
  218. reg = 5 << 0;
  219. reg |= k_thresh << 4;
  220. reg |= 1 << 19;
  221. reg |= 1 << 21;
  222. ret = msi001_wreg(dev, reg);
  223. if (ret)
  224. goto err;
  225. reg = 2 << 0;
  226. reg |= k_frac << 4;
  227. reg |= div_n << 16;
  228. ret = msi001_wreg(dev, reg);
  229. if (ret)
  230. goto err;
  231. ret = msi001_set_gain(dev, dev->lna_gain->cur.val,
  232. dev->mixer_gain->cur.val, dev->if_gain->cur.val);
  233. if (ret)
  234. goto err;
  235. reg = 6 << 0;
  236. reg |= 63 << 4;
  237. reg |= 4095 << 10;
  238. ret = msi001_wreg(dev, reg);
  239. if (ret)
  240. goto err;
  241. return 0;
  242. err:
  243. dev_dbg(&spi->dev, "failed %d\n", ret);
  244. return ret;
  245. }
  246. static int msi001_standby(struct v4l2_subdev *sd)
  247. {
  248. struct msi001_dev *dev = sd_to_msi001_dev(sd);
  249. return msi001_wreg(dev, 0x000000);
  250. }
  251. static int msi001_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *v)
  252. {
  253. struct msi001_dev *dev = sd_to_msi001_dev(sd);
  254. struct spi_device *spi = dev->spi;
  255. dev_dbg(&spi->dev, "index=%d\n", v->index);
  256. strscpy(v->name, "Mirics MSi001", sizeof(v->name));
  257. v->type = V4L2_TUNER_RF;
  258. v->capability = V4L2_TUNER_CAP_1HZ | V4L2_TUNER_CAP_FREQ_BANDS;
  259. v->rangelow = 49000000;
  260. v->rangehigh = 960000000;
  261. return 0;
  262. }
  263. static int msi001_s_tuner(struct v4l2_subdev *sd, const struct v4l2_tuner *v)
  264. {
  265. struct msi001_dev *dev = sd_to_msi001_dev(sd);
  266. struct spi_device *spi = dev->spi;
  267. dev_dbg(&spi->dev, "index=%d\n", v->index);
  268. return 0;
  269. }
  270. static int msi001_g_frequency(struct v4l2_subdev *sd, struct v4l2_frequency *f)
  271. {
  272. struct msi001_dev *dev = sd_to_msi001_dev(sd);
  273. struct spi_device *spi = dev->spi;
  274. dev_dbg(&spi->dev, "tuner=%d\n", f->tuner);
  275. f->frequency = dev->f_tuner;
  276. return 0;
  277. }
  278. static int msi001_s_frequency(struct v4l2_subdev *sd,
  279. const struct v4l2_frequency *f)
  280. {
  281. struct msi001_dev *dev = sd_to_msi001_dev(sd);
  282. struct spi_device *spi = dev->spi;
  283. unsigned int band;
  284. dev_dbg(&spi->dev, "tuner=%d type=%d frequency=%u\n",
  285. f->tuner, f->type, f->frequency);
  286. if (f->frequency < ((bands[0].rangehigh + bands[1].rangelow) / 2))
  287. band = 0;
  288. else
  289. band = 1;
  290. dev->f_tuner = clamp_t(unsigned int, f->frequency,
  291. bands[band].rangelow, bands[band].rangehigh);
  292. return msi001_set_tuner(dev);
  293. }
  294. static int msi001_enum_freq_bands(struct v4l2_subdev *sd,
  295. struct v4l2_frequency_band *band)
  296. {
  297. struct msi001_dev *dev = sd_to_msi001_dev(sd);
  298. struct spi_device *spi = dev->spi;
  299. dev_dbg(&spi->dev, "tuner=%d type=%d index=%d\n",
  300. band->tuner, band->type, band->index);
  301. if (band->index >= ARRAY_SIZE(bands))
  302. return -EINVAL;
  303. band->capability = bands[band->index].capability;
  304. band->rangelow = bands[band->index].rangelow;
  305. band->rangehigh = bands[band->index].rangehigh;
  306. return 0;
  307. }
  308. static const struct v4l2_subdev_tuner_ops msi001_tuner_ops = {
  309. .standby = msi001_standby,
  310. .g_tuner = msi001_g_tuner,
  311. .s_tuner = msi001_s_tuner,
  312. .g_frequency = msi001_g_frequency,
  313. .s_frequency = msi001_s_frequency,
  314. .enum_freq_bands = msi001_enum_freq_bands,
  315. };
  316. static const struct v4l2_subdev_ops msi001_ops = {
  317. .tuner = &msi001_tuner_ops,
  318. };
  319. static int msi001_s_ctrl(struct v4l2_ctrl *ctrl)
  320. {
  321. struct msi001_dev *dev = container_of(ctrl->handler, struct msi001_dev, hdl);
  322. struct spi_device *spi = dev->spi;
  323. int ret;
  324. dev_dbg(&spi->dev, "id=%d name=%s val=%d min=%lld max=%lld step=%lld\n",
  325. ctrl->id, ctrl->name, ctrl->val, ctrl->minimum, ctrl->maximum,
  326. ctrl->step);
  327. switch (ctrl->id) {
  328. case V4L2_CID_RF_TUNER_BANDWIDTH_AUTO:
  329. case V4L2_CID_RF_TUNER_BANDWIDTH:
  330. ret = msi001_set_tuner(dev);
  331. break;
  332. case V4L2_CID_RF_TUNER_LNA_GAIN:
  333. ret = msi001_set_gain(dev, dev->lna_gain->val,
  334. dev->mixer_gain->cur.val,
  335. dev->if_gain->cur.val);
  336. break;
  337. case V4L2_CID_RF_TUNER_MIXER_GAIN:
  338. ret = msi001_set_gain(dev, dev->lna_gain->cur.val,
  339. dev->mixer_gain->val,
  340. dev->if_gain->cur.val);
  341. break;
  342. case V4L2_CID_RF_TUNER_IF_GAIN:
  343. ret = msi001_set_gain(dev, dev->lna_gain->cur.val,
  344. dev->mixer_gain->cur.val,
  345. dev->if_gain->val);
  346. break;
  347. default:
  348. dev_dbg(&spi->dev, "unknown control %d\n", ctrl->id);
  349. ret = -EINVAL;
  350. }
  351. return ret;
  352. }
  353. static const struct v4l2_ctrl_ops msi001_ctrl_ops = {
  354. .s_ctrl = msi001_s_ctrl,
  355. };
  356. static int msi001_probe(struct spi_device *spi)
  357. {
  358. struct msi001_dev *dev;
  359. int ret;
  360. dev_dbg(&spi->dev, "\n");
  361. dev = kzalloc(sizeof(*dev), GFP_KERNEL);
  362. if (!dev) {
  363. ret = -ENOMEM;
  364. goto err;
  365. }
  366. dev->spi = spi;
  367. dev->f_tuner = bands[0].rangelow;
  368. v4l2_spi_subdev_init(&dev->sd, spi, &msi001_ops);
  369. /* Register controls */
  370. v4l2_ctrl_handler_init(&dev->hdl, 5);
  371. dev->bandwidth_auto = v4l2_ctrl_new_std(&dev->hdl, &msi001_ctrl_ops,
  372. V4L2_CID_RF_TUNER_BANDWIDTH_AUTO, 0, 1, 1, 1);
  373. dev->bandwidth = v4l2_ctrl_new_std(&dev->hdl, &msi001_ctrl_ops,
  374. V4L2_CID_RF_TUNER_BANDWIDTH, 200000, 8000000, 1, 200000);
  375. if (dev->hdl.error) {
  376. ret = dev->hdl.error;
  377. dev_err(&spi->dev, "Could not initialize controls\n");
  378. /* control init failed, free handler */
  379. goto err_ctrl_handler_free;
  380. }
  381. v4l2_ctrl_auto_cluster(2, &dev->bandwidth_auto, 0, false);
  382. dev->lna_gain = v4l2_ctrl_new_std(&dev->hdl, &msi001_ctrl_ops,
  383. V4L2_CID_RF_TUNER_LNA_GAIN, 0, 1, 1, 1);
  384. dev->mixer_gain = v4l2_ctrl_new_std(&dev->hdl, &msi001_ctrl_ops,
  385. V4L2_CID_RF_TUNER_MIXER_GAIN, 0, 1, 1, 1);
  386. dev->if_gain = v4l2_ctrl_new_std(&dev->hdl, &msi001_ctrl_ops,
  387. V4L2_CID_RF_TUNER_IF_GAIN, 0, 59, 1, 0);
  388. if (dev->hdl.error) {
  389. ret = dev->hdl.error;
  390. dev_err(&spi->dev, "Could not initialize controls\n");
  391. /* control init failed, free handler */
  392. goto err_ctrl_handler_free;
  393. }
  394. dev->sd.ctrl_handler = &dev->hdl;
  395. return 0;
  396. err_ctrl_handler_free:
  397. v4l2_ctrl_handler_free(&dev->hdl);
  398. kfree(dev);
  399. err:
  400. return ret;
  401. }
  402. static int msi001_remove(struct spi_device *spi)
  403. {
  404. struct v4l2_subdev *sd = spi_get_drvdata(spi);
  405. struct msi001_dev *dev = sd_to_msi001_dev(sd);
  406. dev_dbg(&spi->dev, "\n");
  407. /*
  408. * Registered by v4l2_spi_new_subdev() from master driver, but we must
  409. * unregister it from here. Weird.
  410. */
  411. v4l2_device_unregister_subdev(&dev->sd);
  412. v4l2_ctrl_handler_free(&dev->hdl);
  413. kfree(dev);
  414. return 0;
  415. }
  416. static const struct spi_device_id msi001_id_table[] = {
  417. {"msi001", 0},
  418. {}
  419. };
  420. MODULE_DEVICE_TABLE(spi, msi001_id_table);
  421. static struct spi_driver msi001_driver = {
  422. .driver = {
  423. .name = "msi001",
  424. .suppress_bind_attrs = true,
  425. },
  426. .probe = msi001_probe,
  427. .remove = msi001_remove,
  428. .id_table = msi001_id_table,
  429. };
  430. module_spi_driver(msi001_driver);
  431. MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
  432. MODULE_DESCRIPTION("Mirics MSi001");
  433. MODULE_LICENSE("GPL");