sunxi-cir.c 9.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Driver for Allwinner sunXi IR controller
  4. *
  5. * Copyright (C) 2014 Alexsey Shestacov <wingrime@linux-sunxi.org>
  6. * Copyright (C) 2014 Alexander Bersenev <bay@hackerdom.ru>
  7. *
  8. * Based on sun5i-ir.c:
  9. * Copyright (C) 2007-2012 Daniel Wang
  10. * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
  11. */
  12. #include <linux/clk.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/module.h>
  15. #include <linux/of_platform.h>
  16. #include <linux/reset.h>
  17. #include <media/rc-core.h>
  18. #define SUNXI_IR_DEV "sunxi-ir"
  19. /* Registers */
  20. /* IR Control */
  21. #define SUNXI_IR_CTL_REG 0x00
  22. /* Global Enable */
  23. #define REG_CTL_GEN BIT(0)
  24. /* RX block enable */
  25. #define REG_CTL_RXEN BIT(1)
  26. /* CIR mode */
  27. #define REG_CTL_MD (BIT(4) | BIT(5))
  28. /* Rx Config */
  29. #define SUNXI_IR_RXCTL_REG 0x10
  30. /* Pulse Polarity Invert flag */
  31. #define REG_RXCTL_RPPI BIT(2)
  32. /* Rx Data */
  33. #define SUNXI_IR_RXFIFO_REG 0x20
  34. /* Rx Interrupt Enable */
  35. #define SUNXI_IR_RXINT_REG 0x2C
  36. /* Rx FIFO Overflow Interrupt Enable */
  37. #define REG_RXINT_ROI_EN BIT(0)
  38. /* Rx Packet End Interrupt Enable */
  39. #define REG_RXINT_RPEI_EN BIT(1)
  40. /* Rx FIFO Data Available Interrupt Enable */
  41. #define REG_RXINT_RAI_EN BIT(4)
  42. /* Rx FIFO available byte level */
  43. #define REG_RXINT_RAL(val) ((val) << 8)
  44. /* Rx Interrupt Status */
  45. #define SUNXI_IR_RXSTA_REG 0x30
  46. /* Rx FIFO Overflow */
  47. #define REG_RXSTA_ROI REG_RXINT_ROI_EN
  48. /* Rx Packet End */
  49. #define REG_RXSTA_RPE REG_RXINT_RPEI_EN
  50. /* Rx FIFO Data Available */
  51. #define REG_RXSTA_RA REG_RXINT_RAI_EN
  52. /* RX FIFO Get Available Counter */
  53. #define REG_RXSTA_GET_AC(val) (((val) >> 8) & (ir->fifo_size * 2 - 1))
  54. /* Clear all interrupt status value */
  55. #define REG_RXSTA_CLEARALL 0xff
  56. /* IR Sample Config */
  57. #define SUNXI_IR_CIR_REG 0x34
  58. /* CIR_REG register noise threshold */
  59. #define REG_CIR_NTHR(val) (((val) << 2) & (GENMASK(7, 2)))
  60. /* CIR_REG register idle threshold */
  61. #define REG_CIR_ITHR(val) (((val) << 8) & (GENMASK(15, 8)))
  62. /* Required frequency for IR0 or IR1 clock in CIR mode (default) */
  63. #define SUNXI_IR_BASE_CLK 8000000
  64. /* Noise threshold in samples */
  65. #define SUNXI_IR_RXNOISE 1
  66. /* Idle Threshold in samples */
  67. #define SUNXI_IR_RXIDLE 20
  68. /* Time after which device stops sending data in ms */
  69. #define SUNXI_IR_TIMEOUT 120
  70. /**
  71. * struct sunxi_ir_quirks - Differences between SoC variants.
  72. *
  73. * @has_reset: SoC needs reset deasserted.
  74. * @fifo_size: size of the fifo.
  75. */
  76. struct sunxi_ir_quirks {
  77. bool has_reset;
  78. int fifo_size;
  79. };
  80. struct sunxi_ir {
  81. spinlock_t ir_lock;
  82. struct rc_dev *rc;
  83. void __iomem *base;
  84. int irq;
  85. int fifo_size;
  86. struct clk *clk;
  87. struct clk *apb_clk;
  88. struct reset_control *rst;
  89. const char *map_name;
  90. };
  91. static irqreturn_t sunxi_ir_irq(int irqno, void *dev_id)
  92. {
  93. unsigned long status;
  94. unsigned char dt;
  95. unsigned int cnt, rc;
  96. struct sunxi_ir *ir = dev_id;
  97. struct ir_raw_event rawir = {};
  98. spin_lock(&ir->ir_lock);
  99. status = readl(ir->base + SUNXI_IR_RXSTA_REG);
  100. /* clean all pending statuses */
  101. writel(status | REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG);
  102. if (status & (REG_RXSTA_RA | REG_RXSTA_RPE)) {
  103. /* How many messages in fifo */
  104. rc = REG_RXSTA_GET_AC(status);
  105. /* Sanity check */
  106. rc = rc > ir->fifo_size ? ir->fifo_size : rc;
  107. /* If we have data */
  108. for (cnt = 0; cnt < rc; cnt++) {
  109. /* for each bit in fifo */
  110. dt = readb(ir->base + SUNXI_IR_RXFIFO_REG);
  111. rawir.pulse = (dt & 0x80) != 0;
  112. rawir.duration = ((dt & 0x7f) + 1) *
  113. ir->rc->rx_resolution;
  114. ir_raw_event_store_with_filter(ir->rc, &rawir);
  115. }
  116. }
  117. if (status & REG_RXSTA_ROI) {
  118. ir_raw_event_reset(ir->rc);
  119. } else if (status & REG_RXSTA_RPE) {
  120. ir_raw_event_set_idle(ir->rc, true);
  121. ir_raw_event_handle(ir->rc);
  122. } else {
  123. ir_raw_event_handle(ir->rc);
  124. }
  125. spin_unlock(&ir->ir_lock);
  126. return IRQ_HANDLED;
  127. }
  128. static int sunxi_ir_probe(struct platform_device *pdev)
  129. {
  130. int ret = 0;
  131. unsigned long tmp = 0;
  132. struct device *dev = &pdev->dev;
  133. struct device_node *dn = dev->of_node;
  134. const struct sunxi_ir_quirks *quirks;
  135. struct resource *res;
  136. struct sunxi_ir *ir;
  137. u32 b_clk_freq = SUNXI_IR_BASE_CLK;
  138. ir = devm_kzalloc(dev, sizeof(struct sunxi_ir), GFP_KERNEL);
  139. if (!ir)
  140. return -ENOMEM;
  141. quirks = of_device_get_match_data(&pdev->dev);
  142. if (!quirks) {
  143. dev_err(&pdev->dev, "Failed to determine the quirks to use\n");
  144. return -ENODEV;
  145. }
  146. spin_lock_init(&ir->ir_lock);
  147. ir->fifo_size = quirks->fifo_size;
  148. /* Clock */
  149. ir->apb_clk = devm_clk_get(dev, "apb");
  150. if (IS_ERR(ir->apb_clk)) {
  151. dev_err(dev, "failed to get a apb clock.\n");
  152. return PTR_ERR(ir->apb_clk);
  153. }
  154. ir->clk = devm_clk_get(dev, "ir");
  155. if (IS_ERR(ir->clk)) {
  156. dev_err(dev, "failed to get a ir clock.\n");
  157. return PTR_ERR(ir->clk);
  158. }
  159. /* Base clock frequency (optional) */
  160. of_property_read_u32(dn, "clock-frequency", &b_clk_freq);
  161. /* Reset */
  162. if (quirks->has_reset) {
  163. ir->rst = devm_reset_control_get_exclusive(dev, NULL);
  164. if (IS_ERR(ir->rst))
  165. return PTR_ERR(ir->rst);
  166. ret = reset_control_deassert(ir->rst);
  167. if (ret)
  168. return ret;
  169. }
  170. ret = clk_set_rate(ir->clk, b_clk_freq);
  171. if (ret) {
  172. dev_err(dev, "set ir base clock failed!\n");
  173. goto exit_reset_assert;
  174. }
  175. dev_dbg(dev, "set base clock frequency to %d Hz.\n", b_clk_freq);
  176. if (clk_prepare_enable(ir->apb_clk)) {
  177. dev_err(dev, "try to enable apb_ir_clk failed\n");
  178. ret = -EINVAL;
  179. goto exit_reset_assert;
  180. }
  181. if (clk_prepare_enable(ir->clk)) {
  182. dev_err(dev, "try to enable ir_clk failed\n");
  183. ret = -EINVAL;
  184. goto exit_clkdisable_apb_clk;
  185. }
  186. /* IO */
  187. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  188. ir->base = devm_ioremap_resource(dev, res);
  189. if (IS_ERR(ir->base)) {
  190. ret = PTR_ERR(ir->base);
  191. goto exit_clkdisable_clk;
  192. }
  193. ir->rc = rc_allocate_device(RC_DRIVER_IR_RAW);
  194. if (!ir->rc) {
  195. dev_err(dev, "failed to allocate device\n");
  196. ret = -ENOMEM;
  197. goto exit_clkdisable_clk;
  198. }
  199. ir->rc->priv = ir;
  200. ir->rc->device_name = SUNXI_IR_DEV;
  201. ir->rc->input_phys = "sunxi-ir/input0";
  202. ir->rc->input_id.bustype = BUS_HOST;
  203. ir->rc->input_id.vendor = 0x0001;
  204. ir->rc->input_id.product = 0x0001;
  205. ir->rc->input_id.version = 0x0100;
  206. ir->map_name = of_get_property(dn, "linux,rc-map-name", NULL);
  207. ir->rc->map_name = ir->map_name ?: RC_MAP_EMPTY;
  208. ir->rc->dev.parent = dev;
  209. ir->rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
  210. /* Frequency after IR internal divider with sample period in ns */
  211. ir->rc->rx_resolution = (USEC_PER_SEC / (b_clk_freq / 64));
  212. ir->rc->timeout = MS_TO_US(SUNXI_IR_TIMEOUT);
  213. ir->rc->driver_name = SUNXI_IR_DEV;
  214. ret = rc_register_device(ir->rc);
  215. if (ret) {
  216. dev_err(dev, "failed to register rc device\n");
  217. goto exit_free_dev;
  218. }
  219. platform_set_drvdata(pdev, ir);
  220. /* IRQ */
  221. ir->irq = platform_get_irq(pdev, 0);
  222. if (ir->irq < 0) {
  223. ret = ir->irq;
  224. goto exit_free_dev;
  225. }
  226. ret = devm_request_irq(dev, ir->irq, sunxi_ir_irq, 0, SUNXI_IR_DEV, ir);
  227. if (ret) {
  228. dev_err(dev, "failed request irq\n");
  229. goto exit_free_dev;
  230. }
  231. /* Enable CIR Mode */
  232. writel(REG_CTL_MD, ir->base+SUNXI_IR_CTL_REG);
  233. /* Set noise threshold and idle threshold */
  234. writel(REG_CIR_NTHR(SUNXI_IR_RXNOISE)|REG_CIR_ITHR(SUNXI_IR_RXIDLE),
  235. ir->base + SUNXI_IR_CIR_REG);
  236. /* Invert Input Signal */
  237. writel(REG_RXCTL_RPPI, ir->base + SUNXI_IR_RXCTL_REG);
  238. /* Clear All Rx Interrupt Status */
  239. writel(REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG);
  240. /*
  241. * Enable IRQ on overflow, packet end, FIFO available with trigger
  242. * level
  243. */
  244. writel(REG_RXINT_ROI_EN | REG_RXINT_RPEI_EN |
  245. REG_RXINT_RAI_EN | REG_RXINT_RAL(ir->fifo_size / 2 - 1),
  246. ir->base + SUNXI_IR_RXINT_REG);
  247. /* Enable IR Module */
  248. tmp = readl(ir->base + SUNXI_IR_CTL_REG);
  249. writel(tmp | REG_CTL_GEN | REG_CTL_RXEN, ir->base + SUNXI_IR_CTL_REG);
  250. dev_info(dev, "initialized sunXi IR driver\n");
  251. return 0;
  252. exit_free_dev:
  253. rc_free_device(ir->rc);
  254. exit_clkdisable_clk:
  255. clk_disable_unprepare(ir->clk);
  256. exit_clkdisable_apb_clk:
  257. clk_disable_unprepare(ir->apb_clk);
  258. exit_reset_assert:
  259. reset_control_assert(ir->rst);
  260. return ret;
  261. }
  262. static int sunxi_ir_remove(struct platform_device *pdev)
  263. {
  264. unsigned long flags;
  265. struct sunxi_ir *ir = platform_get_drvdata(pdev);
  266. clk_disable_unprepare(ir->clk);
  267. clk_disable_unprepare(ir->apb_clk);
  268. reset_control_assert(ir->rst);
  269. spin_lock_irqsave(&ir->ir_lock, flags);
  270. /* disable IR IRQ */
  271. writel(0, ir->base + SUNXI_IR_RXINT_REG);
  272. /* clear All Rx Interrupt Status */
  273. writel(REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG);
  274. /* disable IR */
  275. writel(0, ir->base + SUNXI_IR_CTL_REG);
  276. spin_unlock_irqrestore(&ir->ir_lock, flags);
  277. rc_unregister_device(ir->rc);
  278. return 0;
  279. }
  280. static const struct sunxi_ir_quirks sun4i_a10_ir_quirks = {
  281. .has_reset = false,
  282. .fifo_size = 16,
  283. };
  284. static const struct sunxi_ir_quirks sun5i_a13_ir_quirks = {
  285. .has_reset = false,
  286. .fifo_size = 64,
  287. };
  288. static const struct sunxi_ir_quirks sun6i_a31_ir_quirks = {
  289. .has_reset = true,
  290. .fifo_size = 64,
  291. };
  292. static const struct of_device_id sunxi_ir_match[] = {
  293. {
  294. .compatible = "allwinner,sun4i-a10-ir",
  295. .data = &sun4i_a10_ir_quirks,
  296. },
  297. {
  298. .compatible = "allwinner,sun5i-a13-ir",
  299. .data = &sun5i_a13_ir_quirks,
  300. },
  301. {
  302. .compatible = "allwinner,sun6i-a31-ir",
  303. .data = &sun6i_a31_ir_quirks,
  304. },
  305. {}
  306. };
  307. MODULE_DEVICE_TABLE(of, sunxi_ir_match);
  308. static struct platform_driver sunxi_ir_driver = {
  309. .probe = sunxi_ir_probe,
  310. .remove = sunxi_ir_remove,
  311. .driver = {
  312. .name = SUNXI_IR_DEV,
  313. .of_match_table = sunxi_ir_match,
  314. },
  315. };
  316. module_platform_driver(sunxi_ir_driver);
  317. MODULE_DESCRIPTION("Allwinner sunXi IR controller driver");
  318. MODULE_AUTHOR("Alexsey Shestacov <wingrime@linux-sunxi.org>");
  319. MODULE_LICENSE("GPL");