nuvoton-cir.h 9.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * Driver for Nuvoton Technology Corporation w83667hg/w83677hg-i CIR
  4. *
  5. * Copyright (C) 2010 Jarod Wilson <jarod@redhat.com>
  6. * Copyright (C) 2009 Nuvoton PS Team
  7. *
  8. * Special thanks to Nuvoton for providing hardware, spec sheets and
  9. * sample code upon which portions of this driver are based. Indirect
  10. * thanks also to Maxim Levitsky, whose ene_ir driver this driver is
  11. * modeled after.
  12. */
  13. #include <linux/spinlock.h>
  14. #include <linux/ioctl.h>
  15. /* platform driver name to register */
  16. #define NVT_DRIVER_NAME "nuvoton-cir"
  17. /* debugging module parameter */
  18. static int debug;
  19. #define nvt_dbg(text, ...) \
  20. if (debug) \
  21. printk(KERN_DEBUG \
  22. KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__)
  23. #define nvt_dbg_verbose(text, ...) \
  24. if (debug > 1) \
  25. printk(KERN_DEBUG \
  26. KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__)
  27. #define nvt_dbg_wake(text, ...) \
  28. if (debug > 2) \
  29. printk(KERN_DEBUG \
  30. KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__)
  31. #define RX_BUF_LEN 32
  32. #define SIO_ID_MASK 0xfff0
  33. enum nvt_chip_ver {
  34. NVT_UNKNOWN = 0,
  35. NVT_W83667HG = 0xa510,
  36. NVT_6775F = 0xb470,
  37. NVT_6776F = 0xc330,
  38. NVT_6779D = 0xc560,
  39. NVT_INVALID = 0xffff,
  40. };
  41. struct nvt_chip {
  42. const char *name;
  43. enum nvt_chip_ver chip_ver;
  44. };
  45. struct nvt_dev {
  46. struct rc_dev *rdev;
  47. spinlock_t lock;
  48. /* for rx */
  49. u8 buf[RX_BUF_LEN];
  50. unsigned int pkts;
  51. /* EFER Config register index/data pair */
  52. u32 cr_efir;
  53. u32 cr_efdr;
  54. /* hardware I/O settings */
  55. unsigned long cir_addr;
  56. unsigned long cir_wake_addr;
  57. int cir_irq;
  58. enum nvt_chip_ver chip_ver;
  59. /* hardware id */
  60. u8 chip_major;
  61. u8 chip_minor;
  62. /* carrier period = 1 / frequency */
  63. u32 carrier;
  64. };
  65. /* buffer packet constants */
  66. #define BUF_PULSE_BIT 0x80
  67. #define BUF_LEN_MASK 0x7f
  68. #define BUF_REPEAT_BYTE 0x70
  69. #define BUF_REPEAT_MASK 0xf0
  70. /* CIR settings */
  71. /* total length of CIR and CIR WAKE */
  72. #define CIR_IOREG_LENGTH 0x0f
  73. /* RX limit length, 8 high bits for SLCH, 8 low bits for SLCL */
  74. #define CIR_RX_LIMIT_COUNT (IR_DEFAULT_TIMEOUT / SAMPLE_PERIOD)
  75. /* CIR Regs */
  76. #define CIR_IRCON 0x00
  77. #define CIR_IRSTS 0x01
  78. #define CIR_IREN 0x02
  79. #define CIR_RXFCONT 0x03
  80. #define CIR_CP 0x04
  81. #define CIR_CC 0x05
  82. #define CIR_SLCH 0x06
  83. #define CIR_SLCL 0x07
  84. #define CIR_FIFOCON 0x08
  85. #define CIR_IRFIFOSTS 0x09
  86. #define CIR_SRXFIFO 0x0a
  87. #define CIR_TXFCONT 0x0b
  88. #define CIR_STXFIFO 0x0c
  89. #define CIR_FCCH 0x0d
  90. #define CIR_FCCL 0x0e
  91. #define CIR_IRFSM 0x0f
  92. /* CIR IRCON settings */
  93. #define CIR_IRCON_RECV 0x80
  94. #define CIR_IRCON_WIREN 0x40
  95. #define CIR_IRCON_TXEN 0x20
  96. #define CIR_IRCON_RXEN 0x10
  97. #define CIR_IRCON_WRXINV 0x08
  98. #define CIR_IRCON_RXINV 0x04
  99. #define CIR_IRCON_SAMPLE_PERIOD_SEL_1 0x00
  100. #define CIR_IRCON_SAMPLE_PERIOD_SEL_25 0x01
  101. #define CIR_IRCON_SAMPLE_PERIOD_SEL_50 0x02
  102. #define CIR_IRCON_SAMPLE_PERIOD_SEL_100 0x03
  103. /* FIXME: make this a runtime option */
  104. /* select sample period as 50us */
  105. #define CIR_IRCON_SAMPLE_PERIOD_SEL CIR_IRCON_SAMPLE_PERIOD_SEL_50
  106. /* CIR IRSTS settings */
  107. #define CIR_IRSTS_RDR 0x80
  108. #define CIR_IRSTS_RTR 0x40
  109. #define CIR_IRSTS_PE 0x20
  110. #define CIR_IRSTS_RFO 0x10
  111. #define CIR_IRSTS_TE 0x08
  112. #define CIR_IRSTS_TTR 0x04
  113. #define CIR_IRSTS_TFU 0x02
  114. #define CIR_IRSTS_GH 0x01
  115. /* CIR IREN settings */
  116. #define CIR_IREN_RDR 0x80
  117. #define CIR_IREN_RTR 0x40
  118. #define CIR_IREN_PE 0x20
  119. #define CIR_IREN_RFO 0x10
  120. #define CIR_IREN_TE 0x08
  121. #define CIR_IREN_TTR 0x04
  122. #define CIR_IREN_TFU 0x02
  123. #define CIR_IREN_GH 0x01
  124. /* CIR FIFOCON settings */
  125. #define CIR_FIFOCON_TXFIFOCLR 0x80
  126. #define CIR_FIFOCON_TX_TRIGGER_LEV_31 0x00
  127. #define CIR_FIFOCON_TX_TRIGGER_LEV_24 0x10
  128. #define CIR_FIFOCON_TX_TRIGGER_LEV_16 0x20
  129. #define CIR_FIFOCON_TX_TRIGGER_LEV_8 0x30
  130. /* FIXME: make this a runtime option */
  131. /* select TX trigger level as 16 */
  132. #define CIR_FIFOCON_TX_TRIGGER_LEV CIR_FIFOCON_TX_TRIGGER_LEV_16
  133. #define CIR_FIFOCON_RXFIFOCLR 0x08
  134. #define CIR_FIFOCON_RX_TRIGGER_LEV_1 0x00
  135. #define CIR_FIFOCON_RX_TRIGGER_LEV_8 0x01
  136. #define CIR_FIFOCON_RX_TRIGGER_LEV_16 0x02
  137. #define CIR_FIFOCON_RX_TRIGGER_LEV_24 0x03
  138. /* FIXME: make this a runtime option */
  139. /* select RX trigger level as 24 */
  140. #define CIR_FIFOCON_RX_TRIGGER_LEV CIR_FIFOCON_RX_TRIGGER_LEV_24
  141. /* CIR IRFIFOSTS settings */
  142. #define CIR_IRFIFOSTS_IR_PENDING 0x80
  143. #define CIR_IRFIFOSTS_RX_GS 0x40
  144. #define CIR_IRFIFOSTS_RX_FTA 0x20
  145. #define CIR_IRFIFOSTS_RX_EMPTY 0x10
  146. #define CIR_IRFIFOSTS_RX_FULL 0x08
  147. #define CIR_IRFIFOSTS_TX_FTA 0x04
  148. #define CIR_IRFIFOSTS_TX_EMPTY 0x02
  149. #define CIR_IRFIFOSTS_TX_FULL 0x01
  150. /* CIR WAKE UP Regs */
  151. #define CIR_WAKE_IRCON 0x00
  152. #define CIR_WAKE_IRSTS 0x01
  153. #define CIR_WAKE_IREN 0x02
  154. #define CIR_WAKE_FIFO_CMP_DEEP 0x03
  155. #define CIR_WAKE_FIFO_CMP_TOL 0x04
  156. #define CIR_WAKE_FIFO_COUNT 0x05
  157. #define CIR_WAKE_SLCH 0x06
  158. #define CIR_WAKE_SLCL 0x07
  159. #define CIR_WAKE_FIFOCON 0x08
  160. #define CIR_WAKE_SRXFSTS 0x09
  161. #define CIR_WAKE_SAMPLE_RX_FIFO 0x0a
  162. #define CIR_WAKE_WR_FIFO_DATA 0x0b
  163. #define CIR_WAKE_RD_FIFO_ONLY 0x0c
  164. #define CIR_WAKE_RD_FIFO_ONLY_IDX 0x0d
  165. #define CIR_WAKE_FIFO_IGNORE 0x0e
  166. #define CIR_WAKE_IRFSM 0x0f
  167. /* CIR WAKE UP IRCON settings */
  168. #define CIR_WAKE_IRCON_DEC_RST 0x80
  169. #define CIR_WAKE_IRCON_MODE1 0x40
  170. #define CIR_WAKE_IRCON_MODE0 0x20
  171. #define CIR_WAKE_IRCON_RXEN 0x10
  172. #define CIR_WAKE_IRCON_R 0x08
  173. #define CIR_WAKE_IRCON_RXINV 0x04
  174. /* FIXME/jarod: make this a runtime option */
  175. /* select a same sample period like cir register */
  176. #define CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL CIR_IRCON_SAMPLE_PERIOD_SEL_50
  177. /* CIR WAKE IRSTS Bits */
  178. #define CIR_WAKE_IRSTS_RDR 0x80
  179. #define CIR_WAKE_IRSTS_RTR 0x40
  180. #define CIR_WAKE_IRSTS_PE 0x20
  181. #define CIR_WAKE_IRSTS_RFO 0x10
  182. #define CIR_WAKE_IRSTS_GH 0x08
  183. #define CIR_WAKE_IRSTS_IR_PENDING 0x01
  184. /* CIR WAKE UP IREN Bits */
  185. #define CIR_WAKE_IREN_RDR 0x80
  186. #define CIR_WAKE_IREN_RTR 0x40
  187. #define CIR_WAKE_IREN_PE 0x20
  188. #define CIR_WAKE_IREN_RFO 0x10
  189. #define CIR_WAKE_IREN_GH 0x08
  190. /* CIR WAKE FIFOCON settings */
  191. #define CIR_WAKE_FIFOCON_RXFIFOCLR 0x08
  192. #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_67 0x00
  193. #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_66 0x01
  194. #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_65 0x02
  195. #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_64 0x03
  196. /* FIXME: make this a runtime option */
  197. /* select WAKE UP RX trigger level as 67 */
  198. #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_67
  199. /* CIR WAKE SRXFSTS settings */
  200. #define CIR_WAKE_IRFIFOSTS_RX_GS 0x80
  201. #define CIR_WAKE_IRFIFOSTS_RX_FTA 0x40
  202. #define CIR_WAKE_IRFIFOSTS_RX_EMPTY 0x20
  203. #define CIR_WAKE_IRFIFOSTS_RX_FULL 0x10
  204. /*
  205. * The CIR Wake FIFO buffer is 67 bytes long, but the stock remote wakes
  206. * the system comparing only 65 bytes (fails with this set to 67)
  207. */
  208. #define CIR_WAKE_FIFO_CMP_BYTES 65
  209. /* CIR Wake byte comparison tolerance */
  210. #define CIR_WAKE_CMP_TOLERANCE 5
  211. /*
  212. * Extended Function Enable Registers:
  213. * Extended Function Index Register
  214. * Extended Function Data Register
  215. */
  216. #define CR_EFIR 0x2e
  217. #define CR_EFDR 0x2f
  218. /* Possible alternate EFER values, depends on how the chip is wired */
  219. #define CR_EFIR2 0x4e
  220. #define CR_EFDR2 0x4f
  221. /* Extended Function Mode enable/disable magic values */
  222. #define EFER_EFM_ENABLE 0x87
  223. #define EFER_EFM_DISABLE 0xaa
  224. /* Config regs we need to care about */
  225. #define CR_SOFTWARE_RESET 0x02
  226. #define CR_LOGICAL_DEV_SEL 0x07
  227. #define CR_CHIP_ID_HI 0x20
  228. #define CR_CHIP_ID_LO 0x21
  229. #define CR_DEV_POWER_DOWN 0x22 /* bit 2 is CIR power, default power on */
  230. #define CR_OUTPUT_PIN_SEL 0x27
  231. #define CR_MULTIFUNC_PIN_SEL 0x2c
  232. #define CR_LOGICAL_DEV_EN 0x30 /* valid for all logical devices */
  233. /* next three regs valid for both the CIR and CIR_WAKE logical devices */
  234. #define CR_CIR_BASE_ADDR_HI 0x60
  235. #define CR_CIR_BASE_ADDR_LO 0x61
  236. #define CR_CIR_IRQ_RSRC 0x70
  237. /* next three regs valid only for ACPI logical dev */
  238. #define CR_ACPI_CIR_WAKE 0xe0
  239. #define CR_ACPI_IRQ_EVENTS 0xf6
  240. #define CR_ACPI_IRQ_EVENTS2 0xf7
  241. /* Logical devices that we need to care about */
  242. #define LOGICAL_DEV_LPT 0x01
  243. #define LOGICAL_DEV_CIR 0x06
  244. #define LOGICAL_DEV_ACPI 0x0a
  245. #define LOGICAL_DEV_CIR_WAKE 0x0e
  246. #define LOGICAL_DEV_DISABLE 0x00
  247. #define LOGICAL_DEV_ENABLE 0x01
  248. #define CIR_WAKE_ENABLE_BIT 0x08
  249. #define PME_INTR_CIR_PASS_BIT 0x08
  250. /* w83677hg CIR pin config */
  251. #define OUTPUT_PIN_SEL_MASK 0xbc
  252. #define OUTPUT_ENABLE_CIR 0x01 /* Pin95=CIRRX, Pin96=CIRTX1 */
  253. #define OUTPUT_ENABLE_CIRWB 0x40 /* enable wide-band sensor */
  254. /* w83667hg CIR pin config */
  255. #define MULTIFUNC_PIN_SEL_MASK 0x1f
  256. #define MULTIFUNC_ENABLE_CIR 0x80 /* Pin75=CIRRX, Pin76=CIRTX1 */
  257. #define MULTIFUNC_ENABLE_CIRWB 0x20 /* enable wide-band sensor */
  258. /* MCE CIR signal length, related on sample period */
  259. /* MCE CIR controller signal length: about 43ms
  260. * 43ms / 50us (sample period) * 0.85 (inaccuracy)
  261. */
  262. #define CONTROLLER_BUF_LEN_MIN 830
  263. /* MCE CIR keyboard signal length: about 26ms
  264. * 26ms / 50us (sample period) * 0.85 (inaccuracy)
  265. */
  266. #define KEYBOARD_BUF_LEN_MAX 650
  267. #define KEYBOARD_BUF_LEN_MIN 610
  268. /* MCE CIR mouse signal length: about 24ms
  269. * 24ms / 50us (sample period) * 0.85 (inaccuracy)
  270. */
  271. #define MOUSE_BUF_LEN_MIN 565
  272. #define CIR_SAMPLE_PERIOD 50
  273. #define CIR_SAMPLE_LOW_INACCURACY 0.85
  274. /* MAX silence time that driver will sent to lirc */
  275. #define MAX_SILENCE_TIME 60000
  276. #if CIR_IRCON_SAMPLE_PERIOD_SEL == CIR_IRCON_SAMPLE_PERIOD_SEL_100
  277. #define SAMPLE_PERIOD 100
  278. #elif CIR_IRCON_SAMPLE_PERIOD_SEL == CIR_IRCON_SAMPLE_PERIOD_SEL_50
  279. #define SAMPLE_PERIOD 50
  280. #elif CIR_IRCON_SAMPLE_PERIOD_SEL == CIR_IRCON_SAMPLE_PERIOD_SEL_25
  281. #define SAMPLE_PERIOD 25
  282. #else
  283. #define SAMPLE_PERIOD 1
  284. #endif
  285. /* as VISTA MCE definition, valid carrier value */
  286. #define MAX_CARRIER 60000
  287. #define MIN_CARRIER 30000
  288. /* max wakeup sequence length */
  289. #define WAKEUP_MAX_SIZE 65