mtk-cir.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Driver for Mediatek IR Receiver Controller
  4. *
  5. * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
  6. */
  7. #include <linux/clk.h>
  8. #include <linux/interrupt.h>
  9. #include <linux/module.h>
  10. #include <linux/of_platform.h>
  11. #include <linux/reset.h>
  12. #include <media/rc-core.h>
  13. #define MTK_IR_DEV KBUILD_MODNAME
  14. /* Register to enable PWM and IR */
  15. #define MTK_CONFIG_HIGH_REG 0x0c
  16. /* Bit to enable IR pulse width detection */
  17. #define MTK_PWM_EN BIT(13)
  18. /*
  19. * Register to setting ok count whose unit based on hardware sampling period
  20. * indicating IR receiving completion and then making IRQ fires
  21. */
  22. #define MTK_OK_COUNT(x) (((x) & GENMASK(23, 16)) << 16)
  23. /* Bit to enable IR hardware function */
  24. #define MTK_IR_EN BIT(0)
  25. /* Bit to restart IR receiving */
  26. #define MTK_IRCLR BIT(0)
  27. /* Fields containing pulse width data */
  28. #define MTK_WIDTH_MASK (GENMASK(7, 0))
  29. /* IR threshold */
  30. #define MTK_IRTHD 0x14
  31. #define MTK_DG_CNT_MASK (GENMASK(12, 8))
  32. #define MTK_DG_CNT(x) ((x) << 8)
  33. /* Bit to enable interrupt */
  34. #define MTK_IRINT_EN BIT(0)
  35. /* Bit to clear interrupt status */
  36. #define MTK_IRINT_CLR BIT(0)
  37. /* Maximum count of samples */
  38. #define MTK_MAX_SAMPLES 0xff
  39. /* Indicate the end of IR message */
  40. #define MTK_IR_END(v, p) ((v) == MTK_MAX_SAMPLES && (p) == 0)
  41. /* Number of registers to record the pulse width */
  42. #define MTK_CHKDATA_SZ 17
  43. /* Sample period in us */
  44. #define MTK_IR_SAMPLE 46
  45. enum mtk_fields {
  46. /* Register to setting software sampling period */
  47. MTK_CHK_PERIOD,
  48. /* Register to setting hardware sampling period */
  49. MTK_HW_PERIOD,
  50. };
  51. enum mtk_regs {
  52. /* Register to clear state of state machine */
  53. MTK_IRCLR_REG,
  54. /* Register containing pulse width data */
  55. MTK_CHKDATA_REG,
  56. /* Register to enable IR interrupt */
  57. MTK_IRINT_EN_REG,
  58. /* Register to ack IR interrupt */
  59. MTK_IRINT_CLR_REG
  60. };
  61. static const u32 mt7623_regs[] = {
  62. [MTK_IRCLR_REG] = 0x20,
  63. [MTK_CHKDATA_REG] = 0x88,
  64. [MTK_IRINT_EN_REG] = 0xcc,
  65. [MTK_IRINT_CLR_REG] = 0xd0,
  66. };
  67. static const u32 mt7622_regs[] = {
  68. [MTK_IRCLR_REG] = 0x18,
  69. [MTK_CHKDATA_REG] = 0x30,
  70. [MTK_IRINT_EN_REG] = 0x1c,
  71. [MTK_IRINT_CLR_REG] = 0x20,
  72. };
  73. struct mtk_field_type {
  74. u32 reg;
  75. u8 offset;
  76. u32 mask;
  77. };
  78. /*
  79. * struct mtk_ir_data - This is the structure holding all differences among
  80. various hardwares
  81. * @regs: The pointer to the array holding registers offset
  82. * @fields: The pointer to the array holding fields location
  83. * @div: The internal divisor for the based reference clock
  84. * @ok_count: The count indicating the completion of IR data
  85. * receiving when count is reached
  86. * @hw_period: The value indicating the hardware sampling period
  87. */
  88. struct mtk_ir_data {
  89. const u32 *regs;
  90. const struct mtk_field_type *fields;
  91. u8 div;
  92. u8 ok_count;
  93. u32 hw_period;
  94. };
  95. static const struct mtk_field_type mt7623_fields[] = {
  96. [MTK_CHK_PERIOD] = {0x10, 8, GENMASK(20, 8)},
  97. [MTK_HW_PERIOD] = {0x10, 0, GENMASK(7, 0)},
  98. };
  99. static const struct mtk_field_type mt7622_fields[] = {
  100. [MTK_CHK_PERIOD] = {0x24, 0, GENMASK(24, 0)},
  101. [MTK_HW_PERIOD] = {0x10, 0, GENMASK(24, 0)},
  102. };
  103. /*
  104. * struct mtk_ir - This is the main datasructure for holding the state
  105. * of the driver
  106. * @dev: The device pointer
  107. * @rc: The rc instrance
  108. * @base: The mapped register i/o base
  109. * @irq: The IRQ that we are using
  110. * @clk: The clock that IR internal is using
  111. * @bus: The clock that software decoder is using
  112. * @data: Holding specific data for vaious platform
  113. */
  114. struct mtk_ir {
  115. struct device *dev;
  116. struct rc_dev *rc;
  117. void __iomem *base;
  118. int irq;
  119. struct clk *clk;
  120. struct clk *bus;
  121. const struct mtk_ir_data *data;
  122. };
  123. static inline u32 mtk_chkdata_reg(struct mtk_ir *ir, u32 i)
  124. {
  125. return ir->data->regs[MTK_CHKDATA_REG] + 4 * i;
  126. }
  127. static inline u32 mtk_chk_period(struct mtk_ir *ir)
  128. {
  129. u32 val;
  130. /*
  131. * Period for software decoder used in the
  132. * unit of raw software sampling
  133. */
  134. val = DIV_ROUND_CLOSEST(clk_get_rate(ir->bus),
  135. USEC_PER_SEC * ir->data->div / MTK_IR_SAMPLE);
  136. dev_dbg(ir->dev, "@pwm clk = \t%lu\n",
  137. clk_get_rate(ir->bus) / ir->data->div);
  138. dev_dbg(ir->dev, "@chkperiod = %08x\n", val);
  139. return val;
  140. }
  141. static void mtk_w32_mask(struct mtk_ir *ir, u32 val, u32 mask, unsigned int reg)
  142. {
  143. u32 tmp;
  144. tmp = __raw_readl(ir->base + reg);
  145. tmp = (tmp & ~mask) | val;
  146. __raw_writel(tmp, ir->base + reg);
  147. }
  148. static void mtk_w32(struct mtk_ir *ir, u32 val, unsigned int reg)
  149. {
  150. __raw_writel(val, ir->base + reg);
  151. }
  152. static u32 mtk_r32(struct mtk_ir *ir, unsigned int reg)
  153. {
  154. return __raw_readl(ir->base + reg);
  155. }
  156. static inline void mtk_irq_disable(struct mtk_ir *ir, u32 mask)
  157. {
  158. u32 val;
  159. val = mtk_r32(ir, ir->data->regs[MTK_IRINT_EN_REG]);
  160. mtk_w32(ir, val & ~mask, ir->data->regs[MTK_IRINT_EN_REG]);
  161. }
  162. static inline void mtk_irq_enable(struct mtk_ir *ir, u32 mask)
  163. {
  164. u32 val;
  165. val = mtk_r32(ir, ir->data->regs[MTK_IRINT_EN_REG]);
  166. mtk_w32(ir, val | mask, ir->data->regs[MTK_IRINT_EN_REG]);
  167. }
  168. static irqreturn_t mtk_ir_irq(int irqno, void *dev_id)
  169. {
  170. struct mtk_ir *ir = dev_id;
  171. u8 wid = 0;
  172. u32 i, j, val;
  173. struct ir_raw_event rawir = {};
  174. /*
  175. * Reset decoder state machine explicitly is required
  176. * because 1) the longest duration for space MTK IR hardware
  177. * could record is not safely long. e.g 12ms if rx resolution
  178. * is 46us by default. There is still the risk to satisfying
  179. * every decoder to reset themselves through long enough
  180. * trailing spaces and 2) the IRQ handler guarantees that
  181. * start of IR message is always contained in and starting
  182. * from register mtk_chkdata_reg(ir, i).
  183. */
  184. ir_raw_event_reset(ir->rc);
  185. /* First message must be pulse */
  186. rawir.pulse = false;
  187. /* Handle all pulse and space IR controller captures */
  188. for (i = 0 ; i < MTK_CHKDATA_SZ ; i++) {
  189. val = mtk_r32(ir, mtk_chkdata_reg(ir, i));
  190. dev_dbg(ir->dev, "@reg%d=0x%08x\n", i, val);
  191. for (j = 0 ; j < 4 ; j++) {
  192. wid = (val & (MTK_WIDTH_MASK << j * 8)) >> j * 8;
  193. rawir.pulse = !rawir.pulse;
  194. rawir.duration = wid * (MTK_IR_SAMPLE + 1);
  195. ir_raw_event_store_with_filter(ir->rc, &rawir);
  196. }
  197. }
  198. /*
  199. * The maximum number of edges the IR controller can
  200. * hold is MTK_CHKDATA_SZ * 4. So if received IR messages
  201. * is over the limit, the last incomplete IR message would
  202. * be appended trailing space and still would be sent into
  203. * ir-rc-raw to decode. That helps it is possible that it
  204. * has enough information to decode a scancode even if the
  205. * trailing end of the message is missing.
  206. */
  207. if (!MTK_IR_END(wid, rawir.pulse)) {
  208. rawir.pulse = false;
  209. rawir.duration = MTK_MAX_SAMPLES * (MTK_IR_SAMPLE + 1);
  210. ir_raw_event_store_with_filter(ir->rc, &rawir);
  211. }
  212. ir_raw_event_handle(ir->rc);
  213. /*
  214. * Restart controller for the next receive that would
  215. * clear up all CHKDATA registers
  216. */
  217. mtk_w32_mask(ir, 0x1, MTK_IRCLR, ir->data->regs[MTK_IRCLR_REG]);
  218. /* Clear interrupt status */
  219. mtk_w32_mask(ir, 0x1, MTK_IRINT_CLR,
  220. ir->data->regs[MTK_IRINT_CLR_REG]);
  221. return IRQ_HANDLED;
  222. }
  223. static const struct mtk_ir_data mt7623_data = {
  224. .regs = mt7623_regs,
  225. .fields = mt7623_fields,
  226. .ok_count = 0xf,
  227. .hw_period = 0xff,
  228. .div = 4,
  229. };
  230. static const struct mtk_ir_data mt7622_data = {
  231. .regs = mt7622_regs,
  232. .fields = mt7622_fields,
  233. .ok_count = 0xf,
  234. .hw_period = 0xffff,
  235. .div = 32,
  236. };
  237. static const struct of_device_id mtk_ir_match[] = {
  238. { .compatible = "mediatek,mt7623-cir", .data = &mt7623_data},
  239. { .compatible = "mediatek,mt7622-cir", .data = &mt7622_data},
  240. {},
  241. };
  242. MODULE_DEVICE_TABLE(of, mtk_ir_match);
  243. static int mtk_ir_probe(struct platform_device *pdev)
  244. {
  245. struct device *dev = &pdev->dev;
  246. struct device_node *dn = dev->of_node;
  247. struct resource *res;
  248. struct mtk_ir *ir;
  249. u32 val;
  250. int ret = 0;
  251. const char *map_name;
  252. ir = devm_kzalloc(dev, sizeof(struct mtk_ir), GFP_KERNEL);
  253. if (!ir)
  254. return -ENOMEM;
  255. ir->dev = dev;
  256. ir->data = of_device_get_match_data(dev);
  257. ir->clk = devm_clk_get(dev, "clk");
  258. if (IS_ERR(ir->clk)) {
  259. dev_err(dev, "failed to get a ir clock.\n");
  260. return PTR_ERR(ir->clk);
  261. }
  262. ir->bus = devm_clk_get(dev, "bus");
  263. if (IS_ERR(ir->bus)) {
  264. /*
  265. * For compatibility with older device trees try unnamed
  266. * ir->bus uses the same clock as ir->clock.
  267. */
  268. ir->bus = ir->clk;
  269. }
  270. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  271. ir->base = devm_ioremap_resource(dev, res);
  272. if (IS_ERR(ir->base))
  273. return PTR_ERR(ir->base);
  274. ir->rc = devm_rc_allocate_device(dev, RC_DRIVER_IR_RAW);
  275. if (!ir->rc) {
  276. dev_err(dev, "failed to allocate device\n");
  277. return -ENOMEM;
  278. }
  279. ir->rc->priv = ir;
  280. ir->rc->device_name = MTK_IR_DEV;
  281. ir->rc->input_phys = MTK_IR_DEV "/input0";
  282. ir->rc->input_id.bustype = BUS_HOST;
  283. ir->rc->input_id.vendor = 0x0001;
  284. ir->rc->input_id.product = 0x0001;
  285. ir->rc->input_id.version = 0x0001;
  286. map_name = of_get_property(dn, "linux,rc-map-name", NULL);
  287. ir->rc->map_name = map_name ?: RC_MAP_EMPTY;
  288. ir->rc->dev.parent = dev;
  289. ir->rc->driver_name = MTK_IR_DEV;
  290. ir->rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
  291. ir->rc->rx_resolution = MTK_IR_SAMPLE;
  292. ir->rc->timeout = MTK_MAX_SAMPLES * (MTK_IR_SAMPLE + 1);
  293. ret = devm_rc_register_device(dev, ir->rc);
  294. if (ret) {
  295. dev_err(dev, "failed to register rc device\n");
  296. return ret;
  297. }
  298. platform_set_drvdata(pdev, ir);
  299. ir->irq = platform_get_irq(pdev, 0);
  300. if (ir->irq < 0)
  301. return -ENODEV;
  302. if (clk_prepare_enable(ir->clk)) {
  303. dev_err(dev, "try to enable ir_clk failed\n");
  304. return -EINVAL;
  305. }
  306. if (clk_prepare_enable(ir->bus)) {
  307. dev_err(dev, "try to enable ir_clk failed\n");
  308. ret = -EINVAL;
  309. goto exit_clkdisable_clk;
  310. }
  311. /*
  312. * Enable interrupt after proper hardware
  313. * setup and IRQ handler registration
  314. */
  315. mtk_irq_disable(ir, MTK_IRINT_EN);
  316. ret = devm_request_irq(dev, ir->irq, mtk_ir_irq, 0, MTK_IR_DEV, ir);
  317. if (ret) {
  318. dev_err(dev, "failed request irq\n");
  319. goto exit_clkdisable_bus;
  320. }
  321. /*
  322. * Setup software sample period as the reference of software decoder
  323. */
  324. val = (mtk_chk_period(ir) << ir->data->fields[MTK_CHK_PERIOD].offset) &
  325. ir->data->fields[MTK_CHK_PERIOD].mask;
  326. mtk_w32_mask(ir, val, ir->data->fields[MTK_CHK_PERIOD].mask,
  327. ir->data->fields[MTK_CHK_PERIOD].reg);
  328. /*
  329. * Setup hardware sampling period used to setup the proper timeout for
  330. * indicating end of IR receiving completion
  331. */
  332. val = (ir->data->hw_period << ir->data->fields[MTK_HW_PERIOD].offset) &
  333. ir->data->fields[MTK_HW_PERIOD].mask;
  334. mtk_w32_mask(ir, val, ir->data->fields[MTK_HW_PERIOD].mask,
  335. ir->data->fields[MTK_HW_PERIOD].reg);
  336. /* Set de-glitch counter */
  337. mtk_w32_mask(ir, MTK_DG_CNT(1), MTK_DG_CNT_MASK, MTK_IRTHD);
  338. /* Enable IR and PWM */
  339. val = mtk_r32(ir, MTK_CONFIG_HIGH_REG);
  340. val |= MTK_OK_COUNT(ir->data->ok_count) | MTK_PWM_EN | MTK_IR_EN;
  341. mtk_w32(ir, val, MTK_CONFIG_HIGH_REG);
  342. mtk_irq_enable(ir, MTK_IRINT_EN);
  343. dev_info(dev, "Initialized MT7623 IR driver, sample period = %dus\n",
  344. MTK_IR_SAMPLE);
  345. return 0;
  346. exit_clkdisable_bus:
  347. clk_disable_unprepare(ir->bus);
  348. exit_clkdisable_clk:
  349. clk_disable_unprepare(ir->clk);
  350. return ret;
  351. }
  352. static int mtk_ir_remove(struct platform_device *pdev)
  353. {
  354. struct mtk_ir *ir = platform_get_drvdata(pdev);
  355. /*
  356. * Avoid contention between remove handler and
  357. * IRQ handler so that disabling IR interrupt and
  358. * waiting for pending IRQ handler to complete
  359. */
  360. mtk_irq_disable(ir, MTK_IRINT_EN);
  361. synchronize_irq(ir->irq);
  362. clk_disable_unprepare(ir->bus);
  363. clk_disable_unprepare(ir->clk);
  364. return 0;
  365. }
  366. static struct platform_driver mtk_ir_driver = {
  367. .probe = mtk_ir_probe,
  368. .remove = mtk_ir_remove,
  369. .driver = {
  370. .name = MTK_IR_DEV,
  371. .of_match_table = mtk_ir_match,
  372. },
  373. };
  374. module_platform_driver(mtk_ir_driver);
  375. MODULE_DESCRIPTION("Mediatek IR Receiver Controller Driver");
  376. MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
  377. MODULE_LICENSE("GPL");