ite-cir.h 16 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463
  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * Driver for ITE Tech Inc. IT8712F/IT8512F CIR
  4. *
  5. * Copyright (C) 2010 Juan Jesús García de Soria <skandalfo@gmail.com>
  6. */
  7. /* platform driver name to register */
  8. #define ITE_DRIVER_NAME "ite-cir"
  9. /* logging macros */
  10. #define ite_pr(level, text, ...) \
  11. printk(level KBUILD_MODNAME ": " text, ## __VA_ARGS__)
  12. #define ite_dbg(text, ...) do { \
  13. if (debug) \
  14. printk(KERN_DEBUG \
  15. KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__); \
  16. } while (0)
  17. #define ite_dbg_verbose(text, ...) do {\
  18. if (debug > 1) \
  19. printk(KERN_DEBUG \
  20. KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__); \
  21. } while (0)
  22. /* FIFO sizes */
  23. #define ITE_TX_FIFO_LEN 32
  24. #define ITE_RX_FIFO_LEN 32
  25. /* interrupt types */
  26. #define ITE_IRQ_TX_FIFO 1
  27. #define ITE_IRQ_RX_FIFO 2
  28. #define ITE_IRQ_RX_FIFO_OVERRUN 4
  29. /* forward declaration */
  30. struct ite_dev;
  31. /* struct for storing the parameters of different recognized devices */
  32. struct ite_dev_params {
  33. /* model of the device */
  34. const char *model;
  35. /* size of the I/O region */
  36. int io_region_size;
  37. /* IR pnp I/O resource number */
  38. int io_rsrc_no;
  39. /* true if the hardware supports transmission */
  40. bool hw_tx_capable;
  41. /* base sampling period, in ns */
  42. u32 sample_period;
  43. /* rx low carrier frequency, in Hz, 0 means no demodulation */
  44. unsigned int rx_low_carrier_freq;
  45. /* tx high carrier frequency, in Hz, 0 means no demodulation */
  46. unsigned int rx_high_carrier_freq;
  47. /* tx carrier frequency, in Hz */
  48. unsigned int tx_carrier_freq;
  49. /* duty cycle, 0-100 */
  50. int tx_duty_cycle;
  51. /* hw-specific operation function pointers; most of these must be
  52. * called while holding the spin lock, except for the TX FIFO length
  53. * one */
  54. /* get pending interrupt causes */
  55. int (*get_irq_causes) (struct ite_dev *dev);
  56. /* enable rx */
  57. void (*enable_rx) (struct ite_dev *dev);
  58. /* make rx enter the idle state; keep listening for a pulse, but stop
  59. * streaming space bytes */
  60. void (*idle_rx) (struct ite_dev *dev);
  61. /* disable rx completely */
  62. void (*disable_rx) (struct ite_dev *dev);
  63. /* read bytes from RX FIFO; return read count */
  64. int (*get_rx_bytes) (struct ite_dev *dev, u8 *buf, int buf_size);
  65. /* enable tx FIFO space available interrupt */
  66. void (*enable_tx_interrupt) (struct ite_dev *dev);
  67. /* disable tx FIFO space available interrupt */
  68. void (*disable_tx_interrupt) (struct ite_dev *dev);
  69. /* get number of full TX FIFO slots */
  70. int (*get_tx_used_slots) (struct ite_dev *dev);
  71. /* put a byte to the TX FIFO */
  72. void (*put_tx_byte) (struct ite_dev *dev, u8 value);
  73. /* disable hardware completely */
  74. void (*disable) (struct ite_dev *dev);
  75. /* initialize the hardware */
  76. void (*init_hardware) (struct ite_dev *dev);
  77. /* set the carrier parameters */
  78. void (*set_carrier_params) (struct ite_dev *dev, bool high_freq,
  79. bool use_demodulator, u8 carrier_freq_bits,
  80. u8 allowance_bits, u8 pulse_width_bits);
  81. };
  82. /* ITE CIR device structure */
  83. struct ite_dev {
  84. struct pnp_dev *pdev;
  85. struct rc_dev *rdev;
  86. struct ir_raw_event rawir;
  87. /* sync data */
  88. spinlock_t lock;
  89. bool in_use, transmitting;
  90. /* transmit support */
  91. int tx_fifo_allowance;
  92. wait_queue_head_t tx_queue, tx_ended;
  93. /* hardware I/O settings */
  94. unsigned long cir_addr;
  95. int cir_irq;
  96. /* overridable copy of model parameters */
  97. struct ite_dev_params params;
  98. };
  99. /* common values for all kinds of hardware */
  100. /* baud rate divisor default */
  101. #define ITE_BAUDRATE_DIVISOR 1
  102. /* low-speed carrier frequency limits (Hz) */
  103. #define ITE_LCF_MIN_CARRIER_FREQ 27000
  104. #define ITE_LCF_MAX_CARRIER_FREQ 58000
  105. /* high-speed carrier frequency limits (Hz) */
  106. #define ITE_HCF_MIN_CARRIER_FREQ 400000
  107. #define ITE_HCF_MAX_CARRIER_FREQ 500000
  108. /* default carrier freq for when demodulator is off (Hz) */
  109. #define ITE_DEFAULT_CARRIER_FREQ 38000
  110. /* convert bits to us */
  111. #define ITE_BITS_TO_US(bits, sample_period) \
  112. ((u32)((bits) * ITE_BAUDRATE_DIVISOR * (sample_period) / 1000))
  113. /*
  114. * n in RDCR produces a tolerance of +/- n * 6.25% around the center
  115. * carrier frequency...
  116. *
  117. * From two limit frequencies, L (low) and H (high), we can get both the
  118. * center frequency F = (L + H) / 2 and the variation from the center
  119. * frequency A = (H - L) / (H + L). We can use this in order to honor the
  120. * s_rx_carrier_range() call in ir-core. We'll suppose that any request
  121. * setting L=0 means we must shut down the demodulator.
  122. */
  123. #define ITE_RXDCR_PER_10000_STEP 625
  124. /* high speed carrier freq values */
  125. #define ITE_CFQ_400 0x03
  126. #define ITE_CFQ_450 0x08
  127. #define ITE_CFQ_480 0x0b
  128. #define ITE_CFQ_500 0x0d
  129. /* values for pulse widths */
  130. #define ITE_TXMPW_A 0x02
  131. #define ITE_TXMPW_B 0x03
  132. #define ITE_TXMPW_C 0x04
  133. #define ITE_TXMPW_D 0x05
  134. #define ITE_TXMPW_E 0x06
  135. /* values for demodulator carrier range allowance */
  136. #define ITE_RXDCR_DEFAULT 0x01 /* default carrier range */
  137. #define ITE_RXDCR_MAX 0x07 /* default carrier range */
  138. /* DR TX bits */
  139. #define ITE_TX_PULSE 0x00
  140. #define ITE_TX_SPACE 0x80
  141. #define ITE_TX_MAX_RLE 0x80
  142. #define ITE_TX_RLE_MASK 0x7f
  143. /*
  144. * IT8712F
  145. *
  146. * hardware data obtained from:
  147. *
  148. * IT8712F
  149. * Environment Control – Low Pin Count Input / Output
  150. * (EC - LPC I/O)
  151. * Preliminary Specification V0. 81
  152. */
  153. /* register offsets */
  154. #define IT87_DR 0x00 /* data register */
  155. #define IT87_IER 0x01 /* interrupt enable register */
  156. #define IT87_RCR 0x02 /* receiver control register */
  157. #define IT87_TCR1 0x03 /* transmitter control register 1 */
  158. #define IT87_TCR2 0x04 /* transmitter control register 2 */
  159. #define IT87_TSR 0x05 /* transmitter status register */
  160. #define IT87_RSR 0x06 /* receiver status register */
  161. #define IT87_BDLR 0x05 /* baud rate divisor low byte register */
  162. #define IT87_BDHR 0x06 /* baud rate divisor high byte register */
  163. #define IT87_IIR 0x07 /* interrupt identification register */
  164. #define IT87_IOREG_LENGTH 0x08 /* length of register file */
  165. /* IER bits */
  166. #define IT87_TLDLIE 0x01 /* transmitter low data interrupt enable */
  167. #define IT87_RDAIE 0x02 /* receiver data available interrupt enable */
  168. #define IT87_RFOIE 0x04 /* receiver FIFO overrun interrupt enable */
  169. #define IT87_IEC 0x08 /* interrupt enable control */
  170. #define IT87_BR 0x10 /* baud rate register enable */
  171. #define IT87_RESET 0x20 /* reset */
  172. /* RCR bits */
  173. #define IT87_RXDCR 0x07 /* receiver demodulation carrier range mask */
  174. #define IT87_RXACT 0x08 /* receiver active */
  175. #define IT87_RXEND 0x10 /* receiver demodulation enable */
  176. #define IT87_RXEN 0x20 /* receiver enable */
  177. #define IT87_HCFS 0x40 /* high-speed carrier frequency select */
  178. #define IT87_RDWOS 0x80 /* receiver data without sync */
  179. /* TCR1 bits */
  180. #define IT87_TXMPM 0x03 /* transmitter modulation pulse mode mask */
  181. #define IT87_TXMPM_DEFAULT 0x00 /* modulation pulse mode default */
  182. #define IT87_TXENDF 0x04 /* transmitter deferral */
  183. #define IT87_TXRLE 0x08 /* transmitter run length enable */
  184. #define IT87_FIFOTL 0x30 /* FIFO level threshold mask */
  185. #define IT87_FIFOTL_DEFAULT 0x20 /* FIFO level threshold default
  186. * 0x00 -> 1, 0x10 -> 7, 0x20 -> 17,
  187. * 0x30 -> 25 */
  188. #define IT87_ILE 0x40 /* internal loopback enable */
  189. #define IT87_FIFOCLR 0x80 /* FIFO clear bit */
  190. /* TCR2 bits */
  191. #define IT87_TXMPW 0x07 /* transmitter modulation pulse width mask */
  192. #define IT87_TXMPW_DEFAULT 0x04 /* default modulation pulse width */
  193. #define IT87_CFQ 0xf8 /* carrier frequency mask */
  194. #define IT87_CFQ_SHIFT 3 /* carrier frequency bit shift */
  195. /* TSR bits */
  196. #define IT87_TXFBC 0x3f /* transmitter FIFO byte count mask */
  197. /* RSR bits */
  198. #define IT87_RXFBC 0x3f /* receiver FIFO byte count mask */
  199. #define IT87_RXFTO 0x80 /* receiver FIFO time-out */
  200. /* IIR bits */
  201. #define IT87_IP 0x01 /* interrupt pending */
  202. #define IT87_II 0x06 /* interrupt identification mask */
  203. #define IT87_II_NOINT 0x00 /* no interrupt */
  204. #define IT87_II_TXLDL 0x02 /* transmitter low data level */
  205. #define IT87_II_RXDS 0x04 /* receiver data stored */
  206. #define IT87_II_RXFO 0x06 /* receiver FIFO overrun */
  207. /*
  208. * IT8512E/F
  209. *
  210. * Hardware data obtained from:
  211. *
  212. * IT8512E/F
  213. * Embedded Controller
  214. * Preliminary Specification V0.4.1
  215. *
  216. * Note that the CIR registers are not directly available to the host, because
  217. * they only are accessible to the integrated microcontroller. Thus, in order
  218. * use it, some kind of bridging is required. As the bridging may depend on
  219. * the controller firmware in use, we are going to use the PNP ID in order to
  220. * determine the strategy and ports available. See after these generic
  221. * IT8512E/F register definitions for register definitions for those
  222. * strategies.
  223. */
  224. /* register offsets */
  225. #define IT85_C0DR 0x00 /* data register */
  226. #define IT85_C0MSTCR 0x01 /* master control register */
  227. #define IT85_C0IER 0x02 /* interrupt enable register */
  228. #define IT85_C0IIR 0x03 /* interrupt identification register */
  229. #define IT85_C0CFR 0x04 /* carrier frequency register */
  230. #define IT85_C0RCR 0x05 /* receiver control register */
  231. #define IT85_C0TCR 0x06 /* transmitter control register */
  232. #define IT85_C0SCK 0x07 /* slow clock control register */
  233. #define IT85_C0BDLR 0x08 /* baud rate divisor low byte register */
  234. #define IT85_C0BDHR 0x09 /* baud rate divisor high byte register */
  235. #define IT85_C0TFSR 0x0a /* transmitter FIFO status register */
  236. #define IT85_C0RFSR 0x0b /* receiver FIFO status register */
  237. #define IT85_C0WCL 0x0d /* wakeup code length register */
  238. #define IT85_C0WCR 0x0e /* wakeup code read/write register */
  239. #define IT85_C0WPS 0x0f /* wakeup power control/status register */
  240. #define IT85_IOREG_LENGTH 0x10 /* length of register file */
  241. /* C0MSTCR bits */
  242. #define IT85_RESET 0x01 /* reset */
  243. #define IT85_FIFOCLR 0x02 /* FIFO clear bit */
  244. #define IT85_FIFOTL 0x0c /* FIFO level threshold mask */
  245. #define IT85_FIFOTL_DEFAULT 0x08 /* FIFO level threshold default
  246. * 0x00 -> 1, 0x04 -> 7, 0x08 -> 17,
  247. * 0x0c -> 25 */
  248. #define IT85_ILE 0x10 /* internal loopback enable */
  249. #define IT85_ILSEL 0x20 /* internal loopback select */
  250. /* C0IER bits */
  251. #define IT85_TLDLIE 0x01 /* TX low data level interrupt enable */
  252. #define IT85_RDAIE 0x02 /* RX data available interrupt enable */
  253. #define IT85_RFOIE 0x04 /* RX FIFO overrun interrupt enable */
  254. #define IT85_IEC 0x80 /* interrupt enable function control */
  255. /* C0IIR bits */
  256. #define IT85_TLDLI 0x01 /* transmitter low data level interrupt */
  257. #define IT85_RDAI 0x02 /* receiver data available interrupt */
  258. #define IT85_RFOI 0x04 /* receiver FIFO overrun interrupt */
  259. #define IT85_NIP 0x80 /* no interrupt pending */
  260. /* C0CFR bits */
  261. #define IT85_CFQ 0x1f /* carrier frequency mask */
  262. #define IT85_HCFS 0x20 /* high speed carrier frequency select */
  263. /* C0RCR bits */
  264. #define IT85_RXDCR 0x07 /* receiver demodulation carrier range mask */
  265. #define IT85_RXACT 0x08 /* receiver active */
  266. #define IT85_RXEND 0x10 /* receiver demodulation enable */
  267. #define IT85_RDWOS 0x20 /* receiver data without sync */
  268. #define IT85_RXEN 0x80 /* receiver enable */
  269. /* C0TCR bits */
  270. #define IT85_TXMPW 0x07 /* transmitter modulation pulse width mask */
  271. #define IT85_TXMPW_DEFAULT 0x04 /* default modulation pulse width */
  272. #define IT85_TXMPM 0x18 /* transmitter modulation pulse mode mask */
  273. #define IT85_TXMPM_DEFAULT 0x00 /* modulation pulse mode default */
  274. #define IT85_TXENDF 0x20 /* transmitter deferral */
  275. #define IT85_TXRLE 0x40 /* transmitter run length enable */
  276. /* C0SCK bits */
  277. #define IT85_SCKS 0x01 /* slow clock select */
  278. #define IT85_TXDCKG 0x02 /* TXD clock gating */
  279. #define IT85_DLL1P8E 0x04 /* DLL 1.8432M enable */
  280. #define IT85_DLLTE 0x08 /* DLL test enable */
  281. #define IT85_BRCM 0x70 /* baud rate count mode */
  282. #define IT85_DLLOCK 0x80 /* DLL lock */
  283. /* C0TFSR bits */
  284. #define IT85_TXFBC 0x3f /* transmitter FIFO count mask */
  285. /* C0RFSR bits */
  286. #define IT85_RXFBC 0x3f /* receiver FIFO count mask */
  287. #define IT85_RXFTO 0x80 /* receiver FIFO time-out */
  288. /* C0WCL bits */
  289. #define IT85_WCL 0x3f /* wakeup code length mask */
  290. /* C0WPS bits */
  291. #define IT85_CIRPOSIE 0x01 /* power on/off status interrupt enable */
  292. #define IT85_CIRPOIS 0x02 /* power on/off interrupt status */
  293. #define IT85_CIRPOII 0x04 /* power on/off interrupt identification */
  294. #define IT85_RCRST 0x10 /* wakeup code reading counter reset bit */
  295. #define IT85_WCRST 0x20 /* wakeup code writing counter reset bit */
  296. /*
  297. * ITE8708
  298. *
  299. * Hardware data obtained from hacked driver for IT8512 in this forum post:
  300. *
  301. * http://ubuntuforums.org/showthread.php?t=1028640
  302. *
  303. * Although there's no official documentation for that driver, analysis would
  304. * suggest that it maps the 16 registers of IT8512 onto two 8-register banks,
  305. * selectable by a single bank-select bit that's mapped onto both banks. The
  306. * IT8512 registers are mapped in a different order, so that the first bank
  307. * maps the ones that are used more often, and two registers that share a
  308. * reserved high-order bit are placed at the same offset in both banks in
  309. * order to reuse the reserved bit as the bank select bit.
  310. */
  311. /* register offsets */
  312. /* mapped onto both banks */
  313. #define IT8708_BANKSEL 0x07 /* bank select register */
  314. #define IT8708_HRAE 0x80 /* high registers access enable */
  315. /* mapped onto the low bank */
  316. #define IT8708_C0DR 0x00 /* data register */
  317. #define IT8708_C0MSTCR 0x01 /* master control register */
  318. #define IT8708_C0IER 0x02 /* interrupt enable register */
  319. #define IT8708_C0IIR 0x03 /* interrupt identification register */
  320. #define IT8708_C0RFSR 0x04 /* receiver FIFO status register */
  321. #define IT8708_C0RCR 0x05 /* receiver control register */
  322. #define IT8708_C0TFSR 0x06 /* transmitter FIFO status register */
  323. #define IT8708_C0TCR 0x07 /* transmitter control register */
  324. /* mapped onto the high bank */
  325. #define IT8708_C0BDLR 0x01 /* baud rate divisor low byte register */
  326. #define IT8708_C0BDHR 0x02 /* baud rate divisor high byte register */
  327. #define IT8708_C0CFR 0x04 /* carrier frequency register */
  328. /* registers whose bank mapping we don't know, since they weren't being used
  329. * in the hacked driver... most probably they belong to the high bank too,
  330. * since they fit in the holes the other registers leave */
  331. #define IT8708_C0SCK 0x03 /* slow clock control register */
  332. #define IT8708_C0WCL 0x05 /* wakeup code length register */
  333. #define IT8708_C0WCR 0x06 /* wakeup code read/write register */
  334. #define IT8708_C0WPS 0x07 /* wakeup power control/status register */
  335. #define IT8708_IOREG_LENGTH 0x08 /* length of register file */
  336. /* two more registers that are defined in the hacked driver, but can't be
  337. * found in the data sheets; no idea what they are or how they are accessed,
  338. * since the hacked driver doesn't seem to use them */
  339. #define IT8708_CSCRR 0x00
  340. #define IT8708_CGPINTR 0x01
  341. /* CSCRR bits */
  342. #define IT8708_CSCRR_SCRB 0x3f
  343. #define IT8708_CSCRR_PM 0x80
  344. /* CGPINTR bits */
  345. #define IT8708_CGPINT 0x01
  346. /*
  347. * ITE8709
  348. *
  349. * Hardware interfacing data obtained from the original lirc_ite8709 driver.
  350. * Verbatim from its sources:
  351. *
  352. * The ITE8709 device seems to be the combination of IT8512 superIO chip and
  353. * a specific firmware running on the IT8512's embedded micro-controller.
  354. * In addition of the embedded micro-controller, the IT8512 chip contains a
  355. * CIR module and several other modules. A few modules are directly accessible
  356. * by the host CPU, but most of them are only accessible by the
  357. * micro-controller. The CIR module is only accessible by the
  358. * micro-controller.
  359. *
  360. * The battery-backed SRAM module is accessible by the host CPU and the
  361. * micro-controller. So one of the MC's firmware role is to act as a bridge
  362. * between the host CPU and the CIR module. The firmware implements a kind of
  363. * communication protocol using the SRAM module as a shared memory. The IT8512
  364. * specification is publicly available on ITE's web site, but the
  365. * communication protocol is not, so it was reverse-engineered.
  366. */
  367. /* register offsets */
  368. #define IT8709_RAM_IDX 0x00 /* index into the SRAM module bytes */
  369. #define IT8709_RAM_VAL 0x01 /* read/write data to the indexed byte */
  370. #define IT8709_IOREG_LENGTH 0x02 /* length of register file */
  371. /* register offsets inside the SRAM module */
  372. #define IT8709_MODE 0x1a /* request/ack byte */
  373. #define IT8709_REG_IDX 0x1b /* index of the CIR register to access */
  374. #define IT8709_REG_VAL 0x1c /* value read/to be written */
  375. #define IT8709_IIR 0x1e /* interrupt identification register */
  376. #define IT8709_RFSR 0x1f /* receiver FIFO status register */
  377. #define IT8709_FIFO 0x20 /* start of in RAM RX FIFO copy */
  378. /* MODE values */
  379. #define IT8709_IDLE 0x00
  380. #define IT8709_WRITE 0x01
  381. #define IT8709_READ 0x02