ir-hix5hd2.c 9.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2014 Linaro Ltd.
  4. * Copyright (c) 2014 Hisilicon Limited.
  5. */
  6. #include <linux/clk.h>
  7. #include <linux/delay.h>
  8. #include <linux/interrupt.h>
  9. #include <linux/mfd/syscon.h>
  10. #include <linux/module.h>
  11. #include <linux/of_device.h>
  12. #include <linux/regmap.h>
  13. #include <media/rc-core.h>
  14. #define IR_ENABLE 0x00
  15. #define IR_CONFIG 0x04
  16. #define CNT_LEADS 0x08
  17. #define CNT_LEADE 0x0c
  18. #define CNT_SLEADE 0x10
  19. #define CNT0_B 0x14
  20. #define CNT1_B 0x18
  21. #define IR_BUSY 0x1c
  22. #define IR_DATAH 0x20
  23. #define IR_DATAL 0x24
  24. #define IR_INTM 0x28
  25. #define IR_INTS 0x2c
  26. #define IR_INTC 0x30
  27. #define IR_START 0x34
  28. /* interrupt mask */
  29. #define INTMS_SYMBRCV (BIT(24) | BIT(8))
  30. #define INTMS_TIMEOUT (BIT(25) | BIT(9))
  31. #define INTMS_OVERFLOW (BIT(26) | BIT(10))
  32. #define INT_CLR_OVERFLOW BIT(18)
  33. #define INT_CLR_TIMEOUT BIT(17)
  34. #define INT_CLR_RCV BIT(16)
  35. #define INT_CLR_RCVTIMEOUT (BIT(16) | BIT(17))
  36. #define IR_CLK_ENABLE BIT(4)
  37. #define IR_CLK_RESET BIT(5)
  38. /* IR_ENABLE register bits */
  39. #define IR_ENABLE_EN BIT(0)
  40. #define IR_ENABLE_EN_EXTRA BIT(8)
  41. #define IR_CFG_WIDTH_MASK 0xffff
  42. #define IR_CFG_WIDTH_SHIFT 16
  43. #define IR_CFG_FORMAT_MASK 0x3
  44. #define IR_CFG_FORMAT_SHIFT 14
  45. #define IR_CFG_INT_LEVEL_MASK 0x3f
  46. #define IR_CFG_INT_LEVEL_SHIFT 8
  47. /* only support raw mode */
  48. #define IR_CFG_MODE_RAW BIT(7)
  49. #define IR_CFG_FREQ_MASK 0x7f
  50. #define IR_CFG_FREQ_SHIFT 0
  51. #define IR_CFG_INT_THRESHOLD 1
  52. /* symbol start from low to high, symbol stream end at high*/
  53. #define IR_CFG_SYMBOL_FMT 0
  54. #define IR_CFG_SYMBOL_MAXWIDTH 0x3e80
  55. #define IR_HIX5HD2_NAME "hix5hd2-ir"
  56. /* Need to set extra bit for enabling IR */
  57. #define HIX5HD2_FLAG_EXTRA_ENABLE BIT(0)
  58. struct hix5hd2_soc_data {
  59. u32 clk_reg;
  60. u32 flags;
  61. };
  62. static const struct hix5hd2_soc_data hix5hd2_data = {
  63. .clk_reg = 0x48,
  64. };
  65. static const struct hix5hd2_soc_data hi3796cv300_data = {
  66. .clk_reg = 0x60,
  67. .flags = HIX5HD2_FLAG_EXTRA_ENABLE,
  68. };
  69. struct hix5hd2_ir_priv {
  70. int irq;
  71. void __iomem *base;
  72. struct device *dev;
  73. struct rc_dev *rdev;
  74. struct regmap *regmap;
  75. struct clk *clock;
  76. unsigned long rate;
  77. const struct hix5hd2_soc_data *socdata;
  78. };
  79. static int hix5hd2_ir_clk_enable(struct hix5hd2_ir_priv *dev, bool on)
  80. {
  81. u32 clk_reg = dev->socdata->clk_reg;
  82. u32 val;
  83. int ret = 0;
  84. if (dev->regmap) {
  85. regmap_read(dev->regmap, clk_reg, &val);
  86. if (on) {
  87. val &= ~IR_CLK_RESET;
  88. val |= IR_CLK_ENABLE;
  89. } else {
  90. val &= ~IR_CLK_ENABLE;
  91. val |= IR_CLK_RESET;
  92. }
  93. regmap_write(dev->regmap, clk_reg, val);
  94. } else {
  95. if (on)
  96. ret = clk_prepare_enable(dev->clock);
  97. else
  98. clk_disable_unprepare(dev->clock);
  99. }
  100. return ret;
  101. }
  102. static inline void hix5hd2_ir_enable(struct hix5hd2_ir_priv *priv)
  103. {
  104. u32 val = IR_ENABLE_EN;
  105. if (priv->socdata->flags & HIX5HD2_FLAG_EXTRA_ENABLE)
  106. val |= IR_ENABLE_EN_EXTRA;
  107. writel_relaxed(val, priv->base + IR_ENABLE);
  108. }
  109. static int hix5hd2_ir_config(struct hix5hd2_ir_priv *priv)
  110. {
  111. int timeout = 10000;
  112. u32 val, rate;
  113. hix5hd2_ir_enable(priv);
  114. while (readl_relaxed(priv->base + IR_BUSY)) {
  115. if (timeout--) {
  116. udelay(1);
  117. } else {
  118. dev_err(priv->dev, "IR_BUSY timeout\n");
  119. return -ETIMEDOUT;
  120. }
  121. }
  122. /* Now only support raw mode, with symbol start from low to high */
  123. rate = DIV_ROUND_CLOSEST(priv->rate, 1000000);
  124. val = IR_CFG_SYMBOL_MAXWIDTH & IR_CFG_WIDTH_MASK << IR_CFG_WIDTH_SHIFT;
  125. val |= IR_CFG_SYMBOL_FMT & IR_CFG_FORMAT_MASK << IR_CFG_FORMAT_SHIFT;
  126. val |= (IR_CFG_INT_THRESHOLD - 1) & IR_CFG_INT_LEVEL_MASK
  127. << IR_CFG_INT_LEVEL_SHIFT;
  128. val |= IR_CFG_MODE_RAW;
  129. val |= (rate - 1) & IR_CFG_FREQ_MASK << IR_CFG_FREQ_SHIFT;
  130. writel_relaxed(val, priv->base + IR_CONFIG);
  131. writel_relaxed(0x00, priv->base + IR_INTM);
  132. /* write arbitrary value to start */
  133. writel_relaxed(0x01, priv->base + IR_START);
  134. return 0;
  135. }
  136. static int hix5hd2_ir_open(struct rc_dev *rdev)
  137. {
  138. struct hix5hd2_ir_priv *priv = rdev->priv;
  139. int ret;
  140. ret = hix5hd2_ir_clk_enable(priv, true);
  141. if (ret)
  142. return ret;
  143. ret = hix5hd2_ir_config(priv);
  144. if (ret) {
  145. hix5hd2_ir_clk_enable(priv, false);
  146. return ret;
  147. }
  148. return 0;
  149. }
  150. static void hix5hd2_ir_close(struct rc_dev *rdev)
  151. {
  152. struct hix5hd2_ir_priv *priv = rdev->priv;
  153. hix5hd2_ir_clk_enable(priv, false);
  154. }
  155. static irqreturn_t hix5hd2_ir_rx_interrupt(int irq, void *data)
  156. {
  157. u32 symb_num, symb_val, symb_time;
  158. u32 data_l, data_h;
  159. u32 irq_sr, i;
  160. struct hix5hd2_ir_priv *priv = data;
  161. irq_sr = readl_relaxed(priv->base + IR_INTS);
  162. if (irq_sr & INTMS_OVERFLOW) {
  163. /*
  164. * we must read IR_DATAL first, then we can clean up
  165. * IR_INTS availably since logic would not clear
  166. * fifo when overflow, drv do the job
  167. */
  168. ir_raw_event_reset(priv->rdev);
  169. symb_num = readl_relaxed(priv->base + IR_DATAH);
  170. for (i = 0; i < symb_num; i++)
  171. readl_relaxed(priv->base + IR_DATAL);
  172. writel_relaxed(INT_CLR_OVERFLOW, priv->base + IR_INTC);
  173. dev_info(priv->dev, "overflow, level=%d\n",
  174. IR_CFG_INT_THRESHOLD);
  175. }
  176. if ((irq_sr & INTMS_SYMBRCV) || (irq_sr & INTMS_TIMEOUT)) {
  177. struct ir_raw_event ev = {};
  178. symb_num = readl_relaxed(priv->base + IR_DATAH);
  179. for (i = 0; i < symb_num; i++) {
  180. symb_val = readl_relaxed(priv->base + IR_DATAL);
  181. data_l = ((symb_val & 0xffff) * 10);
  182. data_h = ((symb_val >> 16) & 0xffff) * 10;
  183. symb_time = (data_l + data_h) / 10;
  184. ev.duration = data_l;
  185. ev.pulse = true;
  186. ir_raw_event_store(priv->rdev, &ev);
  187. if (symb_time < IR_CFG_SYMBOL_MAXWIDTH) {
  188. ev.duration = data_h;
  189. ev.pulse = false;
  190. ir_raw_event_store(priv->rdev, &ev);
  191. } else {
  192. ir_raw_event_set_idle(priv->rdev, true);
  193. }
  194. }
  195. if (irq_sr & INTMS_SYMBRCV)
  196. writel_relaxed(INT_CLR_RCV, priv->base + IR_INTC);
  197. if (irq_sr & INTMS_TIMEOUT)
  198. writel_relaxed(INT_CLR_TIMEOUT, priv->base + IR_INTC);
  199. }
  200. /* Empty software fifo */
  201. ir_raw_event_handle(priv->rdev);
  202. return IRQ_HANDLED;
  203. }
  204. static const struct of_device_id hix5hd2_ir_table[] = {
  205. { .compatible = "hisilicon,hix5hd2-ir", &hix5hd2_data, },
  206. { .compatible = "hisilicon,hi3796cv300-ir", &hi3796cv300_data, },
  207. {},
  208. };
  209. MODULE_DEVICE_TABLE(of, hix5hd2_ir_table);
  210. static int hix5hd2_ir_probe(struct platform_device *pdev)
  211. {
  212. struct rc_dev *rdev;
  213. struct device *dev = &pdev->dev;
  214. struct resource *res;
  215. struct hix5hd2_ir_priv *priv;
  216. struct device_node *node = pdev->dev.of_node;
  217. const struct of_device_id *of_id;
  218. const char *map_name;
  219. int ret;
  220. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  221. if (!priv)
  222. return -ENOMEM;
  223. of_id = of_match_device(hix5hd2_ir_table, dev);
  224. if (!of_id) {
  225. dev_err(dev, "Unable to initialize IR data\n");
  226. return -ENODEV;
  227. }
  228. priv->socdata = of_id->data;
  229. priv->regmap = syscon_regmap_lookup_by_phandle(node,
  230. "hisilicon,power-syscon");
  231. if (IS_ERR(priv->regmap)) {
  232. dev_info(dev, "no power-reg\n");
  233. priv->regmap = NULL;
  234. }
  235. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  236. priv->base = devm_ioremap_resource(dev, res);
  237. if (IS_ERR(priv->base))
  238. return PTR_ERR(priv->base);
  239. priv->irq = platform_get_irq(pdev, 0);
  240. if (priv->irq < 0)
  241. return priv->irq;
  242. rdev = rc_allocate_device(RC_DRIVER_IR_RAW);
  243. if (!rdev)
  244. return -ENOMEM;
  245. priv->clock = devm_clk_get(dev, NULL);
  246. if (IS_ERR(priv->clock)) {
  247. dev_err(dev, "clock not found\n");
  248. ret = PTR_ERR(priv->clock);
  249. goto err;
  250. }
  251. ret = clk_prepare_enable(priv->clock);
  252. if (ret)
  253. goto err;
  254. priv->rate = clk_get_rate(priv->clock);
  255. rdev->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
  256. rdev->priv = priv;
  257. rdev->open = hix5hd2_ir_open;
  258. rdev->close = hix5hd2_ir_close;
  259. rdev->driver_name = IR_HIX5HD2_NAME;
  260. map_name = of_get_property(node, "linux,rc-map-name", NULL);
  261. rdev->map_name = map_name ?: RC_MAP_EMPTY;
  262. rdev->device_name = IR_HIX5HD2_NAME;
  263. rdev->input_phys = IR_HIX5HD2_NAME "/input0";
  264. rdev->input_id.bustype = BUS_HOST;
  265. rdev->input_id.vendor = 0x0001;
  266. rdev->input_id.product = 0x0001;
  267. rdev->input_id.version = 0x0100;
  268. rdev->rx_resolution = 10;
  269. rdev->timeout = IR_CFG_SYMBOL_MAXWIDTH * 10;
  270. ret = rc_register_device(rdev);
  271. if (ret < 0)
  272. goto clkerr;
  273. if (devm_request_irq(dev, priv->irq, hix5hd2_ir_rx_interrupt,
  274. 0, pdev->name, priv) < 0) {
  275. dev_err(dev, "IRQ %d register failed\n", priv->irq);
  276. ret = -EINVAL;
  277. goto regerr;
  278. }
  279. priv->rdev = rdev;
  280. priv->dev = dev;
  281. platform_set_drvdata(pdev, priv);
  282. return ret;
  283. regerr:
  284. rc_unregister_device(rdev);
  285. rdev = NULL;
  286. clkerr:
  287. clk_disable_unprepare(priv->clock);
  288. err:
  289. rc_free_device(rdev);
  290. dev_err(dev, "Unable to register device (%d)\n", ret);
  291. return ret;
  292. }
  293. static int hix5hd2_ir_remove(struct platform_device *pdev)
  294. {
  295. struct hix5hd2_ir_priv *priv = platform_get_drvdata(pdev);
  296. clk_disable_unprepare(priv->clock);
  297. rc_unregister_device(priv->rdev);
  298. return 0;
  299. }
  300. #ifdef CONFIG_PM_SLEEP
  301. static int hix5hd2_ir_suspend(struct device *dev)
  302. {
  303. struct hix5hd2_ir_priv *priv = dev_get_drvdata(dev);
  304. clk_disable_unprepare(priv->clock);
  305. hix5hd2_ir_clk_enable(priv, false);
  306. return 0;
  307. }
  308. static int hix5hd2_ir_resume(struct device *dev)
  309. {
  310. struct hix5hd2_ir_priv *priv = dev_get_drvdata(dev);
  311. int ret;
  312. ret = hix5hd2_ir_clk_enable(priv, true);
  313. if (ret)
  314. return ret;
  315. ret = clk_prepare_enable(priv->clock);
  316. if (ret) {
  317. hix5hd2_ir_clk_enable(priv, false);
  318. return ret;
  319. }
  320. hix5hd2_ir_enable(priv);
  321. writel_relaxed(0x00, priv->base + IR_INTM);
  322. writel_relaxed(0xff, priv->base + IR_INTC);
  323. writel_relaxed(0x01, priv->base + IR_START);
  324. return 0;
  325. }
  326. #endif
  327. static SIMPLE_DEV_PM_OPS(hix5hd2_ir_pm_ops, hix5hd2_ir_suspend,
  328. hix5hd2_ir_resume);
  329. static struct platform_driver hix5hd2_ir_driver = {
  330. .driver = {
  331. .name = IR_HIX5HD2_NAME,
  332. .of_match_table = hix5hd2_ir_table,
  333. .pm = &hix5hd2_ir_pm_ops,
  334. },
  335. .probe = hix5hd2_ir_probe,
  336. .remove = hix5hd2_ir_remove,
  337. };
  338. module_platform_driver(hix5hd2_ir_driver);
  339. MODULE_DESCRIPTION("IR controller driver for hix5hd2 platforms");
  340. MODULE_AUTHOR("Guoxiong Yan <yanguoxiong@huawei.com>");
  341. MODULE_LICENSE("GPL v2");
  342. MODULE_ALIAS("platform:hix5hd2-ir");