fintek-cir.h 5.8 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * Driver for Feature Integration Technology Inc. (aka Fintek) LPC CIR
  4. *
  5. * Copyright (C) 2011 Jarod Wilson <jarod@redhat.com>
  6. *
  7. * Special thanks to Fintek for providing hardware and spec sheets.
  8. * This driver is based upon the nuvoton, ite and ene drivers for
  9. * similar hardware.
  10. */
  11. #include <linux/spinlock.h>
  12. #include <linux/ioctl.h>
  13. /* platform driver name to register */
  14. #define FINTEK_DRIVER_NAME "fintek-cir"
  15. #define FINTEK_DESCRIPTION "Fintek LPC SuperIO Consumer IR Transceiver"
  16. #define VENDOR_ID_FINTEK 0x1934
  17. /* debugging module parameter */
  18. static int debug;
  19. #define fit_pr(level, text, ...) \
  20. printk(level KBUILD_MODNAME ": " text, ## __VA_ARGS__)
  21. #define fit_dbg(text, ...) \
  22. if (debug) \
  23. printk(KERN_DEBUG \
  24. KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__)
  25. #define fit_dbg_verbose(text, ...) \
  26. if (debug > 1) \
  27. printk(KERN_DEBUG \
  28. KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__)
  29. #define fit_dbg_wake(text, ...) \
  30. if (debug > 2) \
  31. printk(KERN_DEBUG \
  32. KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__)
  33. #define TX_BUF_LEN 256
  34. #define RX_BUF_LEN 32
  35. struct fintek_dev {
  36. struct pnp_dev *pdev;
  37. struct rc_dev *rdev;
  38. spinlock_t fintek_lock;
  39. /* for rx */
  40. u8 buf[RX_BUF_LEN];
  41. unsigned int pkts;
  42. struct {
  43. spinlock_t lock;
  44. u8 buf[TX_BUF_LEN];
  45. unsigned int buf_count;
  46. unsigned int cur_buf_num;
  47. wait_queue_head_t queue;
  48. } tx;
  49. /* Config register index/data port pair */
  50. u32 cr_ip;
  51. u32 cr_dp;
  52. /* hardware I/O settings */
  53. unsigned long cir_addr;
  54. int cir_irq;
  55. int cir_port_len;
  56. /* hardware id */
  57. u8 chip_major;
  58. u8 chip_minor;
  59. u16 chip_vendor;
  60. u8 logical_dev_cir;
  61. /* hardware features */
  62. bool hw_learning_capable;
  63. bool hw_tx_capable;
  64. /* rx settings */
  65. bool learning_enabled;
  66. bool carrier_detect_enabled;
  67. enum {
  68. CMD_HEADER = 0,
  69. SUBCMD,
  70. CMD_DATA,
  71. PARSE_IRDATA,
  72. } parser_state;
  73. u8 cmd, rem;
  74. /* carrier period = 1 / frequency */
  75. u32 carrier;
  76. };
  77. /* buffer packet constants, largely identical to mceusb.c */
  78. #define BUF_PULSE_BIT 0x80
  79. #define BUF_LEN_MASK 0x1f
  80. #define BUF_SAMPLE_MASK 0x7f
  81. #define BUF_COMMAND_HEADER 0x9f
  82. #define BUF_COMMAND_MASK 0xe0
  83. #define BUF_COMMAND_NULL 0x00
  84. #define BUF_HW_CMD_HEADER 0xff
  85. #define BUF_CMD_G_REVISION 0x0b
  86. #define BUF_CMD_S_CARRIER 0x06
  87. #define BUF_CMD_S_TIMEOUT 0x0c
  88. #define BUF_CMD_SIG_END 0x01
  89. #define BUF_CMD_S_TXMASK 0x08
  90. #define BUF_CMD_S_RXSENSOR 0x14
  91. #define BUF_RSP_PULSE_COUNT 0x15
  92. #define CIR_SAMPLE_PERIOD 50
  93. /*
  94. * Configuration Register:
  95. * Index Port
  96. * Data Port
  97. */
  98. #define CR_INDEX_PORT 0x2e
  99. #define CR_DATA_PORT 0x2f
  100. /* Possible alternate values, depends on how the chip is wired */
  101. #define CR_INDEX_PORT2 0x4e
  102. #define CR_DATA_PORT2 0x4f
  103. /*
  104. * GCR_CONFIG_PORT_SEL bit 4 specifies which Index Port value is
  105. * active. 1 = 0x4e, 0 = 0x2e
  106. */
  107. #define PORT_SEL_PORT_4E_EN 0x10
  108. /* Extended Function Mode enable/disable magic values */
  109. #define CONFIG_REG_ENABLE 0x87
  110. #define CONFIG_REG_DISABLE 0xaa
  111. /* Chip IDs found in CR_CHIP_ID_{HI,LO} */
  112. #define CHIP_ID_HIGH_F71809U 0x04
  113. #define CHIP_ID_LOW_F71809U 0x08
  114. /*
  115. * Global control regs we need to care about:
  116. * Global Control def.
  117. * Register name addr val. */
  118. #define GCR_SOFTWARE_RESET 0x02 /* 0x00 */
  119. #define GCR_LOGICAL_DEV_NO 0x07 /* 0x00 */
  120. #define GCR_CHIP_ID_HI 0x20 /* 0x04 */
  121. #define GCR_CHIP_ID_LO 0x21 /* 0x08 */
  122. #define GCR_VENDOR_ID_HI 0x23 /* 0x19 */
  123. #define GCR_VENDOR_ID_LO 0x24 /* 0x34 */
  124. #define GCR_CONFIG_PORT_SEL 0x25 /* 0x01 */
  125. #define GCR_KBMOUSE_WAKEUP 0x27
  126. #define LOGICAL_DEV_DISABLE 0x00
  127. #define LOGICAL_DEV_ENABLE 0x01
  128. /* Logical device number of the CIR function */
  129. #define LOGICAL_DEV_CIR_REV1 0x05
  130. #define LOGICAL_DEV_CIR_REV2 0x08
  131. /* CIR Logical Device (LDN 0x08) config registers */
  132. #define CIR_CR_COMMAND_INDEX 0x04
  133. #define CIR_CR_IRCS 0x05 /* Before host writes command to IR, host
  134. must set to 1. When host finshes write
  135. command to IR, host must clear to 0. */
  136. #define CIR_CR_COMMAND_DATA 0x06 /* Host read or write command data */
  137. #define CIR_CR_CLASS 0x07 /* 0xff = rx-only, 0x66 = rx + 2 tx,
  138. 0x33 = rx + 1 tx */
  139. #define CIR_CR_DEV_EN 0x30 /* bit0 = 1 enables CIR */
  140. #define CIR_CR_BASE_ADDR_HI 0x60 /* MSB of CIR IO base addr */
  141. #define CIR_CR_BASE_ADDR_LO 0x61 /* LSB of CIR IO base addr */
  142. #define CIR_CR_IRQ_SEL 0x70 /* bits3-0 store CIR IRQ */
  143. #define CIR_CR_PSOUT_STATUS 0xf1
  144. #define CIR_CR_WAKE_KEY3_ADDR 0xf8
  145. #define CIR_CR_WAKE_KEY3_CODE 0xf9
  146. #define CIR_CR_WAKE_KEY3_DC 0xfa
  147. #define CIR_CR_WAKE_CONTROL 0xfb
  148. #define CIR_CR_WAKE_KEY12_ADDR 0xfc
  149. #define CIR_CR_WAKE_KEY4_ADDR 0xfd
  150. #define CIR_CR_WAKE_KEY5_ADDR 0xfe
  151. #define CLASS_RX_ONLY 0xff
  152. #define CLASS_RX_2TX 0x66
  153. #define CLASS_RX_1TX 0x33
  154. /* CIR device registers */
  155. #define CIR_STATUS 0x00
  156. #define CIR_RX_DATA 0x01
  157. #define CIR_TX_CONTROL 0x02
  158. #define CIR_TX_DATA 0x03
  159. #define CIR_CONTROL 0x04
  160. /* Bits to enable CIR wake */
  161. #define LOGICAL_DEV_ACPI 0x01
  162. #define LDEV_ACPI_WAKE_EN_REG 0xe8
  163. #define ACPI_WAKE_EN_CIR_BIT 0x04
  164. #define LDEV_ACPI_PME_EN_REG 0xf0
  165. #define LDEV_ACPI_PME_CLR_REG 0xf1
  166. #define ACPI_PME_CIR_BIT 0x02
  167. #define LDEV_ACPI_STATE_REG 0xf4
  168. #define ACPI_STATE_CIR_BIT 0x20
  169. /*
  170. * CIR status register (0x00):
  171. * 7 - CIR_IRQ_EN (1 = enable CIR IRQ, 0 = disable)
  172. * 3 - TX_FINISH (1 when TX finished, write 1 to clear)
  173. * 2 - TX_UNDERRUN (1 on TX underrun, write 1 to clear)
  174. * 1 - RX_TIMEOUT (1 on RX timeout, write 1 to clear)
  175. * 0 - RX_RECEIVE (1 on RX receive, write 1 to clear)
  176. */
  177. #define CIR_STATUS_IRQ_EN 0x80
  178. #define CIR_STATUS_TX_FINISH 0x08
  179. #define CIR_STATUS_TX_UNDERRUN 0x04
  180. #define CIR_STATUS_RX_TIMEOUT 0x02
  181. #define CIR_STATUS_RX_RECEIVE 0x01
  182. #define CIR_STATUS_IRQ_MASK 0x0f
  183. /*
  184. * CIR TX control register (0x02):
  185. * 7 - TX_START (1 to indicate TX start, auto-cleared when done)
  186. * 6 - TX_END (1 to indicate TX data written to TX fifo)
  187. */
  188. #define CIR_TX_CONTROL_TX_START 0x80
  189. #define CIR_TX_CONTROL_TX_END 0x40