fintek-cir.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Driver for Feature Integration Technology Inc. (aka Fintek) LPC CIR
  4. *
  5. * Copyright (C) 2011 Jarod Wilson <jarod@redhat.com>
  6. *
  7. * Special thanks to Fintek for providing hardware and spec sheets.
  8. * This driver is based upon the nuvoton, ite and ene drivers for
  9. * similar hardware.
  10. */
  11. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  12. #include <linux/kernel.h>
  13. #include <linux/module.h>
  14. #include <linux/pnp.h>
  15. #include <linux/io.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/sched.h>
  18. #include <linux/slab.h>
  19. #include <media/rc-core.h>
  20. #include "fintek-cir.h"
  21. /* write val to config reg */
  22. static inline void fintek_cr_write(struct fintek_dev *fintek, u8 val, u8 reg)
  23. {
  24. fit_dbg("%s: reg 0x%02x, val 0x%02x (ip/dp: %02x/%02x)",
  25. __func__, reg, val, fintek->cr_ip, fintek->cr_dp);
  26. outb(reg, fintek->cr_ip);
  27. outb(val, fintek->cr_dp);
  28. }
  29. /* read val from config reg */
  30. static inline u8 fintek_cr_read(struct fintek_dev *fintek, u8 reg)
  31. {
  32. u8 val;
  33. outb(reg, fintek->cr_ip);
  34. val = inb(fintek->cr_dp);
  35. fit_dbg("%s: reg 0x%02x, val 0x%02x (ip/dp: %02x/%02x)",
  36. __func__, reg, val, fintek->cr_ip, fintek->cr_dp);
  37. return val;
  38. }
  39. /* update config register bit without changing other bits */
  40. static inline void fintek_set_reg_bit(struct fintek_dev *fintek, u8 val, u8 reg)
  41. {
  42. u8 tmp = fintek_cr_read(fintek, reg) | val;
  43. fintek_cr_write(fintek, tmp, reg);
  44. }
  45. /* enter config mode */
  46. static inline void fintek_config_mode_enable(struct fintek_dev *fintek)
  47. {
  48. /* Enabling Config Mode explicitly requires writing 2x */
  49. outb(CONFIG_REG_ENABLE, fintek->cr_ip);
  50. outb(CONFIG_REG_ENABLE, fintek->cr_ip);
  51. }
  52. /* exit config mode */
  53. static inline void fintek_config_mode_disable(struct fintek_dev *fintek)
  54. {
  55. outb(CONFIG_REG_DISABLE, fintek->cr_ip);
  56. }
  57. /*
  58. * When you want to address a specific logical device, write its logical
  59. * device number to GCR_LOGICAL_DEV_NO
  60. */
  61. static inline void fintek_select_logical_dev(struct fintek_dev *fintek, u8 ldev)
  62. {
  63. fintek_cr_write(fintek, ldev, GCR_LOGICAL_DEV_NO);
  64. }
  65. /* write val to cir config register */
  66. static inline void fintek_cir_reg_write(struct fintek_dev *fintek, u8 val, u8 offset)
  67. {
  68. outb(val, fintek->cir_addr + offset);
  69. }
  70. /* read val from cir config register */
  71. static u8 fintek_cir_reg_read(struct fintek_dev *fintek, u8 offset)
  72. {
  73. return inb(fintek->cir_addr + offset);
  74. }
  75. /* dump current cir register contents */
  76. static void cir_dump_regs(struct fintek_dev *fintek)
  77. {
  78. fintek_config_mode_enable(fintek);
  79. fintek_select_logical_dev(fintek, fintek->logical_dev_cir);
  80. pr_info("%s: Dump CIR logical device registers:\n", FINTEK_DRIVER_NAME);
  81. pr_info(" * CR CIR BASE ADDR: 0x%x\n",
  82. (fintek_cr_read(fintek, CIR_CR_BASE_ADDR_HI) << 8) |
  83. fintek_cr_read(fintek, CIR_CR_BASE_ADDR_LO));
  84. pr_info(" * CR CIR IRQ NUM: 0x%x\n",
  85. fintek_cr_read(fintek, CIR_CR_IRQ_SEL));
  86. fintek_config_mode_disable(fintek);
  87. pr_info("%s: Dump CIR registers:\n", FINTEK_DRIVER_NAME);
  88. pr_info(" * STATUS: 0x%x\n",
  89. fintek_cir_reg_read(fintek, CIR_STATUS));
  90. pr_info(" * CONTROL: 0x%x\n",
  91. fintek_cir_reg_read(fintek, CIR_CONTROL));
  92. pr_info(" * RX_DATA: 0x%x\n",
  93. fintek_cir_reg_read(fintek, CIR_RX_DATA));
  94. pr_info(" * TX_CONTROL: 0x%x\n",
  95. fintek_cir_reg_read(fintek, CIR_TX_CONTROL));
  96. pr_info(" * TX_DATA: 0x%x\n",
  97. fintek_cir_reg_read(fintek, CIR_TX_DATA));
  98. }
  99. /* detect hardware features */
  100. static int fintek_hw_detect(struct fintek_dev *fintek)
  101. {
  102. unsigned long flags;
  103. u8 chip_major, chip_minor;
  104. u8 vendor_major, vendor_minor;
  105. u8 portsel, ir_class;
  106. u16 vendor, chip;
  107. fintek_config_mode_enable(fintek);
  108. /* Check if we're using config port 0x4e or 0x2e */
  109. portsel = fintek_cr_read(fintek, GCR_CONFIG_PORT_SEL);
  110. if (portsel == 0xff) {
  111. fit_pr(KERN_INFO, "first portsel read was bunk, trying alt");
  112. fintek_config_mode_disable(fintek);
  113. fintek->cr_ip = CR_INDEX_PORT2;
  114. fintek->cr_dp = CR_DATA_PORT2;
  115. fintek_config_mode_enable(fintek);
  116. portsel = fintek_cr_read(fintek, GCR_CONFIG_PORT_SEL);
  117. }
  118. fit_dbg("portsel reg: 0x%02x", portsel);
  119. ir_class = fintek_cir_reg_read(fintek, CIR_CR_CLASS);
  120. fit_dbg("ir_class reg: 0x%02x", ir_class);
  121. switch (ir_class) {
  122. case CLASS_RX_2TX:
  123. case CLASS_RX_1TX:
  124. fintek->hw_tx_capable = true;
  125. break;
  126. case CLASS_RX_ONLY:
  127. default:
  128. fintek->hw_tx_capable = false;
  129. break;
  130. }
  131. chip_major = fintek_cr_read(fintek, GCR_CHIP_ID_HI);
  132. chip_minor = fintek_cr_read(fintek, GCR_CHIP_ID_LO);
  133. chip = chip_major << 8 | chip_minor;
  134. vendor_major = fintek_cr_read(fintek, GCR_VENDOR_ID_HI);
  135. vendor_minor = fintek_cr_read(fintek, GCR_VENDOR_ID_LO);
  136. vendor = vendor_major << 8 | vendor_minor;
  137. if (vendor != VENDOR_ID_FINTEK)
  138. fit_pr(KERN_WARNING, "Unknown vendor ID: 0x%04x", vendor);
  139. else
  140. fit_dbg("Read Fintek vendor ID from chip");
  141. fintek_config_mode_disable(fintek);
  142. spin_lock_irqsave(&fintek->fintek_lock, flags);
  143. fintek->chip_major = chip_major;
  144. fintek->chip_minor = chip_minor;
  145. fintek->chip_vendor = vendor;
  146. /*
  147. * Newer reviews of this chipset uses port 8 instead of 5
  148. */
  149. if ((chip != 0x0408) && (chip != 0x0804))
  150. fintek->logical_dev_cir = LOGICAL_DEV_CIR_REV2;
  151. else
  152. fintek->logical_dev_cir = LOGICAL_DEV_CIR_REV1;
  153. spin_unlock_irqrestore(&fintek->fintek_lock, flags);
  154. return 0;
  155. }
  156. static void fintek_cir_ldev_init(struct fintek_dev *fintek)
  157. {
  158. /* Select CIR logical device and enable */
  159. fintek_select_logical_dev(fintek, fintek->logical_dev_cir);
  160. fintek_cr_write(fintek, LOGICAL_DEV_ENABLE, CIR_CR_DEV_EN);
  161. /* Write allocated CIR address and IRQ information to hardware */
  162. fintek_cr_write(fintek, fintek->cir_addr >> 8, CIR_CR_BASE_ADDR_HI);
  163. fintek_cr_write(fintek, fintek->cir_addr & 0xff, CIR_CR_BASE_ADDR_LO);
  164. fintek_cr_write(fintek, fintek->cir_irq, CIR_CR_IRQ_SEL);
  165. fit_dbg("CIR initialized, base io address: 0x%lx, irq: %d (len: %d)",
  166. fintek->cir_addr, fintek->cir_irq, fintek->cir_port_len);
  167. }
  168. /* enable CIR interrupts */
  169. static void fintek_enable_cir_irq(struct fintek_dev *fintek)
  170. {
  171. fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_EN, CIR_STATUS);
  172. }
  173. static void fintek_cir_regs_init(struct fintek_dev *fintek)
  174. {
  175. /* clear any and all stray interrupts */
  176. fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_MASK, CIR_STATUS);
  177. /* and finally, enable interrupts */
  178. fintek_enable_cir_irq(fintek);
  179. }
  180. static void fintek_enable_wake(struct fintek_dev *fintek)
  181. {
  182. fintek_config_mode_enable(fintek);
  183. fintek_select_logical_dev(fintek, LOGICAL_DEV_ACPI);
  184. /* Allow CIR PME's to wake system */
  185. fintek_set_reg_bit(fintek, ACPI_WAKE_EN_CIR_BIT, LDEV_ACPI_WAKE_EN_REG);
  186. /* Enable CIR PME's */
  187. fintek_set_reg_bit(fintek, ACPI_PME_CIR_BIT, LDEV_ACPI_PME_EN_REG);
  188. /* Clear CIR PME status register */
  189. fintek_set_reg_bit(fintek, ACPI_PME_CIR_BIT, LDEV_ACPI_PME_CLR_REG);
  190. /* Save state */
  191. fintek_set_reg_bit(fintek, ACPI_STATE_CIR_BIT, LDEV_ACPI_STATE_REG);
  192. fintek_config_mode_disable(fintek);
  193. }
  194. static int fintek_cmdsize(u8 cmd, u8 subcmd)
  195. {
  196. int datasize = 0;
  197. switch (cmd) {
  198. case BUF_COMMAND_NULL:
  199. if (subcmd == BUF_HW_CMD_HEADER)
  200. datasize = 1;
  201. break;
  202. case BUF_HW_CMD_HEADER:
  203. if (subcmd == BUF_CMD_G_REVISION)
  204. datasize = 2;
  205. break;
  206. case BUF_COMMAND_HEADER:
  207. switch (subcmd) {
  208. case BUF_CMD_S_CARRIER:
  209. case BUF_CMD_S_TIMEOUT:
  210. case BUF_RSP_PULSE_COUNT:
  211. datasize = 2;
  212. break;
  213. case BUF_CMD_SIG_END:
  214. case BUF_CMD_S_TXMASK:
  215. case BUF_CMD_S_RXSENSOR:
  216. datasize = 1;
  217. break;
  218. }
  219. }
  220. return datasize;
  221. }
  222. /* process ir data stored in driver buffer */
  223. static void fintek_process_rx_ir_data(struct fintek_dev *fintek)
  224. {
  225. struct ir_raw_event rawir = {};
  226. u8 sample;
  227. bool event = false;
  228. int i;
  229. for (i = 0; i < fintek->pkts; i++) {
  230. sample = fintek->buf[i];
  231. switch (fintek->parser_state) {
  232. case CMD_HEADER:
  233. fintek->cmd = sample;
  234. if ((fintek->cmd == BUF_COMMAND_HEADER) ||
  235. ((fintek->cmd & BUF_COMMAND_MASK) !=
  236. BUF_PULSE_BIT)) {
  237. fintek->parser_state = SUBCMD;
  238. continue;
  239. }
  240. fintek->rem = (fintek->cmd & BUF_LEN_MASK);
  241. fit_dbg("%s: rem: 0x%02x", __func__, fintek->rem);
  242. if (fintek->rem)
  243. fintek->parser_state = PARSE_IRDATA;
  244. else
  245. ir_raw_event_reset(fintek->rdev);
  246. break;
  247. case SUBCMD:
  248. fintek->rem = fintek_cmdsize(fintek->cmd, sample);
  249. fintek->parser_state = CMD_DATA;
  250. break;
  251. case CMD_DATA:
  252. fintek->rem--;
  253. break;
  254. case PARSE_IRDATA:
  255. fintek->rem--;
  256. rawir.pulse = ((sample & BUF_PULSE_BIT) != 0);
  257. rawir.duration = (sample & BUF_SAMPLE_MASK)
  258. * CIR_SAMPLE_PERIOD;
  259. fit_dbg("Storing %s with duration %d",
  260. rawir.pulse ? "pulse" : "space",
  261. rawir.duration);
  262. if (ir_raw_event_store_with_filter(fintek->rdev,
  263. &rawir))
  264. event = true;
  265. break;
  266. }
  267. if ((fintek->parser_state != CMD_HEADER) && !fintek->rem)
  268. fintek->parser_state = CMD_HEADER;
  269. }
  270. fintek->pkts = 0;
  271. if (event) {
  272. fit_dbg("Calling ir_raw_event_handle");
  273. ir_raw_event_handle(fintek->rdev);
  274. }
  275. }
  276. /* copy data from hardware rx register into driver buffer */
  277. static void fintek_get_rx_ir_data(struct fintek_dev *fintek, u8 rx_irqs)
  278. {
  279. unsigned long flags;
  280. u8 sample, status;
  281. spin_lock_irqsave(&fintek->fintek_lock, flags);
  282. /*
  283. * We must read data from CIR_RX_DATA until the hardware IR buffer
  284. * is empty and clears the RX_TIMEOUT and/or RX_RECEIVE flags in
  285. * the CIR_STATUS register
  286. */
  287. do {
  288. sample = fintek_cir_reg_read(fintek, CIR_RX_DATA);
  289. fit_dbg("%s: sample: 0x%02x", __func__, sample);
  290. fintek->buf[fintek->pkts] = sample;
  291. fintek->pkts++;
  292. status = fintek_cir_reg_read(fintek, CIR_STATUS);
  293. if (!(status & CIR_STATUS_IRQ_EN))
  294. break;
  295. } while (status & rx_irqs);
  296. fintek_process_rx_ir_data(fintek);
  297. spin_unlock_irqrestore(&fintek->fintek_lock, flags);
  298. }
  299. static void fintek_cir_log_irqs(u8 status)
  300. {
  301. fit_pr(KERN_INFO, "IRQ 0x%02x:%s%s%s%s%s", status,
  302. status & CIR_STATUS_IRQ_EN ? " IRQEN" : "",
  303. status & CIR_STATUS_TX_FINISH ? " TXF" : "",
  304. status & CIR_STATUS_TX_UNDERRUN ? " TXU" : "",
  305. status & CIR_STATUS_RX_TIMEOUT ? " RXTO" : "",
  306. status & CIR_STATUS_RX_RECEIVE ? " RXOK" : "");
  307. }
  308. /* interrupt service routine for incoming and outgoing CIR data */
  309. static irqreturn_t fintek_cir_isr(int irq, void *data)
  310. {
  311. struct fintek_dev *fintek = data;
  312. u8 status, rx_irqs;
  313. fit_dbg_verbose("%s firing", __func__);
  314. fintek_config_mode_enable(fintek);
  315. fintek_select_logical_dev(fintek, fintek->logical_dev_cir);
  316. fintek_config_mode_disable(fintek);
  317. /*
  318. * Get IR Status register contents. Write 1 to ack/clear
  319. *
  320. * bit: reg name - description
  321. * 3: TX_FINISH - TX is finished
  322. * 2: TX_UNDERRUN - TX underrun
  323. * 1: RX_TIMEOUT - RX data timeout
  324. * 0: RX_RECEIVE - RX data received
  325. */
  326. status = fintek_cir_reg_read(fintek, CIR_STATUS);
  327. if (!(status & CIR_STATUS_IRQ_MASK) || status == 0xff) {
  328. fit_dbg_verbose("%s exiting, IRSTS 0x%02x", __func__, status);
  329. fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_MASK, CIR_STATUS);
  330. return IRQ_RETVAL(IRQ_NONE);
  331. }
  332. if (debug)
  333. fintek_cir_log_irqs(status);
  334. rx_irqs = status & (CIR_STATUS_RX_RECEIVE | CIR_STATUS_RX_TIMEOUT);
  335. if (rx_irqs)
  336. fintek_get_rx_ir_data(fintek, rx_irqs);
  337. /* ack/clear all irq flags we've got */
  338. fintek_cir_reg_write(fintek, status, CIR_STATUS);
  339. fit_dbg_verbose("%s done", __func__);
  340. return IRQ_RETVAL(IRQ_HANDLED);
  341. }
  342. static void fintek_enable_cir(struct fintek_dev *fintek)
  343. {
  344. /* set IRQ enabled */
  345. fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_EN, CIR_STATUS);
  346. fintek_config_mode_enable(fintek);
  347. /* enable the CIR logical device */
  348. fintek_select_logical_dev(fintek, fintek->logical_dev_cir);
  349. fintek_cr_write(fintek, LOGICAL_DEV_ENABLE, CIR_CR_DEV_EN);
  350. fintek_config_mode_disable(fintek);
  351. /* clear all pending interrupts */
  352. fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_MASK, CIR_STATUS);
  353. /* enable interrupts */
  354. fintek_enable_cir_irq(fintek);
  355. }
  356. static void fintek_disable_cir(struct fintek_dev *fintek)
  357. {
  358. fintek_config_mode_enable(fintek);
  359. /* disable the CIR logical device */
  360. fintek_select_logical_dev(fintek, fintek->logical_dev_cir);
  361. fintek_cr_write(fintek, LOGICAL_DEV_DISABLE, CIR_CR_DEV_EN);
  362. fintek_config_mode_disable(fintek);
  363. }
  364. static int fintek_open(struct rc_dev *dev)
  365. {
  366. struct fintek_dev *fintek = dev->priv;
  367. unsigned long flags;
  368. spin_lock_irqsave(&fintek->fintek_lock, flags);
  369. fintek_enable_cir(fintek);
  370. spin_unlock_irqrestore(&fintek->fintek_lock, flags);
  371. return 0;
  372. }
  373. static void fintek_close(struct rc_dev *dev)
  374. {
  375. struct fintek_dev *fintek = dev->priv;
  376. unsigned long flags;
  377. spin_lock_irqsave(&fintek->fintek_lock, flags);
  378. fintek_disable_cir(fintek);
  379. spin_unlock_irqrestore(&fintek->fintek_lock, flags);
  380. }
  381. /* Allocate memory, probe hardware, and initialize everything */
  382. static int fintek_probe(struct pnp_dev *pdev, const struct pnp_device_id *dev_id)
  383. {
  384. struct fintek_dev *fintek;
  385. struct rc_dev *rdev;
  386. int ret = -ENOMEM;
  387. fintek = kzalloc(sizeof(struct fintek_dev), GFP_KERNEL);
  388. if (!fintek)
  389. return ret;
  390. /* input device for IR remote (and tx) */
  391. rdev = rc_allocate_device(RC_DRIVER_IR_RAW);
  392. if (!rdev)
  393. goto exit_free_dev_rdev;
  394. ret = -ENODEV;
  395. /* validate pnp resources */
  396. if (!pnp_port_valid(pdev, 0)) {
  397. dev_err(&pdev->dev, "IR PNP Port not valid!\n");
  398. goto exit_free_dev_rdev;
  399. }
  400. if (!pnp_irq_valid(pdev, 0)) {
  401. dev_err(&pdev->dev, "IR PNP IRQ not valid!\n");
  402. goto exit_free_dev_rdev;
  403. }
  404. fintek->cir_addr = pnp_port_start(pdev, 0);
  405. fintek->cir_irq = pnp_irq(pdev, 0);
  406. fintek->cir_port_len = pnp_port_len(pdev, 0);
  407. fintek->cr_ip = CR_INDEX_PORT;
  408. fintek->cr_dp = CR_DATA_PORT;
  409. spin_lock_init(&fintek->fintek_lock);
  410. pnp_set_drvdata(pdev, fintek);
  411. fintek->pdev = pdev;
  412. ret = fintek_hw_detect(fintek);
  413. if (ret)
  414. goto exit_free_dev_rdev;
  415. /* Initialize CIR & CIR Wake Logical Devices */
  416. fintek_config_mode_enable(fintek);
  417. fintek_cir_ldev_init(fintek);
  418. fintek_config_mode_disable(fintek);
  419. /* Initialize CIR & CIR Wake Config Registers */
  420. fintek_cir_regs_init(fintek);
  421. /* Set up the rc device */
  422. rdev->priv = fintek;
  423. rdev->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
  424. rdev->open = fintek_open;
  425. rdev->close = fintek_close;
  426. rdev->device_name = FINTEK_DESCRIPTION;
  427. rdev->input_phys = "fintek/cir0";
  428. rdev->input_id.bustype = BUS_HOST;
  429. rdev->input_id.vendor = VENDOR_ID_FINTEK;
  430. rdev->input_id.product = fintek->chip_major;
  431. rdev->input_id.version = fintek->chip_minor;
  432. rdev->dev.parent = &pdev->dev;
  433. rdev->driver_name = FINTEK_DRIVER_NAME;
  434. rdev->map_name = RC_MAP_RC6_MCE;
  435. rdev->timeout = 1000;
  436. /* rx resolution is hardwired to 50us atm, 1, 25, 100 also possible */
  437. rdev->rx_resolution = CIR_SAMPLE_PERIOD;
  438. fintek->rdev = rdev;
  439. ret = -EBUSY;
  440. /* now claim resources */
  441. if (!request_region(fintek->cir_addr,
  442. fintek->cir_port_len, FINTEK_DRIVER_NAME))
  443. goto exit_free_dev_rdev;
  444. if (request_irq(fintek->cir_irq, fintek_cir_isr, IRQF_SHARED,
  445. FINTEK_DRIVER_NAME, (void *)fintek))
  446. goto exit_free_cir_addr;
  447. ret = rc_register_device(rdev);
  448. if (ret)
  449. goto exit_free_irq;
  450. device_init_wakeup(&pdev->dev, true);
  451. fit_pr(KERN_NOTICE, "driver has been successfully loaded\n");
  452. if (debug)
  453. cir_dump_regs(fintek);
  454. return 0;
  455. exit_free_irq:
  456. free_irq(fintek->cir_irq, fintek);
  457. exit_free_cir_addr:
  458. release_region(fintek->cir_addr, fintek->cir_port_len);
  459. exit_free_dev_rdev:
  460. rc_free_device(rdev);
  461. kfree(fintek);
  462. return ret;
  463. }
  464. static void fintek_remove(struct pnp_dev *pdev)
  465. {
  466. struct fintek_dev *fintek = pnp_get_drvdata(pdev);
  467. unsigned long flags;
  468. spin_lock_irqsave(&fintek->fintek_lock, flags);
  469. /* disable CIR */
  470. fintek_disable_cir(fintek);
  471. fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_MASK, CIR_STATUS);
  472. /* enable CIR Wake (for IR power-on) */
  473. fintek_enable_wake(fintek);
  474. spin_unlock_irqrestore(&fintek->fintek_lock, flags);
  475. /* free resources */
  476. free_irq(fintek->cir_irq, fintek);
  477. release_region(fintek->cir_addr, fintek->cir_port_len);
  478. rc_unregister_device(fintek->rdev);
  479. kfree(fintek);
  480. }
  481. static int fintek_suspend(struct pnp_dev *pdev, pm_message_t state)
  482. {
  483. struct fintek_dev *fintek = pnp_get_drvdata(pdev);
  484. unsigned long flags;
  485. fit_dbg("%s called", __func__);
  486. spin_lock_irqsave(&fintek->fintek_lock, flags);
  487. /* disable all CIR interrupts */
  488. fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_MASK, CIR_STATUS);
  489. spin_unlock_irqrestore(&fintek->fintek_lock, flags);
  490. fintek_config_mode_enable(fintek);
  491. /* disable cir logical dev */
  492. fintek_select_logical_dev(fintek, fintek->logical_dev_cir);
  493. fintek_cr_write(fintek, LOGICAL_DEV_DISABLE, CIR_CR_DEV_EN);
  494. fintek_config_mode_disable(fintek);
  495. /* make sure wake is enabled */
  496. fintek_enable_wake(fintek);
  497. return 0;
  498. }
  499. static int fintek_resume(struct pnp_dev *pdev)
  500. {
  501. struct fintek_dev *fintek = pnp_get_drvdata(pdev);
  502. fit_dbg("%s called", __func__);
  503. /* open interrupt */
  504. fintek_enable_cir_irq(fintek);
  505. /* Enable CIR logical device */
  506. fintek_config_mode_enable(fintek);
  507. fintek_select_logical_dev(fintek, fintek->logical_dev_cir);
  508. fintek_cr_write(fintek, LOGICAL_DEV_ENABLE, CIR_CR_DEV_EN);
  509. fintek_config_mode_disable(fintek);
  510. fintek_cir_regs_init(fintek);
  511. return 0;
  512. }
  513. static void fintek_shutdown(struct pnp_dev *pdev)
  514. {
  515. struct fintek_dev *fintek = pnp_get_drvdata(pdev);
  516. fintek_enable_wake(fintek);
  517. }
  518. static const struct pnp_device_id fintek_ids[] = {
  519. { "FIT0002", 0 }, /* CIR */
  520. { "", 0 },
  521. };
  522. static struct pnp_driver fintek_driver = {
  523. .name = FINTEK_DRIVER_NAME,
  524. .id_table = fintek_ids,
  525. .flags = PNP_DRIVER_RES_DO_NOT_CHANGE,
  526. .probe = fintek_probe,
  527. .remove = fintek_remove,
  528. .suspend = fintek_suspend,
  529. .resume = fintek_resume,
  530. .shutdown = fintek_shutdown,
  531. };
  532. module_param(debug, int, S_IRUGO | S_IWUSR);
  533. MODULE_PARM_DESC(debug, "Enable debugging output");
  534. MODULE_DEVICE_TABLE(pnp, fintek_ids);
  535. MODULE_DESCRIPTION(FINTEK_DESCRIPTION " driver");
  536. MODULE_AUTHOR("Jarod Wilson <jarod@redhat.com>");
  537. MODULE_LICENSE("GPL");
  538. module_pnp_driver(fintek_driver);