tw9910.c 24 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * tw9910 Video Driver
  4. *
  5. * Copyright (C) 2017 Jacopo Mondi <jacopo+renesas@jmondi.org>
  6. *
  7. * Copyright (C) 2008 Renesas Solutions Corp.
  8. * Kuninori Morimoto <morimoto.kuninori@renesas.com>
  9. *
  10. * Based on ov772x driver,
  11. *
  12. * Copyright (C) 2008 Kuninori Morimoto <morimoto.kuninori@renesas.com>
  13. * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
  14. * Copyright (C) 2008 Magnus Damm
  15. * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
  16. */
  17. #include <linux/clk.h>
  18. #include <linux/delay.h>
  19. #include <linux/gpio/consumer.h>
  20. #include <linux/i2c.h>
  21. #include <linux/init.h>
  22. #include <linux/kernel.h>
  23. #include <linux/module.h>
  24. #include <linux/slab.h>
  25. #include <linux/v4l2-mediabus.h>
  26. #include <linux/videodev2.h>
  27. #include <media/i2c/tw9910.h>
  28. #include <media/v4l2-subdev.h>
  29. #define GET_ID(val) ((val & 0xF8) >> 3)
  30. #define GET_REV(val) (val & 0x07)
  31. /*
  32. * register offset
  33. */
  34. #define ID 0x00 /* Product ID Code Register */
  35. #define STATUS1 0x01 /* Chip Status Register I */
  36. #define INFORM 0x02 /* Input Format */
  37. #define OPFORM 0x03 /* Output Format Control Register */
  38. #define DLYCTR 0x04 /* Hysteresis and HSYNC Delay Control */
  39. #define OUTCTR1 0x05 /* Output Control I */
  40. #define ACNTL1 0x06 /* Analog Control Register 1 */
  41. #define CROP_HI 0x07 /* Cropping Register, High */
  42. #define VDELAY_LO 0x08 /* Vertical Delay Register, Low */
  43. #define VACTIVE_LO 0x09 /* Vertical Active Register, Low */
  44. #define HDELAY_LO 0x0A /* Horizontal Delay Register, Low */
  45. #define HACTIVE_LO 0x0B /* Horizontal Active Register, Low */
  46. #define CNTRL1 0x0C /* Control Register I */
  47. #define VSCALE_LO 0x0D /* Vertical Scaling Register, Low */
  48. #define SCALE_HI 0x0E /* Scaling Register, High */
  49. #define HSCALE_LO 0x0F /* Horizontal Scaling Register, Low */
  50. #define BRIGHT 0x10 /* BRIGHTNESS Control Register */
  51. #define CONTRAST 0x11 /* CONTRAST Control Register */
  52. #define SHARPNESS 0x12 /* SHARPNESS Control Register I */
  53. #define SAT_U 0x13 /* Chroma (U) Gain Register */
  54. #define SAT_V 0x14 /* Chroma (V) Gain Register */
  55. #define HUE 0x15 /* Hue Control Register */
  56. #define CORING1 0x17
  57. #define CORING2 0x18 /* Coring and IF compensation */
  58. #define VBICNTL 0x19 /* VBI Control Register */
  59. #define ACNTL2 0x1A /* Analog Control 2 */
  60. #define OUTCTR2 0x1B /* Output Control 2 */
  61. #define SDT 0x1C /* Standard Selection */
  62. #define SDTR 0x1D /* Standard Recognition */
  63. #define TEST 0x1F /* Test Control Register */
  64. #define CLMPG 0x20 /* Clamping Gain */
  65. #define IAGC 0x21 /* Individual AGC Gain */
  66. #define AGCGAIN 0x22 /* AGC Gain */
  67. #define PEAKWT 0x23 /* White Peak Threshold */
  68. #define CLMPL 0x24 /* Clamp level */
  69. #define SYNCT 0x25 /* Sync Amplitude */
  70. #define MISSCNT 0x26 /* Sync Miss Count Register */
  71. #define PCLAMP 0x27 /* Clamp Position Register */
  72. #define VCNTL1 0x28 /* Vertical Control I */
  73. #define VCNTL2 0x29 /* Vertical Control II */
  74. #define CKILL 0x2A /* Color Killer Level Control */
  75. #define COMB 0x2B /* Comb Filter Control */
  76. #define LDLY 0x2C /* Luma Delay and H Filter Control */
  77. #define MISC1 0x2D /* Miscellaneous Control I */
  78. #define LOOP 0x2E /* LOOP Control Register */
  79. #define MISC2 0x2F /* Miscellaneous Control II */
  80. #define MVSN 0x30 /* Macrovision Detection */
  81. #define STATUS2 0x31 /* Chip STATUS II */
  82. #define HFREF 0x32 /* H monitor */
  83. #define CLMD 0x33 /* CLAMP MODE */
  84. #define IDCNTL 0x34 /* ID Detection Control */
  85. #define CLCNTL1 0x35 /* Clamp Control I */
  86. #define ANAPLLCTL 0x4C
  87. #define VBIMIN 0x4D
  88. #define HSLOWCTL 0x4E
  89. #define WSS3 0x4F
  90. #define FILLDATA 0x50
  91. #define SDID 0x51
  92. #define DID 0x52
  93. #define WSS1 0x53
  94. #define WSS2 0x54
  95. #define VVBI 0x55
  96. #define LCTL6 0x56
  97. #define LCTL7 0x57
  98. #define LCTL8 0x58
  99. #define LCTL9 0x59
  100. #define LCTL10 0x5A
  101. #define LCTL11 0x5B
  102. #define LCTL12 0x5C
  103. #define LCTL13 0x5D
  104. #define LCTL14 0x5E
  105. #define LCTL15 0x5F
  106. #define LCTL16 0x60
  107. #define LCTL17 0x61
  108. #define LCTL18 0x62
  109. #define LCTL19 0x63
  110. #define LCTL20 0x64
  111. #define LCTL21 0x65
  112. #define LCTL22 0x66
  113. #define LCTL23 0x67
  114. #define LCTL24 0x68
  115. #define LCTL25 0x69
  116. #define LCTL26 0x6A
  117. #define HSBEGIN 0x6B
  118. #define HSEND 0x6C
  119. #define OVSDLY 0x6D
  120. #define OVSEND 0x6E
  121. #define VBIDELAY 0x6F
  122. /*
  123. * register detail
  124. */
  125. /* INFORM */
  126. #define FC27_ON 0x40 /* 1 : Input crystal clock frequency is 27MHz */
  127. #define FC27_FF 0x00 /* 0 : Square pixel mode. */
  128. /* Must use 24.54MHz for 60Hz field rate */
  129. /* source or 29.5MHz for 50Hz field rate */
  130. #define IFSEL_S 0x10 /* 01 : S-video decoding */
  131. #define IFSEL_C 0x00 /* 00 : Composite video decoding */
  132. /* Y input video selection */
  133. #define YSEL_M0 0x00 /* 00 : Mux0 selected */
  134. #define YSEL_M1 0x04 /* 01 : Mux1 selected */
  135. #define YSEL_M2 0x08 /* 10 : Mux2 selected */
  136. #define YSEL_M3 0x10 /* 11 : Mux3 selected */
  137. /* OPFORM */
  138. #define MODE 0x80 /* 0 : CCIR601 compatible YCrCb 4:2:2 format */
  139. /* 1 : ITU-R-656 compatible data sequence format */
  140. #define LEN 0x40 /* 0 : 8-bit YCrCb 4:2:2 output format */
  141. /* 1 : 16-bit YCrCb 4:2:2 output format.*/
  142. #define LLCMODE 0x20 /* 1 : LLC output mode. */
  143. /* 0 : free-run output mode */
  144. #define AINC 0x10 /* Serial interface auto-indexing control */
  145. /* 0 : auto-increment */
  146. /* 1 : non-auto */
  147. #define VSCTL 0x08 /* 1 : Vertical out ctrl by DVALID */
  148. /* 0 : Vertical out ctrl by HACTIVE and DVALID */
  149. #define OEN_TRI_SEL_MASK 0x07
  150. #define OEN_TRI_SEL_ALL_ON 0x00 /* Enable output for Rev0/Rev1 */
  151. #define OEN_TRI_SEL_ALL_OFF_r0 0x06 /* All tri-stated for Rev0 */
  152. #define OEN_TRI_SEL_ALL_OFF_r1 0x07 /* All tri-stated for Rev1 */
  153. /* OUTCTR1 */
  154. #define VSP_LO 0x00 /* 0 : VS pin output polarity is active low */
  155. #define VSP_HI 0x80 /* 1 : VS pin output polarity is active high. */
  156. /* VS pin output control */
  157. #define VSSL_VSYNC 0x00 /* 0 : VSYNC */
  158. #define VSSL_VACT 0x10 /* 1 : VACT */
  159. #define VSSL_FIELD 0x20 /* 2 : FIELD */
  160. #define VSSL_VVALID 0x30 /* 3 : VVALID */
  161. #define VSSL_ZERO 0x70 /* 7 : 0 */
  162. #define HSP_LOW 0x00 /* 0 : HS pin output polarity is active low */
  163. #define HSP_HI 0x08 /* 1 : HS pin output polarity is active high.*/
  164. /* HS pin output control */
  165. #define HSSL_HACT 0x00 /* 0 : HACT */
  166. #define HSSL_HSYNC 0x01 /* 1 : HSYNC */
  167. #define HSSL_DVALID 0x02 /* 2 : DVALID */
  168. #define HSSL_HLOCK 0x03 /* 3 : HLOCK */
  169. #define HSSL_ASYNCW 0x04 /* 4 : ASYNCW */
  170. #define HSSL_ZERO 0x07 /* 7 : 0 */
  171. /* ACNTL1 */
  172. #define SRESET 0x80 /* resets the device to its default state
  173. * but all register content remain unchanged.
  174. * This bit is self-resetting.
  175. */
  176. #define ACNTL1_PDN_MASK 0x0e
  177. #define CLK_PDN 0x08 /* system clock power down */
  178. #define Y_PDN 0x04 /* Luma ADC power down */
  179. #define C_PDN 0x02 /* Chroma ADC power down */
  180. /* ACNTL2 */
  181. #define ACNTL2_PDN_MASK 0x40
  182. #define PLL_PDN 0x40 /* PLL power down */
  183. /* VBICNTL */
  184. /* RTSEL : control the real time signal output from the MPOUT pin */
  185. #define RTSEL_MASK 0x07
  186. #define RTSEL_VLOSS 0x00 /* 0000 = Video loss */
  187. #define RTSEL_HLOCK 0x01 /* 0001 = H-lock */
  188. #define RTSEL_SLOCK 0x02 /* 0010 = S-lock */
  189. #define RTSEL_VLOCK 0x03 /* 0011 = V-lock */
  190. #define RTSEL_MONO 0x04 /* 0100 = MONO */
  191. #define RTSEL_DET50 0x05 /* 0101 = DET50 */
  192. #define RTSEL_FIELD 0x06 /* 0110 = FIELD */
  193. #define RTSEL_RTCO 0x07 /* 0111 = RTCO ( Real Time Control ) */
  194. /* HSYNC start and end are constant for now */
  195. #define HSYNC_START 0x0260
  196. #define HSYNC_END 0x0300
  197. /*
  198. * structure
  199. */
  200. struct regval_list {
  201. unsigned char reg_num;
  202. unsigned char value;
  203. };
  204. struct tw9910_scale_ctrl {
  205. char *name;
  206. unsigned short width;
  207. unsigned short height;
  208. u16 hscale;
  209. u16 vscale;
  210. };
  211. struct tw9910_priv {
  212. struct v4l2_subdev subdev;
  213. struct clk *clk;
  214. struct tw9910_video_info *info;
  215. struct gpio_desc *pdn_gpio;
  216. struct gpio_desc *rstb_gpio;
  217. const struct tw9910_scale_ctrl *scale;
  218. v4l2_std_id norm;
  219. u32 revision;
  220. };
  221. static const struct tw9910_scale_ctrl tw9910_ntsc_scales[] = {
  222. {
  223. .name = "NTSC SQ",
  224. .width = 640,
  225. .height = 480,
  226. .hscale = 0x0100,
  227. .vscale = 0x0100,
  228. },
  229. {
  230. .name = "NTSC CCIR601",
  231. .width = 720,
  232. .height = 480,
  233. .hscale = 0x0100,
  234. .vscale = 0x0100,
  235. },
  236. {
  237. .name = "NTSC SQ (CIF)",
  238. .width = 320,
  239. .height = 240,
  240. .hscale = 0x0200,
  241. .vscale = 0x0200,
  242. },
  243. {
  244. .name = "NTSC CCIR601 (CIF)",
  245. .width = 360,
  246. .height = 240,
  247. .hscale = 0x0200,
  248. .vscale = 0x0200,
  249. },
  250. {
  251. .name = "NTSC SQ (QCIF)",
  252. .width = 160,
  253. .height = 120,
  254. .hscale = 0x0400,
  255. .vscale = 0x0400,
  256. },
  257. {
  258. .name = "NTSC CCIR601 (QCIF)",
  259. .width = 180,
  260. .height = 120,
  261. .hscale = 0x0400,
  262. .vscale = 0x0400,
  263. },
  264. };
  265. static const struct tw9910_scale_ctrl tw9910_pal_scales[] = {
  266. {
  267. .name = "PAL SQ",
  268. .width = 768,
  269. .height = 576,
  270. .hscale = 0x0100,
  271. .vscale = 0x0100,
  272. },
  273. {
  274. .name = "PAL CCIR601",
  275. .width = 720,
  276. .height = 576,
  277. .hscale = 0x0100,
  278. .vscale = 0x0100,
  279. },
  280. {
  281. .name = "PAL SQ (CIF)",
  282. .width = 384,
  283. .height = 288,
  284. .hscale = 0x0200,
  285. .vscale = 0x0200,
  286. },
  287. {
  288. .name = "PAL CCIR601 (CIF)",
  289. .width = 360,
  290. .height = 288,
  291. .hscale = 0x0200,
  292. .vscale = 0x0200,
  293. },
  294. {
  295. .name = "PAL SQ (QCIF)",
  296. .width = 192,
  297. .height = 144,
  298. .hscale = 0x0400,
  299. .vscale = 0x0400,
  300. },
  301. {
  302. .name = "PAL CCIR601 (QCIF)",
  303. .width = 180,
  304. .height = 144,
  305. .hscale = 0x0400,
  306. .vscale = 0x0400,
  307. },
  308. };
  309. /*
  310. * general function
  311. */
  312. static struct tw9910_priv *to_tw9910(const struct i2c_client *client)
  313. {
  314. return container_of(i2c_get_clientdata(client), struct tw9910_priv,
  315. subdev);
  316. }
  317. static int tw9910_mask_set(struct i2c_client *client, u8 command,
  318. u8 mask, u8 set)
  319. {
  320. s32 val = i2c_smbus_read_byte_data(client, command);
  321. if (val < 0)
  322. return val;
  323. val &= ~mask;
  324. val |= set & mask;
  325. return i2c_smbus_write_byte_data(client, command, val);
  326. }
  327. static int tw9910_set_scale(struct i2c_client *client,
  328. const struct tw9910_scale_ctrl *scale)
  329. {
  330. int ret;
  331. ret = i2c_smbus_write_byte_data(client, SCALE_HI,
  332. (scale->vscale & 0x0F00) >> 4 |
  333. (scale->hscale & 0x0F00) >> 8);
  334. if (ret < 0)
  335. return ret;
  336. ret = i2c_smbus_write_byte_data(client, HSCALE_LO,
  337. scale->hscale & 0x00FF);
  338. if (ret < 0)
  339. return ret;
  340. ret = i2c_smbus_write_byte_data(client, VSCALE_LO,
  341. scale->vscale & 0x00FF);
  342. return ret;
  343. }
  344. static int tw9910_set_hsync(struct i2c_client *client)
  345. {
  346. struct tw9910_priv *priv = to_tw9910(client);
  347. int ret;
  348. /* bit 10 - 3 */
  349. ret = i2c_smbus_write_byte_data(client, HSBEGIN,
  350. (HSYNC_START & 0x07F8) >> 3);
  351. if (ret < 0)
  352. return ret;
  353. /* bit 10 - 3 */
  354. ret = i2c_smbus_write_byte_data(client, HSEND,
  355. (HSYNC_END & 0x07F8) >> 3);
  356. if (ret < 0)
  357. return ret;
  358. /* So far only revisions 0 and 1 have been seen. */
  359. /* bit 2 - 0 */
  360. if (priv->revision == 1)
  361. ret = tw9910_mask_set(client, HSLOWCTL, 0x77,
  362. (HSYNC_START & 0x0007) << 4 |
  363. (HSYNC_END & 0x0007));
  364. return ret;
  365. }
  366. static void tw9910_reset(struct i2c_client *client)
  367. {
  368. tw9910_mask_set(client, ACNTL1, SRESET, SRESET);
  369. usleep_range(1000, 5000);
  370. }
  371. static int tw9910_power(struct i2c_client *client, int enable)
  372. {
  373. int ret;
  374. u8 acntl1;
  375. u8 acntl2;
  376. if (enable) {
  377. acntl1 = 0;
  378. acntl2 = 0;
  379. } else {
  380. acntl1 = CLK_PDN | Y_PDN | C_PDN;
  381. acntl2 = PLL_PDN;
  382. }
  383. ret = tw9910_mask_set(client, ACNTL1, ACNTL1_PDN_MASK, acntl1);
  384. if (ret < 0)
  385. return ret;
  386. return tw9910_mask_set(client, ACNTL2, ACNTL2_PDN_MASK, acntl2);
  387. }
  388. static const struct tw9910_scale_ctrl *tw9910_select_norm(v4l2_std_id norm,
  389. u32 width, u32 height)
  390. {
  391. const struct tw9910_scale_ctrl *scale;
  392. const struct tw9910_scale_ctrl *ret = NULL;
  393. __u32 diff = 0xffffffff, tmp;
  394. int size, i;
  395. if (norm & V4L2_STD_NTSC) {
  396. scale = tw9910_ntsc_scales;
  397. size = ARRAY_SIZE(tw9910_ntsc_scales);
  398. } else if (norm & V4L2_STD_PAL) {
  399. scale = tw9910_pal_scales;
  400. size = ARRAY_SIZE(tw9910_pal_scales);
  401. } else {
  402. return NULL;
  403. }
  404. for (i = 0; i < size; i++) {
  405. tmp = abs(width - scale[i].width) +
  406. abs(height - scale[i].height);
  407. if (tmp < diff) {
  408. diff = tmp;
  409. ret = scale + i;
  410. }
  411. }
  412. return ret;
  413. }
  414. /*
  415. * subdevice operations
  416. */
  417. static int tw9910_s_stream(struct v4l2_subdev *sd, int enable)
  418. {
  419. struct i2c_client *client = v4l2_get_subdevdata(sd);
  420. struct tw9910_priv *priv = to_tw9910(client);
  421. u8 val;
  422. int ret;
  423. if (!enable) {
  424. switch (priv->revision) {
  425. case 0:
  426. val = OEN_TRI_SEL_ALL_OFF_r0;
  427. break;
  428. case 1:
  429. val = OEN_TRI_SEL_ALL_OFF_r1;
  430. break;
  431. default:
  432. dev_err(&client->dev, "un-supported revision\n");
  433. return -EINVAL;
  434. }
  435. } else {
  436. val = OEN_TRI_SEL_ALL_ON;
  437. if (!priv->scale) {
  438. dev_err(&client->dev, "norm select error\n");
  439. return -EPERM;
  440. }
  441. dev_dbg(&client->dev, "%s %dx%d\n",
  442. priv->scale->name,
  443. priv->scale->width,
  444. priv->scale->height);
  445. }
  446. ret = tw9910_mask_set(client, OPFORM, OEN_TRI_SEL_MASK, val);
  447. if (ret < 0)
  448. return ret;
  449. return tw9910_power(client, enable);
  450. }
  451. static int tw9910_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm)
  452. {
  453. struct i2c_client *client = v4l2_get_subdevdata(sd);
  454. struct tw9910_priv *priv = to_tw9910(client);
  455. *norm = priv->norm;
  456. return 0;
  457. }
  458. static int tw9910_s_std(struct v4l2_subdev *sd, v4l2_std_id norm)
  459. {
  460. struct i2c_client *client = v4l2_get_subdevdata(sd);
  461. struct tw9910_priv *priv = to_tw9910(client);
  462. const unsigned int hact = 720;
  463. const unsigned int hdelay = 15;
  464. unsigned int vact;
  465. unsigned int vdelay;
  466. int ret;
  467. if (!(norm & (V4L2_STD_NTSC | V4L2_STD_PAL)))
  468. return -EINVAL;
  469. priv->norm = norm;
  470. if (norm & V4L2_STD_525_60) {
  471. vact = 240;
  472. vdelay = 18;
  473. ret = tw9910_mask_set(client, VVBI, 0x10, 0x10);
  474. } else {
  475. vact = 288;
  476. vdelay = 24;
  477. ret = tw9910_mask_set(client, VVBI, 0x10, 0x00);
  478. }
  479. if (!ret)
  480. ret = i2c_smbus_write_byte_data(client, CROP_HI,
  481. ((vdelay >> 2) & 0xc0) |
  482. ((vact >> 4) & 0x30) |
  483. ((hdelay >> 6) & 0x0c) |
  484. ((hact >> 8) & 0x03));
  485. if (!ret)
  486. ret = i2c_smbus_write_byte_data(client, VDELAY_LO,
  487. vdelay & 0xff);
  488. if (!ret)
  489. ret = i2c_smbus_write_byte_data(client, VACTIVE_LO,
  490. vact & 0xff);
  491. return ret;
  492. }
  493. #ifdef CONFIG_VIDEO_ADV_DEBUG
  494. static int tw9910_g_register(struct v4l2_subdev *sd,
  495. struct v4l2_dbg_register *reg)
  496. {
  497. struct i2c_client *client = v4l2_get_subdevdata(sd);
  498. int ret;
  499. if (reg->reg > 0xff)
  500. return -EINVAL;
  501. reg->size = 1;
  502. ret = i2c_smbus_read_byte_data(client, reg->reg);
  503. if (ret < 0)
  504. return ret;
  505. /*
  506. * ret = int
  507. * reg->val = __u64
  508. */
  509. reg->val = (__u64)ret;
  510. return 0;
  511. }
  512. static int tw9910_s_register(struct v4l2_subdev *sd,
  513. const struct v4l2_dbg_register *reg)
  514. {
  515. struct i2c_client *client = v4l2_get_subdevdata(sd);
  516. if (reg->reg > 0xff ||
  517. reg->val > 0xff)
  518. return -EINVAL;
  519. return i2c_smbus_write_byte_data(client, reg->reg, reg->val);
  520. }
  521. #endif
  522. static void tw9910_set_gpio_value(struct gpio_desc *desc, int value)
  523. {
  524. if (desc) {
  525. gpiod_set_value(desc, value);
  526. usleep_range(500, 1000);
  527. }
  528. }
  529. static int tw9910_power_on(struct tw9910_priv *priv)
  530. {
  531. struct i2c_client *client = v4l2_get_subdevdata(&priv->subdev);
  532. int ret;
  533. if (priv->clk) {
  534. ret = clk_prepare_enable(priv->clk);
  535. if (ret)
  536. return ret;
  537. }
  538. tw9910_set_gpio_value(priv->pdn_gpio, 0);
  539. /*
  540. * FIXME: The reset signal is connected to a shared GPIO on some
  541. * platforms (namely the SuperH Migo-R). Until a framework becomes
  542. * available to handle this cleanly, request the GPIO temporarily
  543. * to avoid conflicts.
  544. */
  545. priv->rstb_gpio = gpiod_get_optional(&client->dev, "rstb",
  546. GPIOD_OUT_LOW);
  547. if (IS_ERR(priv->rstb_gpio)) {
  548. dev_info(&client->dev, "Unable to get GPIO \"rstb\"");
  549. clk_disable_unprepare(priv->clk);
  550. tw9910_set_gpio_value(priv->pdn_gpio, 1);
  551. return PTR_ERR(priv->rstb_gpio);
  552. }
  553. if (priv->rstb_gpio) {
  554. tw9910_set_gpio_value(priv->rstb_gpio, 1);
  555. tw9910_set_gpio_value(priv->rstb_gpio, 0);
  556. gpiod_put(priv->rstb_gpio);
  557. }
  558. return 0;
  559. }
  560. static int tw9910_power_off(struct tw9910_priv *priv)
  561. {
  562. clk_disable_unprepare(priv->clk);
  563. tw9910_set_gpio_value(priv->pdn_gpio, 1);
  564. return 0;
  565. }
  566. static int tw9910_s_power(struct v4l2_subdev *sd, int on)
  567. {
  568. struct i2c_client *client = v4l2_get_subdevdata(sd);
  569. struct tw9910_priv *priv = to_tw9910(client);
  570. return on ? tw9910_power_on(priv) : tw9910_power_off(priv);
  571. }
  572. static int tw9910_set_frame(struct v4l2_subdev *sd, u32 *width, u32 *height)
  573. {
  574. struct i2c_client *client = v4l2_get_subdevdata(sd);
  575. struct tw9910_priv *priv = to_tw9910(client);
  576. int ret = -EINVAL;
  577. u8 val;
  578. /* Select suitable norm. */
  579. priv->scale = tw9910_select_norm(priv->norm, *width, *height);
  580. if (!priv->scale)
  581. goto tw9910_set_fmt_error;
  582. /* Reset hardware. */
  583. tw9910_reset(client);
  584. /* Set bus width. */
  585. val = 0x00;
  586. if (priv->info->buswidth == 16)
  587. val = LEN;
  588. ret = tw9910_mask_set(client, OPFORM, LEN, val);
  589. if (ret < 0)
  590. goto tw9910_set_fmt_error;
  591. /* Select MPOUT behavior. */
  592. switch (priv->info->mpout) {
  593. case TW9910_MPO_VLOSS:
  594. val = RTSEL_VLOSS; break;
  595. case TW9910_MPO_HLOCK:
  596. val = RTSEL_HLOCK; break;
  597. case TW9910_MPO_SLOCK:
  598. val = RTSEL_SLOCK; break;
  599. case TW9910_MPO_VLOCK:
  600. val = RTSEL_VLOCK; break;
  601. case TW9910_MPO_MONO:
  602. val = RTSEL_MONO; break;
  603. case TW9910_MPO_DET50:
  604. val = RTSEL_DET50; break;
  605. case TW9910_MPO_FIELD:
  606. val = RTSEL_FIELD; break;
  607. case TW9910_MPO_RTCO:
  608. val = RTSEL_RTCO; break;
  609. default:
  610. val = 0;
  611. }
  612. ret = tw9910_mask_set(client, VBICNTL, RTSEL_MASK, val);
  613. if (ret < 0)
  614. goto tw9910_set_fmt_error;
  615. /* Set scale. */
  616. ret = tw9910_set_scale(client, priv->scale);
  617. if (ret < 0)
  618. goto tw9910_set_fmt_error;
  619. /* Set hsync. */
  620. ret = tw9910_set_hsync(client);
  621. if (ret < 0)
  622. goto tw9910_set_fmt_error;
  623. *width = priv->scale->width;
  624. *height = priv->scale->height;
  625. return ret;
  626. tw9910_set_fmt_error:
  627. tw9910_reset(client);
  628. priv->scale = NULL;
  629. return ret;
  630. }
  631. static int tw9910_get_selection(struct v4l2_subdev *sd,
  632. struct v4l2_subdev_pad_config *cfg,
  633. struct v4l2_subdev_selection *sel)
  634. {
  635. struct i2c_client *client = v4l2_get_subdevdata(sd);
  636. struct tw9910_priv *priv = to_tw9910(client);
  637. if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE)
  638. return -EINVAL;
  639. /* Only CROP, CROP_DEFAULT and CROP_BOUNDS are supported. */
  640. if (sel->target > V4L2_SEL_TGT_CROP_BOUNDS)
  641. return -EINVAL;
  642. sel->r.left = 0;
  643. sel->r.top = 0;
  644. if (priv->norm & V4L2_STD_NTSC) {
  645. sel->r.width = 640;
  646. sel->r.height = 480;
  647. } else {
  648. sel->r.width = 768;
  649. sel->r.height = 576;
  650. }
  651. return 0;
  652. }
  653. static int tw9910_get_fmt(struct v4l2_subdev *sd,
  654. struct v4l2_subdev_pad_config *cfg,
  655. struct v4l2_subdev_format *format)
  656. {
  657. struct v4l2_mbus_framefmt *mf = &format->format;
  658. struct i2c_client *client = v4l2_get_subdevdata(sd);
  659. struct tw9910_priv *priv = to_tw9910(client);
  660. if (format->pad)
  661. return -EINVAL;
  662. if (!priv->scale) {
  663. priv->scale = tw9910_select_norm(priv->norm, 640, 480);
  664. if (!priv->scale)
  665. return -EINVAL;
  666. }
  667. mf->width = priv->scale->width;
  668. mf->height = priv->scale->height;
  669. mf->code = MEDIA_BUS_FMT_UYVY8_2X8;
  670. mf->colorspace = V4L2_COLORSPACE_SMPTE170M;
  671. mf->field = V4L2_FIELD_INTERLACED_BT;
  672. return 0;
  673. }
  674. static int tw9910_s_fmt(struct v4l2_subdev *sd,
  675. struct v4l2_mbus_framefmt *mf)
  676. {
  677. u32 width = mf->width, height = mf->height;
  678. int ret;
  679. WARN_ON(mf->field != V4L2_FIELD_ANY &&
  680. mf->field != V4L2_FIELD_INTERLACED_BT);
  681. /* Check color format. */
  682. if (mf->code != MEDIA_BUS_FMT_UYVY8_2X8)
  683. return -EINVAL;
  684. mf->colorspace = V4L2_COLORSPACE_SMPTE170M;
  685. ret = tw9910_set_frame(sd, &width, &height);
  686. if (ret)
  687. return ret;
  688. mf->width = width;
  689. mf->height = height;
  690. return 0;
  691. }
  692. static int tw9910_set_fmt(struct v4l2_subdev *sd,
  693. struct v4l2_subdev_pad_config *cfg,
  694. struct v4l2_subdev_format *format)
  695. {
  696. struct v4l2_mbus_framefmt *mf = &format->format;
  697. struct i2c_client *client = v4l2_get_subdevdata(sd);
  698. struct tw9910_priv *priv = to_tw9910(client);
  699. const struct tw9910_scale_ctrl *scale;
  700. if (format->pad)
  701. return -EINVAL;
  702. if (mf->field == V4L2_FIELD_ANY) {
  703. mf->field = V4L2_FIELD_INTERLACED_BT;
  704. } else if (mf->field != V4L2_FIELD_INTERLACED_BT) {
  705. dev_err(&client->dev, "Field type %d invalid\n", mf->field);
  706. return -EINVAL;
  707. }
  708. mf->code = MEDIA_BUS_FMT_UYVY8_2X8;
  709. mf->colorspace = V4L2_COLORSPACE_SMPTE170M;
  710. /* Select suitable norm. */
  711. scale = tw9910_select_norm(priv->norm, mf->width, mf->height);
  712. if (!scale)
  713. return -EINVAL;
  714. mf->width = scale->width;
  715. mf->height = scale->height;
  716. if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE)
  717. return tw9910_s_fmt(sd, mf);
  718. cfg->try_fmt = *mf;
  719. return 0;
  720. }
  721. static int tw9910_video_probe(struct i2c_client *client)
  722. {
  723. struct tw9910_priv *priv = to_tw9910(client);
  724. s32 id;
  725. int ret;
  726. /* TW9910 only use 8 or 16 bit bus width. */
  727. if (priv->info->buswidth != 16 && priv->info->buswidth != 8) {
  728. dev_err(&client->dev, "bus width error\n");
  729. return -ENODEV;
  730. }
  731. ret = tw9910_s_power(&priv->subdev, 1);
  732. if (ret < 0)
  733. return ret;
  734. /*
  735. * Check and show Product ID.
  736. * So far only revisions 0 and 1 have been seen.
  737. */
  738. id = i2c_smbus_read_byte_data(client, ID);
  739. priv->revision = GET_REV(id);
  740. id = GET_ID(id);
  741. if (id != 0x0b || priv->revision > 0x01) {
  742. dev_err(&client->dev, "Product ID error %x:%x\n",
  743. id, priv->revision);
  744. ret = -ENODEV;
  745. goto done;
  746. }
  747. dev_info(&client->dev, "tw9910 Product ID %0x:%0x\n",
  748. id, priv->revision);
  749. priv->norm = V4L2_STD_NTSC;
  750. priv->scale = &tw9910_ntsc_scales[0];
  751. done:
  752. tw9910_s_power(&priv->subdev, 0);
  753. return ret;
  754. }
  755. static const struct v4l2_subdev_core_ops tw9910_subdev_core_ops = {
  756. #ifdef CONFIG_VIDEO_ADV_DEBUG
  757. .g_register = tw9910_g_register,
  758. .s_register = tw9910_s_register,
  759. #endif
  760. .s_power = tw9910_s_power,
  761. };
  762. static int tw9910_enum_mbus_code(struct v4l2_subdev *sd,
  763. struct v4l2_subdev_pad_config *cfg,
  764. struct v4l2_subdev_mbus_code_enum *code)
  765. {
  766. if (code->pad || code->index)
  767. return -EINVAL;
  768. code->code = MEDIA_BUS_FMT_UYVY8_2X8;
  769. return 0;
  770. }
  771. static int tw9910_g_tvnorms(struct v4l2_subdev *sd, v4l2_std_id *norm)
  772. {
  773. *norm = V4L2_STD_NTSC | V4L2_STD_PAL;
  774. return 0;
  775. }
  776. static const struct v4l2_subdev_video_ops tw9910_subdev_video_ops = {
  777. .s_std = tw9910_s_std,
  778. .g_std = tw9910_g_std,
  779. .s_stream = tw9910_s_stream,
  780. .g_tvnorms = tw9910_g_tvnorms,
  781. };
  782. static const struct v4l2_subdev_pad_ops tw9910_subdev_pad_ops = {
  783. .enum_mbus_code = tw9910_enum_mbus_code,
  784. .get_selection = tw9910_get_selection,
  785. .get_fmt = tw9910_get_fmt,
  786. .set_fmt = tw9910_set_fmt,
  787. };
  788. static const struct v4l2_subdev_ops tw9910_subdev_ops = {
  789. .core = &tw9910_subdev_core_ops,
  790. .video = &tw9910_subdev_video_ops,
  791. .pad = &tw9910_subdev_pad_ops,
  792. };
  793. /*
  794. * i2c_driver function
  795. */
  796. static int tw9910_probe(struct i2c_client *client,
  797. const struct i2c_device_id *did)
  798. {
  799. struct tw9910_priv *priv;
  800. struct tw9910_video_info *info;
  801. struct i2c_adapter *adapter = client->adapter;
  802. int ret;
  803. if (!client->dev.platform_data) {
  804. dev_err(&client->dev, "TW9910: missing platform data!\n");
  805. return -EINVAL;
  806. }
  807. info = client->dev.platform_data;
  808. if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) {
  809. dev_err(&client->dev,
  810. "I2C-Adapter doesn't support I2C_FUNC_SMBUS_BYTE_DATA\n");
  811. return -EIO;
  812. }
  813. priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL);
  814. if (!priv)
  815. return -ENOMEM;
  816. priv->info = info;
  817. v4l2_i2c_subdev_init(&priv->subdev, client, &tw9910_subdev_ops);
  818. priv->clk = clk_get(&client->dev, "xti");
  819. if (PTR_ERR(priv->clk) == -ENOENT) {
  820. priv->clk = NULL;
  821. } else if (IS_ERR(priv->clk)) {
  822. dev_err(&client->dev, "Unable to get xti clock\n");
  823. return PTR_ERR(priv->clk);
  824. }
  825. priv->pdn_gpio = gpiod_get_optional(&client->dev, "pdn",
  826. GPIOD_OUT_HIGH);
  827. if (IS_ERR(priv->pdn_gpio)) {
  828. dev_info(&client->dev, "Unable to get GPIO \"pdn\"");
  829. ret = PTR_ERR(priv->pdn_gpio);
  830. goto error_clk_put;
  831. }
  832. ret = tw9910_video_probe(client);
  833. if (ret < 0)
  834. goto error_gpio_put;
  835. ret = v4l2_async_register_subdev(&priv->subdev);
  836. if (ret)
  837. goto error_gpio_put;
  838. return ret;
  839. error_gpio_put:
  840. if (priv->pdn_gpio)
  841. gpiod_put(priv->pdn_gpio);
  842. error_clk_put:
  843. clk_put(priv->clk);
  844. return ret;
  845. }
  846. static int tw9910_remove(struct i2c_client *client)
  847. {
  848. struct tw9910_priv *priv = to_tw9910(client);
  849. if (priv->pdn_gpio)
  850. gpiod_put(priv->pdn_gpio);
  851. clk_put(priv->clk);
  852. v4l2_async_unregister_subdev(&priv->subdev);
  853. return 0;
  854. }
  855. static const struct i2c_device_id tw9910_id[] = {
  856. { "tw9910", 0 },
  857. { }
  858. };
  859. MODULE_DEVICE_TABLE(i2c, tw9910_id);
  860. static struct i2c_driver tw9910_i2c_driver = {
  861. .driver = {
  862. .name = "tw9910",
  863. },
  864. .probe = tw9910_probe,
  865. .remove = tw9910_remove,
  866. .id_table = tw9910_id,
  867. };
  868. module_i2c_driver(tw9910_i2c_driver);
  869. MODULE_DESCRIPTION("V4L2 driver for TW9910 video decoder");
  870. MODULE_AUTHOR("Kuninori Morimoto");
  871. MODULE_LICENSE("GPL v2");