tvp514x_regs.h 7.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * drivers/media/i2c/tvp514x_regs.h
  4. *
  5. * Copyright (C) 2008 Texas Instruments Inc
  6. * Author: Vaibhav Hiremath <hvaibhav@ti.com>
  7. *
  8. * Contributors:
  9. * Sivaraj R <sivaraj@ti.com>
  10. * Brijesh R Jadav <brijesh.j@ti.com>
  11. * Hardik Shah <hardik.shah@ti.com>
  12. * Manjunath Hadli <mrh@ti.com>
  13. * Karicheri Muralidharan <m-karicheri2@ti.com>
  14. */
  15. #ifndef _TVP514X_REGS_H
  16. #define _TVP514X_REGS_H
  17. /*
  18. * TVP5146/47 registers
  19. */
  20. #define REG_INPUT_SEL (0x00)
  21. #define REG_AFE_GAIN_CTRL (0x01)
  22. #define REG_VIDEO_STD (0x02)
  23. #define REG_OPERATION_MODE (0x03)
  24. #define REG_AUTOSWITCH_MASK (0x04)
  25. #define REG_COLOR_KILLER (0x05)
  26. #define REG_LUMA_CONTROL1 (0x06)
  27. #define REG_LUMA_CONTROL2 (0x07)
  28. #define REG_LUMA_CONTROL3 (0x08)
  29. #define REG_BRIGHTNESS (0x09)
  30. #define REG_CONTRAST (0x0A)
  31. #define REG_SATURATION (0x0B)
  32. #define REG_HUE (0x0C)
  33. #define REG_CHROMA_CONTROL1 (0x0D)
  34. #define REG_CHROMA_CONTROL2 (0x0E)
  35. /* 0x0F Reserved */
  36. #define REG_COMP_PR_SATURATION (0x10)
  37. #define REG_COMP_Y_CONTRAST (0x11)
  38. #define REG_COMP_PB_SATURATION (0x12)
  39. /* 0x13 Reserved */
  40. #define REG_COMP_Y_BRIGHTNESS (0x14)
  41. /* 0x15 Reserved */
  42. #define REG_AVID_START_PIXEL_LSB (0x16)
  43. #define REG_AVID_START_PIXEL_MSB (0x17)
  44. #define REG_AVID_STOP_PIXEL_LSB (0x18)
  45. #define REG_AVID_STOP_PIXEL_MSB (0x19)
  46. #define REG_HSYNC_START_PIXEL_LSB (0x1A)
  47. #define REG_HSYNC_START_PIXEL_MSB (0x1B)
  48. #define REG_HSYNC_STOP_PIXEL_LSB (0x1C)
  49. #define REG_HSYNC_STOP_PIXEL_MSB (0x1D)
  50. #define REG_VSYNC_START_LINE_LSB (0x1E)
  51. #define REG_VSYNC_START_LINE_MSB (0x1F)
  52. #define REG_VSYNC_STOP_LINE_LSB (0x20)
  53. #define REG_VSYNC_STOP_LINE_MSB (0x21)
  54. #define REG_VBLK_START_LINE_LSB (0x22)
  55. #define REG_VBLK_START_LINE_MSB (0x23)
  56. #define REG_VBLK_STOP_LINE_LSB (0x24)
  57. #define REG_VBLK_STOP_LINE_MSB (0x25)
  58. /* 0x26 - 0x27 Reserved */
  59. #define REG_FAST_SWTICH_CONTROL (0x28)
  60. /* 0x29 Reserved */
  61. #define REG_FAST_SWTICH_SCART_DELAY (0x2A)
  62. /* 0x2B Reserved */
  63. #define REG_SCART_DELAY (0x2C)
  64. #define REG_CTI_DELAY (0x2D)
  65. #define REG_CTI_CONTROL (0x2E)
  66. /* 0x2F - 0x31 Reserved */
  67. #define REG_SYNC_CONTROL (0x32)
  68. #define REG_OUTPUT_FORMATTER1 (0x33)
  69. #define REG_OUTPUT_FORMATTER2 (0x34)
  70. #define REG_OUTPUT_FORMATTER3 (0x35)
  71. #define REG_OUTPUT_FORMATTER4 (0x36)
  72. #define REG_OUTPUT_FORMATTER5 (0x37)
  73. #define REG_OUTPUT_FORMATTER6 (0x38)
  74. #define REG_CLEAR_LOST_LOCK (0x39)
  75. #define REG_STATUS1 (0x3A)
  76. #define REG_STATUS2 (0x3B)
  77. #define REG_AGC_GAIN_STATUS_LSB (0x3C)
  78. #define REG_AGC_GAIN_STATUS_MSB (0x3D)
  79. /* 0x3E Reserved */
  80. #define REG_VIDEO_STD_STATUS (0x3F)
  81. #define REG_GPIO_INPUT1 (0x40)
  82. #define REG_GPIO_INPUT2 (0x41)
  83. /* 0x42 - 0x45 Reserved */
  84. #define REG_AFE_COARSE_GAIN_CH1 (0x46)
  85. #define REG_AFE_COARSE_GAIN_CH2 (0x47)
  86. #define REG_AFE_COARSE_GAIN_CH3 (0x48)
  87. #define REG_AFE_COARSE_GAIN_CH4 (0x49)
  88. #define REG_AFE_FINE_GAIN_PB_B_LSB (0x4A)
  89. #define REG_AFE_FINE_GAIN_PB_B_MSB (0x4B)
  90. #define REG_AFE_FINE_GAIN_Y_G_CHROMA_LSB (0x4C)
  91. #define REG_AFE_FINE_GAIN_Y_G_CHROMA_MSB (0x4D)
  92. #define REG_AFE_FINE_GAIN_PR_R_LSB (0x4E)
  93. #define REG_AFE_FINE_GAIN_PR_R_MSB (0x4F)
  94. #define REG_AFE_FINE_GAIN_CVBS_LUMA_LSB (0x50)
  95. #define REG_AFE_FINE_GAIN_CVBS_LUMA_MSB (0x51)
  96. /* 0x52 - 0x68 Reserved */
  97. #define REG_FBIT_VBIT_CONTROL1 (0x69)
  98. /* 0x6A - 0x6B Reserved */
  99. #define REG_BACKEND_AGC_CONTROL (0x6C)
  100. /* 0x6D - 0x6E Reserved */
  101. #define REG_AGC_DECREMENT_SPEED_CONTROL (0x6F)
  102. #define REG_ROM_VERSION (0x70)
  103. /* 0x71 - 0x73 Reserved */
  104. #define REG_AGC_WHITE_PEAK_PROCESSING (0x74)
  105. #define REG_FBIT_VBIT_CONTROL2 (0x75)
  106. #define REG_VCR_TRICK_MODE_CONTROL (0x76)
  107. #define REG_HORIZONTAL_SHAKE_INCREMENT (0x77)
  108. #define REG_AGC_INCREMENT_SPEED (0x78)
  109. #define REG_AGC_INCREMENT_DELAY (0x79)
  110. /* 0x7A - 0x7F Reserved */
  111. #define REG_CHIP_ID_MSB (0x80)
  112. #define REG_CHIP_ID_LSB (0x81)
  113. /* 0x82 Reserved */
  114. #define REG_CPLL_SPEED_CONTROL (0x83)
  115. /* 0x84 - 0x96 Reserved */
  116. #define REG_STATUS_REQUEST (0x97)
  117. /* 0x98 - 0x99 Reserved */
  118. #define REG_VERTICAL_LINE_COUNT_LSB (0x9A)
  119. #define REG_VERTICAL_LINE_COUNT_MSB (0x9B)
  120. /* 0x9C - 0x9D Reserved */
  121. #define REG_AGC_DECREMENT_DELAY (0x9E)
  122. /* 0x9F - 0xB0 Reserved */
  123. #define REG_VDP_TTX_FILTER_1_MASK1 (0xB1)
  124. #define REG_VDP_TTX_FILTER_1_MASK2 (0xB2)
  125. #define REG_VDP_TTX_FILTER_1_MASK3 (0xB3)
  126. #define REG_VDP_TTX_FILTER_1_MASK4 (0xB4)
  127. #define REG_VDP_TTX_FILTER_1_MASK5 (0xB5)
  128. #define REG_VDP_TTX_FILTER_2_MASK1 (0xB6)
  129. #define REG_VDP_TTX_FILTER_2_MASK2 (0xB7)
  130. #define REG_VDP_TTX_FILTER_2_MASK3 (0xB8)
  131. #define REG_VDP_TTX_FILTER_2_MASK4 (0xB9)
  132. #define REG_VDP_TTX_FILTER_2_MASK5 (0xBA)
  133. #define REG_VDP_TTX_FILTER_CONTROL (0xBB)
  134. #define REG_VDP_FIFO_WORD_COUNT (0xBC)
  135. #define REG_VDP_FIFO_INTERRUPT_THRLD (0xBD)
  136. /* 0xBE Reserved */
  137. #define REG_VDP_FIFO_RESET (0xBF)
  138. #define REG_VDP_FIFO_OUTPUT_CONTROL (0xC0)
  139. #define REG_VDP_LINE_NUMBER_INTERRUPT (0xC1)
  140. #define REG_VDP_PIXEL_ALIGNMENT_LSB (0xC2)
  141. #define REG_VDP_PIXEL_ALIGNMENT_MSB (0xC3)
  142. /* 0xC4 - 0xD5 Reserved */
  143. #define REG_VDP_LINE_START (0xD6)
  144. #define REG_VDP_LINE_STOP (0xD7)
  145. #define REG_VDP_GLOBAL_LINE_MODE (0xD8)
  146. #define REG_VDP_FULL_FIELD_ENABLE (0xD9)
  147. #define REG_VDP_FULL_FIELD_MODE (0xDA)
  148. /* 0xDB - 0xDF Reserved */
  149. #define REG_VBUS_DATA_ACCESS_NO_VBUS_ADDR_INCR (0xE0)
  150. #define REG_VBUS_DATA_ACCESS_VBUS_ADDR_INCR (0xE1)
  151. #define REG_FIFO_READ_DATA (0xE2)
  152. /* 0xE3 - 0xE7 Reserved */
  153. #define REG_VBUS_ADDRESS_ACCESS1 (0xE8)
  154. #define REG_VBUS_ADDRESS_ACCESS2 (0xE9)
  155. #define REG_VBUS_ADDRESS_ACCESS3 (0xEA)
  156. /* 0xEB - 0xEF Reserved */
  157. #define REG_INTERRUPT_RAW_STATUS0 (0xF0)
  158. #define REG_INTERRUPT_RAW_STATUS1 (0xF1)
  159. #define REG_INTERRUPT_STATUS0 (0xF2)
  160. #define REG_INTERRUPT_STATUS1 (0xF3)
  161. #define REG_INTERRUPT_MASK0 (0xF4)
  162. #define REG_INTERRUPT_MASK1 (0xF5)
  163. #define REG_INTERRUPT_CLEAR0 (0xF6)
  164. #define REG_INTERRUPT_CLEAR1 (0xF7)
  165. /* 0xF8 - 0xFF Reserved */
  166. /*
  167. * Mask and bit definitions of TVP5146/47 registers
  168. */
  169. /* The ID values we are looking for */
  170. #define TVP514X_CHIP_ID_MSB (0x51)
  171. #define TVP5146_CHIP_ID_LSB (0x46)
  172. #define TVP5147_CHIP_ID_LSB (0x47)
  173. #define VIDEO_STD_MASK (0x07)
  174. #define VIDEO_STD_AUTO_SWITCH_BIT (0x00)
  175. #define VIDEO_STD_NTSC_MJ_BIT (0x01)
  176. #define VIDEO_STD_PAL_BDGHIN_BIT (0x02)
  177. #define VIDEO_STD_PAL_M_BIT (0x03)
  178. #define VIDEO_STD_PAL_COMBINATION_N_BIT (0x04)
  179. #define VIDEO_STD_NTSC_4_43_BIT (0x05)
  180. #define VIDEO_STD_SECAM_BIT (0x06)
  181. #define VIDEO_STD_PAL_60_BIT (0x07)
  182. /*
  183. * Status bit
  184. */
  185. #define STATUS_TV_VCR_BIT (1<<0)
  186. #define STATUS_HORZ_SYNC_LOCK_BIT (1<<1)
  187. #define STATUS_VIRT_SYNC_LOCK_BIT (1<<2)
  188. #define STATUS_CLR_SUBCAR_LOCK_BIT (1<<3)
  189. #define STATUS_LOST_LOCK_DETECT_BIT (1<<4)
  190. #define STATUS_FEILD_RATE_BIT (1<<5)
  191. #define STATUS_LINE_ALTERNATING_BIT (1<<6)
  192. #define STATUS_PEAK_WHITE_DETECT_BIT (1<<7)
  193. /* Tokens for register write */
  194. #define TOK_WRITE (0) /* token for write operation */
  195. #define TOK_TERM (1) /* terminating token */
  196. #define TOK_DELAY (2) /* delay token for reg list */
  197. #define TOK_SKIP (3) /* token to skip a register */
  198. /**
  199. * struct tvp514x_reg - Structure for TVP5146/47 register initialization values
  200. * @token - Token: TOK_WRITE, TOK_TERM etc..
  201. * @reg - Register offset
  202. * @val - Register Value for TOK_WRITE or delay in ms for TOK_DELAY
  203. */
  204. struct tvp514x_reg {
  205. u8 token;
  206. u8 reg;
  207. u32 val;
  208. };
  209. #endif /* ifndef _TVP514X_REGS_H */