st-mipid02.c 27 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Driver for ST MIPID02 CSI-2 to PARALLEL bridge
  4. *
  5. * Copyright (C) STMicroelectronics SA 2019
  6. * Authors: Mickael Guene <mickael.guene@st.com>
  7. * for STMicroelectronics.
  8. *
  9. *
  10. */
  11. #include <linux/clk.h>
  12. #include <linux/delay.h>
  13. #include <linux/gpio/consumer.h>
  14. #include <linux/i2c.h>
  15. #include <linux/module.h>
  16. #include <linux/of_graph.h>
  17. #include <linux/regulator/consumer.h>
  18. #include <media/v4l2-async.h>
  19. #include <media/v4l2-ctrls.h>
  20. #include <media/v4l2-device.h>
  21. #include <media/v4l2-fwnode.h>
  22. #include <media/v4l2-subdev.h>
  23. #define MIPID02_CLK_LANE_WR_REG1 0x01
  24. #define MIPID02_CLK_LANE_REG1 0x02
  25. #define MIPID02_CLK_LANE_REG3 0x04
  26. #define MIPID02_DATA_LANE0_REG1 0x05
  27. #define MIPID02_DATA_LANE0_REG2 0x06
  28. #define MIPID02_DATA_LANE1_REG1 0x09
  29. #define MIPID02_DATA_LANE1_REG2 0x0a
  30. #define MIPID02_MODE_REG1 0x14
  31. #define MIPID02_MODE_REG2 0x15
  32. #define MIPID02_DATA_ID_RREG 0x17
  33. #define MIPID02_DATA_SELECTION_CTRL 0x19
  34. #define MIPID02_PIX_WIDTH_CTRL 0x1e
  35. #define MIPID02_PIX_WIDTH_CTRL_EMB 0x1f
  36. /* Bits definition for MIPID02_CLK_LANE_REG1 */
  37. #define CLK_ENABLE BIT(0)
  38. /* Bits definition for MIPID02_CLK_LANE_REG3 */
  39. #define CLK_MIPI_CSI BIT(1)
  40. /* Bits definition for MIPID02_DATA_LANE0_REG1 */
  41. #define DATA_ENABLE BIT(0)
  42. /* Bits definition for MIPID02_DATA_LANEx_REG2 */
  43. #define DATA_MIPI_CSI BIT(0)
  44. /* Bits definition for MIPID02_MODE_REG1 */
  45. #define MODE_DATA_SWAP BIT(2)
  46. #define MODE_NO_BYPASS BIT(6)
  47. /* Bits definition for MIPID02_MODE_REG2 */
  48. #define MODE_HSYNC_ACTIVE_HIGH BIT(1)
  49. #define MODE_VSYNC_ACTIVE_HIGH BIT(2)
  50. /* Bits definition for MIPID02_DATA_SELECTION_CTRL */
  51. #define SELECTION_MANUAL_DATA BIT(2)
  52. #define SELECTION_MANUAL_WIDTH BIT(3)
  53. static const u32 mipid02_supported_fmt_codes[] = {
  54. MEDIA_BUS_FMT_SBGGR8_1X8, MEDIA_BUS_FMT_SGBRG8_1X8,
  55. MEDIA_BUS_FMT_SGRBG8_1X8, MEDIA_BUS_FMT_SRGGB8_1X8,
  56. MEDIA_BUS_FMT_SBGGR10_1X10, MEDIA_BUS_FMT_SGBRG10_1X10,
  57. MEDIA_BUS_FMT_SGRBG10_1X10, MEDIA_BUS_FMT_SRGGB10_1X10,
  58. MEDIA_BUS_FMT_SBGGR12_1X12, MEDIA_BUS_FMT_SGBRG12_1X12,
  59. MEDIA_BUS_FMT_SGRBG12_1X12, MEDIA_BUS_FMT_SRGGB12_1X12,
  60. MEDIA_BUS_FMT_UYVY8_1X16, MEDIA_BUS_FMT_BGR888_1X24,
  61. MEDIA_BUS_FMT_RGB565_2X8_LE, MEDIA_BUS_FMT_RGB565_2X8_BE,
  62. MEDIA_BUS_FMT_YUYV8_2X8, MEDIA_BUS_FMT_UYVY8_2X8,
  63. MEDIA_BUS_FMT_JPEG_1X8
  64. };
  65. /* regulator supplies */
  66. static const char * const mipid02_supply_name[] = {
  67. "VDDE", /* 1.8V digital I/O supply */
  68. "VDDIN", /* 1V8 voltage regulator supply */
  69. };
  70. #define MIPID02_NUM_SUPPLIES ARRAY_SIZE(mipid02_supply_name)
  71. #define MIPID02_SINK_0 0
  72. #define MIPID02_SINK_1 1
  73. #define MIPID02_SOURCE 2
  74. #define MIPID02_PAD_NB 3
  75. struct mipid02_dev {
  76. struct i2c_client *i2c_client;
  77. struct regulator_bulk_data supplies[MIPID02_NUM_SUPPLIES];
  78. struct v4l2_subdev sd;
  79. struct media_pad pad[MIPID02_PAD_NB];
  80. struct clk *xclk;
  81. struct gpio_desc *reset_gpio;
  82. /* endpoints info */
  83. struct v4l2_fwnode_endpoint rx;
  84. u64 link_frequency;
  85. struct v4l2_fwnode_endpoint tx;
  86. /* remote source */
  87. struct v4l2_async_subdev asd;
  88. struct v4l2_async_notifier notifier;
  89. struct v4l2_subdev *s_subdev;
  90. /* registers */
  91. struct {
  92. u8 clk_lane_reg1;
  93. u8 data_lane0_reg1;
  94. u8 data_lane1_reg1;
  95. u8 mode_reg1;
  96. u8 mode_reg2;
  97. u8 data_selection_ctrl;
  98. u8 data_id_rreg;
  99. u8 pix_width_ctrl;
  100. u8 pix_width_ctrl_emb;
  101. } r;
  102. /* lock to protect all members below */
  103. struct mutex lock;
  104. bool streaming;
  105. struct v4l2_mbus_framefmt fmt;
  106. };
  107. static int bpp_from_code(__u32 code)
  108. {
  109. switch (code) {
  110. case MEDIA_BUS_FMT_SBGGR8_1X8:
  111. case MEDIA_BUS_FMT_SGBRG8_1X8:
  112. case MEDIA_BUS_FMT_SGRBG8_1X8:
  113. case MEDIA_BUS_FMT_SRGGB8_1X8:
  114. return 8;
  115. case MEDIA_BUS_FMT_SBGGR10_1X10:
  116. case MEDIA_BUS_FMT_SGBRG10_1X10:
  117. case MEDIA_BUS_FMT_SGRBG10_1X10:
  118. case MEDIA_BUS_FMT_SRGGB10_1X10:
  119. return 10;
  120. case MEDIA_BUS_FMT_SBGGR12_1X12:
  121. case MEDIA_BUS_FMT_SGBRG12_1X12:
  122. case MEDIA_BUS_FMT_SGRBG12_1X12:
  123. case MEDIA_BUS_FMT_SRGGB12_1X12:
  124. return 12;
  125. case MEDIA_BUS_FMT_UYVY8_1X16:
  126. case MEDIA_BUS_FMT_YUYV8_2X8:
  127. case MEDIA_BUS_FMT_UYVY8_2X8:
  128. case MEDIA_BUS_FMT_RGB565_2X8_LE:
  129. case MEDIA_BUS_FMT_RGB565_2X8_BE:
  130. return 16;
  131. case MEDIA_BUS_FMT_BGR888_1X24:
  132. return 24;
  133. default:
  134. return 0;
  135. }
  136. }
  137. static u8 data_type_from_code(__u32 code)
  138. {
  139. switch (code) {
  140. case MEDIA_BUS_FMT_SBGGR8_1X8:
  141. case MEDIA_BUS_FMT_SGBRG8_1X8:
  142. case MEDIA_BUS_FMT_SGRBG8_1X8:
  143. case MEDIA_BUS_FMT_SRGGB8_1X8:
  144. return 0x2a;
  145. case MEDIA_BUS_FMT_SBGGR10_1X10:
  146. case MEDIA_BUS_FMT_SGBRG10_1X10:
  147. case MEDIA_BUS_FMT_SGRBG10_1X10:
  148. case MEDIA_BUS_FMT_SRGGB10_1X10:
  149. return 0x2b;
  150. case MEDIA_BUS_FMT_SBGGR12_1X12:
  151. case MEDIA_BUS_FMT_SGBRG12_1X12:
  152. case MEDIA_BUS_FMT_SGRBG12_1X12:
  153. case MEDIA_BUS_FMT_SRGGB12_1X12:
  154. return 0x2c;
  155. case MEDIA_BUS_FMT_UYVY8_1X16:
  156. case MEDIA_BUS_FMT_YUYV8_2X8:
  157. case MEDIA_BUS_FMT_UYVY8_2X8:
  158. return 0x1e;
  159. case MEDIA_BUS_FMT_BGR888_1X24:
  160. return 0x24;
  161. case MEDIA_BUS_FMT_RGB565_2X8_LE:
  162. case MEDIA_BUS_FMT_RGB565_2X8_BE:
  163. return 0x22;
  164. default:
  165. return 0;
  166. }
  167. }
  168. static void init_format(struct v4l2_mbus_framefmt *fmt)
  169. {
  170. fmt->code = MEDIA_BUS_FMT_SBGGR8_1X8;
  171. fmt->field = V4L2_FIELD_NONE;
  172. fmt->colorspace = V4L2_COLORSPACE_SRGB;
  173. fmt->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(V4L2_COLORSPACE_SRGB);
  174. fmt->quantization = V4L2_QUANTIZATION_FULL_RANGE;
  175. fmt->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(V4L2_COLORSPACE_SRGB);
  176. fmt->width = 640;
  177. fmt->height = 480;
  178. }
  179. static __u32 get_fmt_code(__u32 code)
  180. {
  181. unsigned int i;
  182. for (i = 0; i < ARRAY_SIZE(mipid02_supported_fmt_codes); i++) {
  183. if (code == mipid02_supported_fmt_codes[i])
  184. return code;
  185. }
  186. return mipid02_supported_fmt_codes[0];
  187. }
  188. static __u32 serial_to_parallel_code(__u32 serial)
  189. {
  190. if (serial == MEDIA_BUS_FMT_UYVY8_1X16)
  191. return MEDIA_BUS_FMT_UYVY8_2X8;
  192. if (serial == MEDIA_BUS_FMT_BGR888_1X24)
  193. return MEDIA_BUS_FMT_BGR888_3X8;
  194. return serial;
  195. }
  196. static inline struct mipid02_dev *to_mipid02_dev(struct v4l2_subdev *sd)
  197. {
  198. return container_of(sd, struct mipid02_dev, sd);
  199. }
  200. static int mipid02_read_reg(struct mipid02_dev *bridge, u16 reg, u8 *val)
  201. {
  202. struct i2c_client *client = bridge->i2c_client;
  203. struct i2c_msg msg[2];
  204. u8 buf[2];
  205. int ret;
  206. buf[0] = reg >> 8;
  207. buf[1] = reg & 0xff;
  208. msg[0].addr = client->addr;
  209. msg[0].flags = client->flags;
  210. msg[0].buf = buf;
  211. msg[0].len = sizeof(buf);
  212. msg[1].addr = client->addr;
  213. msg[1].flags = client->flags | I2C_M_RD;
  214. msg[1].buf = val;
  215. msg[1].len = 1;
  216. ret = i2c_transfer(client->adapter, msg, 2);
  217. if (ret < 0) {
  218. dev_dbg(&client->dev, "%s: %x i2c_transfer, reg: %x => %d\n",
  219. __func__, client->addr, reg, ret);
  220. return ret;
  221. }
  222. return 0;
  223. }
  224. static int mipid02_write_reg(struct mipid02_dev *bridge, u16 reg, u8 val)
  225. {
  226. struct i2c_client *client = bridge->i2c_client;
  227. struct i2c_msg msg;
  228. u8 buf[3];
  229. int ret;
  230. buf[0] = reg >> 8;
  231. buf[1] = reg & 0xff;
  232. buf[2] = val;
  233. msg.addr = client->addr;
  234. msg.flags = client->flags;
  235. msg.buf = buf;
  236. msg.len = sizeof(buf);
  237. ret = i2c_transfer(client->adapter, &msg, 1);
  238. if (ret < 0) {
  239. dev_dbg(&client->dev, "%s: i2c_transfer, reg: %x => %d\n",
  240. __func__, reg, ret);
  241. return ret;
  242. }
  243. return 0;
  244. }
  245. static int mipid02_get_regulators(struct mipid02_dev *bridge)
  246. {
  247. unsigned int i;
  248. for (i = 0; i < MIPID02_NUM_SUPPLIES; i++)
  249. bridge->supplies[i].supply = mipid02_supply_name[i];
  250. return devm_regulator_bulk_get(&bridge->i2c_client->dev,
  251. MIPID02_NUM_SUPPLIES,
  252. bridge->supplies);
  253. }
  254. static void mipid02_apply_reset(struct mipid02_dev *bridge)
  255. {
  256. gpiod_set_value_cansleep(bridge->reset_gpio, 0);
  257. usleep_range(5000, 10000);
  258. gpiod_set_value_cansleep(bridge->reset_gpio, 1);
  259. usleep_range(5000, 10000);
  260. gpiod_set_value_cansleep(bridge->reset_gpio, 0);
  261. usleep_range(5000, 10000);
  262. }
  263. static int mipid02_set_power_on(struct mipid02_dev *bridge)
  264. {
  265. struct i2c_client *client = bridge->i2c_client;
  266. int ret;
  267. ret = clk_prepare_enable(bridge->xclk);
  268. if (ret) {
  269. dev_err(&client->dev, "%s: failed to enable clock\n", __func__);
  270. return ret;
  271. }
  272. ret = regulator_bulk_enable(MIPID02_NUM_SUPPLIES,
  273. bridge->supplies);
  274. if (ret) {
  275. dev_err(&client->dev, "%s: failed to enable regulators\n",
  276. __func__);
  277. goto xclk_off;
  278. }
  279. if (bridge->reset_gpio) {
  280. dev_dbg(&client->dev, "apply reset");
  281. mipid02_apply_reset(bridge);
  282. } else {
  283. dev_dbg(&client->dev, "don't apply reset");
  284. usleep_range(5000, 10000);
  285. }
  286. return 0;
  287. xclk_off:
  288. clk_disable_unprepare(bridge->xclk);
  289. return ret;
  290. }
  291. static void mipid02_set_power_off(struct mipid02_dev *bridge)
  292. {
  293. regulator_bulk_disable(MIPID02_NUM_SUPPLIES, bridge->supplies);
  294. clk_disable_unprepare(bridge->xclk);
  295. }
  296. static int mipid02_detect(struct mipid02_dev *bridge)
  297. {
  298. u8 reg;
  299. /*
  300. * There is no version registers. Just try to read register
  301. * MIPID02_CLK_LANE_WR_REG1.
  302. */
  303. return mipid02_read_reg(bridge, MIPID02_CLK_LANE_WR_REG1, &reg);
  304. }
  305. static u32 mipid02_get_link_freq_from_cid_link_freq(struct mipid02_dev *bridge,
  306. struct v4l2_subdev *subdev)
  307. {
  308. struct v4l2_querymenu qm = {.id = V4L2_CID_LINK_FREQ, };
  309. struct v4l2_ctrl *ctrl;
  310. int ret;
  311. ctrl = v4l2_ctrl_find(subdev->ctrl_handler, V4L2_CID_LINK_FREQ);
  312. if (!ctrl)
  313. return 0;
  314. qm.index = v4l2_ctrl_g_ctrl(ctrl);
  315. ret = v4l2_querymenu(subdev->ctrl_handler, &qm);
  316. if (ret)
  317. return 0;
  318. return qm.value;
  319. }
  320. static u32 mipid02_get_link_freq_from_cid_pixel_rate(struct mipid02_dev *bridge,
  321. struct v4l2_subdev *subdev)
  322. {
  323. struct v4l2_fwnode_endpoint *ep = &bridge->rx;
  324. struct v4l2_ctrl *ctrl;
  325. u32 pixel_clock;
  326. u32 bpp = bpp_from_code(bridge->fmt.code);
  327. ctrl = v4l2_ctrl_find(subdev->ctrl_handler, V4L2_CID_PIXEL_RATE);
  328. if (!ctrl)
  329. return 0;
  330. pixel_clock = v4l2_ctrl_g_ctrl_int64(ctrl);
  331. return pixel_clock * bpp / (2 * ep->bus.mipi_csi2.num_data_lanes);
  332. }
  333. /*
  334. * We need to know link frequency to setup clk_lane_reg1 timings. Link frequency
  335. * will be computed using connected device V4L2_CID_PIXEL_RATE, bit per pixel
  336. * and number of lanes.
  337. */
  338. static int mipid02_configure_from_rx_speed(struct mipid02_dev *bridge)
  339. {
  340. struct i2c_client *client = bridge->i2c_client;
  341. struct v4l2_subdev *subdev = bridge->s_subdev;
  342. u32 link_freq;
  343. link_freq = mipid02_get_link_freq_from_cid_link_freq(bridge, subdev);
  344. if (!link_freq) {
  345. link_freq = mipid02_get_link_freq_from_cid_pixel_rate(bridge,
  346. subdev);
  347. if (!link_freq) {
  348. dev_err(&client->dev, "Failed to get link frequency");
  349. return -EINVAL;
  350. }
  351. }
  352. dev_dbg(&client->dev, "detect link_freq = %d Hz", link_freq);
  353. bridge->r.clk_lane_reg1 |= (2000000000 / link_freq) << 2;
  354. return 0;
  355. }
  356. static int mipid02_configure_clk_lane(struct mipid02_dev *bridge)
  357. {
  358. struct i2c_client *client = bridge->i2c_client;
  359. struct v4l2_fwnode_endpoint *ep = &bridge->rx;
  360. bool *polarities = ep->bus.mipi_csi2.lane_polarities;
  361. /* midid02 doesn't support clock lane remapping */
  362. if (ep->bus.mipi_csi2.clock_lane != 0) {
  363. dev_err(&client->dev, "clk lane must be map to lane 0\n");
  364. return -EINVAL;
  365. }
  366. bridge->r.clk_lane_reg1 |= (polarities[0] << 1) | CLK_ENABLE;
  367. return 0;
  368. }
  369. static int mipid02_configure_data0_lane(struct mipid02_dev *bridge, int nb,
  370. bool are_lanes_swap, bool *polarities)
  371. {
  372. bool are_pin_swap = are_lanes_swap ? polarities[2] : polarities[1];
  373. if (nb == 1 && are_lanes_swap)
  374. return 0;
  375. /*
  376. * data lane 0 as pin swap polarity reversed compared to clock and
  377. * data lane 1
  378. */
  379. if (!are_pin_swap)
  380. bridge->r.data_lane0_reg1 = 1 << 1;
  381. bridge->r.data_lane0_reg1 |= DATA_ENABLE;
  382. return 0;
  383. }
  384. static int mipid02_configure_data1_lane(struct mipid02_dev *bridge, int nb,
  385. bool are_lanes_swap, bool *polarities)
  386. {
  387. bool are_pin_swap = are_lanes_swap ? polarities[1] : polarities[2];
  388. if (nb == 1 && !are_lanes_swap)
  389. return 0;
  390. if (are_pin_swap)
  391. bridge->r.data_lane1_reg1 = 1 << 1;
  392. bridge->r.data_lane1_reg1 |= DATA_ENABLE;
  393. return 0;
  394. }
  395. static int mipid02_configure_from_rx(struct mipid02_dev *bridge)
  396. {
  397. struct v4l2_fwnode_endpoint *ep = &bridge->rx;
  398. bool are_lanes_swap = ep->bus.mipi_csi2.data_lanes[0] == 2;
  399. bool *polarities = ep->bus.mipi_csi2.lane_polarities;
  400. int nb = ep->bus.mipi_csi2.num_data_lanes;
  401. int ret;
  402. ret = mipid02_configure_clk_lane(bridge);
  403. if (ret)
  404. return ret;
  405. ret = mipid02_configure_data0_lane(bridge, nb, are_lanes_swap,
  406. polarities);
  407. if (ret)
  408. return ret;
  409. ret = mipid02_configure_data1_lane(bridge, nb, are_lanes_swap,
  410. polarities);
  411. if (ret)
  412. return ret;
  413. bridge->r.mode_reg1 |= are_lanes_swap ? MODE_DATA_SWAP : 0;
  414. bridge->r.mode_reg1 |= (nb - 1) << 1;
  415. return mipid02_configure_from_rx_speed(bridge);
  416. }
  417. static int mipid02_configure_from_tx(struct mipid02_dev *bridge)
  418. {
  419. struct v4l2_fwnode_endpoint *ep = &bridge->tx;
  420. bridge->r.data_selection_ctrl = SELECTION_MANUAL_WIDTH;
  421. bridge->r.pix_width_ctrl = ep->bus.parallel.bus_width;
  422. bridge->r.pix_width_ctrl_emb = ep->bus.parallel.bus_width;
  423. if (ep->bus.parallel.flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
  424. bridge->r.mode_reg2 |= MODE_HSYNC_ACTIVE_HIGH;
  425. if (ep->bus.parallel.flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
  426. bridge->r.mode_reg2 |= MODE_VSYNC_ACTIVE_HIGH;
  427. return 0;
  428. }
  429. static int mipid02_configure_from_code(struct mipid02_dev *bridge)
  430. {
  431. u8 data_type;
  432. bridge->r.data_id_rreg = 0;
  433. if (bridge->fmt.code != MEDIA_BUS_FMT_JPEG_1X8) {
  434. bridge->r.data_selection_ctrl |= SELECTION_MANUAL_DATA;
  435. data_type = data_type_from_code(bridge->fmt.code);
  436. if (!data_type)
  437. return -EINVAL;
  438. bridge->r.data_id_rreg = data_type;
  439. }
  440. return 0;
  441. }
  442. static int mipid02_stream_disable(struct mipid02_dev *bridge)
  443. {
  444. struct i2c_client *client = bridge->i2c_client;
  445. int ret;
  446. /* Disable all lanes */
  447. ret = mipid02_write_reg(bridge, MIPID02_CLK_LANE_REG1, 0);
  448. if (ret)
  449. goto error;
  450. ret = mipid02_write_reg(bridge, MIPID02_DATA_LANE0_REG1, 0);
  451. if (ret)
  452. goto error;
  453. ret = mipid02_write_reg(bridge, MIPID02_DATA_LANE1_REG1, 0);
  454. if (ret)
  455. goto error;
  456. error:
  457. if (ret)
  458. dev_err(&client->dev, "failed to stream off %d", ret);
  459. return ret;
  460. }
  461. static int mipid02_stream_enable(struct mipid02_dev *bridge)
  462. {
  463. struct i2c_client *client = bridge->i2c_client;
  464. int ret = -EINVAL;
  465. if (!bridge->s_subdev)
  466. goto error;
  467. memset(&bridge->r, 0, sizeof(bridge->r));
  468. /* build registers content */
  469. ret = mipid02_configure_from_rx(bridge);
  470. if (ret)
  471. goto error;
  472. ret = mipid02_configure_from_tx(bridge);
  473. if (ret)
  474. goto error;
  475. ret = mipid02_configure_from_code(bridge);
  476. if (ret)
  477. goto error;
  478. /* write mipi registers */
  479. ret = mipid02_write_reg(bridge, MIPID02_CLK_LANE_REG1,
  480. bridge->r.clk_lane_reg1);
  481. if (ret)
  482. goto error;
  483. ret = mipid02_write_reg(bridge, MIPID02_CLK_LANE_REG3, CLK_MIPI_CSI);
  484. if (ret)
  485. goto error;
  486. ret = mipid02_write_reg(bridge, MIPID02_DATA_LANE0_REG1,
  487. bridge->r.data_lane0_reg1);
  488. if (ret)
  489. goto error;
  490. ret = mipid02_write_reg(bridge, MIPID02_DATA_LANE0_REG2,
  491. DATA_MIPI_CSI);
  492. if (ret)
  493. goto error;
  494. ret = mipid02_write_reg(bridge, MIPID02_DATA_LANE1_REG1,
  495. bridge->r.data_lane1_reg1);
  496. if (ret)
  497. goto error;
  498. ret = mipid02_write_reg(bridge, MIPID02_DATA_LANE1_REG2,
  499. DATA_MIPI_CSI);
  500. if (ret)
  501. goto error;
  502. ret = mipid02_write_reg(bridge, MIPID02_MODE_REG1,
  503. MODE_NO_BYPASS | bridge->r.mode_reg1);
  504. if (ret)
  505. goto error;
  506. ret = mipid02_write_reg(bridge, MIPID02_MODE_REG2,
  507. bridge->r.mode_reg2);
  508. if (ret)
  509. goto error;
  510. ret = mipid02_write_reg(bridge, MIPID02_DATA_ID_RREG,
  511. bridge->r.data_id_rreg);
  512. if (ret)
  513. goto error;
  514. ret = mipid02_write_reg(bridge, MIPID02_DATA_SELECTION_CTRL,
  515. bridge->r.data_selection_ctrl);
  516. if (ret)
  517. goto error;
  518. ret = mipid02_write_reg(bridge, MIPID02_PIX_WIDTH_CTRL,
  519. bridge->r.pix_width_ctrl);
  520. if (ret)
  521. goto error;
  522. ret = mipid02_write_reg(bridge, MIPID02_PIX_WIDTH_CTRL_EMB,
  523. bridge->r.pix_width_ctrl_emb);
  524. if (ret)
  525. goto error;
  526. return 0;
  527. error:
  528. dev_err(&client->dev, "failed to stream on %d", ret);
  529. mipid02_stream_disable(bridge);
  530. return ret;
  531. }
  532. static int mipid02_s_stream(struct v4l2_subdev *sd, int enable)
  533. {
  534. struct mipid02_dev *bridge = to_mipid02_dev(sd);
  535. struct i2c_client *client = bridge->i2c_client;
  536. int ret = 0;
  537. dev_dbg(&client->dev, "%s : requested %d / current = %d", __func__,
  538. enable, bridge->streaming);
  539. mutex_lock(&bridge->lock);
  540. if (bridge->streaming == enable)
  541. goto out;
  542. ret = enable ? mipid02_stream_enable(bridge) :
  543. mipid02_stream_disable(bridge);
  544. if (!ret)
  545. bridge->streaming = enable;
  546. out:
  547. dev_dbg(&client->dev, "%s current now = %d / %d", __func__,
  548. bridge->streaming, ret);
  549. mutex_unlock(&bridge->lock);
  550. return ret;
  551. }
  552. static int mipid02_enum_mbus_code(struct v4l2_subdev *sd,
  553. struct v4l2_subdev_pad_config *cfg,
  554. struct v4l2_subdev_mbus_code_enum *code)
  555. {
  556. struct mipid02_dev *bridge = to_mipid02_dev(sd);
  557. int ret = 0;
  558. switch (code->pad) {
  559. case MIPID02_SINK_0:
  560. if (code->index >= ARRAY_SIZE(mipid02_supported_fmt_codes))
  561. ret = -EINVAL;
  562. else
  563. code->code = mipid02_supported_fmt_codes[code->index];
  564. break;
  565. case MIPID02_SOURCE:
  566. if (code->index == 0)
  567. code->code = serial_to_parallel_code(bridge->fmt.code);
  568. else
  569. ret = -EINVAL;
  570. break;
  571. default:
  572. ret = -EINVAL;
  573. }
  574. return ret;
  575. }
  576. static int mipid02_get_fmt(struct v4l2_subdev *sd,
  577. struct v4l2_subdev_pad_config *cfg,
  578. struct v4l2_subdev_format *format)
  579. {
  580. struct v4l2_mbus_framefmt *mbus_fmt = &format->format;
  581. struct mipid02_dev *bridge = to_mipid02_dev(sd);
  582. struct i2c_client *client = bridge->i2c_client;
  583. struct v4l2_mbus_framefmt *fmt;
  584. dev_dbg(&client->dev, "%s probe %d", __func__, format->pad);
  585. if (format->pad >= MIPID02_PAD_NB)
  586. return -EINVAL;
  587. /* second CSI-2 pad not yet supported */
  588. if (format->pad == MIPID02_SINK_1)
  589. return -EINVAL;
  590. if (format->which == V4L2_SUBDEV_FORMAT_TRY)
  591. fmt = v4l2_subdev_get_try_format(&bridge->sd, cfg, format->pad);
  592. else
  593. fmt = &bridge->fmt;
  594. mutex_lock(&bridge->lock);
  595. *mbus_fmt = *fmt;
  596. /* code may need to be converted for source */
  597. if (format->pad == MIPID02_SOURCE)
  598. mbus_fmt->code = serial_to_parallel_code(mbus_fmt->code);
  599. mutex_unlock(&bridge->lock);
  600. return 0;
  601. }
  602. static void mipid02_set_fmt_source(struct v4l2_subdev *sd,
  603. struct v4l2_subdev_pad_config *cfg,
  604. struct v4l2_subdev_format *format)
  605. {
  606. struct mipid02_dev *bridge = to_mipid02_dev(sd);
  607. /* source pad mirror active sink pad */
  608. format->format = bridge->fmt;
  609. /* but code may need to be converted */
  610. format->format.code = serial_to_parallel_code(format->format.code);
  611. /* only apply format for V4L2_SUBDEV_FORMAT_TRY case */
  612. if (format->which != V4L2_SUBDEV_FORMAT_TRY)
  613. return;
  614. *v4l2_subdev_get_try_format(sd, cfg, format->pad) = format->format;
  615. }
  616. static void mipid02_set_fmt_sink(struct v4l2_subdev *sd,
  617. struct v4l2_subdev_pad_config *cfg,
  618. struct v4l2_subdev_format *format)
  619. {
  620. struct mipid02_dev *bridge = to_mipid02_dev(sd);
  621. struct v4l2_mbus_framefmt *fmt;
  622. format->format.code = get_fmt_code(format->format.code);
  623. if (format->which == V4L2_SUBDEV_FORMAT_TRY)
  624. fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
  625. else
  626. fmt = &bridge->fmt;
  627. *fmt = format->format;
  628. }
  629. static int mipid02_set_fmt(struct v4l2_subdev *sd,
  630. struct v4l2_subdev_pad_config *cfg,
  631. struct v4l2_subdev_format *format)
  632. {
  633. struct mipid02_dev *bridge = to_mipid02_dev(sd);
  634. struct i2c_client *client = bridge->i2c_client;
  635. int ret = 0;
  636. dev_dbg(&client->dev, "%s for %d", __func__, format->pad);
  637. if (format->pad >= MIPID02_PAD_NB)
  638. return -EINVAL;
  639. /* second CSI-2 pad not yet supported */
  640. if (format->pad == MIPID02_SINK_1)
  641. return -EINVAL;
  642. mutex_lock(&bridge->lock);
  643. if (bridge->streaming) {
  644. ret = -EBUSY;
  645. goto error;
  646. }
  647. if (format->pad == MIPID02_SOURCE)
  648. mipid02_set_fmt_source(sd, cfg, format);
  649. else
  650. mipid02_set_fmt_sink(sd, cfg, format);
  651. error:
  652. mutex_unlock(&bridge->lock);
  653. return ret;
  654. }
  655. static const struct v4l2_subdev_video_ops mipid02_video_ops = {
  656. .s_stream = mipid02_s_stream,
  657. };
  658. static const struct v4l2_subdev_pad_ops mipid02_pad_ops = {
  659. .enum_mbus_code = mipid02_enum_mbus_code,
  660. .get_fmt = mipid02_get_fmt,
  661. .set_fmt = mipid02_set_fmt,
  662. };
  663. static const struct v4l2_subdev_ops mipid02_subdev_ops = {
  664. .video = &mipid02_video_ops,
  665. .pad = &mipid02_pad_ops,
  666. };
  667. static const struct media_entity_operations mipid02_subdev_entity_ops = {
  668. .link_validate = v4l2_subdev_link_validate,
  669. };
  670. static int mipid02_async_bound(struct v4l2_async_notifier *notifier,
  671. struct v4l2_subdev *s_subdev,
  672. struct v4l2_async_subdev *asd)
  673. {
  674. struct mipid02_dev *bridge = to_mipid02_dev(notifier->sd);
  675. struct i2c_client *client = bridge->i2c_client;
  676. int source_pad;
  677. int ret;
  678. dev_dbg(&client->dev, "sensor_async_bound call %p", s_subdev);
  679. source_pad = media_entity_get_fwnode_pad(&s_subdev->entity,
  680. s_subdev->fwnode,
  681. MEDIA_PAD_FL_SOURCE);
  682. if (source_pad < 0) {
  683. dev_err(&client->dev, "Couldn't find output pad for subdev %s\n",
  684. s_subdev->name);
  685. return source_pad;
  686. }
  687. ret = media_create_pad_link(&s_subdev->entity, source_pad,
  688. &bridge->sd.entity, 0,
  689. MEDIA_LNK_FL_ENABLED |
  690. MEDIA_LNK_FL_IMMUTABLE);
  691. if (ret) {
  692. dev_err(&client->dev, "Couldn't create media link %d", ret);
  693. return ret;
  694. }
  695. bridge->s_subdev = s_subdev;
  696. return 0;
  697. }
  698. static void mipid02_async_unbind(struct v4l2_async_notifier *notifier,
  699. struct v4l2_subdev *s_subdev,
  700. struct v4l2_async_subdev *asd)
  701. {
  702. struct mipid02_dev *bridge = to_mipid02_dev(notifier->sd);
  703. bridge->s_subdev = NULL;
  704. }
  705. static const struct v4l2_async_notifier_operations mipid02_notifier_ops = {
  706. .bound = mipid02_async_bound,
  707. .unbind = mipid02_async_unbind,
  708. };
  709. static int mipid02_parse_rx_ep(struct mipid02_dev *bridge)
  710. {
  711. struct v4l2_fwnode_endpoint ep = { .bus_type = V4L2_MBUS_CSI2_DPHY };
  712. struct i2c_client *client = bridge->i2c_client;
  713. struct device_node *ep_node;
  714. int ret;
  715. /* parse rx (endpoint 0) */
  716. ep_node = of_graph_get_endpoint_by_regs(bridge->i2c_client->dev.of_node,
  717. 0, 0);
  718. if (!ep_node) {
  719. dev_err(&client->dev, "unable to find port0 ep");
  720. ret = -EINVAL;
  721. goto error;
  722. }
  723. ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep_node), &ep);
  724. if (ret) {
  725. dev_err(&client->dev, "Could not parse v4l2 endpoint %d\n",
  726. ret);
  727. goto error_of_node_put;
  728. }
  729. /* do some sanity checks */
  730. if (ep.bus.mipi_csi2.num_data_lanes > 2) {
  731. dev_err(&client->dev, "max supported data lanes is 2 / got %d",
  732. ep.bus.mipi_csi2.num_data_lanes);
  733. ret = -EINVAL;
  734. goto error_of_node_put;
  735. }
  736. /* register it for later use */
  737. bridge->rx = ep;
  738. /* register async notifier so we get noticed when sensor is connected */
  739. bridge->asd.match.fwnode =
  740. fwnode_graph_get_remote_port_parent(of_fwnode_handle(ep_node));
  741. bridge->asd.match_type = V4L2_ASYNC_MATCH_FWNODE;
  742. of_node_put(ep_node);
  743. v4l2_async_notifier_init(&bridge->notifier);
  744. ret = v4l2_async_notifier_add_subdev(&bridge->notifier, &bridge->asd);
  745. if (ret) {
  746. dev_err(&client->dev, "fail to register asd to notifier %d",
  747. ret);
  748. fwnode_handle_put(bridge->asd.match.fwnode);
  749. return ret;
  750. }
  751. bridge->notifier.ops = &mipid02_notifier_ops;
  752. ret = v4l2_async_subdev_notifier_register(&bridge->sd,
  753. &bridge->notifier);
  754. if (ret)
  755. v4l2_async_notifier_cleanup(&bridge->notifier);
  756. return ret;
  757. error_of_node_put:
  758. of_node_put(ep_node);
  759. error:
  760. return ret;
  761. }
  762. static int mipid02_parse_tx_ep(struct mipid02_dev *bridge)
  763. {
  764. struct v4l2_fwnode_endpoint ep = { .bus_type = V4L2_MBUS_PARALLEL };
  765. struct i2c_client *client = bridge->i2c_client;
  766. struct device_node *ep_node;
  767. int ret;
  768. /* parse tx (endpoint 2) */
  769. ep_node = of_graph_get_endpoint_by_regs(bridge->i2c_client->dev.of_node,
  770. 2, 0);
  771. if (!ep_node) {
  772. dev_err(&client->dev, "unable to find port1 ep");
  773. ret = -EINVAL;
  774. goto error;
  775. }
  776. ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep_node), &ep);
  777. if (ret) {
  778. dev_err(&client->dev, "Could not parse v4l2 endpoint\n");
  779. goto error_of_node_put;
  780. }
  781. of_node_put(ep_node);
  782. bridge->tx = ep;
  783. return 0;
  784. error_of_node_put:
  785. of_node_put(ep_node);
  786. error:
  787. return -EINVAL;
  788. }
  789. static int mipid02_probe(struct i2c_client *client)
  790. {
  791. struct device *dev = &client->dev;
  792. struct mipid02_dev *bridge;
  793. u32 clk_freq;
  794. int ret;
  795. bridge = devm_kzalloc(dev, sizeof(*bridge), GFP_KERNEL);
  796. if (!bridge)
  797. return -ENOMEM;
  798. init_format(&bridge->fmt);
  799. bridge->i2c_client = client;
  800. v4l2_i2c_subdev_init(&bridge->sd, client, &mipid02_subdev_ops);
  801. /* got and check clock */
  802. bridge->xclk = devm_clk_get(dev, "xclk");
  803. if (IS_ERR(bridge->xclk)) {
  804. dev_err(dev, "failed to get xclk\n");
  805. return PTR_ERR(bridge->xclk);
  806. }
  807. clk_freq = clk_get_rate(bridge->xclk);
  808. if (clk_freq < 6000000 || clk_freq > 27000000) {
  809. dev_err(dev, "xclk freq must be in 6-27 Mhz range. got %d Hz\n",
  810. clk_freq);
  811. return -EINVAL;
  812. }
  813. bridge->reset_gpio = devm_gpiod_get_optional(dev, "reset",
  814. GPIOD_OUT_HIGH);
  815. if (IS_ERR(bridge->reset_gpio)) {
  816. dev_err(dev, "failed to get reset GPIO\n");
  817. return PTR_ERR(bridge->reset_gpio);
  818. }
  819. ret = mipid02_get_regulators(bridge);
  820. if (ret) {
  821. dev_err(dev, "failed to get regulators %d", ret);
  822. return ret;
  823. }
  824. mutex_init(&bridge->lock);
  825. bridge->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
  826. bridge->sd.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
  827. bridge->sd.entity.ops = &mipid02_subdev_entity_ops;
  828. bridge->pad[0].flags = MEDIA_PAD_FL_SINK;
  829. bridge->pad[1].flags = MEDIA_PAD_FL_SINK;
  830. bridge->pad[2].flags = MEDIA_PAD_FL_SOURCE;
  831. ret = media_entity_pads_init(&bridge->sd.entity, MIPID02_PAD_NB,
  832. bridge->pad);
  833. if (ret) {
  834. dev_err(&client->dev, "pads init failed %d", ret);
  835. goto mutex_cleanup;
  836. }
  837. /* enable clock, power and reset device if available */
  838. ret = mipid02_set_power_on(bridge);
  839. if (ret)
  840. goto entity_cleanup;
  841. ret = mipid02_detect(bridge);
  842. if (ret) {
  843. dev_err(&client->dev, "failed to detect mipid02 %d", ret);
  844. goto power_off;
  845. }
  846. ret = mipid02_parse_tx_ep(bridge);
  847. if (ret) {
  848. dev_err(&client->dev, "failed to parse tx %d", ret);
  849. goto power_off;
  850. }
  851. ret = mipid02_parse_rx_ep(bridge);
  852. if (ret) {
  853. dev_err(&client->dev, "failed to parse rx %d", ret);
  854. goto power_off;
  855. }
  856. ret = v4l2_async_register_subdev(&bridge->sd);
  857. if (ret < 0) {
  858. dev_err(&client->dev, "v4l2_async_register_subdev failed %d",
  859. ret);
  860. goto unregister_notifier;
  861. }
  862. dev_info(&client->dev, "mipid02 device probe successfully");
  863. return 0;
  864. unregister_notifier:
  865. v4l2_async_notifier_unregister(&bridge->notifier);
  866. v4l2_async_notifier_cleanup(&bridge->notifier);
  867. power_off:
  868. mipid02_set_power_off(bridge);
  869. entity_cleanup:
  870. media_entity_cleanup(&bridge->sd.entity);
  871. mutex_cleanup:
  872. mutex_destroy(&bridge->lock);
  873. return ret;
  874. }
  875. static int mipid02_remove(struct i2c_client *client)
  876. {
  877. struct v4l2_subdev *sd = i2c_get_clientdata(client);
  878. struct mipid02_dev *bridge = to_mipid02_dev(sd);
  879. v4l2_async_notifier_unregister(&bridge->notifier);
  880. v4l2_async_notifier_cleanup(&bridge->notifier);
  881. v4l2_async_unregister_subdev(&bridge->sd);
  882. mipid02_set_power_off(bridge);
  883. media_entity_cleanup(&bridge->sd.entity);
  884. mutex_destroy(&bridge->lock);
  885. return 0;
  886. }
  887. static const struct of_device_id mipid02_dt_ids[] = {
  888. { .compatible = "st,st-mipid02" },
  889. { /* sentinel */ }
  890. };
  891. MODULE_DEVICE_TABLE(of, mipid02_dt_ids);
  892. static struct i2c_driver mipid02_i2c_driver = {
  893. .driver = {
  894. .name = "st-mipid02",
  895. .of_match_table = mipid02_dt_ids,
  896. },
  897. .probe_new = mipid02_probe,
  898. .remove = mipid02_remove,
  899. };
  900. module_i2c_driver(mipid02_i2c_driver);
  901. MODULE_AUTHOR("Mickael Guene <mickael.guene@st.com>");
  902. MODULE_DESCRIPTION("STMicroelectronics MIPID02 CSI-2 bridge driver");
  903. MODULE_LICENSE("GPL v2");