smiapp-pll.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * drivers/media/i2c/smiapp-pll.c
  4. *
  5. * Generic driver for SMIA/SMIA++ compliant camera modules
  6. *
  7. * Copyright (C) 2011--2012 Nokia Corporation
  8. * Contact: Sakari Ailus <sakari.ailus@iki.fi>
  9. */
  10. #include <linux/device.h>
  11. #include <linux/gcd.h>
  12. #include <linux/lcm.h>
  13. #include <linux/module.h>
  14. #include "smiapp-pll.h"
  15. /* Return an even number or one. */
  16. static inline uint32_t clk_div_even(uint32_t a)
  17. {
  18. return max_t(uint32_t, 1, a & ~1);
  19. }
  20. /* Return an even number or one. */
  21. static inline uint32_t clk_div_even_up(uint32_t a)
  22. {
  23. if (a == 1)
  24. return 1;
  25. return (a + 1) & ~1;
  26. }
  27. static inline uint32_t is_one_or_even(uint32_t a)
  28. {
  29. if (a == 1)
  30. return 1;
  31. if (a & 1)
  32. return 0;
  33. return 1;
  34. }
  35. static int bounds_check(struct device *dev, uint32_t val,
  36. uint32_t min, uint32_t max, char *str)
  37. {
  38. if (val >= min && val <= max)
  39. return 0;
  40. dev_dbg(dev, "%s out of bounds: %d (%d--%d)\n", str, val, min, max);
  41. return -EINVAL;
  42. }
  43. static void print_pll(struct device *dev, struct smiapp_pll *pll)
  44. {
  45. dev_dbg(dev, "pre_pll_clk_div\t%u\n", pll->pre_pll_clk_div);
  46. dev_dbg(dev, "pll_multiplier \t%u\n", pll->pll_multiplier);
  47. if (!(pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS)) {
  48. dev_dbg(dev, "op_sys_clk_div \t%u\n", pll->op.sys_clk_div);
  49. dev_dbg(dev, "op_pix_clk_div \t%u\n", pll->op.pix_clk_div);
  50. }
  51. dev_dbg(dev, "vt_sys_clk_div \t%u\n", pll->vt.sys_clk_div);
  52. dev_dbg(dev, "vt_pix_clk_div \t%u\n", pll->vt.pix_clk_div);
  53. dev_dbg(dev, "ext_clk_freq_hz \t%u\n", pll->ext_clk_freq_hz);
  54. dev_dbg(dev, "pll_ip_clk_freq_hz \t%u\n", pll->pll_ip_clk_freq_hz);
  55. dev_dbg(dev, "pll_op_clk_freq_hz \t%u\n", pll->pll_op_clk_freq_hz);
  56. if (!(pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS)) {
  57. dev_dbg(dev, "op_sys_clk_freq_hz \t%u\n",
  58. pll->op.sys_clk_freq_hz);
  59. dev_dbg(dev, "op_pix_clk_freq_hz \t%u\n",
  60. pll->op.pix_clk_freq_hz);
  61. }
  62. dev_dbg(dev, "vt_sys_clk_freq_hz \t%u\n", pll->vt.sys_clk_freq_hz);
  63. dev_dbg(dev, "vt_pix_clk_freq_hz \t%u\n", pll->vt.pix_clk_freq_hz);
  64. }
  65. static int check_all_bounds(struct device *dev,
  66. const struct smiapp_pll_limits *limits,
  67. const struct smiapp_pll_branch_limits *op_limits,
  68. struct smiapp_pll *pll,
  69. struct smiapp_pll_branch *op_pll)
  70. {
  71. int rval;
  72. rval = bounds_check(dev, pll->pll_ip_clk_freq_hz,
  73. limits->min_pll_ip_freq_hz,
  74. limits->max_pll_ip_freq_hz,
  75. "pll_ip_clk_freq_hz");
  76. if (!rval)
  77. rval = bounds_check(
  78. dev, pll->pll_multiplier,
  79. limits->min_pll_multiplier, limits->max_pll_multiplier,
  80. "pll_multiplier");
  81. if (!rval)
  82. rval = bounds_check(
  83. dev, pll->pll_op_clk_freq_hz,
  84. limits->min_pll_op_freq_hz, limits->max_pll_op_freq_hz,
  85. "pll_op_clk_freq_hz");
  86. if (!rval)
  87. rval = bounds_check(
  88. dev, op_pll->sys_clk_div,
  89. op_limits->min_sys_clk_div, op_limits->max_sys_clk_div,
  90. "op_sys_clk_div");
  91. if (!rval)
  92. rval = bounds_check(
  93. dev, op_pll->sys_clk_freq_hz,
  94. op_limits->min_sys_clk_freq_hz,
  95. op_limits->max_sys_clk_freq_hz,
  96. "op_sys_clk_freq_hz");
  97. if (!rval)
  98. rval = bounds_check(
  99. dev, op_pll->pix_clk_freq_hz,
  100. op_limits->min_pix_clk_freq_hz,
  101. op_limits->max_pix_clk_freq_hz,
  102. "op_pix_clk_freq_hz");
  103. /*
  104. * If there are no OP clocks, the VT clocks are contained in
  105. * the OP clock struct.
  106. */
  107. if (pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS)
  108. return rval;
  109. if (!rval)
  110. rval = bounds_check(
  111. dev, pll->vt.sys_clk_freq_hz,
  112. limits->vt.min_sys_clk_freq_hz,
  113. limits->vt.max_sys_clk_freq_hz,
  114. "vt_sys_clk_freq_hz");
  115. if (!rval)
  116. rval = bounds_check(
  117. dev, pll->vt.pix_clk_freq_hz,
  118. limits->vt.min_pix_clk_freq_hz,
  119. limits->vt.max_pix_clk_freq_hz,
  120. "vt_pix_clk_freq_hz");
  121. return rval;
  122. }
  123. /*
  124. * Heuristically guess the PLL tree for a given common multiplier and
  125. * divisor. Begin with the operational timing and continue to video
  126. * timing once operational timing has been verified.
  127. *
  128. * @mul is the PLL multiplier and @div is the common divisor
  129. * (pre_pll_clk_div and op_sys_clk_div combined). The final PLL
  130. * multiplier will be a multiple of @mul.
  131. *
  132. * @return Zero on success, error code on error.
  133. */
  134. static int __smiapp_pll_calculate(
  135. struct device *dev, const struct smiapp_pll_limits *limits,
  136. const struct smiapp_pll_branch_limits *op_limits,
  137. struct smiapp_pll *pll, struct smiapp_pll_branch *op_pll, uint32_t mul,
  138. uint32_t div, uint32_t lane_op_clock_ratio)
  139. {
  140. uint32_t sys_div;
  141. uint32_t best_pix_div = INT_MAX >> 1;
  142. uint32_t vt_op_binning_div;
  143. /*
  144. * Higher multipliers (and divisors) are often required than
  145. * necessitated by the external clock and the output clocks.
  146. * There are limits for all values in the clock tree. These
  147. * are the minimum and maximum multiplier for mul.
  148. */
  149. uint32_t more_mul_min, more_mul_max;
  150. uint32_t more_mul_factor;
  151. uint32_t min_vt_div, max_vt_div, vt_div;
  152. uint32_t min_sys_div, max_sys_div;
  153. unsigned int i;
  154. /*
  155. * Get pre_pll_clk_div so that our pll_op_clk_freq_hz won't be
  156. * too high.
  157. */
  158. dev_dbg(dev, "pre_pll_clk_div %u\n", pll->pre_pll_clk_div);
  159. /* Don't go above max pll multiplier. */
  160. more_mul_max = limits->max_pll_multiplier / mul;
  161. dev_dbg(dev, "more_mul_max: max_pll_multiplier check: %u\n",
  162. more_mul_max);
  163. /* Don't go above max pll op frequency. */
  164. more_mul_max =
  165. min_t(uint32_t,
  166. more_mul_max,
  167. limits->max_pll_op_freq_hz
  168. / (pll->ext_clk_freq_hz / pll->pre_pll_clk_div * mul));
  169. dev_dbg(dev, "more_mul_max: max_pll_op_freq_hz check: %u\n",
  170. more_mul_max);
  171. /* Don't go above the division capability of op sys clock divider. */
  172. more_mul_max = min(more_mul_max,
  173. op_limits->max_sys_clk_div * pll->pre_pll_clk_div
  174. / div);
  175. dev_dbg(dev, "more_mul_max: max_op_sys_clk_div check: %u\n",
  176. more_mul_max);
  177. /* Ensure we won't go above min_pll_multiplier. */
  178. more_mul_max = min(more_mul_max,
  179. DIV_ROUND_UP(limits->max_pll_multiplier, mul));
  180. dev_dbg(dev, "more_mul_max: min_pll_multiplier check: %u\n",
  181. more_mul_max);
  182. /* Ensure we won't go below min_pll_op_freq_hz. */
  183. more_mul_min = DIV_ROUND_UP(limits->min_pll_op_freq_hz,
  184. pll->ext_clk_freq_hz / pll->pre_pll_clk_div
  185. * mul);
  186. dev_dbg(dev, "more_mul_min: min_pll_op_freq_hz check: %u\n",
  187. more_mul_min);
  188. /* Ensure we won't go below min_pll_multiplier. */
  189. more_mul_min = max(more_mul_min,
  190. DIV_ROUND_UP(limits->min_pll_multiplier, mul));
  191. dev_dbg(dev, "more_mul_min: min_pll_multiplier check: %u\n",
  192. more_mul_min);
  193. if (more_mul_min > more_mul_max) {
  194. dev_dbg(dev,
  195. "unable to compute more_mul_min and more_mul_max\n");
  196. return -EINVAL;
  197. }
  198. more_mul_factor = lcm(div, pll->pre_pll_clk_div) / div;
  199. dev_dbg(dev, "more_mul_factor: %u\n", more_mul_factor);
  200. more_mul_factor = lcm(more_mul_factor, op_limits->min_sys_clk_div);
  201. dev_dbg(dev, "more_mul_factor: min_op_sys_clk_div: %d\n",
  202. more_mul_factor);
  203. i = roundup(more_mul_min, more_mul_factor);
  204. if (!is_one_or_even(i))
  205. i <<= 1;
  206. dev_dbg(dev, "final more_mul: %u\n", i);
  207. if (i > more_mul_max) {
  208. dev_dbg(dev, "final more_mul is bad, max %u\n", more_mul_max);
  209. return -EINVAL;
  210. }
  211. pll->pll_multiplier = mul * i;
  212. op_pll->sys_clk_div = div * i / pll->pre_pll_clk_div;
  213. dev_dbg(dev, "op_sys_clk_div: %u\n", op_pll->sys_clk_div);
  214. pll->pll_ip_clk_freq_hz = pll->ext_clk_freq_hz
  215. / pll->pre_pll_clk_div;
  216. pll->pll_op_clk_freq_hz = pll->pll_ip_clk_freq_hz
  217. * pll->pll_multiplier;
  218. /* Derive pll_op_clk_freq_hz. */
  219. op_pll->sys_clk_freq_hz =
  220. pll->pll_op_clk_freq_hz / op_pll->sys_clk_div;
  221. op_pll->pix_clk_div = pll->bits_per_pixel;
  222. dev_dbg(dev, "op_pix_clk_div: %u\n", op_pll->pix_clk_div);
  223. op_pll->pix_clk_freq_hz =
  224. op_pll->sys_clk_freq_hz / op_pll->pix_clk_div;
  225. if (pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS) {
  226. /* No OP clocks --- VT clocks are used instead. */
  227. goto out_skip_vt_calc;
  228. }
  229. /*
  230. * Some sensors perform analogue binning and some do this
  231. * digitally. The ones doing this digitally can be roughly be
  232. * found out using this formula. The ones doing this digitally
  233. * should run at higher clock rate, so smaller divisor is used
  234. * on video timing side.
  235. */
  236. if (limits->min_line_length_pck_bin > limits->min_line_length_pck
  237. / pll->binning_horizontal)
  238. vt_op_binning_div = pll->binning_horizontal;
  239. else
  240. vt_op_binning_div = 1;
  241. dev_dbg(dev, "vt_op_binning_div: %u\n", vt_op_binning_div);
  242. /*
  243. * Profile 2 supports vt_pix_clk_div E [4, 10]
  244. *
  245. * Horizontal binning can be used as a base for difference in
  246. * divisors. One must make sure that horizontal blanking is
  247. * enough to accommodate the CSI-2 sync codes.
  248. *
  249. * Take scaling factor into account as well.
  250. *
  251. * Find absolute limits for the factor of vt divider.
  252. */
  253. dev_dbg(dev, "scale_m: %u\n", pll->scale_m);
  254. min_vt_div = DIV_ROUND_UP(op_pll->pix_clk_div * op_pll->sys_clk_div
  255. * pll->scale_n,
  256. lane_op_clock_ratio * vt_op_binning_div
  257. * pll->scale_m);
  258. /* Find smallest and biggest allowed vt divisor. */
  259. dev_dbg(dev, "min_vt_div: %u\n", min_vt_div);
  260. min_vt_div = max(min_vt_div,
  261. DIV_ROUND_UP(pll->pll_op_clk_freq_hz,
  262. limits->vt.max_pix_clk_freq_hz));
  263. dev_dbg(dev, "min_vt_div: max_vt_pix_clk_freq_hz: %u\n",
  264. min_vt_div);
  265. min_vt_div = max_t(uint32_t, min_vt_div,
  266. limits->vt.min_pix_clk_div
  267. * limits->vt.min_sys_clk_div);
  268. dev_dbg(dev, "min_vt_div: min_vt_clk_div: %u\n", min_vt_div);
  269. max_vt_div = limits->vt.max_sys_clk_div * limits->vt.max_pix_clk_div;
  270. dev_dbg(dev, "max_vt_div: %u\n", max_vt_div);
  271. max_vt_div = min(max_vt_div,
  272. DIV_ROUND_UP(pll->pll_op_clk_freq_hz,
  273. limits->vt.min_pix_clk_freq_hz));
  274. dev_dbg(dev, "max_vt_div: min_vt_pix_clk_freq_hz: %u\n",
  275. max_vt_div);
  276. /*
  277. * Find limitsits for sys_clk_div. Not all values are possible
  278. * with all values of pix_clk_div.
  279. */
  280. min_sys_div = limits->vt.min_sys_clk_div;
  281. dev_dbg(dev, "min_sys_div: %u\n", min_sys_div);
  282. min_sys_div = max(min_sys_div,
  283. DIV_ROUND_UP(min_vt_div,
  284. limits->vt.max_pix_clk_div));
  285. dev_dbg(dev, "min_sys_div: max_vt_pix_clk_div: %u\n", min_sys_div);
  286. min_sys_div = max(min_sys_div,
  287. pll->pll_op_clk_freq_hz
  288. / limits->vt.max_sys_clk_freq_hz);
  289. dev_dbg(dev, "min_sys_div: max_pll_op_clk_freq_hz: %u\n", min_sys_div);
  290. min_sys_div = clk_div_even_up(min_sys_div);
  291. dev_dbg(dev, "min_sys_div: one or even: %u\n", min_sys_div);
  292. max_sys_div = limits->vt.max_sys_clk_div;
  293. dev_dbg(dev, "max_sys_div: %u\n", max_sys_div);
  294. max_sys_div = min(max_sys_div,
  295. DIV_ROUND_UP(max_vt_div,
  296. limits->vt.min_pix_clk_div));
  297. dev_dbg(dev, "max_sys_div: min_vt_pix_clk_div: %u\n", max_sys_div);
  298. max_sys_div = min(max_sys_div,
  299. DIV_ROUND_UP(pll->pll_op_clk_freq_hz,
  300. limits->vt.min_pix_clk_freq_hz));
  301. dev_dbg(dev, "max_sys_div: min_vt_pix_clk_freq_hz: %u\n", max_sys_div);
  302. /*
  303. * Find pix_div such that a legal pix_div * sys_div results
  304. * into a value which is not smaller than div, the desired
  305. * divisor.
  306. */
  307. for (vt_div = min_vt_div; vt_div <= max_vt_div;
  308. vt_div += 2 - (vt_div & 1)) {
  309. for (sys_div = min_sys_div;
  310. sys_div <= max_sys_div;
  311. sys_div += 2 - (sys_div & 1)) {
  312. uint16_t pix_div = DIV_ROUND_UP(vt_div, sys_div);
  313. if (pix_div < limits->vt.min_pix_clk_div
  314. || pix_div > limits->vt.max_pix_clk_div) {
  315. dev_dbg(dev,
  316. "pix_div %u too small or too big (%u--%u)\n",
  317. pix_div,
  318. limits->vt.min_pix_clk_div,
  319. limits->vt.max_pix_clk_div);
  320. continue;
  321. }
  322. /* Check if this one is better. */
  323. if (pix_div * sys_div
  324. <= roundup(min_vt_div, best_pix_div))
  325. best_pix_div = pix_div;
  326. }
  327. if (best_pix_div < INT_MAX >> 1)
  328. break;
  329. }
  330. pll->vt.sys_clk_div = DIV_ROUND_UP(min_vt_div, best_pix_div);
  331. pll->vt.pix_clk_div = best_pix_div;
  332. pll->vt.sys_clk_freq_hz =
  333. pll->pll_op_clk_freq_hz / pll->vt.sys_clk_div;
  334. pll->vt.pix_clk_freq_hz =
  335. pll->vt.sys_clk_freq_hz / pll->vt.pix_clk_div;
  336. out_skip_vt_calc:
  337. pll->pixel_rate_csi =
  338. op_pll->pix_clk_freq_hz * lane_op_clock_ratio;
  339. pll->pixel_rate_pixel_array = pll->vt.pix_clk_freq_hz;
  340. return check_all_bounds(dev, limits, op_limits, pll, op_pll);
  341. }
  342. int smiapp_pll_calculate(struct device *dev,
  343. const struct smiapp_pll_limits *limits,
  344. struct smiapp_pll *pll)
  345. {
  346. const struct smiapp_pll_branch_limits *op_limits = &limits->op;
  347. struct smiapp_pll_branch *op_pll = &pll->op;
  348. uint16_t min_pre_pll_clk_div;
  349. uint16_t max_pre_pll_clk_div;
  350. uint32_t lane_op_clock_ratio;
  351. uint32_t mul, div;
  352. unsigned int i;
  353. int rval = -EINVAL;
  354. if (pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS) {
  355. /*
  356. * If there's no OP PLL at all, use the VT values
  357. * instead. The OP values are ignored for the rest of
  358. * the PLL calculation.
  359. */
  360. op_limits = &limits->vt;
  361. op_pll = &pll->vt;
  362. }
  363. if (pll->flags & SMIAPP_PLL_FLAG_OP_PIX_CLOCK_PER_LANE)
  364. lane_op_clock_ratio = pll->csi2.lanes;
  365. else
  366. lane_op_clock_ratio = 1;
  367. dev_dbg(dev, "lane_op_clock_ratio: %u\n", lane_op_clock_ratio);
  368. dev_dbg(dev, "binning: %ux%u\n", pll->binning_horizontal,
  369. pll->binning_vertical);
  370. switch (pll->bus_type) {
  371. case SMIAPP_PLL_BUS_TYPE_CSI2:
  372. /* CSI transfers 2 bits per clock per lane; thus times 2 */
  373. pll->pll_op_clk_freq_hz = pll->link_freq * 2
  374. * (pll->csi2.lanes / lane_op_clock_ratio);
  375. break;
  376. case SMIAPP_PLL_BUS_TYPE_PARALLEL:
  377. pll->pll_op_clk_freq_hz = pll->link_freq * pll->bits_per_pixel
  378. / DIV_ROUND_UP(pll->bits_per_pixel,
  379. pll->parallel.bus_width);
  380. break;
  381. default:
  382. return -EINVAL;
  383. }
  384. /* Figure out limits for pre-pll divider based on extclk */
  385. dev_dbg(dev, "min / max pre_pll_clk_div: %u / %u\n",
  386. limits->min_pre_pll_clk_div, limits->max_pre_pll_clk_div);
  387. max_pre_pll_clk_div =
  388. min_t(uint16_t, limits->max_pre_pll_clk_div,
  389. clk_div_even(pll->ext_clk_freq_hz /
  390. limits->min_pll_ip_freq_hz));
  391. min_pre_pll_clk_div =
  392. max_t(uint16_t, limits->min_pre_pll_clk_div,
  393. clk_div_even_up(
  394. DIV_ROUND_UP(pll->ext_clk_freq_hz,
  395. limits->max_pll_ip_freq_hz)));
  396. dev_dbg(dev, "pre-pll check: min / max pre_pll_clk_div: %u / %u\n",
  397. min_pre_pll_clk_div, max_pre_pll_clk_div);
  398. i = gcd(pll->pll_op_clk_freq_hz, pll->ext_clk_freq_hz);
  399. mul = div_u64(pll->pll_op_clk_freq_hz, i);
  400. div = pll->ext_clk_freq_hz / i;
  401. dev_dbg(dev, "mul %u / div %u\n", mul, div);
  402. min_pre_pll_clk_div =
  403. max_t(uint16_t, min_pre_pll_clk_div,
  404. clk_div_even_up(
  405. DIV_ROUND_UP(mul * pll->ext_clk_freq_hz,
  406. limits->max_pll_op_freq_hz)));
  407. dev_dbg(dev, "pll_op check: min / max pre_pll_clk_div: %u / %u\n",
  408. min_pre_pll_clk_div, max_pre_pll_clk_div);
  409. for (pll->pre_pll_clk_div = min_pre_pll_clk_div;
  410. pll->pre_pll_clk_div <= max_pre_pll_clk_div;
  411. pll->pre_pll_clk_div += 2 - (pll->pre_pll_clk_div & 1)) {
  412. rval = __smiapp_pll_calculate(dev, limits, op_limits, pll,
  413. op_pll, mul, div,
  414. lane_op_clock_ratio);
  415. if (rval)
  416. continue;
  417. print_pll(dev, pll);
  418. return 0;
  419. }
  420. dev_dbg(dev, "unable to compute pre_pll divisor\n");
  421. return rval;
  422. }
  423. EXPORT_SYMBOL_GPL(smiapp_pll_calculate);
  424. MODULE_AUTHOR("Sakari Ailus <sakari.ailus@iki.fi>");
  425. MODULE_DESCRIPTION("Generic SMIA/SMIA++ PLL calculator");
  426. MODULE_LICENSE("GPL");