saa711x_regs.h 23 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * saa711x - Philips SAA711x video decoder register specifications
  4. *
  5. * Copyright (c) 2006 Mauro Carvalho Chehab <mchehab@kernel.org>
  6. */
  7. #define R_00_CHIP_VERSION 0x00
  8. /* Video Decoder */
  9. /* Video Decoder - Frontend part */
  10. #define R_01_INC_DELAY 0x01
  11. #define R_02_INPUT_CNTL_1 0x02
  12. #define R_03_INPUT_CNTL_2 0x03
  13. #define R_04_INPUT_CNTL_3 0x04
  14. #define R_05_INPUT_CNTL_4 0x05
  15. /* Video Decoder - Decoder part */
  16. #define R_06_H_SYNC_START 0x06
  17. #define R_07_H_SYNC_STOP 0x07
  18. #define R_08_SYNC_CNTL 0x08
  19. #define R_09_LUMA_CNTL 0x09
  20. #define R_0A_LUMA_BRIGHT_CNTL 0x0a
  21. #define R_0B_LUMA_CONTRAST_CNTL 0x0b
  22. #define R_0C_CHROMA_SAT_CNTL 0x0c
  23. #define R_0D_CHROMA_HUE_CNTL 0x0d
  24. #define R_0E_CHROMA_CNTL_1 0x0e
  25. #define R_0F_CHROMA_GAIN_CNTL 0x0f
  26. #define R_10_CHROMA_CNTL_2 0x10
  27. #define R_11_MODE_DELAY_CNTL 0x11
  28. #define R_12_RT_SIGNAL_CNTL 0x12
  29. #define R_13_RT_X_PORT_OUT_CNTL 0x13
  30. #define R_14_ANAL_ADC_COMPAT_CNTL 0x14
  31. #define R_15_VGATE_START_FID_CHG 0x15
  32. #define R_16_VGATE_STOP 0x16
  33. #define R_17_MISC_VGATE_CONF_AND_MSB 0x17
  34. #define R_18_RAW_DATA_GAIN_CNTL 0x18
  35. #define R_19_RAW_DATA_OFF_CNTL 0x19
  36. #define R_1A_COLOR_KILL_LVL_CNTL 0x1a
  37. #define R_1B_MISC_TVVCRDET 0x1b
  38. #define R_1C_ENHAN_COMB_CTRL1 0x1c
  39. #define R_1D_ENHAN_COMB_CTRL2 0x1d
  40. #define R_1E_STATUS_BYTE_1_VD_DEC 0x1e
  41. #define R_1F_STATUS_BYTE_2_VD_DEC 0x1f
  42. /* Component processing and interrupt masking part */
  43. #define R_23_INPUT_CNTL_5 0x23
  44. #define R_24_INPUT_CNTL_6 0x24
  45. #define R_25_INPUT_CNTL_7 0x25
  46. #define R_29_COMP_DELAY 0x29
  47. #define R_2A_COMP_BRIGHT_CNTL 0x2a
  48. #define R_2B_COMP_CONTRAST_CNTL 0x2b
  49. #define R_2C_COMP_SAT_CNTL 0x2c
  50. #define R_2D_INTERRUPT_MASK_1 0x2d
  51. #define R_2E_INTERRUPT_MASK_2 0x2e
  52. #define R_2F_INTERRUPT_MASK_3 0x2f
  53. /* Audio clock generator part */
  54. #define R_30_AUD_MAST_CLK_CYCLES_PER_FIELD 0x30
  55. #define R_34_AUD_MAST_CLK_NOMINAL_INC 0x34
  56. #define R_38_CLK_RATIO_AMXCLK_TO_ASCLK 0x38
  57. #define R_39_CLK_RATIO_ASCLK_TO_ALRCLK 0x39
  58. #define R_3A_AUD_CLK_GEN_BASIC_SETUP 0x3a
  59. /* General purpose VBI data slicer part */
  60. #define R_40_SLICER_CNTL_1 0x40
  61. #define R_41_LCR_BASE 0x41
  62. #define R_58_PROGRAM_FRAMING_CODE 0x58
  63. #define R_59_H_OFF_FOR_SLICER 0x59
  64. #define R_5A_V_OFF_FOR_SLICER 0x5a
  65. #define R_5B_FLD_OFF_AND_MSB_FOR_H_AND_V_OFF 0x5b
  66. #define R_5D_DID 0x5d
  67. #define R_5E_SDID 0x5e
  68. #define R_60_SLICER_STATUS_BYTE_0 0x60
  69. #define R_61_SLICER_STATUS_BYTE_1 0x61
  70. #define R_62_SLICER_STATUS_BYTE_2 0x62
  71. /* X port, I port and the scaler part */
  72. /* Task independent global settings */
  73. #define R_80_GLOBAL_CNTL_1 0x80
  74. #define R_81_V_SYNC_FLD_ID_SRC_SEL_AND_RETIMED_V_F 0x81
  75. #define R_83_X_PORT_I_O_ENA_AND_OUT_CLK 0x83
  76. #define R_84_I_PORT_SIGNAL_DEF 0x84
  77. #define R_85_I_PORT_SIGNAL_POLAR 0x85
  78. #define R_86_I_PORT_FIFO_FLAG_CNTL_AND_ARBIT 0x86
  79. #define R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED 0x87
  80. #define R_88_POWER_SAVE_ADC_PORT_CNTL 0x88
  81. #define R_8F_STATUS_INFO_SCALER 0x8f
  82. /* Task A definition */
  83. /* Basic settings and acquisition window definition */
  84. #define R_90_A_TASK_HANDLING_CNTL 0x90
  85. #define R_91_A_X_PORT_FORMATS_AND_CONF 0x91
  86. #define R_92_A_X_PORT_INPUT_REFERENCE_SIGNAL 0x92
  87. #define R_93_A_I_PORT_OUTPUT_FORMATS_AND_CONF 0x93
  88. #define R_94_A_HORIZ_INPUT_WINDOW_START 0x94
  89. #define R_95_A_HORIZ_INPUT_WINDOW_START_MSB 0x95
  90. #define R_96_A_HORIZ_INPUT_WINDOW_LENGTH 0x96
  91. #define R_97_A_HORIZ_INPUT_WINDOW_LENGTH_MSB 0x97
  92. #define R_98_A_VERT_INPUT_WINDOW_START 0x98
  93. #define R_99_A_VERT_INPUT_WINDOW_START_MSB 0x99
  94. #define R_9A_A_VERT_INPUT_WINDOW_LENGTH 0x9a
  95. #define R_9B_A_VERT_INPUT_WINDOW_LENGTH_MSB 0x9b
  96. #define R_9C_A_HORIZ_OUTPUT_WINDOW_LENGTH 0x9c
  97. #define R_9D_A_HORIZ_OUTPUT_WINDOW_LENGTH_MSB 0x9d
  98. #define R_9E_A_VERT_OUTPUT_WINDOW_LENGTH 0x9e
  99. #define R_9F_A_VERT_OUTPUT_WINDOW_LENGTH_MSB 0x9f
  100. /* FIR filtering and prescaling */
  101. #define R_A0_A_HORIZ_PRESCALING 0xa0
  102. #define R_A1_A_ACCUMULATION_LENGTH 0xa1
  103. #define R_A2_A_PRESCALER_DC_GAIN_AND_FIR_PREFILTER 0xa2
  104. #define R_A4_A_LUMA_BRIGHTNESS_CNTL 0xa4
  105. #define R_A5_A_LUMA_CONTRAST_CNTL 0xa5
  106. #define R_A6_A_CHROMA_SATURATION_CNTL 0xa6
  107. /* Horizontal phase scaling */
  108. #define R_A8_A_HORIZ_LUMA_SCALING_INC 0xa8
  109. #define R_A9_A_HORIZ_LUMA_SCALING_INC_MSB 0xa9
  110. #define R_AA_A_HORIZ_LUMA_PHASE_OFF 0xaa
  111. #define R_AC_A_HORIZ_CHROMA_SCALING_INC 0xac
  112. #define R_AD_A_HORIZ_CHROMA_SCALING_INC_MSB 0xad
  113. #define R_AE_A_HORIZ_CHROMA_PHASE_OFF 0xae
  114. #define R_AF_A_HORIZ_CHROMA_PHASE_OFF_MSB 0xaf
  115. /* Vertical scaling */
  116. #define R_B0_A_VERT_LUMA_SCALING_INC 0xb0
  117. #define R_B1_A_VERT_LUMA_SCALING_INC_MSB 0xb1
  118. #define R_B2_A_VERT_CHROMA_SCALING_INC 0xb2
  119. #define R_B3_A_VERT_CHROMA_SCALING_INC_MSB 0xb3
  120. #define R_B4_A_VERT_SCALING_MODE_CNTL 0xb4
  121. #define R_B8_A_VERT_CHROMA_PHASE_OFF_00 0xb8
  122. #define R_B9_A_VERT_CHROMA_PHASE_OFF_01 0xb9
  123. #define R_BA_A_VERT_CHROMA_PHASE_OFF_10 0xba
  124. #define R_BB_A_VERT_CHROMA_PHASE_OFF_11 0xbb
  125. #define R_BC_A_VERT_LUMA_PHASE_OFF_00 0xbc
  126. #define R_BD_A_VERT_LUMA_PHASE_OFF_01 0xbd
  127. #define R_BE_A_VERT_LUMA_PHASE_OFF_10 0xbe
  128. #define R_BF_A_VERT_LUMA_PHASE_OFF_11 0xbf
  129. /* Task B definition */
  130. /* Basic settings and acquisition window definition */
  131. #define R_C0_B_TASK_HANDLING_CNTL 0xc0
  132. #define R_C1_B_X_PORT_FORMATS_AND_CONF 0xc1
  133. #define R_C2_B_INPUT_REFERENCE_SIGNAL_DEFINITION 0xc2
  134. #define R_C3_B_I_PORT_FORMATS_AND_CONF 0xc3
  135. #define R_C4_B_HORIZ_INPUT_WINDOW_START 0xc4
  136. #define R_C5_B_HORIZ_INPUT_WINDOW_START_MSB 0xc5
  137. #define R_C6_B_HORIZ_INPUT_WINDOW_LENGTH 0xc6
  138. #define R_C7_B_HORIZ_INPUT_WINDOW_LENGTH_MSB 0xc7
  139. #define R_C8_B_VERT_INPUT_WINDOW_START 0xc8
  140. #define R_C9_B_VERT_INPUT_WINDOW_START_MSB 0xc9
  141. #define R_CA_B_VERT_INPUT_WINDOW_LENGTH 0xca
  142. #define R_CB_B_VERT_INPUT_WINDOW_LENGTH_MSB 0xcb
  143. #define R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH 0xcc
  144. #define R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB 0xcd
  145. #define R_CE_B_VERT_OUTPUT_WINDOW_LENGTH 0xce
  146. #define R_CF_B_VERT_OUTPUT_WINDOW_LENGTH_MSB 0xcf
  147. /* FIR filtering and prescaling */
  148. #define R_D0_B_HORIZ_PRESCALING 0xd0
  149. #define R_D1_B_ACCUMULATION_LENGTH 0xd1
  150. #define R_D2_B_PRESCALER_DC_GAIN_AND_FIR_PREFILTER 0xd2
  151. #define R_D4_B_LUMA_BRIGHTNESS_CNTL 0xd4
  152. #define R_D5_B_LUMA_CONTRAST_CNTL 0xd5
  153. #define R_D6_B_CHROMA_SATURATION_CNTL 0xd6
  154. /* Horizontal phase scaling */
  155. #define R_D8_B_HORIZ_LUMA_SCALING_INC 0xd8
  156. #define R_D9_B_HORIZ_LUMA_SCALING_INC_MSB 0xd9
  157. #define R_DA_B_HORIZ_LUMA_PHASE_OFF 0xda
  158. #define R_DC_B_HORIZ_CHROMA_SCALING 0xdc
  159. #define R_DD_B_HORIZ_CHROMA_SCALING_MSB 0xdd
  160. #define R_DE_B_HORIZ_PHASE_OFFSET_CRHOMA 0xde
  161. /* Vertical scaling */
  162. #define R_E0_B_VERT_LUMA_SCALING_INC 0xe0
  163. #define R_E1_B_VERT_LUMA_SCALING_INC_MSB 0xe1
  164. #define R_E2_B_VERT_CHROMA_SCALING_INC 0xe2
  165. #define R_E3_B_VERT_CHROMA_SCALING_INC_MSB 0xe3
  166. #define R_E4_B_VERT_SCALING_MODE_CNTL 0xe4
  167. #define R_E8_B_VERT_CHROMA_PHASE_OFF_00 0xe8
  168. #define R_E9_B_VERT_CHROMA_PHASE_OFF_01 0xe9
  169. #define R_EA_B_VERT_CHROMA_PHASE_OFF_10 0xea
  170. #define R_EB_B_VERT_CHROMA_PHASE_OFF_11 0xeb
  171. #define R_EC_B_VERT_LUMA_PHASE_OFF_00 0xec
  172. #define R_ED_B_VERT_LUMA_PHASE_OFF_01 0xed
  173. #define R_EE_B_VERT_LUMA_PHASE_OFF_10 0xee
  174. #define R_EF_B_VERT_LUMA_PHASE_OFF_11 0xef
  175. /* second PLL (PLL2) and Pulsegenerator Programming */
  176. #define R_F0_LFCO_PER_LINE 0xf0
  177. #define R_F1_P_I_PARAM_SELECT 0xf1
  178. #define R_F2_NOMINAL_PLL2_DTO 0xf2
  179. #define R_F3_PLL_INCREMENT 0xf3
  180. #define R_F4_PLL2_STATUS 0xf4
  181. #define R_F5_PULSGEN_LINE_LENGTH 0xf5
  182. #define R_F6_PULSE_A_POS_LSB_AND_PULSEGEN_CONFIG 0xf6
  183. #define R_F7_PULSE_A_POS_MSB 0xf7
  184. #define R_F8_PULSE_B_POS 0xf8
  185. #define R_F9_PULSE_B_POS_MSB 0xf9
  186. #define R_FA_PULSE_C_POS 0xfa
  187. #define R_FB_PULSE_C_POS_MSB 0xfb
  188. #define R_FF_S_PLL_MAX_PHASE_ERR_THRESH_NUM_LINES 0xff
  189. /* SAA7113 bit-masks */
  190. #define SAA7113_R_08_HTC_OFFSET 3
  191. #define SAA7113_R_08_HTC_MASK (0x3 << SAA7113_R_08_HTC_OFFSET)
  192. #define SAA7113_R_08_FSEL 0x40
  193. #define SAA7113_R_08_AUFD 0x80
  194. #define SAA7113_R_10_VRLN_OFFSET 3
  195. #define SAA7113_R_10_VRLN_MASK (0x1 << SAA7113_R_10_VRLN_OFFSET)
  196. #define SAA7113_R_10_OFTS_OFFSET 6
  197. #define SAA7113_R_10_OFTS_MASK (0x3 << SAA7113_R_10_OFTS_OFFSET)
  198. #define SAA7113_R_12_RTS0_OFFSET 0
  199. #define SAA7113_R_12_RTS0_MASK (0xf << SAA7113_R_12_RTS0_OFFSET)
  200. #define SAA7113_R_12_RTS1_OFFSET 4
  201. #define SAA7113_R_12_RTS1_MASK (0xf << SAA7113_R_12_RTS1_OFFSET)
  202. #define SAA7113_R_13_ADLSB_OFFSET 7
  203. #define SAA7113_R_13_ADLSB_MASK (0x1 << SAA7113_R_13_ADLSB_OFFSET)
  204. #if 0
  205. /* Those structs will be used in the future for debug purposes */
  206. struct saa711x_reg_descr {
  207. u8 reg;
  208. int count;
  209. char *name;
  210. };
  211. struct saa711x_reg_descr saa711x_regs[] = {
  212. /* REG COUNT NAME */
  213. {R_00_CHIP_VERSION,1,
  214. "Chip version"},
  215. /* Video Decoder: R_01_INC_DELAY to R_1F_STATUS_BYTE_2_VD_DEC */
  216. /* Video Decoder - Frontend part: R_01_INC_DELAY to R_05_INPUT_CNTL_4 */
  217. {R_01_INC_DELAY,1,
  218. "Increment delay"},
  219. {R_02_INPUT_CNTL_1,1,
  220. "Analog input control 1"},
  221. {R_03_INPUT_CNTL_2,1,
  222. "Analog input control 2"},
  223. {R_04_INPUT_CNTL_3,1,
  224. "Analog input control 3"},
  225. {R_05_INPUT_CNTL_4,1,
  226. "Analog input control 4"},
  227. /* Video Decoder - Decoder part: R_06_H_SYNC_START to R_1F_STATUS_BYTE_2_VD_DEC */
  228. {R_06_H_SYNC_START,1,
  229. "Horizontal sync start"},
  230. {R_07_H_SYNC_STOP,1,
  231. "Horizontal sync stop"},
  232. {R_08_SYNC_CNTL,1,
  233. "Sync control"},
  234. {R_09_LUMA_CNTL,1,
  235. "Luminance control"},
  236. {R_0A_LUMA_BRIGHT_CNTL,1,
  237. "Luminance brightness control"},
  238. {R_0B_LUMA_CONTRAST_CNTL,1,
  239. "Luminance contrast control"},
  240. {R_0C_CHROMA_SAT_CNTL,1,
  241. "Chrominance saturation control"},
  242. {R_0D_CHROMA_HUE_CNTL,1,
  243. "Chrominance hue control"},
  244. {R_0E_CHROMA_CNTL_1,1,
  245. "Chrominance control 1"},
  246. {R_0F_CHROMA_GAIN_CNTL,1,
  247. "Chrominance gain control"},
  248. {R_10_CHROMA_CNTL_2,1,
  249. "Chrominance control 2"},
  250. {R_11_MODE_DELAY_CNTL,1,
  251. "Mode/delay control"},
  252. {R_12_RT_SIGNAL_CNTL,1,
  253. "RT signal control"},
  254. {R_13_RT_X_PORT_OUT_CNTL,1,
  255. "RT/X port output control"},
  256. {R_14_ANAL_ADC_COMPAT_CNTL,1,
  257. "Analog/ADC/compatibility control"},
  258. {R_15_VGATE_START_FID_CHG, 1,
  259. "VGATE start FID change"},
  260. {R_16_VGATE_STOP,1,
  261. "VGATE stop"},
  262. {R_17_MISC_VGATE_CONF_AND_MSB, 1,
  263. "Miscellaneous VGATE configuration and MSBs"},
  264. {R_18_RAW_DATA_GAIN_CNTL,1,
  265. "Raw data gain control",},
  266. {R_19_RAW_DATA_OFF_CNTL,1,
  267. "Raw data offset control",},
  268. {R_1A_COLOR_KILL_LVL_CNTL,1,
  269. "Color Killer Level Control"},
  270. { R_1B_MISC_TVVCRDET, 1,
  271. "MISC /TVVCRDET"},
  272. { R_1C_ENHAN_COMB_CTRL1, 1,
  273. "Enhanced comb ctrl1"},
  274. { R_1D_ENHAN_COMB_CTRL2, 1,
  275. "Enhanced comb ctrl1"},
  276. {R_1E_STATUS_BYTE_1_VD_DEC,1,
  277. "Status byte 1 video decoder"},
  278. {R_1F_STATUS_BYTE_2_VD_DEC,1,
  279. "Status byte 2 video decoder"},
  280. /* Component processing and interrupt masking part: 0x20h to R_2F_INTERRUPT_MASK_3 */
  281. /* 0x20 to 0x22 - Reserved */
  282. {R_23_INPUT_CNTL_5,1,
  283. "Analog input control 5"},
  284. {R_24_INPUT_CNTL_6,1,
  285. "Analog input control 6"},
  286. {R_25_INPUT_CNTL_7,1,
  287. "Analog input control 7"},
  288. /* 0x26 to 0x28 - Reserved */
  289. {R_29_COMP_DELAY,1,
  290. "Component delay"},
  291. {R_2A_COMP_BRIGHT_CNTL,1,
  292. "Component brightness control"},
  293. {R_2B_COMP_CONTRAST_CNTL,1,
  294. "Component contrast control"},
  295. {R_2C_COMP_SAT_CNTL,1,
  296. "Component saturation control"},
  297. {R_2D_INTERRUPT_MASK_1,1,
  298. "Interrupt mask 1"},
  299. {R_2E_INTERRUPT_MASK_2,1,
  300. "Interrupt mask 2"},
  301. {R_2F_INTERRUPT_MASK_3,1,
  302. "Interrupt mask 3"},
  303. /* Audio clock generator part: R_30_AUD_MAST_CLK_CYCLES_PER_FIELD to 0x3f */
  304. {R_30_AUD_MAST_CLK_CYCLES_PER_FIELD,3,
  305. "Audio master clock cycles per field"},
  306. /* 0x33 - Reserved */
  307. {R_34_AUD_MAST_CLK_NOMINAL_INC,3,
  308. "Audio master clock nominal increment"},
  309. /* 0x37 - Reserved */
  310. {R_38_CLK_RATIO_AMXCLK_TO_ASCLK,1,
  311. "Clock ratio AMXCLK to ASCLK"},
  312. {R_39_CLK_RATIO_ASCLK_TO_ALRCLK,1,
  313. "Clock ratio ASCLK to ALRCLK"},
  314. {R_3A_AUD_CLK_GEN_BASIC_SETUP,1,
  315. "Audio clock generator basic setup"},
  316. /* 0x3b-0x3f - Reserved */
  317. /* General purpose VBI data slicer part: R_40_SLICER_CNTL_1 to 0x7f */
  318. {R_40_SLICER_CNTL_1,1,
  319. "Slicer control 1"},
  320. {R_41_LCR,23,
  321. "R_41_LCR"},
  322. {R_58_PROGRAM_FRAMING_CODE,1,
  323. "Programmable framing code"},
  324. {R_59_H_OFF_FOR_SLICER,1,
  325. "Horizontal offset for slicer"},
  326. {R_5A_V_OFF_FOR_SLICER,1,
  327. "Vertical offset for slicer"},
  328. {R_5B_FLD_OFF_AND_MSB_FOR_H_AND_V_OFF,1,
  329. "Field offset and MSBs for horizontal and vertical offset"},
  330. {R_5D_DID,1,
  331. "Header and data identification (R_5D_DID)"},
  332. {R_5E_SDID,1,
  333. "Sliced data identification (R_5E_SDID) code"},
  334. {R_60_SLICER_STATUS_BYTE_0,1,
  335. "Slicer status byte 0"},
  336. {R_61_SLICER_STATUS_BYTE_1,1,
  337. "Slicer status byte 1"},
  338. {R_62_SLICER_STATUS_BYTE_2,1,
  339. "Slicer status byte 2"},
  340. /* 0x63-0x7f - Reserved */
  341. /* X port, I port and the scaler part: R_80_GLOBAL_CNTL_1 to R_EF_B_VERT_LUMA_PHASE_OFF_11 */
  342. /* Task independent global settings: R_80_GLOBAL_CNTL_1 to R_8F_STATUS_INFO_SCALER */
  343. {R_80_GLOBAL_CNTL_1,1,
  344. "Global control 1"},
  345. {R_81_V_SYNC_FLD_ID_SRC_SEL_AND_RETIMED_V_F,1,
  346. "Vertical sync and Field ID source selection, retimed V and F signals"},
  347. /* 0x82 - Reserved */
  348. {R_83_X_PORT_I_O_ENA_AND_OUT_CLK,1,
  349. "X port I/O enable and output clock"},
  350. {R_84_I_PORT_SIGNAL_DEF,1,
  351. "I port signal definitions"},
  352. {R_85_I_PORT_SIGNAL_POLAR,1,
  353. "I port signal polarities"},
  354. {R_86_I_PORT_FIFO_FLAG_CNTL_AND_ARBIT,1,
  355. "I port FIFO flag control and arbitration"},
  356. {R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 1,
  357. "I port I/O enable output clock and gated"},
  358. {R_88_POWER_SAVE_ADC_PORT_CNTL,1,
  359. "Power save/ADC port control"},
  360. /* 089-0x8e - Reserved */
  361. {R_8F_STATUS_INFO_SCALER,1,
  362. "Status information scaler part"},
  363. /* Task A definition: R_90_A_TASK_HANDLING_CNTL to R_BF_A_VERT_LUMA_PHASE_OFF_11 */
  364. /* Task A: Basic settings and acquisition window definition */
  365. {R_90_A_TASK_HANDLING_CNTL,1,
  366. "Task A: Task handling control"},
  367. {R_91_A_X_PORT_FORMATS_AND_CONF,1,
  368. "Task A: X port formats and configuration"},
  369. {R_92_A_X_PORT_INPUT_REFERENCE_SIGNAL,1,
  370. "Task A: X port input reference signal definition"},
  371. {R_93_A_I_PORT_OUTPUT_FORMATS_AND_CONF,1,
  372. "Task A: I port output formats and configuration"},
  373. {R_94_A_HORIZ_INPUT_WINDOW_START,2,
  374. "Task A: Horizontal input window start"},
  375. {R_96_A_HORIZ_INPUT_WINDOW_LENGTH,2,
  376. "Task A: Horizontal input window length"},
  377. {R_98_A_VERT_INPUT_WINDOW_START,2,
  378. "Task A: Vertical input window start"},
  379. {R_9A_A_VERT_INPUT_WINDOW_LENGTH,2,
  380. "Task A: Vertical input window length"},
  381. {R_9C_A_HORIZ_OUTPUT_WINDOW_LENGTH,2,
  382. "Task A: Horizontal output window length"},
  383. {R_9E_A_VERT_OUTPUT_WINDOW_LENGTH,2,
  384. "Task A: Vertical output window length"},
  385. /* Task A: FIR filtering and prescaling */
  386. {R_A0_A_HORIZ_PRESCALING,1,
  387. "Task A: Horizontal prescaling"},
  388. {R_A1_A_ACCUMULATION_LENGTH,1,
  389. "Task A: Accumulation length"},
  390. {R_A2_A_PRESCALER_DC_GAIN_AND_FIR_PREFILTER,1,
  391. "Task A: Prescaler DC gain and FIR prefilter"},
  392. /* 0xa3 - Reserved */
  393. {R_A4_A_LUMA_BRIGHTNESS_CNTL,1,
  394. "Task A: Luminance brightness control"},
  395. {R_A5_A_LUMA_CONTRAST_CNTL,1,
  396. "Task A: Luminance contrast control"},
  397. {R_A6_A_CHROMA_SATURATION_CNTL,1,
  398. "Task A: Chrominance saturation control"},
  399. /* 0xa7 - Reserved */
  400. /* Task A: Horizontal phase scaling */
  401. {R_A8_A_HORIZ_LUMA_SCALING_INC,2,
  402. "Task A: Horizontal luminance scaling increment"},
  403. {R_AA_A_HORIZ_LUMA_PHASE_OFF,1,
  404. "Task A: Horizontal luminance phase offset"},
  405. /* 0xab - Reserved */
  406. {R_AC_A_HORIZ_CHROMA_SCALING_INC,2,
  407. "Task A: Horizontal chrominance scaling increment"},
  408. {R_AE_A_HORIZ_CHROMA_PHASE_OFF,1,
  409. "Task A: Horizontal chrominance phase offset"},
  410. /* 0xaf - Reserved */
  411. /* Task A: Vertical scaling */
  412. {R_B0_A_VERT_LUMA_SCALING_INC,2,
  413. "Task A: Vertical luminance scaling increment"},
  414. {R_B2_A_VERT_CHROMA_SCALING_INC,2,
  415. "Task A: Vertical chrominance scaling increment"},
  416. {R_B4_A_VERT_SCALING_MODE_CNTL,1,
  417. "Task A: Vertical scaling mode control"},
  418. /* 0xb5-0xb7 - Reserved */
  419. {R_B8_A_VERT_CHROMA_PHASE_OFF_00,1,
  420. "Task A: Vertical chrominance phase offset '00'"},
  421. {R_B9_A_VERT_CHROMA_PHASE_OFF_01,1,
  422. "Task A: Vertical chrominance phase offset '01'"},
  423. {R_BA_A_VERT_CHROMA_PHASE_OFF_10,1,
  424. "Task A: Vertical chrominance phase offset '10'"},
  425. {R_BB_A_VERT_CHROMA_PHASE_OFF_11,1,
  426. "Task A: Vertical chrominance phase offset '11'"},
  427. {R_BC_A_VERT_LUMA_PHASE_OFF_00,1,
  428. "Task A: Vertical luminance phase offset '00'"},
  429. {R_BD_A_VERT_LUMA_PHASE_OFF_01,1,
  430. "Task A: Vertical luminance phase offset '01'"},
  431. {R_BE_A_VERT_LUMA_PHASE_OFF_10,1,
  432. "Task A: Vertical luminance phase offset '10'"},
  433. {R_BF_A_VERT_LUMA_PHASE_OFF_11,1,
  434. "Task A: Vertical luminance phase offset '11'"},
  435. /* Task B definition: R_C0_B_TASK_HANDLING_CNTL to R_EF_B_VERT_LUMA_PHASE_OFF_11 */
  436. /* Task B: Basic settings and acquisition window definition */
  437. {R_C0_B_TASK_HANDLING_CNTL,1,
  438. "Task B: Task handling control"},
  439. {R_C1_B_X_PORT_FORMATS_AND_CONF,1,
  440. "Task B: X port formats and configuration"},
  441. {R_C2_B_INPUT_REFERENCE_SIGNAL_DEFINITION,1,
  442. "Task B: Input reference signal definition"},
  443. {R_C3_B_I_PORT_FORMATS_AND_CONF,1,
  444. "Task B: I port formats and configuration"},
  445. {R_C4_B_HORIZ_INPUT_WINDOW_START,2,
  446. "Task B: Horizontal input window start"},
  447. {R_C6_B_HORIZ_INPUT_WINDOW_LENGTH,2,
  448. "Task B: Horizontal input window length"},
  449. {R_C8_B_VERT_INPUT_WINDOW_START,2,
  450. "Task B: Vertical input window start"},
  451. {R_CA_B_VERT_INPUT_WINDOW_LENGTH,2,
  452. "Task B: Vertical input window length"},
  453. {R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH,2,
  454. "Task B: Horizontal output window length"},
  455. {R_CE_B_VERT_OUTPUT_WINDOW_LENGTH,2,
  456. "Task B: Vertical output window length"},
  457. /* Task B: FIR filtering and prescaling */
  458. {R_D0_B_HORIZ_PRESCALING,1,
  459. "Task B: Horizontal prescaling"},
  460. {R_D1_B_ACCUMULATION_LENGTH,1,
  461. "Task B: Accumulation length"},
  462. {R_D2_B_PRESCALER_DC_GAIN_AND_FIR_PREFILTER,1,
  463. "Task B: Prescaler DC gain and FIR prefilter"},
  464. /* 0xd3 - Reserved */
  465. {R_D4_B_LUMA_BRIGHTNESS_CNTL,1,
  466. "Task B: Luminance brightness control"},
  467. {R_D5_B_LUMA_CONTRAST_CNTL,1,
  468. "Task B: Luminance contrast control"},
  469. {R_D6_B_CHROMA_SATURATION_CNTL,1,
  470. "Task B: Chrominance saturation control"},
  471. /* 0xd7 - Reserved */
  472. /* Task B: Horizontal phase scaling */
  473. {R_D8_B_HORIZ_LUMA_SCALING_INC,2,
  474. "Task B: Horizontal luminance scaling increment"},
  475. {R_DA_B_HORIZ_LUMA_PHASE_OFF,1,
  476. "Task B: Horizontal luminance phase offset"},
  477. /* 0xdb - Reserved */
  478. {R_DC_B_HORIZ_CHROMA_SCALING,2,
  479. "Task B: Horizontal chrominance scaling"},
  480. {R_DE_B_HORIZ_PHASE_OFFSET_CRHOMA,1,
  481. "Task B: Horizontal Phase Offset Chroma"},
  482. /* 0xdf - Reserved */
  483. /* Task B: Vertical scaling */
  484. {R_E0_B_VERT_LUMA_SCALING_INC,2,
  485. "Task B: Vertical luminance scaling increment"},
  486. {R_E2_B_VERT_CHROMA_SCALING_INC,2,
  487. "Task B: Vertical chrominance scaling increment"},
  488. {R_E4_B_VERT_SCALING_MODE_CNTL,1,
  489. "Task B: Vertical scaling mode control"},
  490. /* 0xe5-0xe7 - Reserved */
  491. {R_E8_B_VERT_CHROMA_PHASE_OFF_00,1,
  492. "Task B: Vertical chrominance phase offset '00'"},
  493. {R_E9_B_VERT_CHROMA_PHASE_OFF_01,1,
  494. "Task B: Vertical chrominance phase offset '01'"},
  495. {R_EA_B_VERT_CHROMA_PHASE_OFF_10,1,
  496. "Task B: Vertical chrominance phase offset '10'"},
  497. {R_EB_B_VERT_CHROMA_PHASE_OFF_11,1,
  498. "Task B: Vertical chrominance phase offset '11'"},
  499. {R_EC_B_VERT_LUMA_PHASE_OFF_00,1,
  500. "Task B: Vertical luminance phase offset '00'"},
  501. {R_ED_B_VERT_LUMA_PHASE_OFF_01,1,
  502. "Task B: Vertical luminance phase offset '01'"},
  503. {R_EE_B_VERT_LUMA_PHASE_OFF_10,1,
  504. "Task B: Vertical luminance phase offset '10'"},
  505. {R_EF_B_VERT_LUMA_PHASE_OFF_11,1,
  506. "Task B: Vertical luminance phase offset '11'"},
  507. /* second PLL (PLL2) and Pulsegenerator Programming */
  508. { R_F0_LFCO_PER_LINE, 1,
  509. "LFCO's per line"},
  510. { R_F1_P_I_PARAM_SELECT,1,
  511. "P-/I- Param. Select., PLL Mode, PLL H-Src., LFCO's per line"},
  512. { R_F2_NOMINAL_PLL2_DTO,1,
  513. "Nominal PLL2 DTO"},
  514. {R_F3_PLL_INCREMENT,1,
  515. "PLL2 Increment"},
  516. {R_F4_PLL2_STATUS,1,
  517. "PLL2 Status"},
  518. {R_F5_PULSGEN_LINE_LENGTH,1,
  519. "Pulsgen. line length"},
  520. {R_F6_PULSE_A_POS_LSB_AND_PULSEGEN_CONFIG,1,
  521. "Pulse A Position, Pulsgen Resync., Pulsgen. H-Src., Pulsgen. line length"},
  522. {R_F7_PULSE_A_POS_MSB,1,
  523. "Pulse A Position"},
  524. {R_F8_PULSE_B_POS,2,
  525. "Pulse B Position"},
  526. {R_FA_PULSE_C_POS,2,
  527. "Pulse C Position"},
  528. /* 0xfc to 0xfe - Reserved */
  529. {R_FF_S_PLL_MAX_PHASE_ERR_THRESH_NUM_LINES,1,
  530. "S_PLL max. phase, error threshold, PLL2 no. of lines, threshold"},
  531. };
  532. #endif