ov9650.c 42 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Omnivision OV9650/OV9652 CMOS Image Sensor driver
  4. *
  5. * Copyright (C) 2013, Sylwester Nawrocki <sylvester.nawrocki@gmail.com>
  6. *
  7. * Register definitions and initial settings based on a driver written
  8. * by Vladimir Fonov.
  9. * Copyright (c) 2010, Vladimir Fonov
  10. */
  11. #include <linux/clk.h>
  12. #include <linux/delay.h>
  13. #include <linux/gpio.h>
  14. #include <linux/gpio/consumer.h>
  15. #include <linux/i2c.h>
  16. #include <linux/kernel.h>
  17. #include <linux/media.h>
  18. #include <linux/module.h>
  19. #include <linux/ratelimit.h>
  20. #include <linux/regmap.h>
  21. #include <linux/slab.h>
  22. #include <linux/string.h>
  23. #include <linux/videodev2.h>
  24. #include <media/media-entity.h>
  25. #include <media/v4l2-async.h>
  26. #include <media/v4l2-ctrls.h>
  27. #include <media/v4l2-device.h>
  28. #include <media/v4l2-event.h>
  29. #include <media/v4l2-image-sizes.h>
  30. #include <media/v4l2-subdev.h>
  31. #include <media/v4l2-mediabus.h>
  32. #include <media/i2c/ov9650.h>
  33. static int debug;
  34. module_param(debug, int, 0644);
  35. MODULE_PARM_DESC(debug, "Debug level (0-2)");
  36. #define DRIVER_NAME "OV9650"
  37. /*
  38. * OV9650/OV9652 register definitions
  39. */
  40. #define REG_GAIN 0x00 /* Gain control, AGC[7:0] */
  41. #define REG_BLUE 0x01 /* AWB - Blue channel gain */
  42. #define REG_RED 0x02 /* AWB - Red channel gain */
  43. #define REG_VREF 0x03 /* [7:6] - AGC[9:8], [5:3]/[2:0] */
  44. #define VREF_GAIN_MASK 0xc0 /* - VREF end/start low 3 bits */
  45. #define REG_COM1 0x04
  46. #define COM1_CCIR656 0x40
  47. #define REG_B_AVE 0x05
  48. #define REG_GB_AVE 0x06
  49. #define REG_GR_AVE 0x07
  50. #define REG_R_AVE 0x08
  51. #define REG_COM2 0x09
  52. #define REG_PID 0x0a /* Product ID MSB */
  53. #define REG_VER 0x0b /* Product ID LSB */
  54. #define REG_COM3 0x0c
  55. #define COM3_SWAP 0x40
  56. #define COM3_VARIOPIXEL1 0x04
  57. #define REG_COM4 0x0d /* Vario Pixels */
  58. #define COM4_VARIOPIXEL2 0x80
  59. #define REG_COM5 0x0e /* System clock options */
  60. #define COM5_SLAVE_MODE 0x10
  61. #define COM5_SYSTEMCLOCK48MHZ 0x80
  62. #define REG_COM6 0x0f /* HREF & ADBLC options */
  63. #define REG_AECH 0x10 /* Exposure value, AEC[9:2] */
  64. #define REG_CLKRC 0x11 /* Clock control */
  65. #define CLK_EXT 0x40 /* Use external clock directly */
  66. #define CLK_SCALE 0x3f /* Mask for internal clock scale */
  67. #define REG_COM7 0x12 /* SCCB reset, output format */
  68. #define COM7_RESET 0x80
  69. #define COM7_FMT_MASK 0x38
  70. #define COM7_FMT_VGA 0x40
  71. #define COM7_FMT_CIF 0x20
  72. #define COM7_FMT_QVGA 0x10
  73. #define COM7_FMT_QCIF 0x08
  74. #define COM7_RGB 0x04
  75. #define COM7_YUV 0x00
  76. #define COM7_BAYER 0x01
  77. #define COM7_PBAYER 0x05
  78. #define REG_COM8 0x13 /* AGC/AEC options */
  79. #define COM8_FASTAEC 0x80 /* Enable fast AGC/AEC */
  80. #define COM8_AECSTEP 0x40 /* Unlimited AEC step size */
  81. #define COM8_BFILT 0x20 /* Band filter enable */
  82. #define COM8_AGC 0x04 /* Auto gain enable */
  83. #define COM8_AWB 0x02 /* White balance enable */
  84. #define COM8_AEC 0x01 /* Auto exposure enable */
  85. #define REG_COM9 0x14 /* Gain ceiling */
  86. #define COM9_GAIN_CEIL_MASK 0x70 /* */
  87. #define REG_COM10 0x15 /* PCLK, HREF, HSYNC signals polarity */
  88. #define COM10_HSYNC 0x40 /* HSYNC instead of HREF */
  89. #define COM10_PCLK_HB 0x20 /* Suppress PCLK on horiz blank */
  90. #define COM10_HREF_REV 0x08 /* Reverse HREF */
  91. #define COM10_VS_LEAD 0x04 /* VSYNC on clock leading edge */
  92. #define COM10_VS_NEG 0x02 /* VSYNC negative */
  93. #define COM10_HS_NEG 0x01 /* HSYNC negative */
  94. #define REG_HSTART 0x17 /* Horiz start high bits */
  95. #define REG_HSTOP 0x18 /* Horiz stop high bits */
  96. #define REG_VSTART 0x19 /* Vert start high bits */
  97. #define REG_VSTOP 0x1a /* Vert stop high bits */
  98. #define REG_PSHFT 0x1b /* Pixel delay after HREF */
  99. #define REG_MIDH 0x1c /* Manufacturer ID MSB */
  100. #define REG_MIDL 0x1d /* Manufufacturer ID LSB */
  101. #define REG_MVFP 0x1e /* Image mirror/flip */
  102. #define MVFP_MIRROR 0x20 /* Mirror image */
  103. #define MVFP_FLIP 0x10 /* Vertical flip */
  104. #define REG_BOS 0x20 /* B channel Offset */
  105. #define REG_GBOS 0x21 /* Gb channel Offset */
  106. #define REG_GROS 0x22 /* Gr channel Offset */
  107. #define REG_ROS 0x23 /* R channel Offset */
  108. #define REG_AEW 0x24 /* AGC upper limit */
  109. #define REG_AEB 0x25 /* AGC lower limit */
  110. #define REG_VPT 0x26 /* AGC/AEC fast mode op region */
  111. #define REG_BBIAS 0x27 /* B channel output bias */
  112. #define REG_GBBIAS 0x28 /* Gb channel output bias */
  113. #define REG_GRCOM 0x29 /* Analog BLC & regulator */
  114. #define REG_EXHCH 0x2a /* Dummy pixel insert MSB */
  115. #define REG_EXHCL 0x2b /* Dummy pixel insert LSB */
  116. #define REG_RBIAS 0x2c /* R channel output bias */
  117. #define REG_ADVFL 0x2d /* LSB of dummy line insert */
  118. #define REG_ADVFH 0x2e /* MSB of dummy line insert */
  119. #define REG_YAVE 0x2f /* Y/G channel average value */
  120. #define REG_HSYST 0x30 /* HSYNC rising edge delay LSB*/
  121. #define REG_HSYEN 0x31 /* HSYNC falling edge delay LSB*/
  122. #define REG_HREF 0x32 /* HREF pieces */
  123. #define REG_CHLF 0x33 /* reserved */
  124. #define REG_ADC 0x37 /* reserved */
  125. #define REG_ACOM 0x38 /* reserved */
  126. #define REG_OFON 0x39 /* Power down register */
  127. #define OFON_PWRDN 0x08 /* Power down bit */
  128. #define REG_TSLB 0x3a /* YUVU format */
  129. #define TSLB_YUYV_MASK 0x0c /* UYVY or VYUY - see com13 */
  130. #define REG_COM11 0x3b /* Night mode, banding filter enable */
  131. #define COM11_NIGHT 0x80 /* Night mode enable */
  132. #define COM11_NMFR 0x60 /* Two bit NM frame rate */
  133. #define COM11_BANDING 0x01 /* Banding filter */
  134. #define COM11_AEC_REF_MASK 0x18 /* AEC reference area selection */
  135. #define REG_COM12 0x3c /* HREF option, UV average */
  136. #define COM12_HREF 0x80 /* HREF always */
  137. #define REG_COM13 0x3d /* Gamma selection, Color matrix en. */
  138. #define COM13_GAMMA 0x80 /* Gamma enable */
  139. #define COM13_UVSAT 0x40 /* UV saturation auto adjustment */
  140. #define COM13_UVSWAP 0x01 /* V before U - w/TSLB */
  141. #define REG_COM14 0x3e /* Edge enhancement options */
  142. #define COM14_EDGE_EN 0x02
  143. #define COM14_EEF_X2 0x01
  144. #define REG_EDGE 0x3f /* Edge enhancement factor */
  145. #define EDGE_FACTOR_MASK 0x0f
  146. #define REG_COM15 0x40 /* Output range, RGB 555/565 */
  147. #define COM15_R10F0 0x00 /* Data range 10 to F0 */
  148. #define COM15_R01FE 0x80 /* 01 to FE */
  149. #define COM15_R00FF 0xc0 /* 00 to FF */
  150. #define COM15_RGB565 0x10 /* RGB565 output */
  151. #define COM15_RGB555 0x30 /* RGB555 output */
  152. #define COM15_SWAPRB 0x04 /* Swap R&B */
  153. #define REG_COM16 0x41 /* Color matrix coeff options */
  154. #define REG_COM17 0x42 /* Single frame out, banding filter */
  155. /* n = 1...9, 0x4f..0x57 */
  156. #define REG_MTX(__n) (0x4f + (__n) - 1)
  157. #define REG_MTXS 0x58
  158. /* Lens Correction Option 1...5, __n = 0...5 */
  159. #define REG_LCC(__n) (0x62 + (__n) - 1)
  160. #define LCC5_LCC_ENABLE 0x01 /* LCC5, enable lens correction */
  161. #define LCC5_LCC_COLOR 0x04
  162. #define REG_MANU 0x67 /* Manual U value */
  163. #define REG_MANV 0x68 /* Manual V value */
  164. #define REG_HV 0x69 /* Manual banding filter MSB */
  165. #define REG_MBD 0x6a /* Manual banding filter value */
  166. #define REG_DBLV 0x6b /* reserved */
  167. #define REG_GSP 0x6c /* Gamma curve */
  168. #define GSP_LEN 15
  169. #define REG_GST 0x7c /* Gamma curve */
  170. #define GST_LEN 15
  171. #define REG_COM21 0x8b
  172. #define REG_COM22 0x8c /* Edge enhancement, denoising */
  173. #define COM22_WHTPCOR 0x02 /* White pixel correction enable */
  174. #define COM22_WHTPCOROPT 0x01 /* White pixel correction option */
  175. #define COM22_DENOISE 0x10 /* White pixel correction option */
  176. #define REG_COM23 0x8d /* Color bar test, color gain */
  177. #define COM23_TEST_MODE 0x10
  178. #define REG_DBLC1 0x8f /* Digital BLC */
  179. #define REG_DBLC_B 0x90 /* Digital BLC B channel offset */
  180. #define REG_DBLC_R 0x91 /* Digital BLC R channel offset */
  181. #define REG_DM_LNL 0x92 /* Dummy line low 8 bits */
  182. #define REG_DM_LNH 0x93 /* Dummy line high 8 bits */
  183. #define REG_LCCFB 0x9d /* Lens Correction B channel */
  184. #define REG_LCCFR 0x9e /* Lens Correction R channel */
  185. #define REG_DBLC_GB 0x9f /* Digital BLC GB chan offset */
  186. #define REG_DBLC_GR 0xa0 /* Digital BLC GR chan offset */
  187. #define REG_AECHM 0xa1 /* Exposure value - bits AEC[15:10] */
  188. #define REG_BD50ST 0xa2 /* Banding filter value for 50Hz */
  189. #define REG_BD60ST 0xa3 /* Banding filter value for 60Hz */
  190. #define REG_NULL 0xff /* Array end token */
  191. #define DEF_CLKRC 0x80
  192. #define OV965X_ID(_msb, _lsb) ((_msb) << 8 | (_lsb))
  193. #define OV9650_ID 0x9650
  194. #define OV9652_ID 0x9652
  195. struct ov965x_ctrls {
  196. struct v4l2_ctrl_handler handler;
  197. struct {
  198. struct v4l2_ctrl *auto_exp;
  199. struct v4l2_ctrl *exposure;
  200. };
  201. struct {
  202. struct v4l2_ctrl *auto_wb;
  203. struct v4l2_ctrl *blue_balance;
  204. struct v4l2_ctrl *red_balance;
  205. };
  206. struct {
  207. struct v4l2_ctrl *hflip;
  208. struct v4l2_ctrl *vflip;
  209. };
  210. struct {
  211. struct v4l2_ctrl *auto_gain;
  212. struct v4l2_ctrl *gain;
  213. };
  214. struct v4l2_ctrl *brightness;
  215. struct v4l2_ctrl *saturation;
  216. struct v4l2_ctrl *sharpness;
  217. struct v4l2_ctrl *light_freq;
  218. u8 update;
  219. };
  220. struct ov965x_framesize {
  221. u16 width;
  222. u16 height;
  223. u16 max_exp_lines;
  224. const u8 *regs;
  225. };
  226. struct ov965x_interval {
  227. struct v4l2_fract interval;
  228. /* Maximum resolution for this interval */
  229. struct v4l2_frmsize_discrete size;
  230. u8 clkrc_div;
  231. };
  232. enum gpio_id {
  233. GPIO_PWDN,
  234. GPIO_RST,
  235. NUM_GPIOS,
  236. };
  237. struct ov965x {
  238. struct v4l2_subdev sd;
  239. struct media_pad pad;
  240. enum v4l2_mbus_type bus_type;
  241. struct gpio_desc *gpios[NUM_GPIOS];
  242. /* External master clock frequency */
  243. unsigned long mclk_frequency;
  244. struct clk *clk;
  245. /* Protects the struct fields below */
  246. struct mutex lock;
  247. struct regmap *regmap;
  248. /* Exposure row interval in us */
  249. unsigned int exp_row_interval;
  250. unsigned short id;
  251. const struct ov965x_framesize *frame_size;
  252. /* YUYV sequence (pixel format) control register */
  253. u8 tslb_reg;
  254. struct v4l2_mbus_framefmt format;
  255. struct ov965x_ctrls ctrls;
  256. /* Pointer to frame rate control data structure */
  257. const struct ov965x_interval *fiv;
  258. int streaming;
  259. int power;
  260. u8 apply_frame_fmt;
  261. };
  262. struct i2c_rv {
  263. u8 addr;
  264. u8 value;
  265. };
  266. static const struct i2c_rv ov965x_init_regs[] = {
  267. { REG_COM2, 0x10 }, /* Set soft sleep mode */
  268. { REG_COM5, 0x00 }, /* System clock options */
  269. { REG_COM2, 0x01 }, /* Output drive, soft sleep mode */
  270. { REG_COM10, 0x00 }, /* Slave mode, HREF vs HSYNC, signals negate */
  271. { REG_EDGE, 0xa6 }, /* Edge enhancement treshhold and factor */
  272. { REG_COM16, 0x02 }, /* Color matrix coeff double option */
  273. { REG_COM17, 0x08 }, /* Single frame out, banding filter */
  274. { 0x16, 0x06 },
  275. { REG_CHLF, 0xc0 }, /* Reserved */
  276. { 0x34, 0xbf },
  277. { 0xa8, 0x80 },
  278. { 0x96, 0x04 },
  279. { 0x8e, 0x00 },
  280. { REG_COM12, 0x77 }, /* HREF option, UV average */
  281. { 0x8b, 0x06 },
  282. { 0x35, 0x91 },
  283. { 0x94, 0x88 },
  284. { 0x95, 0x88 },
  285. { REG_COM15, 0xc1 }, /* Output range, RGB 555/565 */
  286. { REG_GRCOM, 0x2f }, /* Analog BLC & regulator */
  287. { REG_COM6, 0x43 }, /* HREF & ADBLC options */
  288. { REG_COM8, 0xe5 }, /* AGC/AEC options */
  289. { REG_COM13, 0x90 }, /* Gamma selection, colour matrix, UV delay */
  290. { REG_HV, 0x80 }, /* Manual banding filter MSB */
  291. { 0x5c, 0x96 }, /* Reserved up to 0xa5 */
  292. { 0x5d, 0x96 },
  293. { 0x5e, 0x10 },
  294. { 0x59, 0xeb },
  295. { 0x5a, 0x9c },
  296. { 0x5b, 0x55 },
  297. { 0x43, 0xf0 },
  298. { 0x44, 0x10 },
  299. { 0x45, 0x55 },
  300. { 0x46, 0x86 },
  301. { 0x47, 0x64 },
  302. { 0x48, 0x86 },
  303. { 0x5f, 0xe0 },
  304. { 0x60, 0x8c },
  305. { 0x61, 0x20 },
  306. { 0xa5, 0xd9 },
  307. { 0xa4, 0x74 }, /* reserved */
  308. { REG_COM23, 0x02 }, /* Color gain analog/_digital_ */
  309. { REG_COM8, 0xe7 }, /* Enable AEC, AWB, AEC */
  310. { REG_COM22, 0x23 }, /* Edge enhancement, denoising */
  311. { 0xa9, 0xb8 },
  312. { 0xaa, 0x92 },
  313. { 0xab, 0x0a },
  314. { REG_DBLC1, 0xdf }, /* Digital BLC */
  315. { REG_DBLC_B, 0x00 }, /* Digital BLC B chan offset */
  316. { REG_DBLC_R, 0x00 }, /* Digital BLC R chan offset */
  317. { REG_DBLC_GB, 0x00 }, /* Digital BLC GB chan offset */
  318. { REG_DBLC_GR, 0x00 },
  319. { REG_COM9, 0x3a }, /* Gain ceiling 16x */
  320. { REG_NULL, 0 }
  321. };
  322. #define NUM_FMT_REGS 14
  323. /*
  324. * COM7, COM3, COM4, HSTART, HSTOP, HREF, VSTART, VSTOP, VREF,
  325. * EXHCH, EXHCL, ADC, OCOM, OFON
  326. */
  327. static const u8 frame_size_reg_addr[NUM_FMT_REGS] = {
  328. 0x12, 0x0c, 0x0d, 0x17, 0x18, 0x32, 0x19, 0x1a, 0x03,
  329. 0x2a, 0x2b, 0x37, 0x38, 0x39,
  330. };
  331. static const u8 ov965x_sxga_regs[NUM_FMT_REGS] = {
  332. 0x00, 0x00, 0x00, 0x1e, 0xbe, 0xbf, 0x01, 0x81, 0x12,
  333. 0x10, 0x34, 0x81, 0x93, 0x51,
  334. };
  335. static const u8 ov965x_vga_regs[NUM_FMT_REGS] = {
  336. 0x40, 0x04, 0x80, 0x26, 0xc6, 0xed, 0x01, 0x3d, 0x00,
  337. 0x10, 0x40, 0x91, 0x12, 0x43,
  338. };
  339. /* Determined empirically. */
  340. static const u8 ov965x_qvga_regs[NUM_FMT_REGS] = {
  341. 0x10, 0x04, 0x80, 0x25, 0xc5, 0xbf, 0x00, 0x80, 0x12,
  342. 0x10, 0x40, 0x91, 0x12, 0x43,
  343. };
  344. static const struct ov965x_framesize ov965x_framesizes[] = {
  345. {
  346. .width = SXGA_WIDTH,
  347. .height = SXGA_HEIGHT,
  348. .regs = ov965x_sxga_regs,
  349. .max_exp_lines = 1048,
  350. }, {
  351. .width = VGA_WIDTH,
  352. .height = VGA_HEIGHT,
  353. .regs = ov965x_vga_regs,
  354. .max_exp_lines = 498,
  355. }, {
  356. .width = QVGA_WIDTH,
  357. .height = QVGA_HEIGHT,
  358. .regs = ov965x_qvga_regs,
  359. .max_exp_lines = 248,
  360. },
  361. };
  362. struct ov965x_pixfmt {
  363. u32 code;
  364. u32 colorspace;
  365. /* REG_TSLB value, only bits [3:2] may be set. */
  366. u8 tslb_reg;
  367. };
  368. static const struct ov965x_pixfmt ov965x_formats[] = {
  369. { MEDIA_BUS_FMT_YUYV8_2X8, V4L2_COLORSPACE_JPEG, 0x00},
  370. { MEDIA_BUS_FMT_YVYU8_2X8, V4L2_COLORSPACE_JPEG, 0x04},
  371. { MEDIA_BUS_FMT_UYVY8_2X8, V4L2_COLORSPACE_JPEG, 0x0c},
  372. { MEDIA_BUS_FMT_VYUY8_2X8, V4L2_COLORSPACE_JPEG, 0x08},
  373. };
  374. /*
  375. * This table specifies possible frame resolution and interval
  376. * combinations. Default CLKRC[5:0] divider values are valid
  377. * only for 24 MHz external clock frequency.
  378. */
  379. static struct ov965x_interval ov965x_intervals[] = {
  380. {{ 100, 625 }, { SXGA_WIDTH, SXGA_HEIGHT }, 0 }, /* 6.25 fps */
  381. {{ 10, 125 }, { VGA_WIDTH, VGA_HEIGHT }, 1 }, /* 12.5 fps */
  382. {{ 10, 125 }, { QVGA_WIDTH, QVGA_HEIGHT }, 3 }, /* 12.5 fps */
  383. {{ 1, 25 }, { VGA_WIDTH, VGA_HEIGHT }, 0 }, /* 25 fps */
  384. {{ 1, 25 }, { QVGA_WIDTH, QVGA_HEIGHT }, 1 }, /* 25 fps */
  385. };
  386. static inline struct v4l2_subdev *ctrl_to_sd(struct v4l2_ctrl *ctrl)
  387. {
  388. return &container_of(ctrl->handler, struct ov965x, ctrls.handler)->sd;
  389. }
  390. static inline struct ov965x *to_ov965x(struct v4l2_subdev *sd)
  391. {
  392. return container_of(sd, struct ov965x, sd);
  393. }
  394. static int ov965x_read(struct ov965x *ov965x, u8 addr, u8 *val)
  395. {
  396. int ret;
  397. unsigned int buf;
  398. ret = regmap_read(ov965x->regmap, addr, &buf);
  399. if (!ret)
  400. *val = buf;
  401. else
  402. *val = -1;
  403. v4l2_dbg(2, debug, &ov965x->sd, "%s: 0x%02x @ 0x%02x. (%d)\n",
  404. __func__, *val, addr, ret);
  405. return ret;
  406. }
  407. static int ov965x_write(struct ov965x *ov965x, u8 addr, u8 val)
  408. {
  409. int ret;
  410. ret = regmap_write(ov965x->regmap, addr, val);
  411. v4l2_dbg(2, debug, &ov965x->sd, "%s: 0x%02x @ 0x%02X (%d)\n",
  412. __func__, val, addr, ret);
  413. return ret;
  414. }
  415. static int ov965x_write_array(struct ov965x *ov965x,
  416. const struct i2c_rv *regs)
  417. {
  418. int i, ret = 0;
  419. for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
  420. ret = ov965x_write(ov965x, regs[i].addr, regs[i].value);
  421. return ret;
  422. }
  423. static int ov965x_set_default_gamma_curve(struct ov965x *ov965x)
  424. {
  425. static const u8 gamma_curve[] = {
  426. /* Values taken from OV application note. */
  427. 0x40, 0x30, 0x4b, 0x60, 0x70, 0x70, 0x70, 0x70,
  428. 0x60, 0x60, 0x50, 0x48, 0x3a, 0x2e, 0x28, 0x22,
  429. 0x04, 0x07, 0x10, 0x28, 0x36, 0x44, 0x52, 0x60,
  430. 0x6c, 0x78, 0x8c, 0x9e, 0xbb, 0xd2, 0xe6
  431. };
  432. u8 addr = REG_GSP;
  433. unsigned int i;
  434. for (i = 0; i < ARRAY_SIZE(gamma_curve); i++) {
  435. int ret = ov965x_write(ov965x, addr, gamma_curve[i]);
  436. if (ret < 0)
  437. return ret;
  438. addr++;
  439. }
  440. return 0;
  441. };
  442. static int ov965x_set_color_matrix(struct ov965x *ov965x)
  443. {
  444. static const u8 mtx[] = {
  445. /* MTX1..MTX9, MTXS */
  446. 0x3a, 0x3d, 0x03, 0x12, 0x26, 0x38, 0x40, 0x40, 0x40, 0x0d
  447. };
  448. u8 addr = REG_MTX(1);
  449. unsigned int i;
  450. for (i = 0; i < ARRAY_SIZE(mtx); i++) {
  451. int ret = ov965x_write(ov965x, addr, mtx[i]);
  452. if (ret < 0)
  453. return ret;
  454. addr++;
  455. }
  456. return 0;
  457. }
  458. static int __ov965x_set_power(struct ov965x *ov965x, int on)
  459. {
  460. if (on) {
  461. int ret = clk_prepare_enable(ov965x->clk);
  462. if (ret)
  463. return ret;
  464. gpiod_set_value_cansleep(ov965x->gpios[GPIO_PWDN], 0);
  465. gpiod_set_value_cansleep(ov965x->gpios[GPIO_RST], 0);
  466. msleep(25);
  467. } else {
  468. gpiod_set_value_cansleep(ov965x->gpios[GPIO_RST], 1);
  469. gpiod_set_value_cansleep(ov965x->gpios[GPIO_PWDN], 1);
  470. clk_disable_unprepare(ov965x->clk);
  471. }
  472. ov965x->streaming = 0;
  473. return 0;
  474. }
  475. static int ov965x_s_power(struct v4l2_subdev *sd, int on)
  476. {
  477. struct ov965x *ov965x = to_ov965x(sd);
  478. int ret = 0;
  479. v4l2_dbg(1, debug, sd, "%s: on: %d\n", __func__, on);
  480. mutex_lock(&ov965x->lock);
  481. if (ov965x->power == !on) {
  482. ret = __ov965x_set_power(ov965x, on);
  483. if (!ret && on) {
  484. ret = ov965x_write_array(ov965x,
  485. ov965x_init_regs);
  486. ov965x->apply_frame_fmt = 1;
  487. ov965x->ctrls.update = 1;
  488. }
  489. }
  490. if (!ret)
  491. ov965x->power += on ? 1 : -1;
  492. WARN_ON(ov965x->power < 0);
  493. mutex_unlock(&ov965x->lock);
  494. return ret;
  495. }
  496. /*
  497. * V4L2 controls
  498. */
  499. static void ov965x_update_exposure_ctrl(struct ov965x *ov965x)
  500. {
  501. struct v4l2_ctrl *ctrl = ov965x->ctrls.exposure;
  502. unsigned long fint, trow;
  503. int min, max, def;
  504. u8 clkrc;
  505. mutex_lock(&ov965x->lock);
  506. if (WARN_ON(!ctrl || !ov965x->frame_size)) {
  507. mutex_unlock(&ov965x->lock);
  508. return;
  509. }
  510. clkrc = DEF_CLKRC + ov965x->fiv->clkrc_div;
  511. /* Calculate internal clock frequency */
  512. fint = ov965x->mclk_frequency * ((clkrc >> 7) + 1) /
  513. ((2 * ((clkrc & 0x3f) + 1)));
  514. /* and the row interval (in us). */
  515. trow = (2 * 1520 * 1000000UL) / fint;
  516. max = ov965x->frame_size->max_exp_lines * trow;
  517. ov965x->exp_row_interval = trow;
  518. mutex_unlock(&ov965x->lock);
  519. v4l2_dbg(1, debug, &ov965x->sd, "clkrc: %#x, fi: %lu, tr: %lu, %d\n",
  520. clkrc, fint, trow, max);
  521. /* Update exposure time range to match current frame format. */
  522. min = (trow + 100) / 100;
  523. max = (max - 100) / 100;
  524. def = min + (max - min) / 2;
  525. if (v4l2_ctrl_modify_range(ctrl, min, max, 1, def))
  526. v4l2_err(&ov965x->sd, "Exposure ctrl range update failed\n");
  527. }
  528. static int ov965x_set_banding_filter(struct ov965x *ov965x, int value)
  529. {
  530. unsigned long mbd, light_freq;
  531. int ret;
  532. u8 reg;
  533. ret = ov965x_read(ov965x, REG_COM8, &reg);
  534. if (!ret) {
  535. if (value == V4L2_CID_POWER_LINE_FREQUENCY_DISABLED)
  536. reg &= ~COM8_BFILT;
  537. else
  538. reg |= COM8_BFILT;
  539. ret = ov965x_write(ov965x, REG_COM8, reg);
  540. }
  541. if (value == V4L2_CID_POWER_LINE_FREQUENCY_DISABLED)
  542. return 0;
  543. if (WARN_ON(!ov965x->fiv))
  544. return -EINVAL;
  545. /* Set minimal exposure time for 50/60 HZ lighting */
  546. if (value == V4L2_CID_POWER_LINE_FREQUENCY_50HZ)
  547. light_freq = 50;
  548. else
  549. light_freq = 60;
  550. mbd = (1000UL * ov965x->fiv->interval.denominator *
  551. ov965x->frame_size->max_exp_lines) /
  552. ov965x->fiv->interval.numerator;
  553. mbd = ((mbd / (light_freq * 2)) + 500) / 1000UL;
  554. return ov965x_write(ov965x, REG_MBD, mbd);
  555. }
  556. static int ov965x_set_white_balance(struct ov965x *ov965x, int awb)
  557. {
  558. int ret;
  559. u8 reg;
  560. ret = ov965x_read(ov965x, REG_COM8, &reg);
  561. if (!ret) {
  562. reg = awb ? reg | REG_COM8 : reg & ~REG_COM8;
  563. ret = ov965x_write(ov965x, REG_COM8, reg);
  564. }
  565. if (!ret && !awb) {
  566. ret = ov965x_write(ov965x, REG_BLUE,
  567. ov965x->ctrls.blue_balance->val);
  568. if (ret < 0)
  569. return ret;
  570. ret = ov965x_write(ov965x, REG_RED,
  571. ov965x->ctrls.red_balance->val);
  572. }
  573. return ret;
  574. }
  575. #define NUM_BR_LEVELS 7
  576. #define NUM_BR_REGS 3
  577. static int ov965x_set_brightness(struct ov965x *ov965x, int val)
  578. {
  579. static const u8 regs[NUM_BR_LEVELS + 1][NUM_BR_REGS] = {
  580. { REG_AEW, REG_AEB, REG_VPT },
  581. { 0x1c, 0x12, 0x50 }, /* -3 */
  582. { 0x3d, 0x30, 0x71 }, /* -2 */
  583. { 0x50, 0x44, 0x92 }, /* -1 */
  584. { 0x70, 0x64, 0xc3 }, /* 0 */
  585. { 0x90, 0x84, 0xd4 }, /* +1 */
  586. { 0xc4, 0xbf, 0xf9 }, /* +2 */
  587. { 0xd8, 0xd0, 0xfa }, /* +3 */
  588. };
  589. int i, ret = 0;
  590. val += (NUM_BR_LEVELS / 2 + 1);
  591. if (val > NUM_BR_LEVELS)
  592. return -EINVAL;
  593. for (i = 0; i < NUM_BR_REGS && !ret; i++)
  594. ret = ov965x_write(ov965x, regs[0][i],
  595. regs[val][i]);
  596. return ret;
  597. }
  598. static int ov965x_set_gain(struct ov965x *ov965x, int auto_gain)
  599. {
  600. struct ov965x_ctrls *ctrls = &ov965x->ctrls;
  601. int ret = 0;
  602. u8 reg;
  603. /*
  604. * For manual mode we need to disable AGC first, so
  605. * gain value in REG_VREF, REG_GAIN is not overwritten.
  606. */
  607. if (ctrls->auto_gain->is_new) {
  608. ret = ov965x_read(ov965x, REG_COM8, &reg);
  609. if (ret < 0)
  610. return ret;
  611. if (ctrls->auto_gain->val)
  612. reg |= COM8_AGC;
  613. else
  614. reg &= ~COM8_AGC;
  615. ret = ov965x_write(ov965x, REG_COM8, reg);
  616. if (ret < 0)
  617. return ret;
  618. }
  619. if (ctrls->gain->is_new && !auto_gain) {
  620. unsigned int gain = ctrls->gain->val;
  621. unsigned int rgain;
  622. int m;
  623. /*
  624. * Convert gain control value to the sensor's gain
  625. * registers (VREF[7:6], GAIN[7:0]) format.
  626. */
  627. for (m = 6; m >= 0; m--)
  628. if (gain >= (1 << m) * 16)
  629. break;
  630. /* Sanity check: don't adjust the gain with a negative value */
  631. if (m < 0)
  632. return -EINVAL;
  633. rgain = (gain - ((1 << m) * 16)) / (1 << m);
  634. rgain |= (((1 << m) - 1) << 4);
  635. ret = ov965x_write(ov965x, REG_GAIN, rgain & 0xff);
  636. if (ret < 0)
  637. return ret;
  638. ret = ov965x_read(ov965x, REG_VREF, &reg);
  639. if (ret < 0)
  640. return ret;
  641. reg &= ~VREF_GAIN_MASK;
  642. reg |= (((rgain >> 8) & 0x3) << 6);
  643. ret = ov965x_write(ov965x, REG_VREF, reg);
  644. if (ret < 0)
  645. return ret;
  646. /* Return updated control's value to userspace */
  647. ctrls->gain->val = (1 << m) * (16 + (rgain & 0xf));
  648. }
  649. return ret;
  650. }
  651. static int ov965x_set_sharpness(struct ov965x *ov965x, unsigned int value)
  652. {
  653. u8 com14, edge;
  654. int ret;
  655. ret = ov965x_read(ov965x, REG_COM14, &com14);
  656. if (ret < 0)
  657. return ret;
  658. ret = ov965x_read(ov965x, REG_EDGE, &edge);
  659. if (ret < 0)
  660. return ret;
  661. com14 = value ? com14 | COM14_EDGE_EN : com14 & ~COM14_EDGE_EN;
  662. value--;
  663. if (value > 0x0f) {
  664. com14 |= COM14_EEF_X2;
  665. value >>= 1;
  666. } else {
  667. com14 &= ~COM14_EEF_X2;
  668. }
  669. ret = ov965x_write(ov965x, REG_COM14, com14);
  670. if (ret < 0)
  671. return ret;
  672. edge &= ~EDGE_FACTOR_MASK;
  673. edge |= ((u8)value & 0x0f);
  674. return ov965x_write(ov965x, REG_EDGE, edge);
  675. }
  676. static int ov965x_set_exposure(struct ov965x *ov965x, int exp)
  677. {
  678. struct ov965x_ctrls *ctrls = &ov965x->ctrls;
  679. bool auto_exposure = (exp == V4L2_EXPOSURE_AUTO);
  680. int ret;
  681. u8 reg;
  682. if (ctrls->auto_exp->is_new) {
  683. ret = ov965x_read(ov965x, REG_COM8, &reg);
  684. if (ret < 0)
  685. return ret;
  686. if (auto_exposure)
  687. reg |= (COM8_AEC | COM8_AGC);
  688. else
  689. reg &= ~(COM8_AEC | COM8_AGC);
  690. ret = ov965x_write(ov965x, REG_COM8, reg);
  691. if (ret < 0)
  692. return ret;
  693. }
  694. if (!auto_exposure && ctrls->exposure->is_new) {
  695. unsigned int exposure = (ctrls->exposure->val * 100)
  696. / ov965x->exp_row_interval;
  697. /*
  698. * Manual exposure value
  699. * [b15:b0] - AECHM (b15:b10), AECH (b9:b2), COM1 (b1:b0)
  700. */
  701. ret = ov965x_write(ov965x, REG_COM1, exposure & 0x3);
  702. if (!ret)
  703. ret = ov965x_write(ov965x, REG_AECH,
  704. (exposure >> 2) & 0xff);
  705. if (!ret)
  706. ret = ov965x_write(ov965x, REG_AECHM,
  707. (exposure >> 10) & 0x3f);
  708. /* Update the value to minimize rounding errors */
  709. ctrls->exposure->val = ((exposure * ov965x->exp_row_interval)
  710. + 50) / 100;
  711. if (ret < 0)
  712. return ret;
  713. }
  714. v4l2_ctrl_activate(ov965x->ctrls.brightness, !exp);
  715. return 0;
  716. }
  717. static int ov965x_set_flip(struct ov965x *ov965x)
  718. {
  719. u8 mvfp = 0;
  720. if (ov965x->ctrls.hflip->val)
  721. mvfp |= MVFP_MIRROR;
  722. if (ov965x->ctrls.vflip->val)
  723. mvfp |= MVFP_FLIP;
  724. return ov965x_write(ov965x, REG_MVFP, mvfp);
  725. }
  726. #define NUM_SAT_LEVELS 5
  727. #define NUM_SAT_REGS 6
  728. static int ov965x_set_saturation(struct ov965x *ov965x, int val)
  729. {
  730. static const u8 regs[NUM_SAT_LEVELS][NUM_SAT_REGS] = {
  731. /* MTX(1)...MTX(6) */
  732. { 0x1d, 0x1f, 0x02, 0x09, 0x13, 0x1c }, /* -2 */
  733. { 0x2e, 0x31, 0x02, 0x0e, 0x1e, 0x2d }, /* -1 */
  734. { 0x3a, 0x3d, 0x03, 0x12, 0x26, 0x38 }, /* 0 */
  735. { 0x46, 0x49, 0x04, 0x16, 0x2e, 0x43 }, /* +1 */
  736. { 0x57, 0x5c, 0x05, 0x1b, 0x39, 0x54 }, /* +2 */
  737. };
  738. u8 addr = REG_MTX(1);
  739. int i, ret = 0;
  740. val += (NUM_SAT_LEVELS / 2);
  741. if (val >= NUM_SAT_LEVELS)
  742. return -EINVAL;
  743. for (i = 0; i < NUM_SAT_REGS && !ret; i++)
  744. ret = ov965x_write(ov965x, addr + i, regs[val][i]);
  745. return ret;
  746. }
  747. static int ov965x_set_test_pattern(struct ov965x *ov965x, int value)
  748. {
  749. int ret;
  750. u8 reg;
  751. ret = ov965x_read(ov965x, REG_COM23, &reg);
  752. if (ret < 0)
  753. return ret;
  754. reg = value ? reg | COM23_TEST_MODE : reg & ~COM23_TEST_MODE;
  755. return ov965x_write(ov965x, REG_COM23, reg);
  756. }
  757. static int __g_volatile_ctrl(struct ov965x *ov965x, struct v4l2_ctrl *ctrl)
  758. {
  759. unsigned int exposure, gain, m;
  760. u8 reg0, reg1, reg2;
  761. int ret;
  762. if (!ov965x->power)
  763. return 0;
  764. switch (ctrl->id) {
  765. case V4L2_CID_AUTOGAIN:
  766. if (!ctrl->val)
  767. return 0;
  768. ret = ov965x_read(ov965x, REG_GAIN, &reg0);
  769. if (ret < 0)
  770. return ret;
  771. ret = ov965x_read(ov965x, REG_VREF, &reg1);
  772. if (ret < 0)
  773. return ret;
  774. gain = ((reg1 >> 6) << 8) | reg0;
  775. m = 0x01 << fls(gain >> 4);
  776. ov965x->ctrls.gain->val = m * (16 + (gain & 0xf));
  777. break;
  778. case V4L2_CID_EXPOSURE_AUTO:
  779. if (ctrl->val == V4L2_EXPOSURE_MANUAL)
  780. return 0;
  781. ret = ov965x_read(ov965x, REG_COM1, &reg0);
  782. if (ret < 0)
  783. return ret;
  784. ret = ov965x_read(ov965x, REG_AECH, &reg1);
  785. if (ret < 0)
  786. return ret;
  787. ret = ov965x_read(ov965x, REG_AECHM, &reg2);
  788. if (ret < 0)
  789. return ret;
  790. exposure = ((reg2 & 0x3f) << 10) | (reg1 << 2) |
  791. (reg0 & 0x3);
  792. ov965x->ctrls.exposure->val = ((exposure *
  793. ov965x->exp_row_interval) + 50) / 100;
  794. break;
  795. }
  796. return 0;
  797. }
  798. static int ov965x_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
  799. {
  800. struct v4l2_subdev *sd = ctrl_to_sd(ctrl);
  801. struct ov965x *ov965x = to_ov965x(sd);
  802. int ret;
  803. v4l2_dbg(1, debug, sd, "g_ctrl: %s\n", ctrl->name);
  804. mutex_lock(&ov965x->lock);
  805. ret = __g_volatile_ctrl(ov965x, ctrl);
  806. mutex_unlock(&ov965x->lock);
  807. return ret;
  808. }
  809. static int ov965x_s_ctrl(struct v4l2_ctrl *ctrl)
  810. {
  811. struct v4l2_subdev *sd = ctrl_to_sd(ctrl);
  812. struct ov965x *ov965x = to_ov965x(sd);
  813. int ret = -EINVAL;
  814. v4l2_dbg(1, debug, sd, "s_ctrl: %s, value: %d. power: %d\n",
  815. ctrl->name, ctrl->val, ov965x->power);
  816. mutex_lock(&ov965x->lock);
  817. /*
  818. * If the device is not powered up now postpone applying control's
  819. * value to the hardware, until it is ready to accept commands.
  820. */
  821. if (ov965x->power == 0) {
  822. mutex_unlock(&ov965x->lock);
  823. return 0;
  824. }
  825. switch (ctrl->id) {
  826. case V4L2_CID_AUTO_WHITE_BALANCE:
  827. ret = ov965x_set_white_balance(ov965x, ctrl->val);
  828. break;
  829. case V4L2_CID_BRIGHTNESS:
  830. ret = ov965x_set_brightness(ov965x, ctrl->val);
  831. break;
  832. case V4L2_CID_EXPOSURE_AUTO:
  833. ret = ov965x_set_exposure(ov965x, ctrl->val);
  834. break;
  835. case V4L2_CID_AUTOGAIN:
  836. ret = ov965x_set_gain(ov965x, ctrl->val);
  837. break;
  838. case V4L2_CID_HFLIP:
  839. ret = ov965x_set_flip(ov965x);
  840. break;
  841. case V4L2_CID_POWER_LINE_FREQUENCY:
  842. ret = ov965x_set_banding_filter(ov965x, ctrl->val);
  843. break;
  844. case V4L2_CID_SATURATION:
  845. ret = ov965x_set_saturation(ov965x, ctrl->val);
  846. break;
  847. case V4L2_CID_SHARPNESS:
  848. ret = ov965x_set_sharpness(ov965x, ctrl->val);
  849. break;
  850. case V4L2_CID_TEST_PATTERN:
  851. ret = ov965x_set_test_pattern(ov965x, ctrl->val);
  852. break;
  853. }
  854. mutex_unlock(&ov965x->lock);
  855. return ret;
  856. }
  857. static const struct v4l2_ctrl_ops ov965x_ctrl_ops = {
  858. .g_volatile_ctrl = ov965x_g_volatile_ctrl,
  859. .s_ctrl = ov965x_s_ctrl,
  860. };
  861. static const char * const test_pattern_menu[] = {
  862. "Disabled",
  863. "Color bars",
  864. };
  865. static int ov965x_initialize_controls(struct ov965x *ov965x)
  866. {
  867. const struct v4l2_ctrl_ops *ops = &ov965x_ctrl_ops;
  868. struct ov965x_ctrls *ctrls = &ov965x->ctrls;
  869. struct v4l2_ctrl_handler *hdl = &ctrls->handler;
  870. int ret;
  871. ret = v4l2_ctrl_handler_init(hdl, 16);
  872. if (ret < 0)
  873. return ret;
  874. /* Auto/manual white balance */
  875. ctrls->auto_wb = v4l2_ctrl_new_std(hdl, ops,
  876. V4L2_CID_AUTO_WHITE_BALANCE,
  877. 0, 1, 1, 1);
  878. ctrls->blue_balance = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BLUE_BALANCE,
  879. 0, 0xff, 1, 0x80);
  880. ctrls->red_balance = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_RED_BALANCE,
  881. 0, 0xff, 1, 0x80);
  882. /* Auto/manual exposure */
  883. ctrls->auto_exp =
  884. v4l2_ctrl_new_std_menu(hdl, ops,
  885. V4L2_CID_EXPOSURE_AUTO,
  886. V4L2_EXPOSURE_MANUAL, 0,
  887. V4L2_EXPOSURE_AUTO);
  888. /* Exposure time, in 100 us units. min/max is updated dynamically. */
  889. ctrls->exposure = v4l2_ctrl_new_std(hdl, ops,
  890. V4L2_CID_EXPOSURE_ABSOLUTE,
  891. 2, 1500, 1, 500);
  892. /* Auto/manual gain */
  893. ctrls->auto_gain = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_AUTOGAIN,
  894. 0, 1, 1, 1);
  895. ctrls->gain = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAIN,
  896. 16, 64 * (16 + 15), 1, 64 * 16);
  897. ctrls->saturation = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_SATURATION,
  898. -2, 2, 1, 0);
  899. ctrls->brightness = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BRIGHTNESS,
  900. -3, 3, 1, 0);
  901. ctrls->sharpness = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_SHARPNESS,
  902. 0, 32, 1, 6);
  903. ctrls->hflip = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_HFLIP, 0, 1, 1, 0);
  904. ctrls->vflip = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_VFLIP, 0, 1, 1, 0);
  905. ctrls->light_freq =
  906. v4l2_ctrl_new_std_menu(hdl, ops,
  907. V4L2_CID_POWER_LINE_FREQUENCY,
  908. V4L2_CID_POWER_LINE_FREQUENCY_60HZ, ~0x7,
  909. V4L2_CID_POWER_LINE_FREQUENCY_50HZ);
  910. v4l2_ctrl_new_std_menu_items(hdl, ops, V4L2_CID_TEST_PATTERN,
  911. ARRAY_SIZE(test_pattern_menu) - 1, 0, 0,
  912. test_pattern_menu);
  913. if (hdl->error) {
  914. ret = hdl->error;
  915. v4l2_ctrl_handler_free(hdl);
  916. return ret;
  917. }
  918. ctrls->gain->flags |= V4L2_CTRL_FLAG_VOLATILE;
  919. ctrls->exposure->flags |= V4L2_CTRL_FLAG_VOLATILE;
  920. v4l2_ctrl_auto_cluster(3, &ctrls->auto_wb, 0, false);
  921. v4l2_ctrl_auto_cluster(2, &ctrls->auto_gain, 0, true);
  922. v4l2_ctrl_auto_cluster(2, &ctrls->auto_exp, 1, true);
  923. v4l2_ctrl_cluster(2, &ctrls->hflip);
  924. ov965x->sd.ctrl_handler = hdl;
  925. return 0;
  926. }
  927. /*
  928. * V4L2 subdev video and pad level operations
  929. */
  930. static void ov965x_get_default_format(struct v4l2_mbus_framefmt *mf)
  931. {
  932. mf->width = ov965x_framesizes[0].width;
  933. mf->height = ov965x_framesizes[0].height;
  934. mf->colorspace = ov965x_formats[0].colorspace;
  935. mf->code = ov965x_formats[0].code;
  936. mf->field = V4L2_FIELD_NONE;
  937. }
  938. static int ov965x_enum_mbus_code(struct v4l2_subdev *sd,
  939. struct v4l2_subdev_pad_config *cfg,
  940. struct v4l2_subdev_mbus_code_enum *code)
  941. {
  942. if (code->index >= ARRAY_SIZE(ov965x_formats))
  943. return -EINVAL;
  944. code->code = ov965x_formats[code->index].code;
  945. return 0;
  946. }
  947. static int ov965x_enum_frame_sizes(struct v4l2_subdev *sd,
  948. struct v4l2_subdev_pad_config *cfg,
  949. struct v4l2_subdev_frame_size_enum *fse)
  950. {
  951. int i = ARRAY_SIZE(ov965x_formats);
  952. if (fse->index >= ARRAY_SIZE(ov965x_framesizes))
  953. return -EINVAL;
  954. while (--i)
  955. if (fse->code == ov965x_formats[i].code)
  956. break;
  957. fse->code = ov965x_formats[i].code;
  958. fse->min_width = ov965x_framesizes[fse->index].width;
  959. fse->max_width = fse->min_width;
  960. fse->max_height = ov965x_framesizes[fse->index].height;
  961. fse->min_height = fse->max_height;
  962. return 0;
  963. }
  964. static int ov965x_g_frame_interval(struct v4l2_subdev *sd,
  965. struct v4l2_subdev_frame_interval *fi)
  966. {
  967. struct ov965x *ov965x = to_ov965x(sd);
  968. mutex_lock(&ov965x->lock);
  969. fi->interval = ov965x->fiv->interval;
  970. mutex_unlock(&ov965x->lock);
  971. return 0;
  972. }
  973. static int __ov965x_set_frame_interval(struct ov965x *ov965x,
  974. struct v4l2_subdev_frame_interval *fi)
  975. {
  976. struct v4l2_mbus_framefmt *mbus_fmt = &ov965x->format;
  977. const struct ov965x_interval *fiv = &ov965x_intervals[0];
  978. u64 req_int, err, min_err = ~0ULL;
  979. unsigned int i;
  980. if (fi->interval.denominator == 0)
  981. return -EINVAL;
  982. req_int = (u64)fi->interval.numerator * 10000;
  983. do_div(req_int, fi->interval.denominator);
  984. for (i = 0; i < ARRAY_SIZE(ov965x_intervals); i++) {
  985. const struct ov965x_interval *iv = &ov965x_intervals[i];
  986. if (mbus_fmt->width != iv->size.width ||
  987. mbus_fmt->height != iv->size.height)
  988. continue;
  989. err = abs((u64)(iv->interval.numerator * 10000) /
  990. iv->interval.denominator - req_int);
  991. if (err < min_err) {
  992. fiv = iv;
  993. min_err = err;
  994. }
  995. }
  996. ov965x->fiv = fiv;
  997. v4l2_dbg(1, debug, &ov965x->sd, "Changed frame interval to %u us\n",
  998. fiv->interval.numerator * 1000000 / fiv->interval.denominator);
  999. return 0;
  1000. }
  1001. static int ov965x_s_frame_interval(struct v4l2_subdev *sd,
  1002. struct v4l2_subdev_frame_interval *fi)
  1003. {
  1004. struct ov965x *ov965x = to_ov965x(sd);
  1005. int ret;
  1006. v4l2_dbg(1, debug, sd, "Setting %d/%d frame interval\n",
  1007. fi->interval.numerator, fi->interval.denominator);
  1008. mutex_lock(&ov965x->lock);
  1009. ret = __ov965x_set_frame_interval(ov965x, fi);
  1010. ov965x->apply_frame_fmt = 1;
  1011. mutex_unlock(&ov965x->lock);
  1012. return ret;
  1013. }
  1014. static int ov965x_get_fmt(struct v4l2_subdev *sd,
  1015. struct v4l2_subdev_pad_config *cfg,
  1016. struct v4l2_subdev_format *fmt)
  1017. {
  1018. struct ov965x *ov965x = to_ov965x(sd);
  1019. struct v4l2_mbus_framefmt *mf;
  1020. if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
  1021. mf = v4l2_subdev_get_try_format(sd, cfg, 0);
  1022. fmt->format = *mf;
  1023. return 0;
  1024. }
  1025. mutex_lock(&ov965x->lock);
  1026. fmt->format = ov965x->format;
  1027. mutex_unlock(&ov965x->lock);
  1028. return 0;
  1029. }
  1030. static void __ov965x_try_frame_size(struct v4l2_mbus_framefmt *mf,
  1031. const struct ov965x_framesize **size)
  1032. {
  1033. const struct ov965x_framesize *fsize = &ov965x_framesizes[0],
  1034. *match = NULL;
  1035. int i = ARRAY_SIZE(ov965x_framesizes);
  1036. unsigned int min_err = UINT_MAX;
  1037. while (i--) {
  1038. int err = abs(fsize->width - mf->width)
  1039. + abs(fsize->height - mf->height);
  1040. if (err < min_err) {
  1041. min_err = err;
  1042. match = fsize;
  1043. }
  1044. fsize++;
  1045. }
  1046. if (!match)
  1047. match = &ov965x_framesizes[0];
  1048. mf->width = match->width;
  1049. mf->height = match->height;
  1050. if (size)
  1051. *size = match;
  1052. }
  1053. static int ov965x_set_fmt(struct v4l2_subdev *sd,
  1054. struct v4l2_subdev_pad_config *cfg,
  1055. struct v4l2_subdev_format *fmt)
  1056. {
  1057. unsigned int index = ARRAY_SIZE(ov965x_formats);
  1058. struct v4l2_mbus_framefmt *mf = &fmt->format;
  1059. struct ov965x *ov965x = to_ov965x(sd);
  1060. const struct ov965x_framesize *size = NULL;
  1061. int ret = 0;
  1062. __ov965x_try_frame_size(mf, &size);
  1063. while (--index)
  1064. if (ov965x_formats[index].code == mf->code)
  1065. break;
  1066. mf->colorspace = V4L2_COLORSPACE_JPEG;
  1067. mf->code = ov965x_formats[index].code;
  1068. mf->field = V4L2_FIELD_NONE;
  1069. mutex_lock(&ov965x->lock);
  1070. if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
  1071. if (cfg) {
  1072. mf = v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
  1073. *mf = fmt->format;
  1074. }
  1075. } else {
  1076. if (ov965x->streaming) {
  1077. ret = -EBUSY;
  1078. } else {
  1079. ov965x->frame_size = size;
  1080. ov965x->format = fmt->format;
  1081. ov965x->tslb_reg = ov965x_formats[index].tslb_reg;
  1082. ov965x->apply_frame_fmt = 1;
  1083. }
  1084. }
  1085. if (!ret && fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
  1086. struct v4l2_subdev_frame_interval fiv = {
  1087. .interval = { 0, 1 }
  1088. };
  1089. /* Reset to minimum possible frame interval */
  1090. __ov965x_set_frame_interval(ov965x, &fiv);
  1091. }
  1092. mutex_unlock(&ov965x->lock);
  1093. if (!ret)
  1094. ov965x_update_exposure_ctrl(ov965x);
  1095. return ret;
  1096. }
  1097. static int ov965x_set_frame_size(struct ov965x *ov965x)
  1098. {
  1099. int i, ret = 0;
  1100. for (i = 0; ret == 0 && i < NUM_FMT_REGS; i++)
  1101. ret = ov965x_write(ov965x, frame_size_reg_addr[i],
  1102. ov965x->frame_size->regs[i]);
  1103. return ret;
  1104. }
  1105. static int __ov965x_set_params(struct ov965x *ov965x)
  1106. {
  1107. struct ov965x_ctrls *ctrls = &ov965x->ctrls;
  1108. int ret = 0;
  1109. u8 reg;
  1110. if (ov965x->apply_frame_fmt) {
  1111. reg = DEF_CLKRC + ov965x->fiv->clkrc_div;
  1112. ret = ov965x_write(ov965x, REG_CLKRC, reg);
  1113. if (ret < 0)
  1114. return ret;
  1115. ret = ov965x_set_frame_size(ov965x);
  1116. if (ret < 0)
  1117. return ret;
  1118. ret = ov965x_read(ov965x, REG_TSLB, &reg);
  1119. if (ret < 0)
  1120. return ret;
  1121. reg &= ~TSLB_YUYV_MASK;
  1122. reg |= ov965x->tslb_reg;
  1123. ret = ov965x_write(ov965x, REG_TSLB, reg);
  1124. if (ret < 0)
  1125. return ret;
  1126. }
  1127. ret = ov965x_set_default_gamma_curve(ov965x);
  1128. if (ret < 0)
  1129. return ret;
  1130. ret = ov965x_set_color_matrix(ov965x);
  1131. if (ret < 0)
  1132. return ret;
  1133. /*
  1134. * Select manual banding filter, the filter will
  1135. * be enabled further if required.
  1136. */
  1137. ret = ov965x_read(ov965x, REG_COM11, &reg);
  1138. if (!ret)
  1139. reg |= COM11_BANDING;
  1140. ret = ov965x_write(ov965x, REG_COM11, reg);
  1141. if (ret < 0)
  1142. return ret;
  1143. /*
  1144. * Banding filter (REG_MBD value) needs to match selected
  1145. * resolution and frame rate, so it's always updated here.
  1146. */
  1147. return ov965x_set_banding_filter(ov965x, ctrls->light_freq->val);
  1148. }
  1149. static int ov965x_s_stream(struct v4l2_subdev *sd, int on)
  1150. {
  1151. struct ov965x *ov965x = to_ov965x(sd);
  1152. struct ov965x_ctrls *ctrls = &ov965x->ctrls;
  1153. int ret = 0;
  1154. v4l2_dbg(1, debug, sd, "%s: on: %d\n", __func__, on);
  1155. mutex_lock(&ov965x->lock);
  1156. if (ov965x->streaming == !on) {
  1157. if (on)
  1158. ret = __ov965x_set_params(ov965x);
  1159. if (!ret && ctrls->update) {
  1160. /*
  1161. * ov965x_s_ctrl callback takes the mutex
  1162. * so it needs to be released here.
  1163. */
  1164. mutex_unlock(&ov965x->lock);
  1165. ret = v4l2_ctrl_handler_setup(&ctrls->handler);
  1166. mutex_lock(&ov965x->lock);
  1167. if (!ret)
  1168. ctrls->update = 0;
  1169. }
  1170. if (!ret)
  1171. ret = ov965x_write(ov965x, REG_COM2,
  1172. on ? 0x01 : 0x11);
  1173. }
  1174. if (!ret)
  1175. ov965x->streaming += on ? 1 : -1;
  1176. WARN_ON(ov965x->streaming < 0);
  1177. mutex_unlock(&ov965x->lock);
  1178. return ret;
  1179. }
  1180. /*
  1181. * V4L2 subdev internal operations
  1182. */
  1183. static int ov965x_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
  1184. {
  1185. struct v4l2_mbus_framefmt *mf =
  1186. v4l2_subdev_get_try_format(sd, fh->pad, 0);
  1187. ov965x_get_default_format(mf);
  1188. return 0;
  1189. }
  1190. static const struct v4l2_subdev_pad_ops ov965x_pad_ops = {
  1191. .enum_mbus_code = ov965x_enum_mbus_code,
  1192. .enum_frame_size = ov965x_enum_frame_sizes,
  1193. .get_fmt = ov965x_get_fmt,
  1194. .set_fmt = ov965x_set_fmt,
  1195. };
  1196. static const struct v4l2_subdev_video_ops ov965x_video_ops = {
  1197. .s_stream = ov965x_s_stream,
  1198. .g_frame_interval = ov965x_g_frame_interval,
  1199. .s_frame_interval = ov965x_s_frame_interval,
  1200. };
  1201. static const struct v4l2_subdev_internal_ops ov965x_sd_internal_ops = {
  1202. .open = ov965x_open,
  1203. };
  1204. static const struct v4l2_subdev_core_ops ov965x_core_ops = {
  1205. .s_power = ov965x_s_power,
  1206. .log_status = v4l2_ctrl_subdev_log_status,
  1207. .subscribe_event = v4l2_ctrl_subdev_subscribe_event,
  1208. .unsubscribe_event = v4l2_event_subdev_unsubscribe,
  1209. };
  1210. static const struct v4l2_subdev_ops ov965x_subdev_ops = {
  1211. .core = &ov965x_core_ops,
  1212. .pad = &ov965x_pad_ops,
  1213. .video = &ov965x_video_ops,
  1214. };
  1215. /*
  1216. * Reset and power down GPIOs configuration
  1217. */
  1218. static int ov965x_configure_gpios_pdata(struct ov965x *ov965x,
  1219. const struct ov9650_platform_data *pdata)
  1220. {
  1221. int ret, i;
  1222. int gpios[NUM_GPIOS];
  1223. struct device *dev = regmap_get_device(ov965x->regmap);
  1224. gpios[GPIO_PWDN] = pdata->gpio_pwdn;
  1225. gpios[GPIO_RST] = pdata->gpio_reset;
  1226. for (i = 0; i < ARRAY_SIZE(ov965x->gpios); i++) {
  1227. int gpio = gpios[i];
  1228. if (!gpio_is_valid(gpio))
  1229. continue;
  1230. ret = devm_gpio_request_one(dev, gpio,
  1231. GPIOF_OUT_INIT_HIGH, "OV965X");
  1232. if (ret < 0)
  1233. return ret;
  1234. v4l2_dbg(1, debug, &ov965x->sd, "set gpio %d to 1\n", gpio);
  1235. gpio_set_value_cansleep(gpio, 1);
  1236. gpio_export(gpio, 0);
  1237. ov965x->gpios[i] = gpio_to_desc(gpio);
  1238. }
  1239. return 0;
  1240. }
  1241. static int ov965x_configure_gpios(struct ov965x *ov965x)
  1242. {
  1243. struct device *dev = regmap_get_device(ov965x->regmap);
  1244. ov965x->gpios[GPIO_PWDN] = devm_gpiod_get_optional(dev, "powerdown",
  1245. GPIOD_OUT_HIGH);
  1246. if (IS_ERR(ov965x->gpios[GPIO_PWDN])) {
  1247. dev_info(dev, "can't get %s GPIO\n", "powerdown");
  1248. return PTR_ERR(ov965x->gpios[GPIO_PWDN]);
  1249. }
  1250. ov965x->gpios[GPIO_RST] = devm_gpiod_get_optional(dev, "reset",
  1251. GPIOD_OUT_HIGH);
  1252. if (IS_ERR(ov965x->gpios[GPIO_RST])) {
  1253. dev_info(dev, "can't get %s GPIO\n", "reset");
  1254. return PTR_ERR(ov965x->gpios[GPIO_RST]);
  1255. }
  1256. return 0;
  1257. }
  1258. static int ov965x_detect_sensor(struct v4l2_subdev *sd)
  1259. {
  1260. struct ov965x *ov965x = to_ov965x(sd);
  1261. u8 pid, ver;
  1262. int ret;
  1263. mutex_lock(&ov965x->lock);
  1264. ret = __ov965x_set_power(ov965x, 1);
  1265. if (ret)
  1266. goto out;
  1267. msleep(25);
  1268. /* Check sensor revision */
  1269. ret = ov965x_read(ov965x, REG_PID, &pid);
  1270. if (!ret)
  1271. ret = ov965x_read(ov965x, REG_VER, &ver);
  1272. __ov965x_set_power(ov965x, 0);
  1273. if (!ret) {
  1274. ov965x->id = OV965X_ID(pid, ver);
  1275. if (ov965x->id == OV9650_ID || ov965x->id == OV9652_ID) {
  1276. v4l2_info(sd, "Found OV%04X sensor\n", ov965x->id);
  1277. } else {
  1278. v4l2_err(sd, "Sensor detection failed (%04X, %d)\n",
  1279. ov965x->id, ret);
  1280. ret = -ENODEV;
  1281. }
  1282. }
  1283. out:
  1284. mutex_unlock(&ov965x->lock);
  1285. return ret;
  1286. }
  1287. static int ov965x_probe(struct i2c_client *client)
  1288. {
  1289. const struct ov9650_platform_data *pdata = client->dev.platform_data;
  1290. struct v4l2_subdev *sd;
  1291. struct ov965x *ov965x;
  1292. int ret;
  1293. static const struct regmap_config ov965x_regmap_config = {
  1294. .reg_bits = 8,
  1295. .val_bits = 8,
  1296. .max_register = 0xab,
  1297. };
  1298. ov965x = devm_kzalloc(&client->dev, sizeof(*ov965x), GFP_KERNEL);
  1299. if (!ov965x)
  1300. return -ENOMEM;
  1301. ov965x->regmap = devm_regmap_init_sccb(client, &ov965x_regmap_config);
  1302. if (IS_ERR(ov965x->regmap)) {
  1303. dev_err(&client->dev, "Failed to allocate register map\n");
  1304. return PTR_ERR(ov965x->regmap);
  1305. }
  1306. if (pdata) {
  1307. if (pdata->mclk_frequency == 0) {
  1308. dev_err(&client->dev, "MCLK frequency not specified\n");
  1309. return -EINVAL;
  1310. }
  1311. ov965x->mclk_frequency = pdata->mclk_frequency;
  1312. ret = ov965x_configure_gpios_pdata(ov965x, pdata);
  1313. if (ret < 0)
  1314. return ret;
  1315. } else if (dev_fwnode(&client->dev)) {
  1316. ov965x->clk = devm_clk_get(&client->dev, NULL);
  1317. if (IS_ERR(ov965x->clk))
  1318. return PTR_ERR(ov965x->clk);
  1319. ov965x->mclk_frequency = clk_get_rate(ov965x->clk);
  1320. ret = ov965x_configure_gpios(ov965x);
  1321. if (ret < 0)
  1322. return ret;
  1323. } else {
  1324. dev_err(&client->dev,
  1325. "Neither platform data nor device property specified\n");
  1326. return -EINVAL;
  1327. }
  1328. mutex_init(&ov965x->lock);
  1329. sd = &ov965x->sd;
  1330. v4l2_i2c_subdev_init(sd, client, &ov965x_subdev_ops);
  1331. strscpy(sd->name, DRIVER_NAME, sizeof(sd->name));
  1332. sd->internal_ops = &ov965x_sd_internal_ops;
  1333. sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
  1334. V4L2_SUBDEV_FL_HAS_EVENTS;
  1335. ov965x->pad.flags = MEDIA_PAD_FL_SOURCE;
  1336. sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
  1337. ret = media_entity_pads_init(&sd->entity, 1, &ov965x->pad);
  1338. if (ret < 0)
  1339. goto err_mutex;
  1340. ret = ov965x_initialize_controls(ov965x);
  1341. if (ret < 0)
  1342. goto err_me;
  1343. ov965x_get_default_format(&ov965x->format);
  1344. ov965x->frame_size = &ov965x_framesizes[0];
  1345. ov965x->fiv = &ov965x_intervals[0];
  1346. ret = ov965x_detect_sensor(sd);
  1347. if (ret < 0)
  1348. goto err_ctrls;
  1349. /* Update exposure time min/max to match frame format */
  1350. ov965x_update_exposure_ctrl(ov965x);
  1351. ret = v4l2_async_register_subdev(sd);
  1352. if (ret < 0)
  1353. goto err_ctrls;
  1354. return 0;
  1355. err_ctrls:
  1356. v4l2_ctrl_handler_free(sd->ctrl_handler);
  1357. err_me:
  1358. media_entity_cleanup(&sd->entity);
  1359. err_mutex:
  1360. mutex_destroy(&ov965x->lock);
  1361. return ret;
  1362. }
  1363. static int ov965x_remove(struct i2c_client *client)
  1364. {
  1365. struct v4l2_subdev *sd = i2c_get_clientdata(client);
  1366. struct ov965x *ov965x = to_ov965x(sd);
  1367. v4l2_async_unregister_subdev(sd);
  1368. v4l2_ctrl_handler_free(sd->ctrl_handler);
  1369. media_entity_cleanup(&sd->entity);
  1370. mutex_destroy(&ov965x->lock);
  1371. return 0;
  1372. }
  1373. static const struct i2c_device_id ov965x_id[] = {
  1374. { "OV9650", 0 },
  1375. { "OV9652", 0 },
  1376. { /* sentinel */ }
  1377. };
  1378. MODULE_DEVICE_TABLE(i2c, ov965x_id);
  1379. #if IS_ENABLED(CONFIG_OF)
  1380. static const struct of_device_id ov965x_of_match[] = {
  1381. { .compatible = "ovti,ov9650", },
  1382. { .compatible = "ovti,ov9652", },
  1383. { /* sentinel */ }
  1384. };
  1385. MODULE_DEVICE_TABLE(of, ov965x_of_match);
  1386. #endif
  1387. static struct i2c_driver ov965x_i2c_driver = {
  1388. .driver = {
  1389. .name = DRIVER_NAME,
  1390. .of_match_table = of_match_ptr(ov965x_of_match),
  1391. },
  1392. .probe_new = ov965x_probe,
  1393. .remove = ov965x_remove,
  1394. .id_table = ov965x_id,
  1395. };
  1396. module_i2c_driver(ov965x_i2c_driver);
  1397. MODULE_AUTHOR("Sylwester Nawrocki <sylvester.nawrocki@gmail.com>");
  1398. MODULE_DESCRIPTION("OV9650/OV9652 CMOS Image Sensor driver");
  1399. MODULE_LICENSE("GPL");