ov9640.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * OmniVision OV96xx Camera Driver
  4. *
  5. * Copyright (C) 2009 Marek Vasut <marek.vasut@gmail.com>
  6. *
  7. * Based on ov772x camera driver:
  8. *
  9. * Copyright (C) 2008 Renesas Solutions Corp.
  10. * Kuninori Morimoto <morimoto.kuninori@renesas.com>
  11. *
  12. * Based on ov7670 and soc_camera_platform driver,
  13. * transition from soc_camera to pxa_camera based on mt9m111
  14. *
  15. * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
  16. * Copyright (C) 2008 Magnus Damm
  17. * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
  18. */
  19. #include <linux/init.h>
  20. #include <linux/module.h>
  21. #include <linux/i2c.h>
  22. #include <linux/slab.h>
  23. #include <linux/delay.h>
  24. #include <linux/v4l2-mediabus.h>
  25. #include <linux/videodev2.h>
  26. #include <media/v4l2-async.h>
  27. #include <media/v4l2-clk.h>
  28. #include <media/v4l2-common.h>
  29. #include <media/v4l2-ctrls.h>
  30. #include <media/v4l2-device.h>
  31. #include <media/v4l2-event.h>
  32. #include <linux/gpio/consumer.h>
  33. #include "ov9640.h"
  34. #define to_ov9640_sensor(sd) container_of(sd, struct ov9640_priv, subdev)
  35. /* default register setup */
  36. static const struct ov9640_reg ov9640_regs_dflt[] = {
  37. { OV9640_COM5, OV9640_COM5_SYSCLK | OV9640_COM5_LONGEXP },
  38. { OV9640_COM6, OV9640_COM6_OPT_BLC | OV9640_COM6_ADBLC_BIAS |
  39. OV9640_COM6_FMT_RST | OV9640_COM6_ADBLC_OPTEN },
  40. { OV9640_PSHFT, OV9640_PSHFT_VAL(0x01) },
  41. { OV9640_ACOM, OV9640_ACOM_2X_ANALOG | OV9640_ACOM_RSVD },
  42. { OV9640_TSLB, OV9640_TSLB_YUYV_UYVY },
  43. { OV9640_COM16, OV9640_COM16_RB_AVG },
  44. /* Gamma curve P */
  45. { 0x6c, 0x40 }, { 0x6d, 0x30 }, { 0x6e, 0x4b }, { 0x6f, 0x60 },
  46. { 0x70, 0x70 }, { 0x71, 0x70 }, { 0x72, 0x70 }, { 0x73, 0x70 },
  47. { 0x74, 0x60 }, { 0x75, 0x60 }, { 0x76, 0x50 }, { 0x77, 0x48 },
  48. { 0x78, 0x3a }, { 0x79, 0x2e }, { 0x7a, 0x28 }, { 0x7b, 0x22 },
  49. /* Gamma curve T */
  50. { 0x7c, 0x04 }, { 0x7d, 0x07 }, { 0x7e, 0x10 }, { 0x7f, 0x28 },
  51. { 0x80, 0x36 }, { 0x81, 0x44 }, { 0x82, 0x52 }, { 0x83, 0x60 },
  52. { 0x84, 0x6c }, { 0x85, 0x78 }, { 0x86, 0x8c }, { 0x87, 0x9e },
  53. { 0x88, 0xbb }, { 0x89, 0xd2 }, { 0x8a, 0xe6 },
  54. };
  55. /* Configurations
  56. * NOTE: for YUV, alter the following registers:
  57. * COM12 |= OV9640_COM12_YUV_AVG
  58. *
  59. * for RGB, alter the following registers:
  60. * COM7 |= OV9640_COM7_RGB
  61. * COM13 |= OV9640_COM13_RGB_AVG
  62. * COM15 |= proper RGB color encoding mode
  63. */
  64. static const struct ov9640_reg ov9640_regs_qqcif[] = {
  65. { OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x0f) },
  66. { OV9640_COM1, OV9640_COM1_QQFMT | OV9640_COM1_HREF_2SKIP },
  67. { OV9640_COM4, OV9640_COM4_QQ_VP | OV9640_COM4_RSVD },
  68. { OV9640_COM7, OV9640_COM7_QCIF },
  69. { OV9640_COM12, OV9640_COM12_RSVD },
  70. { OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN },
  71. { OV9640_COM15, OV9640_COM15_OR_10F0 },
  72. };
  73. static const struct ov9640_reg ov9640_regs_qqvga[] = {
  74. { OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x07) },
  75. { OV9640_COM1, OV9640_COM1_QQFMT | OV9640_COM1_HREF_2SKIP },
  76. { OV9640_COM4, OV9640_COM4_QQ_VP | OV9640_COM4_RSVD },
  77. { OV9640_COM7, OV9640_COM7_QVGA },
  78. { OV9640_COM12, OV9640_COM12_RSVD },
  79. { OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN },
  80. { OV9640_COM15, OV9640_COM15_OR_10F0 },
  81. };
  82. static const struct ov9640_reg ov9640_regs_qcif[] = {
  83. { OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x07) },
  84. { OV9640_COM4, OV9640_COM4_QQ_VP | OV9640_COM4_RSVD },
  85. { OV9640_COM7, OV9640_COM7_QCIF },
  86. { OV9640_COM12, OV9640_COM12_RSVD },
  87. { OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN },
  88. { OV9640_COM15, OV9640_COM15_OR_10F0 },
  89. };
  90. static const struct ov9640_reg ov9640_regs_qvga[] = {
  91. { OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x03) },
  92. { OV9640_COM4, OV9640_COM4_QQ_VP | OV9640_COM4_RSVD },
  93. { OV9640_COM7, OV9640_COM7_QVGA },
  94. { OV9640_COM12, OV9640_COM12_RSVD },
  95. { OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN },
  96. { OV9640_COM15, OV9640_COM15_OR_10F0 },
  97. };
  98. static const struct ov9640_reg ov9640_regs_cif[] = {
  99. { OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x03) },
  100. { OV9640_COM3, OV9640_COM3_VP },
  101. { OV9640_COM7, OV9640_COM7_CIF },
  102. { OV9640_COM12, OV9640_COM12_RSVD },
  103. { OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN },
  104. { OV9640_COM15, OV9640_COM15_OR_10F0 },
  105. };
  106. static const struct ov9640_reg ov9640_regs_vga[] = {
  107. { OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x01) },
  108. { OV9640_COM3, OV9640_COM3_VP },
  109. { OV9640_COM7, OV9640_COM7_VGA },
  110. { OV9640_COM12, OV9640_COM12_RSVD },
  111. { OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN },
  112. { OV9640_COM15, OV9640_COM15_OR_10F0 },
  113. };
  114. static const struct ov9640_reg ov9640_regs_sxga[] = {
  115. { OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x01) },
  116. { OV9640_COM3, OV9640_COM3_VP },
  117. { OV9640_COM7, 0 },
  118. { OV9640_COM12, OV9640_COM12_RSVD },
  119. { OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN },
  120. { OV9640_COM15, OV9640_COM15_OR_10F0 },
  121. };
  122. static const struct ov9640_reg ov9640_regs_yuv[] = {
  123. { OV9640_MTX1, 0x58 },
  124. { OV9640_MTX2, 0x48 },
  125. { OV9640_MTX3, 0x10 },
  126. { OV9640_MTX4, 0x28 },
  127. { OV9640_MTX5, 0x48 },
  128. { OV9640_MTX6, 0x70 },
  129. { OV9640_MTX7, 0x40 },
  130. { OV9640_MTX8, 0x40 },
  131. { OV9640_MTX9, 0x40 },
  132. { OV9640_MTXS, 0x0f },
  133. };
  134. static const struct ov9640_reg ov9640_regs_rgb[] = {
  135. { OV9640_MTX1, 0x71 },
  136. { OV9640_MTX2, 0x3e },
  137. { OV9640_MTX3, 0x0c },
  138. { OV9640_MTX4, 0x33 },
  139. { OV9640_MTX5, 0x72 },
  140. { OV9640_MTX6, 0x00 },
  141. { OV9640_MTX7, 0x2b },
  142. { OV9640_MTX8, 0x66 },
  143. { OV9640_MTX9, 0xd2 },
  144. { OV9640_MTXS, 0x65 },
  145. };
  146. static const u32 ov9640_codes[] = {
  147. MEDIA_BUS_FMT_UYVY8_2X8,
  148. MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE,
  149. MEDIA_BUS_FMT_RGB565_2X8_LE,
  150. };
  151. /* read a register */
  152. static int ov9640_reg_read(struct i2c_client *client, u8 reg, u8 *val)
  153. {
  154. int ret;
  155. u8 data = reg;
  156. struct i2c_msg msg = {
  157. .addr = client->addr,
  158. .flags = 0,
  159. .len = 1,
  160. .buf = &data,
  161. };
  162. ret = i2c_transfer(client->adapter, &msg, 1);
  163. if (ret < 0)
  164. goto err;
  165. msg.flags = I2C_M_RD;
  166. ret = i2c_transfer(client->adapter, &msg, 1);
  167. if (ret < 0)
  168. goto err;
  169. *val = data;
  170. return 0;
  171. err:
  172. dev_err(&client->dev, "Failed reading register 0x%02x!\n", reg);
  173. return ret;
  174. }
  175. /* write a register */
  176. static int ov9640_reg_write(struct i2c_client *client, u8 reg, u8 val)
  177. {
  178. int ret;
  179. u8 _val;
  180. unsigned char data[2] = { reg, val };
  181. struct i2c_msg msg = {
  182. .addr = client->addr,
  183. .flags = 0,
  184. .len = 2,
  185. .buf = data,
  186. };
  187. ret = i2c_transfer(client->adapter, &msg, 1);
  188. if (ret < 0) {
  189. dev_err(&client->dev, "Failed writing register 0x%02x!\n", reg);
  190. return ret;
  191. }
  192. /* we have to read the register back ... no idea why, maybe HW bug */
  193. ret = ov9640_reg_read(client, reg, &_val);
  194. if (ret)
  195. dev_err(&client->dev,
  196. "Failed reading back register 0x%02x!\n", reg);
  197. return 0;
  198. }
  199. /* Read a register, alter its bits, write it back */
  200. static int ov9640_reg_rmw(struct i2c_client *client, u8 reg, u8 set, u8 unset)
  201. {
  202. u8 val;
  203. int ret;
  204. ret = ov9640_reg_read(client, reg, &val);
  205. if (ret) {
  206. dev_err(&client->dev,
  207. "[Read]-Modify-Write of register %02x failed!\n", reg);
  208. return ret;
  209. }
  210. val |= set;
  211. val &= ~unset;
  212. ret = ov9640_reg_write(client, reg, val);
  213. if (ret)
  214. dev_err(&client->dev,
  215. "Read-Modify-[Write] of register %02x failed!\n", reg);
  216. return ret;
  217. }
  218. /* Soft reset the camera. This has nothing to do with the RESET pin! */
  219. static int ov9640_reset(struct i2c_client *client)
  220. {
  221. int ret;
  222. ret = ov9640_reg_write(client, OV9640_COM7, OV9640_COM7_SCCB_RESET);
  223. if (ret)
  224. dev_err(&client->dev,
  225. "An error occurred while entering soft reset!\n");
  226. return ret;
  227. }
  228. /* Start/Stop streaming from the device */
  229. static int ov9640_s_stream(struct v4l2_subdev *sd, int enable)
  230. {
  231. return 0;
  232. }
  233. /* Set status of additional camera capabilities */
  234. static int ov9640_s_ctrl(struct v4l2_ctrl *ctrl)
  235. {
  236. struct ov9640_priv *priv = container_of(ctrl->handler,
  237. struct ov9640_priv, hdl);
  238. struct i2c_client *client = v4l2_get_subdevdata(&priv->subdev);
  239. switch (ctrl->id) {
  240. case V4L2_CID_VFLIP:
  241. if (ctrl->val)
  242. return ov9640_reg_rmw(client, OV9640_MVFP,
  243. OV9640_MVFP_V, 0);
  244. return ov9640_reg_rmw(client, OV9640_MVFP, 0, OV9640_MVFP_V);
  245. case V4L2_CID_HFLIP:
  246. if (ctrl->val)
  247. return ov9640_reg_rmw(client, OV9640_MVFP,
  248. OV9640_MVFP_H, 0);
  249. return ov9640_reg_rmw(client, OV9640_MVFP, 0, OV9640_MVFP_H);
  250. }
  251. return -EINVAL;
  252. }
  253. #ifdef CONFIG_VIDEO_ADV_DEBUG
  254. static int ov9640_get_register(struct v4l2_subdev *sd,
  255. struct v4l2_dbg_register *reg)
  256. {
  257. struct i2c_client *client = v4l2_get_subdevdata(sd);
  258. int ret;
  259. u8 val;
  260. if (reg->reg & ~0xff)
  261. return -EINVAL;
  262. reg->size = 1;
  263. ret = ov9640_reg_read(client, reg->reg, &val);
  264. if (ret)
  265. return ret;
  266. reg->val = (__u64)val;
  267. return 0;
  268. }
  269. static int ov9640_set_register(struct v4l2_subdev *sd,
  270. const struct v4l2_dbg_register *reg)
  271. {
  272. struct i2c_client *client = v4l2_get_subdevdata(sd);
  273. if (reg->reg & ~0xff || reg->val & ~0xff)
  274. return -EINVAL;
  275. return ov9640_reg_write(client, reg->reg, reg->val);
  276. }
  277. #endif
  278. static int ov9640_s_power(struct v4l2_subdev *sd, int on)
  279. {
  280. struct ov9640_priv *priv = to_ov9640_sensor(sd);
  281. int ret = 0;
  282. if (on) {
  283. gpiod_set_value(priv->gpio_power, 1);
  284. usleep_range(1000, 2000);
  285. ret = v4l2_clk_enable(priv->clk);
  286. usleep_range(1000, 2000);
  287. gpiod_set_value(priv->gpio_reset, 0);
  288. } else {
  289. gpiod_set_value(priv->gpio_reset, 1);
  290. usleep_range(1000, 2000);
  291. v4l2_clk_disable(priv->clk);
  292. usleep_range(1000, 2000);
  293. gpiod_set_value(priv->gpio_power, 0);
  294. }
  295. return ret;
  296. }
  297. /* select nearest higher resolution for capture */
  298. static void ov9640_res_roundup(u32 *width, u32 *height)
  299. {
  300. unsigned int i;
  301. enum { QQCIF, QQVGA, QCIF, QVGA, CIF, VGA, SXGA };
  302. static const u32 res_x[] = { 88, 160, 176, 320, 352, 640, 1280 };
  303. static const u32 res_y[] = { 72, 120, 144, 240, 288, 480, 960 };
  304. for (i = 0; i < ARRAY_SIZE(res_x); i++) {
  305. if (res_x[i] >= *width && res_y[i] >= *height) {
  306. *width = res_x[i];
  307. *height = res_y[i];
  308. return;
  309. }
  310. }
  311. *width = res_x[SXGA];
  312. *height = res_y[SXGA];
  313. }
  314. /* Prepare necessary register changes depending on color encoding */
  315. static void ov9640_alter_regs(u32 code,
  316. struct ov9640_reg_alt *alt)
  317. {
  318. switch (code) {
  319. default:
  320. case MEDIA_BUS_FMT_UYVY8_2X8:
  321. alt->com12 = OV9640_COM12_YUV_AVG;
  322. alt->com13 = OV9640_COM13_Y_DELAY_EN |
  323. OV9640_COM13_YUV_DLY(0x01);
  324. break;
  325. case MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE:
  326. alt->com7 = OV9640_COM7_RGB;
  327. alt->com13 = OV9640_COM13_RGB_AVG;
  328. alt->com15 = OV9640_COM15_RGB_555;
  329. break;
  330. case MEDIA_BUS_FMT_RGB565_2X8_LE:
  331. alt->com7 = OV9640_COM7_RGB;
  332. alt->com13 = OV9640_COM13_RGB_AVG;
  333. alt->com15 = OV9640_COM15_RGB_565;
  334. break;
  335. }
  336. }
  337. /* Setup registers according to resolution and color encoding */
  338. static int ov9640_write_regs(struct i2c_client *client, u32 width,
  339. u32 code, struct ov9640_reg_alt *alts)
  340. {
  341. const struct ov9640_reg *ov9640_regs, *matrix_regs;
  342. unsigned int ov9640_regs_len, matrix_regs_len;
  343. unsigned int i;
  344. int ret;
  345. u8 val;
  346. /* select register configuration for given resolution */
  347. switch (width) {
  348. case W_QQCIF:
  349. ov9640_regs = ov9640_regs_qqcif;
  350. ov9640_regs_len = ARRAY_SIZE(ov9640_regs_qqcif);
  351. break;
  352. case W_QQVGA:
  353. ov9640_regs = ov9640_regs_qqvga;
  354. ov9640_regs_len = ARRAY_SIZE(ov9640_regs_qqvga);
  355. break;
  356. case W_QCIF:
  357. ov9640_regs = ov9640_regs_qcif;
  358. ov9640_regs_len = ARRAY_SIZE(ov9640_regs_qcif);
  359. break;
  360. case W_QVGA:
  361. ov9640_regs = ov9640_regs_qvga;
  362. ov9640_regs_len = ARRAY_SIZE(ov9640_regs_qvga);
  363. break;
  364. case W_CIF:
  365. ov9640_regs = ov9640_regs_cif;
  366. ov9640_regs_len = ARRAY_SIZE(ov9640_regs_cif);
  367. break;
  368. case W_VGA:
  369. ov9640_regs = ov9640_regs_vga;
  370. ov9640_regs_len = ARRAY_SIZE(ov9640_regs_vga);
  371. break;
  372. case W_SXGA:
  373. ov9640_regs = ov9640_regs_sxga;
  374. ov9640_regs_len = ARRAY_SIZE(ov9640_regs_sxga);
  375. break;
  376. default:
  377. dev_err(&client->dev, "Failed to select resolution!\n");
  378. return -EINVAL;
  379. }
  380. /* select color matrix configuration for given color encoding */
  381. if (code == MEDIA_BUS_FMT_UYVY8_2X8) {
  382. matrix_regs = ov9640_regs_yuv;
  383. matrix_regs_len = ARRAY_SIZE(ov9640_regs_yuv);
  384. } else {
  385. matrix_regs = ov9640_regs_rgb;
  386. matrix_regs_len = ARRAY_SIZE(ov9640_regs_rgb);
  387. }
  388. /* write register settings into the module */
  389. for (i = 0; i < ov9640_regs_len; i++) {
  390. val = ov9640_regs[i].val;
  391. switch (ov9640_regs[i].reg) {
  392. case OV9640_COM7:
  393. val |= alts->com7;
  394. break;
  395. case OV9640_COM12:
  396. val |= alts->com12;
  397. break;
  398. case OV9640_COM13:
  399. val |= alts->com13;
  400. break;
  401. case OV9640_COM15:
  402. val |= alts->com15;
  403. break;
  404. }
  405. ret = ov9640_reg_write(client, ov9640_regs[i].reg, val);
  406. if (ret)
  407. return ret;
  408. }
  409. /* write color matrix configuration into the module */
  410. for (i = 0; i < matrix_regs_len; i++) {
  411. ret = ov9640_reg_write(client, matrix_regs[i].reg,
  412. matrix_regs[i].val);
  413. if (ret)
  414. return ret;
  415. }
  416. return 0;
  417. }
  418. /* program default register values */
  419. static int ov9640_prog_dflt(struct i2c_client *client)
  420. {
  421. unsigned int i;
  422. int ret;
  423. for (i = 0; i < ARRAY_SIZE(ov9640_regs_dflt); i++) {
  424. ret = ov9640_reg_write(client, ov9640_regs_dflt[i].reg,
  425. ov9640_regs_dflt[i].val);
  426. if (ret)
  427. return ret;
  428. }
  429. /* wait for the changes to actually happen, 140ms are not enough yet */
  430. msleep(150);
  431. return 0;
  432. }
  433. /* set the format we will capture in */
  434. static int ov9640_s_fmt(struct v4l2_subdev *sd,
  435. struct v4l2_mbus_framefmt *mf)
  436. {
  437. struct i2c_client *client = v4l2_get_subdevdata(sd);
  438. struct ov9640_reg_alt alts = {0};
  439. int ret;
  440. ov9640_alter_regs(mf->code, &alts);
  441. ov9640_reset(client);
  442. ret = ov9640_prog_dflt(client);
  443. if (ret)
  444. return ret;
  445. return ov9640_write_regs(client, mf->width, mf->code, &alts);
  446. }
  447. static int ov9640_set_fmt(struct v4l2_subdev *sd,
  448. struct v4l2_subdev_pad_config *cfg,
  449. struct v4l2_subdev_format *format)
  450. {
  451. struct v4l2_mbus_framefmt *mf = &format->format;
  452. if (format->pad)
  453. return -EINVAL;
  454. ov9640_res_roundup(&mf->width, &mf->height);
  455. mf->field = V4L2_FIELD_NONE;
  456. switch (mf->code) {
  457. case MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE:
  458. case MEDIA_BUS_FMT_RGB565_2X8_LE:
  459. mf->colorspace = V4L2_COLORSPACE_SRGB;
  460. break;
  461. default:
  462. mf->code = MEDIA_BUS_FMT_UYVY8_2X8;
  463. fallthrough;
  464. case MEDIA_BUS_FMT_UYVY8_2X8:
  465. mf->colorspace = V4L2_COLORSPACE_JPEG;
  466. break;
  467. }
  468. if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE)
  469. return ov9640_s_fmt(sd, mf);
  470. cfg->try_fmt = *mf;
  471. return 0;
  472. }
  473. static int ov9640_enum_mbus_code(struct v4l2_subdev *sd,
  474. struct v4l2_subdev_pad_config *cfg,
  475. struct v4l2_subdev_mbus_code_enum *code)
  476. {
  477. if (code->pad || code->index >= ARRAY_SIZE(ov9640_codes))
  478. return -EINVAL;
  479. code->code = ov9640_codes[code->index];
  480. return 0;
  481. }
  482. static int ov9640_get_selection(struct v4l2_subdev *sd,
  483. struct v4l2_subdev_pad_config *cfg,
  484. struct v4l2_subdev_selection *sel)
  485. {
  486. if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE)
  487. return -EINVAL;
  488. sel->r.left = 0;
  489. sel->r.top = 0;
  490. switch (sel->target) {
  491. case V4L2_SEL_TGT_CROP_BOUNDS:
  492. case V4L2_SEL_TGT_CROP:
  493. sel->r.width = W_SXGA;
  494. sel->r.height = H_SXGA;
  495. return 0;
  496. default:
  497. return -EINVAL;
  498. }
  499. }
  500. static int ov9640_video_probe(struct i2c_client *client)
  501. {
  502. struct v4l2_subdev *sd = i2c_get_clientdata(client);
  503. struct ov9640_priv *priv = to_ov9640_sensor(sd);
  504. u8 pid, ver, midh, midl;
  505. const char *devname;
  506. int ret;
  507. ret = ov9640_s_power(&priv->subdev, 1);
  508. if (ret < 0)
  509. return ret;
  510. /*
  511. * check and show product ID and manufacturer ID
  512. */
  513. ret = ov9640_reg_read(client, OV9640_PID, &pid);
  514. if (!ret)
  515. ret = ov9640_reg_read(client, OV9640_VER, &ver);
  516. if (!ret)
  517. ret = ov9640_reg_read(client, OV9640_MIDH, &midh);
  518. if (!ret)
  519. ret = ov9640_reg_read(client, OV9640_MIDL, &midl);
  520. if (ret)
  521. goto done;
  522. switch (VERSION(pid, ver)) {
  523. case OV9640_V2:
  524. devname = "ov9640";
  525. priv->revision = 2;
  526. break;
  527. case OV9640_V3:
  528. devname = "ov9640";
  529. priv->revision = 3;
  530. break;
  531. default:
  532. dev_err(&client->dev, "Product ID error %x:%x\n", pid, ver);
  533. ret = -ENODEV;
  534. goto done;
  535. }
  536. dev_info(&client->dev, "%s Product ID %0x:%0x Manufacturer ID %x:%x\n",
  537. devname, pid, ver, midh, midl);
  538. ret = v4l2_ctrl_handler_setup(&priv->hdl);
  539. done:
  540. ov9640_s_power(&priv->subdev, 0);
  541. return ret;
  542. }
  543. static const struct v4l2_ctrl_ops ov9640_ctrl_ops = {
  544. .s_ctrl = ov9640_s_ctrl,
  545. };
  546. static const struct v4l2_subdev_core_ops ov9640_core_ops = {
  547. #ifdef CONFIG_VIDEO_ADV_DEBUG
  548. .g_register = ov9640_get_register,
  549. .s_register = ov9640_set_register,
  550. #endif
  551. .s_power = ov9640_s_power,
  552. };
  553. /* Request bus settings on camera side */
  554. static int ov9640_get_mbus_config(struct v4l2_subdev *sd,
  555. unsigned int pad,
  556. struct v4l2_mbus_config *cfg)
  557. {
  558. cfg->flags = V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_MASTER |
  559. V4L2_MBUS_VSYNC_ACTIVE_HIGH | V4L2_MBUS_HSYNC_ACTIVE_HIGH |
  560. V4L2_MBUS_DATA_ACTIVE_HIGH;
  561. cfg->type = V4L2_MBUS_PARALLEL;
  562. return 0;
  563. }
  564. static const struct v4l2_subdev_video_ops ov9640_video_ops = {
  565. .s_stream = ov9640_s_stream,
  566. };
  567. static const struct v4l2_subdev_pad_ops ov9640_pad_ops = {
  568. .enum_mbus_code = ov9640_enum_mbus_code,
  569. .get_selection = ov9640_get_selection,
  570. .set_fmt = ov9640_set_fmt,
  571. .get_mbus_config = ov9640_get_mbus_config,
  572. };
  573. static const struct v4l2_subdev_ops ov9640_subdev_ops = {
  574. .core = &ov9640_core_ops,
  575. .video = &ov9640_video_ops,
  576. .pad = &ov9640_pad_ops,
  577. };
  578. /*
  579. * i2c_driver function
  580. */
  581. static int ov9640_probe(struct i2c_client *client,
  582. const struct i2c_device_id *did)
  583. {
  584. struct ov9640_priv *priv;
  585. int ret;
  586. priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL);
  587. if (!priv)
  588. return -ENOMEM;
  589. priv->gpio_power = devm_gpiod_get(&client->dev, "Camera power",
  590. GPIOD_OUT_LOW);
  591. if (IS_ERR(priv->gpio_power)) {
  592. ret = PTR_ERR(priv->gpio_power);
  593. return ret;
  594. }
  595. priv->gpio_reset = devm_gpiod_get(&client->dev, "Camera reset",
  596. GPIOD_OUT_HIGH);
  597. if (IS_ERR(priv->gpio_reset)) {
  598. ret = PTR_ERR(priv->gpio_reset);
  599. return ret;
  600. }
  601. v4l2_i2c_subdev_init(&priv->subdev, client, &ov9640_subdev_ops);
  602. v4l2_ctrl_handler_init(&priv->hdl, 2);
  603. v4l2_ctrl_new_std(&priv->hdl, &ov9640_ctrl_ops,
  604. V4L2_CID_VFLIP, 0, 1, 1, 0);
  605. v4l2_ctrl_new_std(&priv->hdl, &ov9640_ctrl_ops,
  606. V4L2_CID_HFLIP, 0, 1, 1, 0);
  607. if (priv->hdl.error) {
  608. ret = priv->hdl.error;
  609. goto ectrlinit;
  610. }
  611. priv->subdev.ctrl_handler = &priv->hdl;
  612. priv->clk = v4l2_clk_get(&client->dev, "mclk");
  613. if (IS_ERR(priv->clk)) {
  614. ret = PTR_ERR(priv->clk);
  615. goto ectrlinit;
  616. }
  617. ret = ov9640_video_probe(client);
  618. if (ret)
  619. goto eprobe;
  620. priv->subdev.dev = &client->dev;
  621. ret = v4l2_async_register_subdev(&priv->subdev);
  622. if (ret)
  623. goto eprobe;
  624. return 0;
  625. eprobe:
  626. v4l2_clk_put(priv->clk);
  627. ectrlinit:
  628. v4l2_ctrl_handler_free(&priv->hdl);
  629. return ret;
  630. }
  631. static int ov9640_remove(struct i2c_client *client)
  632. {
  633. struct v4l2_subdev *sd = i2c_get_clientdata(client);
  634. struct ov9640_priv *priv = to_ov9640_sensor(sd);
  635. v4l2_clk_put(priv->clk);
  636. v4l2_async_unregister_subdev(&priv->subdev);
  637. v4l2_ctrl_handler_free(&priv->hdl);
  638. return 0;
  639. }
  640. static const struct i2c_device_id ov9640_id[] = {
  641. { "ov9640", 0 },
  642. { }
  643. };
  644. MODULE_DEVICE_TABLE(i2c, ov9640_id);
  645. static struct i2c_driver ov9640_i2c_driver = {
  646. .driver = {
  647. .name = "ov9640",
  648. },
  649. .probe = ov9640_probe,
  650. .remove = ov9640_remove,
  651. .id_table = ov9640_id,
  652. };
  653. module_i2c_driver(ov9640_i2c_driver);
  654. MODULE_DESCRIPTION("OmniVision OV96xx CMOS Image Sensor driver");
  655. MODULE_AUTHOR("Marek Vasut <marek.vasut@gmail.com>");
  656. MODULE_LICENSE("GPL v2");