mt9t112.c 28 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * mt9t112 Camera Driver
  4. *
  5. * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
  6. *
  7. * Copyright (C) 2009 Renesas Solutions Corp.
  8. * Kuninori Morimoto <morimoto.kuninori@renesas.com>
  9. *
  10. * Based on ov772x driver, mt9m111 driver,
  11. *
  12. * Copyright (C) 2008 Kuninori Morimoto <morimoto.kuninori@renesas.com>
  13. * Copyright (C) 2008, Robert Jarzmik <robert.jarzmik@free.fr>
  14. * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
  15. * Copyright (C) 2008 Magnus Damm
  16. * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
  17. *
  18. * TODO: This driver lacks support for frame rate control due to missing
  19. * register level documentation and suitable hardware for testing.
  20. * v4l-utils compliance tools will report errors.
  21. */
  22. #include <linux/clk.h>
  23. #include <linux/delay.h>
  24. #include <linux/gpio/consumer.h>
  25. #include <linux/i2c.h>
  26. #include <linux/init.h>
  27. #include <linux/module.h>
  28. #include <linux/slab.h>
  29. #include <linux/v4l2-mediabus.h>
  30. #include <linux/videodev2.h>
  31. #include <media/i2c/mt9t112.h>
  32. #include <media/v4l2-common.h>
  33. #include <media/v4l2-image-sizes.h>
  34. #include <media/v4l2-subdev.h>
  35. /* you can check PLL/clock info */
  36. /* #define EXT_CLOCK 24000000 */
  37. /************************************************************************
  38. * macro
  39. ***********************************************************************/
  40. /*
  41. * frame size
  42. */
  43. #define MAX_WIDTH 2048
  44. #define MAX_HEIGHT 1536
  45. /*
  46. * macro of read/write
  47. */
  48. #define ECHECKER(ret, x) \
  49. do { \
  50. (ret) = (x); \
  51. if ((ret) < 0) \
  52. return (ret); \
  53. } while (0)
  54. #define mt9t112_reg_write(ret, client, a, b) \
  55. ECHECKER(ret, __mt9t112_reg_write(client, a, b))
  56. #define mt9t112_mcu_write(ret, client, a, b) \
  57. ECHECKER(ret, __mt9t112_mcu_write(client, a, b))
  58. #define mt9t112_reg_mask_set(ret, client, a, b, c) \
  59. ECHECKER(ret, __mt9t112_reg_mask_set(client, a, b, c))
  60. #define mt9t112_mcu_mask_set(ret, client, a, b, c) \
  61. ECHECKER(ret, __mt9t112_mcu_mask_set(client, a, b, c))
  62. #define mt9t112_reg_read(ret, client, a) \
  63. ECHECKER(ret, __mt9t112_reg_read(client, a))
  64. /*
  65. * Logical address
  66. */
  67. #define _VAR(id, offset, base) (base | (id & 0x1f) << 10 | (offset & 0x3ff))
  68. #define VAR(id, offset) _VAR(id, offset, 0x0000)
  69. #define VAR8(id, offset) _VAR(id, offset, 0x8000)
  70. /************************************************************************
  71. * struct
  72. ***********************************************************************/
  73. struct mt9t112_format {
  74. u32 code;
  75. enum v4l2_colorspace colorspace;
  76. u16 fmt;
  77. u16 order;
  78. };
  79. struct mt9t112_priv {
  80. struct v4l2_subdev subdev;
  81. struct mt9t112_platform_data *info;
  82. struct i2c_client *client;
  83. struct v4l2_rect frame;
  84. struct clk *clk;
  85. struct gpio_desc *standby_gpio;
  86. const struct mt9t112_format *format;
  87. int num_formats;
  88. bool init_done;
  89. };
  90. /************************************************************************
  91. * supported format
  92. ***********************************************************************/
  93. static const struct mt9t112_format mt9t112_cfmts[] = {
  94. {
  95. .code = MEDIA_BUS_FMT_UYVY8_2X8,
  96. .colorspace = V4L2_COLORSPACE_SRGB,
  97. .fmt = 1,
  98. .order = 0,
  99. }, {
  100. .code = MEDIA_BUS_FMT_VYUY8_2X8,
  101. .colorspace = V4L2_COLORSPACE_SRGB,
  102. .fmt = 1,
  103. .order = 1,
  104. }, {
  105. .code = MEDIA_BUS_FMT_YUYV8_2X8,
  106. .colorspace = V4L2_COLORSPACE_SRGB,
  107. .fmt = 1,
  108. .order = 2,
  109. }, {
  110. .code = MEDIA_BUS_FMT_YVYU8_2X8,
  111. .colorspace = V4L2_COLORSPACE_SRGB,
  112. .fmt = 1,
  113. .order = 3,
  114. }, {
  115. .code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE,
  116. .colorspace = V4L2_COLORSPACE_SRGB,
  117. .fmt = 8,
  118. .order = 2,
  119. }, {
  120. .code = MEDIA_BUS_FMT_RGB565_2X8_LE,
  121. .colorspace = V4L2_COLORSPACE_SRGB,
  122. .fmt = 4,
  123. .order = 2,
  124. },
  125. };
  126. /************************************************************************
  127. * general function
  128. ***********************************************************************/
  129. static struct mt9t112_priv *to_mt9t112(const struct i2c_client *client)
  130. {
  131. return container_of(i2c_get_clientdata(client),
  132. struct mt9t112_priv,
  133. subdev);
  134. }
  135. static int __mt9t112_reg_read(const struct i2c_client *client, u16 command)
  136. {
  137. struct i2c_msg msg[2];
  138. u8 buf[2];
  139. int ret;
  140. command = swab16(command);
  141. msg[0].addr = client->addr;
  142. msg[0].flags = 0;
  143. msg[0].len = 2;
  144. msg[0].buf = (u8 *)&command;
  145. msg[1].addr = client->addr;
  146. msg[1].flags = I2C_M_RD;
  147. msg[1].len = 2;
  148. msg[1].buf = buf;
  149. /*
  150. * If return value of this function is < 0, it means error, else,
  151. * below 16bit is valid data.
  152. */
  153. ret = i2c_transfer(client->adapter, msg, 2);
  154. if (ret < 0)
  155. return ret;
  156. memcpy(&ret, buf, 2);
  157. return swab16(ret);
  158. }
  159. static int __mt9t112_reg_write(const struct i2c_client *client,
  160. u16 command, u16 data)
  161. {
  162. struct i2c_msg msg;
  163. u8 buf[4];
  164. int ret;
  165. command = swab16(command);
  166. data = swab16(data);
  167. memcpy(buf + 0, &command, 2);
  168. memcpy(buf + 2, &data, 2);
  169. msg.addr = client->addr;
  170. msg.flags = 0;
  171. msg.len = 4;
  172. msg.buf = buf;
  173. /*
  174. * i2c_transfer return message length, but this function should
  175. * return 0 if correct case.
  176. */
  177. ret = i2c_transfer(client->adapter, &msg, 1);
  178. return ret >= 0 ? 0 : ret;
  179. }
  180. static int __mt9t112_reg_mask_set(const struct i2c_client *client,
  181. u16 command, u16 mask, u16 set)
  182. {
  183. int val = __mt9t112_reg_read(client, command);
  184. if (val < 0)
  185. return val;
  186. val &= ~mask;
  187. val |= set & mask;
  188. return __mt9t112_reg_write(client, command, val);
  189. }
  190. /* mcu access */
  191. static int __mt9t112_mcu_read(const struct i2c_client *client, u16 command)
  192. {
  193. int ret;
  194. ret = __mt9t112_reg_write(client, 0x098E, command);
  195. if (ret < 0)
  196. return ret;
  197. return __mt9t112_reg_read(client, 0x0990);
  198. }
  199. static int __mt9t112_mcu_write(const struct i2c_client *client,
  200. u16 command, u16 data)
  201. {
  202. int ret;
  203. ret = __mt9t112_reg_write(client, 0x098E, command);
  204. if (ret < 0)
  205. return ret;
  206. return __mt9t112_reg_write(client, 0x0990, data);
  207. }
  208. static int __mt9t112_mcu_mask_set(const struct i2c_client *client,
  209. u16 command, u16 mask, u16 set)
  210. {
  211. int val = __mt9t112_mcu_read(client, command);
  212. if (val < 0)
  213. return val;
  214. val &= ~mask;
  215. val |= set & mask;
  216. return __mt9t112_mcu_write(client, command, val);
  217. }
  218. static int mt9t112_reset(const struct i2c_client *client)
  219. {
  220. int ret;
  221. mt9t112_reg_mask_set(ret, client, 0x001a, 0x0001, 0x0001);
  222. usleep_range(1000, 5000);
  223. mt9t112_reg_mask_set(ret, client, 0x001a, 0x0001, 0x0000);
  224. return ret;
  225. }
  226. #ifndef EXT_CLOCK
  227. #define CLOCK_INFO(a, b)
  228. #else
  229. #define CLOCK_INFO(a, b) mt9t112_clock_info(a, b)
  230. static int mt9t112_clock_info(const struct i2c_client *client, u32 ext)
  231. {
  232. int m, n, p1, p2, p3, p4, p5, p6, p7;
  233. u32 vco, clk;
  234. char *enable;
  235. ext /= 1000; /* kbyte order */
  236. mt9t112_reg_read(n, client, 0x0012);
  237. p1 = n & 0x000f;
  238. n = n >> 4;
  239. p2 = n & 0x000f;
  240. n = n >> 4;
  241. p3 = n & 0x000f;
  242. mt9t112_reg_read(n, client, 0x002a);
  243. p4 = n & 0x000f;
  244. n = n >> 4;
  245. p5 = n & 0x000f;
  246. n = n >> 4;
  247. p6 = n & 0x000f;
  248. mt9t112_reg_read(n, client, 0x002c);
  249. p7 = n & 0x000f;
  250. mt9t112_reg_read(n, client, 0x0010);
  251. m = n & 0x00ff;
  252. n = (n >> 8) & 0x003f;
  253. enable = ((ext < 6000) || (ext > 54000)) ? "X" : "";
  254. dev_dbg(&client->dev, "EXTCLK : %10u K %s\n", ext, enable);
  255. vco = 2 * m * ext / (n + 1);
  256. enable = ((vco < 384000) || (vco > 768000)) ? "X" : "";
  257. dev_dbg(&client->dev, "VCO : %10u K %s\n", vco, enable);
  258. clk = vco / (p1 + 1) / (p2 + 1);
  259. enable = (clk > 96000) ? "X" : "";
  260. dev_dbg(&client->dev, "PIXCLK : %10u K %s\n", clk, enable);
  261. clk = vco / (p3 + 1);
  262. enable = (clk > 768000) ? "X" : "";
  263. dev_dbg(&client->dev, "MIPICLK : %10u K %s\n", clk, enable);
  264. clk = vco / (p6 + 1);
  265. enable = (clk > 96000) ? "X" : "";
  266. dev_dbg(&client->dev, "MCU CLK : %10u K %s\n", clk, enable);
  267. clk = vco / (p5 + 1);
  268. enable = (clk > 54000) ? "X" : "";
  269. dev_dbg(&client->dev, "SOC CLK : %10u K %s\n", clk, enable);
  270. clk = vco / (p4 + 1);
  271. enable = (clk > 70000) ? "X" : "";
  272. dev_dbg(&client->dev, "Sensor CLK : %10u K %s\n", clk, enable);
  273. clk = vco / (p7 + 1);
  274. dev_dbg(&client->dev, "External sensor : %10u K\n", clk);
  275. clk = ext / (n + 1);
  276. enable = ((clk < 2000) || (clk > 24000)) ? "X" : "";
  277. dev_dbg(&client->dev, "PFD : %10u K %s\n", clk, enable);
  278. return 0;
  279. }
  280. #endif
  281. static int mt9t112_set_a_frame_size(const struct i2c_client *client,
  282. u16 width, u16 height)
  283. {
  284. int ret;
  285. u16 wstart = (MAX_WIDTH - width) / 2;
  286. u16 hstart = (MAX_HEIGHT - height) / 2;
  287. /* (Context A) Image Width/Height. */
  288. mt9t112_mcu_write(ret, client, VAR(26, 0), width);
  289. mt9t112_mcu_write(ret, client, VAR(26, 2), height);
  290. /* (Context A) Output Width/Height. */
  291. mt9t112_mcu_write(ret, client, VAR(18, 43), 8 + width);
  292. mt9t112_mcu_write(ret, client, VAR(18, 45), 8 + height);
  293. /* (Context A) Start Row/Column. */
  294. mt9t112_mcu_write(ret, client, VAR(18, 2), 4 + hstart);
  295. mt9t112_mcu_write(ret, client, VAR(18, 4), 4 + wstart);
  296. /* (Context A) End Row/Column. */
  297. mt9t112_mcu_write(ret, client, VAR(18, 6), 11 + height + hstart);
  298. mt9t112_mcu_write(ret, client, VAR(18, 8), 11 + width + wstart);
  299. mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x06);
  300. return ret;
  301. }
  302. static int mt9t112_set_pll_dividers(const struct i2c_client *client,
  303. u8 m, u8 n, u8 p1, u8 p2, u8 p3, u8 p4,
  304. u8 p5, u8 p6, u8 p7)
  305. {
  306. int ret;
  307. u16 val;
  308. /* N/M */
  309. val = (n << 8) | (m << 0);
  310. mt9t112_reg_mask_set(ret, client, 0x0010, 0x3fff, val);
  311. /* P1/P2/P3 */
  312. val = ((p3 & 0x0F) << 8) | ((p2 & 0x0F) << 4) | ((p1 & 0x0F) << 0);
  313. mt9t112_reg_mask_set(ret, client, 0x0012, 0x0fff, val);
  314. /* P4/P5/P6 */
  315. val = (0x7 << 12) | ((p6 & 0x0F) << 8) | ((p5 & 0x0F) << 4) |
  316. ((p4 & 0x0F) << 0);
  317. mt9t112_reg_mask_set(ret, client, 0x002A, 0x7fff, val);
  318. /* P7 */
  319. val = (0x1 << 12) | ((p7 & 0x0F) << 0);
  320. mt9t112_reg_mask_set(ret, client, 0x002C, 0x100f, val);
  321. return ret;
  322. }
  323. static int mt9t112_init_pll(const struct i2c_client *client)
  324. {
  325. struct mt9t112_priv *priv = to_mt9t112(client);
  326. int data, i, ret;
  327. mt9t112_reg_mask_set(ret, client, 0x0014, 0x003, 0x0001);
  328. /* PLL control: BYPASS PLL = 8517. */
  329. mt9t112_reg_write(ret, client, 0x0014, 0x2145);
  330. /* Replace these registers when new timing parameters are generated. */
  331. mt9t112_set_pll_dividers(client,
  332. priv->info->divider.m, priv->info->divider.n,
  333. priv->info->divider.p1, priv->info->divider.p2,
  334. priv->info->divider.p3, priv->info->divider.p4,
  335. priv->info->divider.p5, priv->info->divider.p6,
  336. priv->info->divider.p7);
  337. /*
  338. * TEST_BYPASS on
  339. * PLL_ENABLE on
  340. * SEL_LOCK_DET on
  341. * TEST_BYPASS off
  342. */
  343. mt9t112_reg_write(ret, client, 0x0014, 0x2525);
  344. mt9t112_reg_write(ret, client, 0x0014, 0x2527);
  345. mt9t112_reg_write(ret, client, 0x0014, 0x3427);
  346. mt9t112_reg_write(ret, client, 0x0014, 0x3027);
  347. mdelay(10);
  348. /*
  349. * PLL_BYPASS off
  350. * Reference clock count
  351. * I2C Master Clock Divider
  352. */
  353. mt9t112_reg_write(ret, client, 0x0014, 0x3046);
  354. /* JPEG initialization workaround */
  355. mt9t112_reg_write(ret, client, 0x0016, 0x0400);
  356. mt9t112_reg_write(ret, client, 0x0022, 0x0190);
  357. mt9t112_reg_write(ret, client, 0x3B84, 0x0212);
  358. /* External sensor clock is PLL bypass. */
  359. mt9t112_reg_write(ret, client, 0x002E, 0x0500);
  360. mt9t112_reg_mask_set(ret, client, 0x0018, 0x0002, 0x0002);
  361. mt9t112_reg_mask_set(ret, client, 0x3B82, 0x0004, 0x0004);
  362. /* MCU disabled. */
  363. mt9t112_reg_mask_set(ret, client, 0x0018, 0x0004, 0x0004);
  364. /* Out of standby. */
  365. mt9t112_reg_mask_set(ret, client, 0x0018, 0x0001, 0);
  366. mdelay(50);
  367. /*
  368. * Standby Workaround
  369. * Disable Secondary I2C Pads
  370. */
  371. mt9t112_reg_write(ret, client, 0x0614, 0x0001);
  372. mdelay(1);
  373. mt9t112_reg_write(ret, client, 0x0614, 0x0001);
  374. mdelay(1);
  375. mt9t112_reg_write(ret, client, 0x0614, 0x0001);
  376. mdelay(1);
  377. mt9t112_reg_write(ret, client, 0x0614, 0x0001);
  378. mdelay(1);
  379. mt9t112_reg_write(ret, client, 0x0614, 0x0001);
  380. mdelay(1);
  381. mt9t112_reg_write(ret, client, 0x0614, 0x0001);
  382. mdelay(1);
  383. /* Poll to verify out of standby. Must Poll this bit. */
  384. for (i = 0; i < 100; i++) {
  385. mt9t112_reg_read(data, client, 0x0018);
  386. if (!(data & 0x4000))
  387. break;
  388. mdelay(10);
  389. }
  390. return ret;
  391. }
  392. static int mt9t112_init_setting(const struct i2c_client *client)
  393. {
  394. int ret;
  395. /* Adaptive Output Clock (A) */
  396. mt9t112_mcu_mask_set(ret, client, VAR(26, 160), 0x0040, 0x0000);
  397. /* Read Mode (A) */
  398. mt9t112_mcu_write(ret, client, VAR(18, 12), 0x0024);
  399. /* Fine Correction (A) */
  400. mt9t112_mcu_write(ret, client, VAR(18, 15), 0x00CC);
  401. /* Fine IT Min (A) */
  402. mt9t112_mcu_write(ret, client, VAR(18, 17), 0x01f1);
  403. /* Fine IT Max Margin (A) */
  404. mt9t112_mcu_write(ret, client, VAR(18, 19), 0x00fF);
  405. /* Base Frame Lines (A) */
  406. mt9t112_mcu_write(ret, client, VAR(18, 29), 0x032D);
  407. /* Min Line Length (A) */
  408. mt9t112_mcu_write(ret, client, VAR(18, 31), 0x073a);
  409. /* Line Length (A) */
  410. mt9t112_mcu_write(ret, client, VAR(18, 37), 0x07d0);
  411. /* Adaptive Output Clock (B) */
  412. mt9t112_mcu_mask_set(ret, client, VAR(27, 160), 0x0040, 0x0000);
  413. /* Row Start (B) */
  414. mt9t112_mcu_write(ret, client, VAR(18, 74), 0x004);
  415. /* Column Start (B) */
  416. mt9t112_mcu_write(ret, client, VAR(18, 76), 0x004);
  417. /* Row End (B) */
  418. mt9t112_mcu_write(ret, client, VAR(18, 78), 0x60B);
  419. /* Column End (B) */
  420. mt9t112_mcu_write(ret, client, VAR(18, 80), 0x80B);
  421. /* Fine Correction (B) */
  422. mt9t112_mcu_write(ret, client, VAR(18, 87), 0x008C);
  423. /* Fine IT Min (B) */
  424. mt9t112_mcu_write(ret, client, VAR(18, 89), 0x01F1);
  425. /* Fine IT Max Margin (B) */
  426. mt9t112_mcu_write(ret, client, VAR(18, 91), 0x00FF);
  427. /* Base Frame Lines (B) */
  428. mt9t112_mcu_write(ret, client, VAR(18, 101), 0x0668);
  429. /* Min Line Length (B) */
  430. mt9t112_mcu_write(ret, client, VAR(18, 103), 0x0AF0);
  431. /* Line Length (B) */
  432. mt9t112_mcu_write(ret, client, VAR(18, 109), 0x0AF0);
  433. /*
  434. * Flicker Detection registers.
  435. * This section should be replaced whenever new timing file is
  436. * generated. All the following registers need to be replaced.
  437. * Following registers are generated from Register Wizard but user can
  438. * modify them. For detail see auto flicker detection tuning.
  439. */
  440. /* FD_FDPERIOD_SELECT */
  441. mt9t112_mcu_write(ret, client, VAR8(8, 5), 0x01);
  442. /* PRI_B_CONFIG_FD_ALGO_RUN */
  443. mt9t112_mcu_write(ret, client, VAR(27, 17), 0x0003);
  444. /* PRI_A_CONFIG_FD_ALGO_RUN */
  445. mt9t112_mcu_write(ret, client, VAR(26, 17), 0x0003);
  446. /*
  447. * AFD range detection tuning registers.
  448. */
  449. /* Search_f1_50 */
  450. mt9t112_mcu_write(ret, client, VAR8(18, 165), 0x25);
  451. /* Search_f2_50 */
  452. mt9t112_mcu_write(ret, client, VAR8(18, 166), 0x28);
  453. /* Search_f1_60 */
  454. mt9t112_mcu_write(ret, client, VAR8(18, 167), 0x2C);
  455. /* Search_f2_60 */
  456. mt9t112_mcu_write(ret, client, VAR8(18, 168), 0x2F);
  457. /* Period_50Hz (A) */
  458. mt9t112_mcu_write(ret, client, VAR8(18, 68), 0xBA);
  459. /* Secret register by Aptina. */
  460. /* Period_50Hz (A MSB) */
  461. mt9t112_mcu_write(ret, client, VAR8(18, 303), 0x00);
  462. /* Period_60Hz (A) */
  463. mt9t112_mcu_write(ret, client, VAR8(18, 69), 0x9B);
  464. /* Secret register by Aptina. */
  465. /* Period_60Hz (A MSB) */
  466. mt9t112_mcu_write(ret, client, VAR8(18, 301), 0x00);
  467. /* Period_50Hz (B) */
  468. mt9t112_mcu_write(ret, client, VAR8(18, 140), 0x82);
  469. /* Secret register by Aptina. */
  470. /* Period_50Hz (B) MSB */
  471. mt9t112_mcu_write(ret, client, VAR8(18, 304), 0x00);
  472. /* Period_60Hz (B) */
  473. mt9t112_mcu_write(ret, client, VAR8(18, 141), 0x6D);
  474. /* Secret register by Aptina. */
  475. /* Period_60Hz (B) MSB */
  476. mt9t112_mcu_write(ret, client, VAR8(18, 302), 0x00);
  477. /* FD Mode */
  478. mt9t112_mcu_write(ret, client, VAR8(8, 2), 0x10);
  479. /* Stat_min */
  480. mt9t112_mcu_write(ret, client, VAR8(8, 9), 0x02);
  481. /* Stat_max */
  482. mt9t112_mcu_write(ret, client, VAR8(8, 10), 0x03);
  483. /* Min_amplitude */
  484. mt9t112_mcu_write(ret, client, VAR8(8, 12), 0x0A);
  485. /* RX FIFO Watermark (A) */
  486. mt9t112_mcu_write(ret, client, VAR(18, 70), 0x0014);
  487. /* RX FIFO Watermark (B) */
  488. mt9t112_mcu_write(ret, client, VAR(18, 142), 0x0014);
  489. /* MCLK: 16MHz
  490. * PCLK: 73MHz
  491. * CorePixCLK: 36.5 MHz
  492. */
  493. mt9t112_mcu_write(ret, client, VAR8(18, 0x0044), 133);
  494. mt9t112_mcu_write(ret, client, VAR8(18, 0x0045), 110);
  495. mt9t112_mcu_write(ret, client, VAR8(18, 0x008c), 130);
  496. mt9t112_mcu_write(ret, client, VAR8(18, 0x008d), 108);
  497. mt9t112_mcu_write(ret, client, VAR8(18, 0x00A5), 27);
  498. mt9t112_mcu_write(ret, client, VAR8(18, 0x00a6), 30);
  499. mt9t112_mcu_write(ret, client, VAR8(18, 0x00a7), 32);
  500. mt9t112_mcu_write(ret, client, VAR8(18, 0x00a8), 35);
  501. return ret;
  502. }
  503. static int mt9t112_auto_focus_setting(const struct i2c_client *client)
  504. {
  505. int ret;
  506. mt9t112_mcu_write(ret, client, VAR(12, 13), 0x000F);
  507. mt9t112_mcu_write(ret, client, VAR(12, 23), 0x0F0F);
  508. mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x06);
  509. mt9t112_reg_write(ret, client, 0x0614, 0x0000);
  510. mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x05);
  511. mt9t112_mcu_write(ret, client, VAR8(12, 2), 0x02);
  512. mt9t112_mcu_write(ret, client, VAR(12, 3), 0x0002);
  513. mt9t112_mcu_write(ret, client, VAR(17, 3), 0x8001);
  514. mt9t112_mcu_write(ret, client, VAR(17, 11), 0x0025);
  515. mt9t112_mcu_write(ret, client, VAR(17, 13), 0x0193);
  516. mt9t112_mcu_write(ret, client, VAR8(17, 33), 0x18);
  517. mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x05);
  518. return ret;
  519. }
  520. static int mt9t112_auto_focus_trigger(const struct i2c_client *client)
  521. {
  522. int ret;
  523. mt9t112_mcu_write(ret, client, VAR8(12, 25), 0x01);
  524. return ret;
  525. }
  526. static int mt9t112_init_camera(const struct i2c_client *client)
  527. {
  528. int ret;
  529. ECHECKER(ret, mt9t112_reset(client));
  530. ECHECKER(ret, mt9t112_init_pll(client));
  531. ECHECKER(ret, mt9t112_init_setting(client));
  532. ECHECKER(ret, mt9t112_auto_focus_setting(client));
  533. mt9t112_reg_mask_set(ret, client, 0x0018, 0x0004, 0);
  534. /* Analog setting B.*/
  535. mt9t112_reg_write(ret, client, 0x3084, 0x2409);
  536. mt9t112_reg_write(ret, client, 0x3092, 0x0A49);
  537. mt9t112_reg_write(ret, client, 0x3094, 0x4949);
  538. mt9t112_reg_write(ret, client, 0x3096, 0x4950);
  539. /*
  540. * Disable adaptive clock.
  541. * PRI_A_CONFIG_JPEG_OB_TX_CONTROL_VAR
  542. * PRI_B_CONFIG_JPEG_OB_TX_CONTROL_VAR
  543. */
  544. mt9t112_mcu_write(ret, client, VAR(26, 160), 0x0A2E);
  545. mt9t112_mcu_write(ret, client, VAR(27, 160), 0x0A2E);
  546. /*
  547. * Configure Status in Status_before_length Format and enable header.
  548. * PRI_B_CONFIG_JPEG_OB_TX_CONTROL_VAR
  549. */
  550. mt9t112_mcu_write(ret, client, VAR(27, 144), 0x0CB4);
  551. /*
  552. * Enable JPEG in context B.
  553. * PRI_B_CONFIG_JPEG_OB_TX_CONTROL_VAR
  554. */
  555. mt9t112_mcu_write(ret, client, VAR8(27, 142), 0x01);
  556. /* Disable Dac_TXLO. */
  557. mt9t112_reg_write(ret, client, 0x316C, 0x350F);
  558. /* Set max slew rates. */
  559. mt9t112_reg_write(ret, client, 0x1E, 0x777);
  560. return ret;
  561. }
  562. /************************************************************************
  563. * v4l2_subdev_core_ops
  564. ***********************************************************************/
  565. #ifdef CONFIG_VIDEO_ADV_DEBUG
  566. static int mt9t112_g_register(struct v4l2_subdev *sd,
  567. struct v4l2_dbg_register *reg)
  568. {
  569. struct i2c_client *client = v4l2_get_subdevdata(sd);
  570. int ret;
  571. reg->size = 2;
  572. mt9t112_reg_read(ret, client, reg->reg);
  573. reg->val = (__u64)ret;
  574. return 0;
  575. }
  576. static int mt9t112_s_register(struct v4l2_subdev *sd,
  577. const struct v4l2_dbg_register *reg)
  578. {
  579. struct i2c_client *client = v4l2_get_subdevdata(sd);
  580. int ret;
  581. mt9t112_reg_write(ret, client, reg->reg, reg->val);
  582. return ret;
  583. }
  584. #endif
  585. static int mt9t112_power_on(struct mt9t112_priv *priv)
  586. {
  587. int ret;
  588. ret = clk_prepare_enable(priv->clk);
  589. if (ret)
  590. return ret;
  591. if (priv->standby_gpio) {
  592. gpiod_set_value(priv->standby_gpio, 0);
  593. msleep(100);
  594. }
  595. return 0;
  596. }
  597. static int mt9t112_power_off(struct mt9t112_priv *priv)
  598. {
  599. clk_disable_unprepare(priv->clk);
  600. if (priv->standby_gpio) {
  601. gpiod_set_value(priv->standby_gpio, 1);
  602. msleep(100);
  603. }
  604. return 0;
  605. }
  606. static int mt9t112_s_power(struct v4l2_subdev *sd, int on)
  607. {
  608. struct i2c_client *client = v4l2_get_subdevdata(sd);
  609. struct mt9t112_priv *priv = to_mt9t112(client);
  610. return on ? mt9t112_power_on(priv) :
  611. mt9t112_power_off(priv);
  612. }
  613. static const struct v4l2_subdev_core_ops mt9t112_subdev_core_ops = {
  614. #ifdef CONFIG_VIDEO_ADV_DEBUG
  615. .g_register = mt9t112_g_register,
  616. .s_register = mt9t112_s_register,
  617. #endif
  618. .s_power = mt9t112_s_power,
  619. };
  620. /************************************************************************
  621. * v4l2_subdev_video_ops
  622. **********************************************************************/
  623. static int mt9t112_s_stream(struct v4l2_subdev *sd, int enable)
  624. {
  625. struct i2c_client *client = v4l2_get_subdevdata(sd);
  626. struct mt9t112_priv *priv = to_mt9t112(client);
  627. int ret = 0;
  628. if (!enable) {
  629. /* FIXME
  630. *
  631. * If user selected large output size, and used it long time,
  632. * mt9t112 camera will be very warm.
  633. *
  634. * But current driver can not stop mt9t112 camera.
  635. * So, set small size here to solve this problem.
  636. */
  637. mt9t112_set_a_frame_size(client, VGA_WIDTH, VGA_HEIGHT);
  638. return ret;
  639. }
  640. if (!priv->init_done) {
  641. u16 param = MT9T112_FLAG_PCLK_RISING_EDGE & priv->info->flags ?
  642. 0x0001 : 0x0000;
  643. ECHECKER(ret, mt9t112_init_camera(client));
  644. /* Invert PCLK (Data sampled on falling edge of pixclk). */
  645. mt9t112_reg_write(ret, client, 0x3C20, param);
  646. mdelay(5);
  647. priv->init_done = true;
  648. }
  649. mt9t112_mcu_write(ret, client, VAR(26, 7), priv->format->fmt);
  650. mt9t112_mcu_write(ret, client, VAR(26, 9), priv->format->order);
  651. mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x06);
  652. mt9t112_set_a_frame_size(client, priv->frame.width, priv->frame.height);
  653. ECHECKER(ret, mt9t112_auto_focus_trigger(client));
  654. dev_dbg(&client->dev, "format : %d\n", priv->format->code);
  655. dev_dbg(&client->dev, "size : %d x %d\n",
  656. priv->frame.width,
  657. priv->frame.height);
  658. CLOCK_INFO(client, EXT_CLOCK);
  659. return ret;
  660. }
  661. static int mt9t112_set_params(struct mt9t112_priv *priv,
  662. const struct v4l2_rect *rect,
  663. u32 code)
  664. {
  665. int i;
  666. /*
  667. * get color format
  668. */
  669. for (i = 0; i < priv->num_formats; i++)
  670. if (mt9t112_cfmts[i].code == code)
  671. break;
  672. if (i == priv->num_formats)
  673. return -EINVAL;
  674. priv->frame = *rect;
  675. /*
  676. * frame size check
  677. */
  678. v4l_bound_align_image(&priv->frame.width, 0, MAX_WIDTH, 0,
  679. &priv->frame.height, 0, MAX_HEIGHT, 0, 0);
  680. priv->format = mt9t112_cfmts + i;
  681. return 0;
  682. }
  683. static int mt9t112_get_selection(struct v4l2_subdev *sd,
  684. struct v4l2_subdev_pad_config *cfg,
  685. struct v4l2_subdev_selection *sel)
  686. {
  687. struct i2c_client *client = v4l2_get_subdevdata(sd);
  688. struct mt9t112_priv *priv = to_mt9t112(client);
  689. if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE)
  690. return -EINVAL;
  691. switch (sel->target) {
  692. case V4L2_SEL_TGT_CROP_BOUNDS:
  693. sel->r.left = 0;
  694. sel->r.top = 0;
  695. sel->r.width = MAX_WIDTH;
  696. sel->r.height = MAX_HEIGHT;
  697. return 0;
  698. case V4L2_SEL_TGT_CROP:
  699. sel->r = priv->frame;
  700. return 0;
  701. default:
  702. return -EINVAL;
  703. }
  704. }
  705. static int mt9t112_set_selection(struct v4l2_subdev *sd,
  706. struct v4l2_subdev_pad_config *cfg,
  707. struct v4l2_subdev_selection *sel)
  708. {
  709. struct i2c_client *client = v4l2_get_subdevdata(sd);
  710. struct mt9t112_priv *priv = to_mt9t112(client);
  711. const struct v4l2_rect *rect = &sel->r;
  712. if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE ||
  713. sel->target != V4L2_SEL_TGT_CROP)
  714. return -EINVAL;
  715. return mt9t112_set_params(priv, rect, priv->format->code);
  716. }
  717. static int mt9t112_get_fmt(struct v4l2_subdev *sd,
  718. struct v4l2_subdev_pad_config *cfg,
  719. struct v4l2_subdev_format *format)
  720. {
  721. struct v4l2_mbus_framefmt *mf = &format->format;
  722. struct i2c_client *client = v4l2_get_subdevdata(sd);
  723. struct mt9t112_priv *priv = to_mt9t112(client);
  724. if (format->pad)
  725. return -EINVAL;
  726. mf->width = priv->frame.width;
  727. mf->height = priv->frame.height;
  728. mf->colorspace = priv->format->colorspace;
  729. mf->code = priv->format->code;
  730. mf->field = V4L2_FIELD_NONE;
  731. return 0;
  732. }
  733. static int mt9t112_s_fmt(struct v4l2_subdev *sd,
  734. struct v4l2_mbus_framefmt *mf)
  735. {
  736. struct i2c_client *client = v4l2_get_subdevdata(sd);
  737. struct mt9t112_priv *priv = to_mt9t112(client);
  738. struct v4l2_rect rect = {
  739. .width = mf->width,
  740. .height = mf->height,
  741. .left = priv->frame.left,
  742. .top = priv->frame.top,
  743. };
  744. int ret;
  745. ret = mt9t112_set_params(priv, &rect, mf->code);
  746. if (!ret)
  747. mf->colorspace = priv->format->colorspace;
  748. return ret;
  749. }
  750. static int mt9t112_set_fmt(struct v4l2_subdev *sd,
  751. struct v4l2_subdev_pad_config *cfg,
  752. struct v4l2_subdev_format *format)
  753. {
  754. struct i2c_client *client = v4l2_get_subdevdata(sd);
  755. struct v4l2_mbus_framefmt *mf = &format->format;
  756. struct mt9t112_priv *priv = to_mt9t112(client);
  757. int i;
  758. if (format->pad)
  759. return -EINVAL;
  760. for (i = 0; i < priv->num_formats; i++)
  761. if (mt9t112_cfmts[i].code == mf->code)
  762. break;
  763. if (i == priv->num_formats) {
  764. mf->code = MEDIA_BUS_FMT_UYVY8_2X8;
  765. mf->colorspace = V4L2_COLORSPACE_JPEG;
  766. } else {
  767. mf->colorspace = mt9t112_cfmts[i].colorspace;
  768. }
  769. v4l_bound_align_image(&mf->width, 0, MAX_WIDTH, 0,
  770. &mf->height, 0, MAX_HEIGHT, 0, 0);
  771. mf->field = V4L2_FIELD_NONE;
  772. if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE)
  773. return mt9t112_s_fmt(sd, mf);
  774. cfg->try_fmt = *mf;
  775. return 0;
  776. }
  777. static int mt9t112_enum_mbus_code(struct v4l2_subdev *sd,
  778. struct v4l2_subdev_pad_config *cfg,
  779. struct v4l2_subdev_mbus_code_enum *code)
  780. {
  781. struct i2c_client *client = v4l2_get_subdevdata(sd);
  782. struct mt9t112_priv *priv = to_mt9t112(client);
  783. if (code->pad || code->index >= priv->num_formats)
  784. return -EINVAL;
  785. code->code = mt9t112_cfmts[code->index].code;
  786. return 0;
  787. }
  788. static const struct v4l2_subdev_video_ops mt9t112_subdev_video_ops = {
  789. .s_stream = mt9t112_s_stream,
  790. };
  791. static const struct v4l2_subdev_pad_ops mt9t112_subdev_pad_ops = {
  792. .enum_mbus_code = mt9t112_enum_mbus_code,
  793. .get_selection = mt9t112_get_selection,
  794. .set_selection = mt9t112_set_selection,
  795. .get_fmt = mt9t112_get_fmt,
  796. .set_fmt = mt9t112_set_fmt,
  797. };
  798. /************************************************************************
  799. * i2c driver
  800. ***********************************************************************/
  801. static const struct v4l2_subdev_ops mt9t112_subdev_ops = {
  802. .core = &mt9t112_subdev_core_ops,
  803. .video = &mt9t112_subdev_video_ops,
  804. .pad = &mt9t112_subdev_pad_ops,
  805. };
  806. static int mt9t112_camera_probe(struct i2c_client *client)
  807. {
  808. struct mt9t112_priv *priv = to_mt9t112(client);
  809. const char *devname;
  810. int chipid;
  811. int ret;
  812. ret = mt9t112_s_power(&priv->subdev, 1);
  813. if (ret < 0)
  814. return ret;
  815. /* Check and show chip ID. */
  816. mt9t112_reg_read(chipid, client, 0x0000);
  817. switch (chipid) {
  818. case 0x2680:
  819. devname = "mt9t111";
  820. priv->num_formats = 1;
  821. break;
  822. case 0x2682:
  823. devname = "mt9t112";
  824. priv->num_formats = ARRAY_SIZE(mt9t112_cfmts);
  825. break;
  826. default:
  827. dev_err(&client->dev, "Product ID error %04x\n", chipid);
  828. ret = -ENODEV;
  829. goto done;
  830. }
  831. dev_info(&client->dev, "%s chip ID %04x\n", devname, chipid);
  832. done:
  833. mt9t112_s_power(&priv->subdev, 0);
  834. return ret;
  835. }
  836. static int mt9t112_probe(struct i2c_client *client,
  837. const struct i2c_device_id *did)
  838. {
  839. struct mt9t112_priv *priv;
  840. int ret;
  841. if (!client->dev.platform_data) {
  842. dev_err(&client->dev, "mt9t112: missing platform data!\n");
  843. return -EINVAL;
  844. }
  845. priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL);
  846. if (!priv)
  847. return -ENOMEM;
  848. priv->info = client->dev.platform_data;
  849. priv->init_done = false;
  850. v4l2_i2c_subdev_init(&priv->subdev, client, &mt9t112_subdev_ops);
  851. priv->clk = devm_clk_get(&client->dev, "extclk");
  852. if (PTR_ERR(priv->clk) == -ENOENT) {
  853. priv->clk = NULL;
  854. } else if (IS_ERR(priv->clk)) {
  855. dev_err(&client->dev, "Unable to get clock \"extclk\"\n");
  856. return PTR_ERR(priv->clk);
  857. }
  858. priv->standby_gpio = devm_gpiod_get_optional(&client->dev, "standby",
  859. GPIOD_OUT_HIGH);
  860. if (IS_ERR(priv->standby_gpio)) {
  861. dev_err(&client->dev, "Unable to get gpio \"standby\"\n");
  862. return PTR_ERR(priv->standby_gpio);
  863. }
  864. ret = mt9t112_camera_probe(client);
  865. if (ret)
  866. return ret;
  867. return v4l2_async_register_subdev(&priv->subdev);
  868. }
  869. static int mt9t112_remove(struct i2c_client *client)
  870. {
  871. struct mt9t112_priv *priv = to_mt9t112(client);
  872. clk_disable_unprepare(priv->clk);
  873. v4l2_async_unregister_subdev(&priv->subdev);
  874. return 0;
  875. }
  876. static const struct i2c_device_id mt9t112_id[] = {
  877. { "mt9t112", 0 },
  878. { }
  879. };
  880. MODULE_DEVICE_TABLE(i2c, mt9t112_id);
  881. static struct i2c_driver mt9t112_i2c_driver = {
  882. .driver = {
  883. .name = "mt9t112",
  884. },
  885. .probe = mt9t112_probe,
  886. .remove = mt9t112_remove,
  887. .id_table = mt9t112_id,
  888. };
  889. module_i2c_driver(mt9t112_i2c_driver);
  890. MODULE_DESCRIPTION("V4L2 driver for MT9T111/MT9T112 camera sensor");
  891. MODULE_AUTHOR("Kuninori Morimoto");
  892. MODULE_LICENSE("GPL v2");