mt9t001.c 27 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Driver for MT9T001 CMOS Image Sensor from Aptina (Micron)
  4. *
  5. * Copyright (C) 2010-2011, Laurent Pinchart <laurent.pinchart@ideasonboard.com>
  6. *
  7. * Based on the MT9M001 driver,
  8. *
  9. * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
  10. */
  11. #include <linux/clk.h>
  12. #include <linux/i2c.h>
  13. #include <linux/log2.h>
  14. #include <linux/module.h>
  15. #include <linux/regulator/consumer.h>
  16. #include <linux/slab.h>
  17. #include <linux/videodev2.h>
  18. #include <linux/v4l2-mediabus.h>
  19. #include <media/i2c/mt9t001.h>
  20. #include <media/v4l2-ctrls.h>
  21. #include <media/v4l2-device.h>
  22. #include <media/v4l2-subdev.h>
  23. #define MT9T001_PIXEL_ARRAY_HEIGHT 1568
  24. #define MT9T001_PIXEL_ARRAY_WIDTH 2112
  25. #define MT9T001_CHIP_VERSION 0x00
  26. #define MT9T001_CHIP_ID 0x1621
  27. #define MT9T001_ROW_START 0x01
  28. #define MT9T001_ROW_START_MIN 0
  29. #define MT9T001_ROW_START_DEF 20
  30. #define MT9T001_ROW_START_MAX 1534
  31. #define MT9T001_COLUMN_START 0x02
  32. #define MT9T001_COLUMN_START_MIN 0
  33. #define MT9T001_COLUMN_START_DEF 32
  34. #define MT9T001_COLUMN_START_MAX 2046
  35. #define MT9T001_WINDOW_HEIGHT 0x03
  36. #define MT9T001_WINDOW_HEIGHT_MIN 1
  37. #define MT9T001_WINDOW_HEIGHT_DEF 1535
  38. #define MT9T001_WINDOW_HEIGHT_MAX 1567
  39. #define MT9T001_WINDOW_WIDTH 0x04
  40. #define MT9T001_WINDOW_WIDTH_MIN 1
  41. #define MT9T001_WINDOW_WIDTH_DEF 2047
  42. #define MT9T001_WINDOW_WIDTH_MAX 2111
  43. #define MT9T001_HORIZONTAL_BLANKING 0x05
  44. #define MT9T001_HORIZONTAL_BLANKING_MIN 21
  45. #define MT9T001_HORIZONTAL_BLANKING_MAX 1023
  46. #define MT9T001_VERTICAL_BLANKING 0x06
  47. #define MT9T001_VERTICAL_BLANKING_MIN 3
  48. #define MT9T001_VERTICAL_BLANKING_MAX 1023
  49. #define MT9T001_OUTPUT_CONTROL 0x07
  50. #define MT9T001_OUTPUT_CONTROL_SYNC (1 << 0)
  51. #define MT9T001_OUTPUT_CONTROL_CHIP_ENABLE (1 << 1)
  52. #define MT9T001_OUTPUT_CONTROL_TEST_DATA (1 << 6)
  53. #define MT9T001_OUTPUT_CONTROL_DEF 0x0002
  54. #define MT9T001_SHUTTER_WIDTH_HIGH 0x08
  55. #define MT9T001_SHUTTER_WIDTH_LOW 0x09
  56. #define MT9T001_SHUTTER_WIDTH_MIN 1
  57. #define MT9T001_SHUTTER_WIDTH_DEF 1561
  58. #define MT9T001_SHUTTER_WIDTH_MAX (1024 * 1024)
  59. #define MT9T001_PIXEL_CLOCK 0x0a
  60. #define MT9T001_PIXEL_CLOCK_INVERT (1 << 15)
  61. #define MT9T001_PIXEL_CLOCK_SHIFT_MASK (7 << 8)
  62. #define MT9T001_PIXEL_CLOCK_SHIFT_SHIFT 8
  63. #define MT9T001_PIXEL_CLOCK_DIVIDE_MASK (0x7f << 0)
  64. #define MT9T001_FRAME_RESTART 0x0b
  65. #define MT9T001_SHUTTER_DELAY 0x0c
  66. #define MT9T001_SHUTTER_DELAY_MAX 2047
  67. #define MT9T001_RESET 0x0d
  68. #define MT9T001_READ_MODE1 0x1e
  69. #define MT9T001_READ_MODE_SNAPSHOT (1 << 8)
  70. #define MT9T001_READ_MODE_STROBE_ENABLE (1 << 9)
  71. #define MT9T001_READ_MODE_STROBE_WIDTH (1 << 10)
  72. #define MT9T001_READ_MODE_STROBE_OVERRIDE (1 << 11)
  73. #define MT9T001_READ_MODE2 0x20
  74. #define MT9T001_READ_MODE_BAD_FRAMES (1 << 0)
  75. #define MT9T001_READ_MODE_LINE_VALID_CONTINUOUS (1 << 9)
  76. #define MT9T001_READ_MODE_LINE_VALID_FRAME (1 << 10)
  77. #define MT9T001_READ_MODE3 0x21
  78. #define MT9T001_READ_MODE_GLOBAL_RESET (1 << 0)
  79. #define MT9T001_READ_MODE_GHST_CTL (1 << 1)
  80. #define MT9T001_ROW_ADDRESS_MODE 0x22
  81. #define MT9T001_ROW_SKIP_MASK (7 << 0)
  82. #define MT9T001_ROW_BIN_MASK (3 << 3)
  83. #define MT9T001_ROW_BIN_SHIFT 3
  84. #define MT9T001_COLUMN_ADDRESS_MODE 0x23
  85. #define MT9T001_COLUMN_SKIP_MASK (7 << 0)
  86. #define MT9T001_COLUMN_BIN_MASK (3 << 3)
  87. #define MT9T001_COLUMN_BIN_SHIFT 3
  88. #define MT9T001_GREEN1_GAIN 0x2b
  89. #define MT9T001_BLUE_GAIN 0x2c
  90. #define MT9T001_RED_GAIN 0x2d
  91. #define MT9T001_GREEN2_GAIN 0x2e
  92. #define MT9T001_TEST_DATA 0x32
  93. #define MT9T001_GLOBAL_GAIN 0x35
  94. #define MT9T001_GLOBAL_GAIN_MIN 8
  95. #define MT9T001_GLOBAL_GAIN_MAX 1024
  96. #define MT9T001_BLACK_LEVEL 0x49
  97. #define MT9T001_ROW_BLACK_DEFAULT_OFFSET 0x4b
  98. #define MT9T001_BLC_DELTA_THRESHOLDS 0x5d
  99. #define MT9T001_CAL_THRESHOLDS 0x5f
  100. #define MT9T001_GREEN1_OFFSET 0x60
  101. #define MT9T001_GREEN2_OFFSET 0x61
  102. #define MT9T001_BLACK_LEVEL_CALIBRATION 0x62
  103. #define MT9T001_BLACK_LEVEL_OVERRIDE (1 << 0)
  104. #define MT9T001_BLACK_LEVEL_DISABLE_OFFSET (1 << 1)
  105. #define MT9T001_BLACK_LEVEL_RECALCULATE (1 << 12)
  106. #define MT9T001_BLACK_LEVEL_LOCK_RED_BLUE (1 << 13)
  107. #define MT9T001_BLACK_LEVEL_LOCK_GREEN (1 << 14)
  108. #define MT9T001_RED_OFFSET 0x63
  109. #define MT9T001_BLUE_OFFSET 0x64
  110. struct mt9t001 {
  111. struct v4l2_subdev subdev;
  112. struct media_pad pad;
  113. struct clk *clk;
  114. struct regulator_bulk_data regulators[2];
  115. struct mutex power_lock; /* lock to protect power_count */
  116. int power_count;
  117. struct v4l2_mbus_framefmt format;
  118. struct v4l2_rect crop;
  119. struct v4l2_ctrl_handler ctrls;
  120. struct v4l2_ctrl *gains[4];
  121. u16 output_control;
  122. u16 black_level;
  123. };
  124. static inline struct mt9t001 *to_mt9t001(struct v4l2_subdev *sd)
  125. {
  126. return container_of(sd, struct mt9t001, subdev);
  127. }
  128. static int mt9t001_read(struct i2c_client *client, u8 reg)
  129. {
  130. return i2c_smbus_read_word_swapped(client, reg);
  131. }
  132. static int mt9t001_write(struct i2c_client *client, u8 reg, u16 data)
  133. {
  134. return i2c_smbus_write_word_swapped(client, reg, data);
  135. }
  136. static int mt9t001_set_output_control(struct mt9t001 *mt9t001, u16 clear,
  137. u16 set)
  138. {
  139. struct i2c_client *client = v4l2_get_subdevdata(&mt9t001->subdev);
  140. u16 value = (mt9t001->output_control & ~clear) | set;
  141. int ret;
  142. if (value == mt9t001->output_control)
  143. return 0;
  144. ret = mt9t001_write(client, MT9T001_OUTPUT_CONTROL, value);
  145. if (ret < 0)
  146. return ret;
  147. mt9t001->output_control = value;
  148. return 0;
  149. }
  150. static int mt9t001_reset(struct mt9t001 *mt9t001)
  151. {
  152. struct i2c_client *client = v4l2_get_subdevdata(&mt9t001->subdev);
  153. int ret;
  154. /* Reset the chip and stop data read out */
  155. ret = mt9t001_write(client, MT9T001_RESET, 1);
  156. if (ret < 0)
  157. return ret;
  158. ret = mt9t001_write(client, MT9T001_RESET, 0);
  159. if (ret < 0)
  160. return ret;
  161. mt9t001->output_control = MT9T001_OUTPUT_CONTROL_DEF;
  162. return mt9t001_set_output_control(mt9t001,
  163. MT9T001_OUTPUT_CONTROL_CHIP_ENABLE,
  164. 0);
  165. }
  166. static int mt9t001_power_on(struct mt9t001 *mt9t001)
  167. {
  168. int ret;
  169. /* Bring up the supplies */
  170. ret = regulator_bulk_enable(ARRAY_SIZE(mt9t001->regulators),
  171. mt9t001->regulators);
  172. if (ret < 0)
  173. return ret;
  174. /* Enable clock */
  175. ret = clk_prepare_enable(mt9t001->clk);
  176. if (ret < 0)
  177. regulator_bulk_disable(ARRAY_SIZE(mt9t001->regulators),
  178. mt9t001->regulators);
  179. return ret;
  180. }
  181. static void mt9t001_power_off(struct mt9t001 *mt9t001)
  182. {
  183. regulator_bulk_disable(ARRAY_SIZE(mt9t001->regulators),
  184. mt9t001->regulators);
  185. clk_disable_unprepare(mt9t001->clk);
  186. }
  187. static int __mt9t001_set_power(struct mt9t001 *mt9t001, bool on)
  188. {
  189. struct i2c_client *client = v4l2_get_subdevdata(&mt9t001->subdev);
  190. int ret;
  191. if (!on) {
  192. mt9t001_power_off(mt9t001);
  193. return 0;
  194. }
  195. ret = mt9t001_power_on(mt9t001);
  196. if (ret < 0)
  197. return ret;
  198. ret = mt9t001_reset(mt9t001);
  199. if (ret < 0) {
  200. dev_err(&client->dev, "Failed to reset the camera\n");
  201. goto e_power;
  202. }
  203. ret = v4l2_ctrl_handler_setup(&mt9t001->ctrls);
  204. if (ret < 0) {
  205. dev_err(&client->dev, "Failed to set up control handlers\n");
  206. goto e_power;
  207. }
  208. return 0;
  209. e_power:
  210. mt9t001_power_off(mt9t001);
  211. return ret;
  212. }
  213. /* -----------------------------------------------------------------------------
  214. * V4L2 subdev video operations
  215. */
  216. static struct v4l2_mbus_framefmt *
  217. __mt9t001_get_pad_format(struct mt9t001 *mt9t001, struct v4l2_subdev_pad_config *cfg,
  218. unsigned int pad, enum v4l2_subdev_format_whence which)
  219. {
  220. switch (which) {
  221. case V4L2_SUBDEV_FORMAT_TRY:
  222. return v4l2_subdev_get_try_format(&mt9t001->subdev, cfg, pad);
  223. case V4L2_SUBDEV_FORMAT_ACTIVE:
  224. return &mt9t001->format;
  225. default:
  226. return NULL;
  227. }
  228. }
  229. static struct v4l2_rect *
  230. __mt9t001_get_pad_crop(struct mt9t001 *mt9t001, struct v4l2_subdev_pad_config *cfg,
  231. unsigned int pad, enum v4l2_subdev_format_whence which)
  232. {
  233. switch (which) {
  234. case V4L2_SUBDEV_FORMAT_TRY:
  235. return v4l2_subdev_get_try_crop(&mt9t001->subdev, cfg, pad);
  236. case V4L2_SUBDEV_FORMAT_ACTIVE:
  237. return &mt9t001->crop;
  238. default:
  239. return NULL;
  240. }
  241. }
  242. static int mt9t001_s_stream(struct v4l2_subdev *subdev, int enable)
  243. {
  244. const u16 mode = MT9T001_OUTPUT_CONTROL_CHIP_ENABLE;
  245. struct i2c_client *client = v4l2_get_subdevdata(subdev);
  246. struct mt9t001_platform_data *pdata = client->dev.platform_data;
  247. struct mt9t001 *mt9t001 = to_mt9t001(subdev);
  248. struct v4l2_mbus_framefmt *format = &mt9t001->format;
  249. struct v4l2_rect *crop = &mt9t001->crop;
  250. unsigned int hratio;
  251. unsigned int vratio;
  252. int ret;
  253. if (!enable)
  254. return mt9t001_set_output_control(mt9t001, mode, 0);
  255. /* Configure the pixel clock polarity */
  256. if (pdata->clk_pol) {
  257. ret = mt9t001_write(client, MT9T001_PIXEL_CLOCK,
  258. MT9T001_PIXEL_CLOCK_INVERT);
  259. if (ret < 0)
  260. return ret;
  261. }
  262. /* Configure the window size and row/column bin */
  263. hratio = DIV_ROUND_CLOSEST(crop->width, format->width);
  264. vratio = DIV_ROUND_CLOSEST(crop->height, format->height);
  265. ret = mt9t001_write(client, MT9T001_ROW_ADDRESS_MODE, hratio - 1);
  266. if (ret < 0)
  267. return ret;
  268. ret = mt9t001_write(client, MT9T001_COLUMN_ADDRESS_MODE, vratio - 1);
  269. if (ret < 0)
  270. return ret;
  271. ret = mt9t001_write(client, MT9T001_COLUMN_START, crop->left);
  272. if (ret < 0)
  273. return ret;
  274. ret = mt9t001_write(client, MT9T001_ROW_START, crop->top);
  275. if (ret < 0)
  276. return ret;
  277. ret = mt9t001_write(client, MT9T001_WINDOW_WIDTH, crop->width - 1);
  278. if (ret < 0)
  279. return ret;
  280. ret = mt9t001_write(client, MT9T001_WINDOW_HEIGHT, crop->height - 1);
  281. if (ret < 0)
  282. return ret;
  283. /* Switch to master "normal" mode */
  284. return mt9t001_set_output_control(mt9t001, 0, mode);
  285. }
  286. static int mt9t001_enum_mbus_code(struct v4l2_subdev *subdev,
  287. struct v4l2_subdev_pad_config *cfg,
  288. struct v4l2_subdev_mbus_code_enum *code)
  289. {
  290. if (code->index > 0)
  291. return -EINVAL;
  292. code->code = MEDIA_BUS_FMT_SGRBG10_1X10;
  293. return 0;
  294. }
  295. static int mt9t001_enum_frame_size(struct v4l2_subdev *subdev,
  296. struct v4l2_subdev_pad_config *cfg,
  297. struct v4l2_subdev_frame_size_enum *fse)
  298. {
  299. if (fse->index >= 8 || fse->code != MEDIA_BUS_FMT_SGRBG10_1X10)
  300. return -EINVAL;
  301. fse->min_width = (MT9T001_WINDOW_WIDTH_DEF + 1) / fse->index;
  302. fse->max_width = fse->min_width;
  303. fse->min_height = (MT9T001_WINDOW_HEIGHT_DEF + 1) / fse->index;
  304. fse->max_height = fse->min_height;
  305. return 0;
  306. }
  307. static int mt9t001_get_format(struct v4l2_subdev *subdev,
  308. struct v4l2_subdev_pad_config *cfg,
  309. struct v4l2_subdev_format *format)
  310. {
  311. struct mt9t001 *mt9t001 = to_mt9t001(subdev);
  312. format->format = *__mt9t001_get_pad_format(mt9t001, cfg, format->pad,
  313. format->which);
  314. return 0;
  315. }
  316. static int mt9t001_set_format(struct v4l2_subdev *subdev,
  317. struct v4l2_subdev_pad_config *cfg,
  318. struct v4l2_subdev_format *format)
  319. {
  320. struct mt9t001 *mt9t001 = to_mt9t001(subdev);
  321. struct v4l2_mbus_framefmt *__format;
  322. struct v4l2_rect *__crop;
  323. unsigned int width;
  324. unsigned int height;
  325. unsigned int hratio;
  326. unsigned int vratio;
  327. __crop = __mt9t001_get_pad_crop(mt9t001, cfg, format->pad,
  328. format->which);
  329. /* Clamp the width and height to avoid dividing by zero. */
  330. width = clamp_t(unsigned int, ALIGN(format->format.width, 2),
  331. max_t(unsigned int, __crop->width / 8,
  332. MT9T001_WINDOW_HEIGHT_MIN + 1),
  333. __crop->width);
  334. height = clamp_t(unsigned int, ALIGN(format->format.height, 2),
  335. max_t(unsigned int, __crop->height / 8,
  336. MT9T001_WINDOW_HEIGHT_MIN + 1),
  337. __crop->height);
  338. hratio = DIV_ROUND_CLOSEST(__crop->width, width);
  339. vratio = DIV_ROUND_CLOSEST(__crop->height, height);
  340. __format = __mt9t001_get_pad_format(mt9t001, cfg, format->pad,
  341. format->which);
  342. __format->width = __crop->width / hratio;
  343. __format->height = __crop->height / vratio;
  344. format->format = *__format;
  345. return 0;
  346. }
  347. static int mt9t001_get_selection(struct v4l2_subdev *subdev,
  348. struct v4l2_subdev_pad_config *cfg,
  349. struct v4l2_subdev_selection *sel)
  350. {
  351. struct mt9t001 *mt9t001 = to_mt9t001(subdev);
  352. if (sel->target != V4L2_SEL_TGT_CROP)
  353. return -EINVAL;
  354. sel->r = *__mt9t001_get_pad_crop(mt9t001, cfg, sel->pad, sel->which);
  355. return 0;
  356. }
  357. static int mt9t001_set_selection(struct v4l2_subdev *subdev,
  358. struct v4l2_subdev_pad_config *cfg,
  359. struct v4l2_subdev_selection *sel)
  360. {
  361. struct mt9t001 *mt9t001 = to_mt9t001(subdev);
  362. struct v4l2_mbus_framefmt *__format;
  363. struct v4l2_rect *__crop;
  364. struct v4l2_rect rect;
  365. if (sel->target != V4L2_SEL_TGT_CROP)
  366. return -EINVAL;
  367. /* Clamp the crop rectangle boundaries and align them to a multiple of 2
  368. * pixels.
  369. */
  370. rect.left = clamp(ALIGN(sel->r.left, 2),
  371. MT9T001_COLUMN_START_MIN,
  372. MT9T001_COLUMN_START_MAX);
  373. rect.top = clamp(ALIGN(sel->r.top, 2),
  374. MT9T001_ROW_START_MIN,
  375. MT9T001_ROW_START_MAX);
  376. rect.width = clamp_t(unsigned int, ALIGN(sel->r.width, 2),
  377. MT9T001_WINDOW_WIDTH_MIN + 1,
  378. MT9T001_WINDOW_WIDTH_MAX + 1);
  379. rect.height = clamp_t(unsigned int, ALIGN(sel->r.height, 2),
  380. MT9T001_WINDOW_HEIGHT_MIN + 1,
  381. MT9T001_WINDOW_HEIGHT_MAX + 1);
  382. rect.width = min_t(unsigned int, rect.width,
  383. MT9T001_PIXEL_ARRAY_WIDTH - rect.left);
  384. rect.height = min_t(unsigned int, rect.height,
  385. MT9T001_PIXEL_ARRAY_HEIGHT - rect.top);
  386. __crop = __mt9t001_get_pad_crop(mt9t001, cfg, sel->pad, sel->which);
  387. if (rect.width != __crop->width || rect.height != __crop->height) {
  388. /* Reset the output image size if the crop rectangle size has
  389. * been modified.
  390. */
  391. __format = __mt9t001_get_pad_format(mt9t001, cfg, sel->pad,
  392. sel->which);
  393. __format->width = rect.width;
  394. __format->height = rect.height;
  395. }
  396. *__crop = rect;
  397. sel->r = rect;
  398. return 0;
  399. }
  400. /* -----------------------------------------------------------------------------
  401. * V4L2 subdev control operations
  402. */
  403. #define V4L2_CID_TEST_PATTERN_COLOR (V4L2_CID_USER_BASE | 0x1001)
  404. #define V4L2_CID_BLACK_LEVEL_AUTO (V4L2_CID_USER_BASE | 0x1002)
  405. #define V4L2_CID_BLACK_LEVEL_OFFSET (V4L2_CID_USER_BASE | 0x1003)
  406. #define V4L2_CID_BLACK_LEVEL_CALIBRATE (V4L2_CID_USER_BASE | 0x1004)
  407. #define V4L2_CID_GAIN_RED (V4L2_CTRL_CLASS_CAMERA | 0x1001)
  408. #define V4L2_CID_GAIN_GREEN_RED (V4L2_CTRL_CLASS_CAMERA | 0x1002)
  409. #define V4L2_CID_GAIN_GREEN_BLUE (V4L2_CTRL_CLASS_CAMERA | 0x1003)
  410. #define V4L2_CID_GAIN_BLUE (V4L2_CTRL_CLASS_CAMERA | 0x1004)
  411. static u16 mt9t001_gain_value(s32 *gain)
  412. {
  413. /* Gain is controlled by 2 analog stages and a digital stage. Valid
  414. * values for the 3 stages are
  415. *
  416. * Stage Min Max Step
  417. * ------------------------------------------
  418. * First analog stage x1 x2 1
  419. * Second analog stage x1 x4 0.125
  420. * Digital stage x1 x16 0.125
  421. *
  422. * To minimize noise, the gain stages should be used in the second
  423. * analog stage, first analog stage, digital stage order. Gain from a
  424. * previous stage should be pushed to its maximum value before the next
  425. * stage is used.
  426. */
  427. if (*gain <= 32)
  428. return *gain;
  429. if (*gain <= 64) {
  430. *gain &= ~1;
  431. return (1 << 6) | (*gain >> 1);
  432. }
  433. *gain &= ~7;
  434. return ((*gain - 64) << 5) | (1 << 6) | 32;
  435. }
  436. static int mt9t001_ctrl_freeze(struct mt9t001 *mt9t001, bool freeze)
  437. {
  438. return mt9t001_set_output_control(mt9t001,
  439. freeze ? 0 : MT9T001_OUTPUT_CONTROL_SYNC,
  440. freeze ? MT9T001_OUTPUT_CONTROL_SYNC : 0);
  441. }
  442. static int mt9t001_s_ctrl(struct v4l2_ctrl *ctrl)
  443. {
  444. static const u8 gains[4] = {
  445. MT9T001_RED_GAIN, MT9T001_GREEN1_GAIN,
  446. MT9T001_GREEN2_GAIN, MT9T001_BLUE_GAIN
  447. };
  448. struct mt9t001 *mt9t001 =
  449. container_of(ctrl->handler, struct mt9t001, ctrls);
  450. struct i2c_client *client = v4l2_get_subdevdata(&mt9t001->subdev);
  451. unsigned int count;
  452. unsigned int i;
  453. u16 value;
  454. int ret;
  455. switch (ctrl->id) {
  456. case V4L2_CID_GAIN_RED:
  457. case V4L2_CID_GAIN_GREEN_RED:
  458. case V4L2_CID_GAIN_GREEN_BLUE:
  459. case V4L2_CID_GAIN_BLUE:
  460. /* Disable control updates if more than one control has changed
  461. * in the cluster.
  462. */
  463. for (i = 0, count = 0; i < 4; ++i) {
  464. struct v4l2_ctrl *gain = mt9t001->gains[i];
  465. if (gain->val != gain->cur.val)
  466. count++;
  467. }
  468. if (count > 1) {
  469. ret = mt9t001_ctrl_freeze(mt9t001, true);
  470. if (ret < 0)
  471. return ret;
  472. }
  473. /* Update the gain controls. */
  474. for (i = 0; i < 4; ++i) {
  475. struct v4l2_ctrl *gain = mt9t001->gains[i];
  476. if (gain->val == gain->cur.val)
  477. continue;
  478. value = mt9t001_gain_value(&gain->val);
  479. ret = mt9t001_write(client, gains[i], value);
  480. if (ret < 0) {
  481. mt9t001_ctrl_freeze(mt9t001, false);
  482. return ret;
  483. }
  484. }
  485. /* Enable control updates. */
  486. if (count > 1) {
  487. ret = mt9t001_ctrl_freeze(mt9t001, false);
  488. if (ret < 0)
  489. return ret;
  490. }
  491. break;
  492. case V4L2_CID_EXPOSURE:
  493. ret = mt9t001_write(client, MT9T001_SHUTTER_WIDTH_LOW,
  494. ctrl->val & 0xffff);
  495. if (ret < 0)
  496. return ret;
  497. return mt9t001_write(client, MT9T001_SHUTTER_WIDTH_HIGH,
  498. ctrl->val >> 16);
  499. case V4L2_CID_TEST_PATTERN:
  500. return mt9t001_set_output_control(mt9t001,
  501. ctrl->val ? 0 : MT9T001_OUTPUT_CONTROL_TEST_DATA,
  502. ctrl->val ? MT9T001_OUTPUT_CONTROL_TEST_DATA : 0);
  503. case V4L2_CID_TEST_PATTERN_COLOR:
  504. return mt9t001_write(client, MT9T001_TEST_DATA, ctrl->val << 2);
  505. case V4L2_CID_BLACK_LEVEL_AUTO:
  506. value = ctrl->val ? 0 : MT9T001_BLACK_LEVEL_OVERRIDE;
  507. ret = mt9t001_write(client, MT9T001_BLACK_LEVEL_CALIBRATION,
  508. value);
  509. if (ret < 0)
  510. return ret;
  511. mt9t001->black_level = value;
  512. break;
  513. case V4L2_CID_BLACK_LEVEL_OFFSET:
  514. ret = mt9t001_write(client, MT9T001_GREEN1_OFFSET, ctrl->val);
  515. if (ret < 0)
  516. return ret;
  517. ret = mt9t001_write(client, MT9T001_GREEN2_OFFSET, ctrl->val);
  518. if (ret < 0)
  519. return ret;
  520. ret = mt9t001_write(client, MT9T001_RED_OFFSET, ctrl->val);
  521. if (ret < 0)
  522. return ret;
  523. return mt9t001_write(client, MT9T001_BLUE_OFFSET, ctrl->val);
  524. case V4L2_CID_BLACK_LEVEL_CALIBRATE:
  525. return mt9t001_write(client, MT9T001_BLACK_LEVEL_CALIBRATION,
  526. MT9T001_BLACK_LEVEL_RECALCULATE |
  527. mt9t001->black_level);
  528. }
  529. return 0;
  530. }
  531. static const struct v4l2_ctrl_ops mt9t001_ctrl_ops = {
  532. .s_ctrl = mt9t001_s_ctrl,
  533. };
  534. static const char * const mt9t001_test_pattern_menu[] = {
  535. "Disabled",
  536. "Enabled",
  537. };
  538. static const struct v4l2_ctrl_config mt9t001_ctrls[] = {
  539. {
  540. .ops = &mt9t001_ctrl_ops,
  541. .id = V4L2_CID_TEST_PATTERN_COLOR,
  542. .type = V4L2_CTRL_TYPE_INTEGER,
  543. .name = "Test Pattern Color",
  544. .min = 0,
  545. .max = 1023,
  546. .step = 1,
  547. .def = 0,
  548. .flags = 0,
  549. }, {
  550. .ops = &mt9t001_ctrl_ops,
  551. .id = V4L2_CID_BLACK_LEVEL_AUTO,
  552. .type = V4L2_CTRL_TYPE_BOOLEAN,
  553. .name = "Black Level, Auto",
  554. .min = 0,
  555. .max = 1,
  556. .step = 1,
  557. .def = 1,
  558. .flags = 0,
  559. }, {
  560. .ops = &mt9t001_ctrl_ops,
  561. .id = V4L2_CID_BLACK_LEVEL_OFFSET,
  562. .type = V4L2_CTRL_TYPE_INTEGER,
  563. .name = "Black Level, Offset",
  564. .min = -256,
  565. .max = 255,
  566. .step = 1,
  567. .def = 32,
  568. .flags = 0,
  569. }, {
  570. .ops = &mt9t001_ctrl_ops,
  571. .id = V4L2_CID_BLACK_LEVEL_CALIBRATE,
  572. .type = V4L2_CTRL_TYPE_BUTTON,
  573. .name = "Black Level, Calibrate",
  574. .min = 0,
  575. .max = 0,
  576. .step = 0,
  577. .def = 0,
  578. .flags = V4L2_CTRL_FLAG_WRITE_ONLY,
  579. },
  580. };
  581. static const struct v4l2_ctrl_config mt9t001_gains[] = {
  582. {
  583. .ops = &mt9t001_ctrl_ops,
  584. .id = V4L2_CID_GAIN_RED,
  585. .type = V4L2_CTRL_TYPE_INTEGER,
  586. .name = "Gain, Red",
  587. .min = MT9T001_GLOBAL_GAIN_MIN,
  588. .max = MT9T001_GLOBAL_GAIN_MAX,
  589. .step = 1,
  590. .def = MT9T001_GLOBAL_GAIN_MIN,
  591. .flags = 0,
  592. }, {
  593. .ops = &mt9t001_ctrl_ops,
  594. .id = V4L2_CID_GAIN_GREEN_RED,
  595. .type = V4L2_CTRL_TYPE_INTEGER,
  596. .name = "Gain, Green (R)",
  597. .min = MT9T001_GLOBAL_GAIN_MIN,
  598. .max = MT9T001_GLOBAL_GAIN_MAX,
  599. .step = 1,
  600. .def = MT9T001_GLOBAL_GAIN_MIN,
  601. .flags = 0,
  602. }, {
  603. .ops = &mt9t001_ctrl_ops,
  604. .id = V4L2_CID_GAIN_GREEN_BLUE,
  605. .type = V4L2_CTRL_TYPE_INTEGER,
  606. .name = "Gain, Green (B)",
  607. .min = MT9T001_GLOBAL_GAIN_MIN,
  608. .max = MT9T001_GLOBAL_GAIN_MAX,
  609. .step = 1,
  610. .def = MT9T001_GLOBAL_GAIN_MIN,
  611. .flags = 0,
  612. }, {
  613. .ops = &mt9t001_ctrl_ops,
  614. .id = V4L2_CID_GAIN_BLUE,
  615. .type = V4L2_CTRL_TYPE_INTEGER,
  616. .name = "Gain, Blue",
  617. .min = MT9T001_GLOBAL_GAIN_MIN,
  618. .max = MT9T001_GLOBAL_GAIN_MAX,
  619. .step = 1,
  620. .def = MT9T001_GLOBAL_GAIN_MIN,
  621. .flags = 0,
  622. },
  623. };
  624. /* -----------------------------------------------------------------------------
  625. * V4L2 subdev core operations
  626. */
  627. static int mt9t001_set_power(struct v4l2_subdev *subdev, int on)
  628. {
  629. struct mt9t001 *mt9t001 = to_mt9t001(subdev);
  630. int ret = 0;
  631. mutex_lock(&mt9t001->power_lock);
  632. /* If the power count is modified from 0 to != 0 or from != 0 to 0,
  633. * update the power state.
  634. */
  635. if (mt9t001->power_count == !on) {
  636. ret = __mt9t001_set_power(mt9t001, !!on);
  637. if (ret < 0)
  638. goto out;
  639. }
  640. /* Update the power count. */
  641. mt9t001->power_count += on ? 1 : -1;
  642. WARN_ON(mt9t001->power_count < 0);
  643. out:
  644. mutex_unlock(&mt9t001->power_lock);
  645. return ret;
  646. }
  647. /* -----------------------------------------------------------------------------
  648. * V4L2 subdev internal operations
  649. */
  650. static int mt9t001_registered(struct v4l2_subdev *subdev)
  651. {
  652. struct i2c_client *client = v4l2_get_subdevdata(subdev);
  653. struct mt9t001 *mt9t001 = to_mt9t001(subdev);
  654. s32 data;
  655. int ret;
  656. ret = mt9t001_power_on(mt9t001);
  657. if (ret < 0) {
  658. dev_err(&client->dev, "MT9T001 power up failed\n");
  659. return ret;
  660. }
  661. /* Read out the chip version register */
  662. data = mt9t001_read(client, MT9T001_CHIP_VERSION);
  663. mt9t001_power_off(mt9t001);
  664. if (data != MT9T001_CHIP_ID) {
  665. dev_err(&client->dev,
  666. "MT9T001 not detected, wrong version 0x%04x\n", data);
  667. return -ENODEV;
  668. }
  669. dev_info(&client->dev, "MT9T001 detected at address 0x%02x\n",
  670. client->addr);
  671. return 0;
  672. }
  673. static int mt9t001_open(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh)
  674. {
  675. struct v4l2_mbus_framefmt *format;
  676. struct v4l2_rect *crop;
  677. crop = v4l2_subdev_get_try_crop(subdev, fh->pad, 0);
  678. crop->left = MT9T001_COLUMN_START_DEF;
  679. crop->top = MT9T001_ROW_START_DEF;
  680. crop->width = MT9T001_WINDOW_WIDTH_DEF + 1;
  681. crop->height = MT9T001_WINDOW_HEIGHT_DEF + 1;
  682. format = v4l2_subdev_get_try_format(subdev, fh->pad, 0);
  683. format->code = MEDIA_BUS_FMT_SGRBG10_1X10;
  684. format->width = MT9T001_WINDOW_WIDTH_DEF + 1;
  685. format->height = MT9T001_WINDOW_HEIGHT_DEF + 1;
  686. format->field = V4L2_FIELD_NONE;
  687. format->colorspace = V4L2_COLORSPACE_SRGB;
  688. return mt9t001_set_power(subdev, 1);
  689. }
  690. static int mt9t001_close(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh)
  691. {
  692. return mt9t001_set_power(subdev, 0);
  693. }
  694. static const struct v4l2_subdev_core_ops mt9t001_subdev_core_ops = {
  695. .s_power = mt9t001_set_power,
  696. };
  697. static const struct v4l2_subdev_video_ops mt9t001_subdev_video_ops = {
  698. .s_stream = mt9t001_s_stream,
  699. };
  700. static const struct v4l2_subdev_pad_ops mt9t001_subdev_pad_ops = {
  701. .enum_mbus_code = mt9t001_enum_mbus_code,
  702. .enum_frame_size = mt9t001_enum_frame_size,
  703. .get_fmt = mt9t001_get_format,
  704. .set_fmt = mt9t001_set_format,
  705. .get_selection = mt9t001_get_selection,
  706. .set_selection = mt9t001_set_selection,
  707. };
  708. static const struct v4l2_subdev_ops mt9t001_subdev_ops = {
  709. .core = &mt9t001_subdev_core_ops,
  710. .video = &mt9t001_subdev_video_ops,
  711. .pad = &mt9t001_subdev_pad_ops,
  712. };
  713. static const struct v4l2_subdev_internal_ops mt9t001_subdev_internal_ops = {
  714. .registered = mt9t001_registered,
  715. .open = mt9t001_open,
  716. .close = mt9t001_close,
  717. };
  718. static int mt9t001_probe(struct i2c_client *client,
  719. const struct i2c_device_id *did)
  720. {
  721. struct mt9t001_platform_data *pdata = client->dev.platform_data;
  722. struct mt9t001 *mt9t001;
  723. unsigned int i;
  724. int ret;
  725. if (pdata == NULL) {
  726. dev_err(&client->dev, "No platform data\n");
  727. return -EINVAL;
  728. }
  729. if (!i2c_check_functionality(client->adapter,
  730. I2C_FUNC_SMBUS_WORD_DATA)) {
  731. dev_warn(&client->adapter->dev,
  732. "I2C-Adapter doesn't support I2C_FUNC_SMBUS_WORD\n");
  733. return -EIO;
  734. }
  735. mt9t001 = devm_kzalloc(&client->dev, sizeof(*mt9t001), GFP_KERNEL);
  736. if (!mt9t001)
  737. return -ENOMEM;
  738. mutex_init(&mt9t001->power_lock);
  739. mt9t001->output_control = MT9T001_OUTPUT_CONTROL_DEF;
  740. mt9t001->regulators[0].supply = "vdd";
  741. mt9t001->regulators[1].supply = "vaa";
  742. ret = devm_regulator_bulk_get(&client->dev, 2, mt9t001->regulators);
  743. if (ret < 0) {
  744. dev_err(&client->dev, "Unable to get regulators\n");
  745. return ret;
  746. }
  747. mt9t001->clk = devm_clk_get(&client->dev, NULL);
  748. if (IS_ERR(mt9t001->clk)) {
  749. dev_err(&client->dev, "Unable to get clock\n");
  750. return PTR_ERR(mt9t001->clk);
  751. }
  752. v4l2_ctrl_handler_init(&mt9t001->ctrls, ARRAY_SIZE(mt9t001_ctrls) +
  753. ARRAY_SIZE(mt9t001_gains) + 4);
  754. v4l2_ctrl_new_std(&mt9t001->ctrls, &mt9t001_ctrl_ops,
  755. V4L2_CID_EXPOSURE, MT9T001_SHUTTER_WIDTH_MIN,
  756. MT9T001_SHUTTER_WIDTH_MAX, 1,
  757. MT9T001_SHUTTER_WIDTH_DEF);
  758. v4l2_ctrl_new_std(&mt9t001->ctrls, &mt9t001_ctrl_ops,
  759. V4L2_CID_BLACK_LEVEL, 1, 1, 1, 1);
  760. v4l2_ctrl_new_std(&mt9t001->ctrls, &mt9t001_ctrl_ops,
  761. V4L2_CID_PIXEL_RATE, pdata->ext_clk, pdata->ext_clk,
  762. 1, pdata->ext_clk);
  763. v4l2_ctrl_new_std_menu_items(&mt9t001->ctrls, &mt9t001_ctrl_ops,
  764. V4L2_CID_TEST_PATTERN,
  765. ARRAY_SIZE(mt9t001_test_pattern_menu) - 1, 0,
  766. 0, mt9t001_test_pattern_menu);
  767. for (i = 0; i < ARRAY_SIZE(mt9t001_ctrls); ++i)
  768. v4l2_ctrl_new_custom(&mt9t001->ctrls, &mt9t001_ctrls[i], NULL);
  769. for (i = 0; i < ARRAY_SIZE(mt9t001_gains); ++i)
  770. mt9t001->gains[i] = v4l2_ctrl_new_custom(&mt9t001->ctrls,
  771. &mt9t001_gains[i], NULL);
  772. v4l2_ctrl_cluster(ARRAY_SIZE(mt9t001_gains), mt9t001->gains);
  773. mt9t001->subdev.ctrl_handler = &mt9t001->ctrls;
  774. if (mt9t001->ctrls.error) {
  775. printk(KERN_INFO "%s: control initialization error %d\n",
  776. __func__, mt9t001->ctrls.error);
  777. ret = -EINVAL;
  778. goto done;
  779. }
  780. mt9t001->crop.left = MT9T001_COLUMN_START_DEF;
  781. mt9t001->crop.top = MT9T001_ROW_START_DEF;
  782. mt9t001->crop.width = MT9T001_WINDOW_WIDTH_DEF + 1;
  783. mt9t001->crop.height = MT9T001_WINDOW_HEIGHT_DEF + 1;
  784. mt9t001->format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
  785. mt9t001->format.width = MT9T001_WINDOW_WIDTH_DEF + 1;
  786. mt9t001->format.height = MT9T001_WINDOW_HEIGHT_DEF + 1;
  787. mt9t001->format.field = V4L2_FIELD_NONE;
  788. mt9t001->format.colorspace = V4L2_COLORSPACE_SRGB;
  789. v4l2_i2c_subdev_init(&mt9t001->subdev, client, &mt9t001_subdev_ops);
  790. mt9t001->subdev.internal_ops = &mt9t001_subdev_internal_ops;
  791. mt9t001->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
  792. mt9t001->subdev.entity.function = MEDIA_ENT_F_CAM_SENSOR;
  793. mt9t001->pad.flags = MEDIA_PAD_FL_SOURCE;
  794. ret = media_entity_pads_init(&mt9t001->subdev.entity, 1, &mt9t001->pad);
  795. done:
  796. if (ret < 0) {
  797. v4l2_ctrl_handler_free(&mt9t001->ctrls);
  798. media_entity_cleanup(&mt9t001->subdev.entity);
  799. }
  800. return ret;
  801. }
  802. static int mt9t001_remove(struct i2c_client *client)
  803. {
  804. struct v4l2_subdev *subdev = i2c_get_clientdata(client);
  805. struct mt9t001 *mt9t001 = to_mt9t001(subdev);
  806. v4l2_ctrl_handler_free(&mt9t001->ctrls);
  807. v4l2_device_unregister_subdev(subdev);
  808. media_entity_cleanup(&subdev->entity);
  809. return 0;
  810. }
  811. static const struct i2c_device_id mt9t001_id[] = {
  812. { "mt9t001", 0 },
  813. { }
  814. };
  815. MODULE_DEVICE_TABLE(i2c, mt9t001_id);
  816. static struct i2c_driver mt9t001_driver = {
  817. .driver = {
  818. .name = "mt9t001",
  819. },
  820. .probe = mt9t001_probe,
  821. .remove = mt9t001_remove,
  822. .id_table = mt9t001_id,
  823. };
  824. module_i2c_driver(mt9t001_driver);
  825. MODULE_DESCRIPTION("Aptina (Micron) MT9T001 Camera driver");
  826. MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
  827. MODULE_LICENSE("GPL");