mt9p031.c 33 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Driver for MT9P031 CMOS Image Sensor from Aptina
  4. *
  5. * Copyright (C) 2011, Laurent Pinchart <laurent.pinchart@ideasonboard.com>
  6. * Copyright (C) 2011, Javier Martin <javier.martin@vista-silicon.com>
  7. * Copyright (C) 2011, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
  8. *
  9. * Based on the MT9V032 driver and Bastian Hecht's code.
  10. */
  11. #include <linux/clk.h>
  12. #include <linux/delay.h>
  13. #include <linux/device.h>
  14. #include <linux/gpio/consumer.h>
  15. #include <linux/i2c.h>
  16. #include <linux/log2.h>
  17. #include <linux/module.h>
  18. #include <linux/of.h>
  19. #include <linux/of_graph.h>
  20. #include <linux/pm.h>
  21. #include <linux/regulator/consumer.h>
  22. #include <linux/slab.h>
  23. #include <linux/videodev2.h>
  24. #include <media/i2c/mt9p031.h>
  25. #include <media/v4l2-async.h>
  26. #include <media/v4l2-ctrls.h>
  27. #include <media/v4l2-device.h>
  28. #include <media/v4l2-subdev.h>
  29. #include "aptina-pll.h"
  30. #define MT9P031_PIXEL_ARRAY_WIDTH 2752
  31. #define MT9P031_PIXEL_ARRAY_HEIGHT 2004
  32. #define MT9P031_CHIP_VERSION 0x00
  33. #define MT9P031_CHIP_VERSION_VALUE 0x1801
  34. #define MT9P031_ROW_START 0x01
  35. #define MT9P031_ROW_START_MIN 0
  36. #define MT9P031_ROW_START_MAX 2004
  37. #define MT9P031_ROW_START_DEF 54
  38. #define MT9P031_COLUMN_START 0x02
  39. #define MT9P031_COLUMN_START_MIN 0
  40. #define MT9P031_COLUMN_START_MAX 2750
  41. #define MT9P031_COLUMN_START_DEF 16
  42. #define MT9P031_WINDOW_HEIGHT 0x03
  43. #define MT9P031_WINDOW_HEIGHT_MIN 2
  44. #define MT9P031_WINDOW_HEIGHT_MAX 2006
  45. #define MT9P031_WINDOW_HEIGHT_DEF 1944
  46. #define MT9P031_WINDOW_WIDTH 0x04
  47. #define MT9P031_WINDOW_WIDTH_MIN 2
  48. #define MT9P031_WINDOW_WIDTH_MAX 2752
  49. #define MT9P031_WINDOW_WIDTH_DEF 2592
  50. #define MT9P031_HORIZONTAL_BLANK 0x05
  51. #define MT9P031_HORIZONTAL_BLANK_MIN 0
  52. #define MT9P031_HORIZONTAL_BLANK_MAX 4095
  53. #define MT9P031_VERTICAL_BLANK 0x06
  54. #define MT9P031_VERTICAL_BLANK_MIN 1
  55. #define MT9P031_VERTICAL_BLANK_MAX 4096
  56. #define MT9P031_VERTICAL_BLANK_DEF 26
  57. #define MT9P031_OUTPUT_CONTROL 0x07
  58. #define MT9P031_OUTPUT_CONTROL_CEN 2
  59. #define MT9P031_OUTPUT_CONTROL_SYN 1
  60. #define MT9P031_OUTPUT_CONTROL_DEF 0x1f82
  61. #define MT9P031_SHUTTER_WIDTH_UPPER 0x08
  62. #define MT9P031_SHUTTER_WIDTH_LOWER 0x09
  63. #define MT9P031_SHUTTER_WIDTH_MIN 1
  64. #define MT9P031_SHUTTER_WIDTH_MAX 1048575
  65. #define MT9P031_SHUTTER_WIDTH_DEF 1943
  66. #define MT9P031_PLL_CONTROL 0x10
  67. #define MT9P031_PLL_CONTROL_PWROFF 0x0050
  68. #define MT9P031_PLL_CONTROL_PWRON 0x0051
  69. #define MT9P031_PLL_CONTROL_USEPLL 0x0052
  70. #define MT9P031_PLL_CONFIG_1 0x11
  71. #define MT9P031_PLL_CONFIG_2 0x12
  72. #define MT9P031_PIXEL_CLOCK_CONTROL 0x0a
  73. #define MT9P031_PIXEL_CLOCK_INVERT (1 << 15)
  74. #define MT9P031_PIXEL_CLOCK_SHIFT(n) ((n) << 8)
  75. #define MT9P031_PIXEL_CLOCK_DIVIDE(n) ((n) << 0)
  76. #define MT9P031_RESTART 0x0b
  77. #define MT9P031_FRAME_PAUSE_RESTART (1 << 1)
  78. #define MT9P031_FRAME_RESTART (1 << 0)
  79. #define MT9P031_SHUTTER_DELAY 0x0c
  80. #define MT9P031_RST 0x0d
  81. #define MT9P031_RST_ENABLE 1
  82. #define MT9P031_RST_DISABLE 0
  83. #define MT9P031_READ_MODE_1 0x1e
  84. #define MT9P031_READ_MODE_2 0x20
  85. #define MT9P031_READ_MODE_2_ROW_MIR (1 << 15)
  86. #define MT9P031_READ_MODE_2_COL_MIR (1 << 14)
  87. #define MT9P031_READ_MODE_2_ROW_BLC (1 << 6)
  88. #define MT9P031_ROW_ADDRESS_MODE 0x22
  89. #define MT9P031_COLUMN_ADDRESS_MODE 0x23
  90. #define MT9P031_GLOBAL_GAIN 0x35
  91. #define MT9P031_GLOBAL_GAIN_MIN 8
  92. #define MT9P031_GLOBAL_GAIN_MAX 1024
  93. #define MT9P031_GLOBAL_GAIN_DEF 8
  94. #define MT9P031_GLOBAL_GAIN_MULT (1 << 6)
  95. #define MT9P031_ROW_BLACK_TARGET 0x49
  96. #define MT9P031_ROW_BLACK_DEF_OFFSET 0x4b
  97. #define MT9P031_GREEN1_OFFSET 0x60
  98. #define MT9P031_GREEN2_OFFSET 0x61
  99. #define MT9P031_BLACK_LEVEL_CALIBRATION 0x62
  100. #define MT9P031_BLC_MANUAL_BLC (1 << 0)
  101. #define MT9P031_RED_OFFSET 0x63
  102. #define MT9P031_BLUE_OFFSET 0x64
  103. #define MT9P031_TEST_PATTERN 0xa0
  104. #define MT9P031_TEST_PATTERN_SHIFT 3
  105. #define MT9P031_TEST_PATTERN_ENABLE (1 << 0)
  106. #define MT9P031_TEST_PATTERN_DISABLE (0 << 0)
  107. #define MT9P031_TEST_PATTERN_GREEN 0xa1
  108. #define MT9P031_TEST_PATTERN_RED 0xa2
  109. #define MT9P031_TEST_PATTERN_BLUE 0xa3
  110. enum mt9p031_model {
  111. MT9P031_MODEL_COLOR,
  112. MT9P031_MODEL_MONOCHROME,
  113. };
  114. struct mt9p031 {
  115. struct v4l2_subdev subdev;
  116. struct media_pad pad;
  117. struct v4l2_rect crop; /* Sensor window */
  118. struct v4l2_mbus_framefmt format;
  119. struct mt9p031_platform_data *pdata;
  120. struct mutex power_lock; /* lock to protect power_count */
  121. int power_count;
  122. struct clk *clk;
  123. struct regulator_bulk_data regulators[3];
  124. enum mt9p031_model model;
  125. struct aptina_pll pll;
  126. unsigned int clk_div;
  127. bool use_pll;
  128. struct gpio_desc *reset;
  129. struct v4l2_ctrl_handler ctrls;
  130. struct v4l2_ctrl *blc_auto;
  131. struct v4l2_ctrl *blc_offset;
  132. /* Registers cache */
  133. u16 output_control;
  134. u16 mode2;
  135. };
  136. static struct mt9p031 *to_mt9p031(struct v4l2_subdev *sd)
  137. {
  138. return container_of(sd, struct mt9p031, subdev);
  139. }
  140. static int mt9p031_read(struct i2c_client *client, u8 reg)
  141. {
  142. return i2c_smbus_read_word_swapped(client, reg);
  143. }
  144. static int mt9p031_write(struct i2c_client *client, u8 reg, u16 data)
  145. {
  146. return i2c_smbus_write_word_swapped(client, reg, data);
  147. }
  148. static int mt9p031_set_output_control(struct mt9p031 *mt9p031, u16 clear,
  149. u16 set)
  150. {
  151. struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev);
  152. u16 value = (mt9p031->output_control & ~clear) | set;
  153. int ret;
  154. ret = mt9p031_write(client, MT9P031_OUTPUT_CONTROL, value);
  155. if (ret < 0)
  156. return ret;
  157. mt9p031->output_control = value;
  158. return 0;
  159. }
  160. static int mt9p031_set_mode2(struct mt9p031 *mt9p031, u16 clear, u16 set)
  161. {
  162. struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev);
  163. u16 value = (mt9p031->mode2 & ~clear) | set;
  164. int ret;
  165. ret = mt9p031_write(client, MT9P031_READ_MODE_2, value);
  166. if (ret < 0)
  167. return ret;
  168. mt9p031->mode2 = value;
  169. return 0;
  170. }
  171. static int mt9p031_reset(struct mt9p031 *mt9p031)
  172. {
  173. struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev);
  174. int ret;
  175. /* Disable chip output, synchronous option update */
  176. ret = mt9p031_write(client, MT9P031_RST, MT9P031_RST_ENABLE);
  177. if (ret < 0)
  178. return ret;
  179. ret = mt9p031_write(client, MT9P031_RST, MT9P031_RST_DISABLE);
  180. if (ret < 0)
  181. return ret;
  182. ret = mt9p031_write(client, MT9P031_PIXEL_CLOCK_CONTROL,
  183. MT9P031_PIXEL_CLOCK_DIVIDE(mt9p031->clk_div));
  184. if (ret < 0)
  185. return ret;
  186. return mt9p031_set_output_control(mt9p031, MT9P031_OUTPUT_CONTROL_CEN,
  187. 0);
  188. }
  189. static int mt9p031_clk_setup(struct mt9p031 *mt9p031)
  190. {
  191. static const struct aptina_pll_limits limits = {
  192. .ext_clock_min = 6000000,
  193. .ext_clock_max = 27000000,
  194. .int_clock_min = 2000000,
  195. .int_clock_max = 13500000,
  196. .out_clock_min = 180000000,
  197. .out_clock_max = 360000000,
  198. .pix_clock_max = 96000000,
  199. .n_min = 1,
  200. .n_max = 64,
  201. .m_min = 16,
  202. .m_max = 255,
  203. .p1_min = 1,
  204. .p1_max = 128,
  205. };
  206. struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev);
  207. struct mt9p031_platform_data *pdata = mt9p031->pdata;
  208. int ret;
  209. mt9p031->clk = devm_clk_get(&client->dev, NULL);
  210. if (IS_ERR(mt9p031->clk))
  211. return PTR_ERR(mt9p031->clk);
  212. ret = clk_set_rate(mt9p031->clk, pdata->ext_freq);
  213. if (ret < 0)
  214. return ret;
  215. /* If the external clock frequency is out of bounds for the PLL use the
  216. * pixel clock divider only and disable the PLL.
  217. */
  218. if (pdata->ext_freq > limits.ext_clock_max) {
  219. unsigned int div;
  220. div = DIV_ROUND_UP(pdata->ext_freq, pdata->target_freq);
  221. div = roundup_pow_of_two(div) / 2;
  222. mt9p031->clk_div = min_t(unsigned int, div, 64);
  223. mt9p031->use_pll = false;
  224. return 0;
  225. }
  226. mt9p031->pll.ext_clock = pdata->ext_freq;
  227. mt9p031->pll.pix_clock = pdata->target_freq;
  228. mt9p031->use_pll = true;
  229. return aptina_pll_calculate(&client->dev, &limits, &mt9p031->pll);
  230. }
  231. static int mt9p031_pll_enable(struct mt9p031 *mt9p031)
  232. {
  233. struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev);
  234. int ret;
  235. if (!mt9p031->use_pll)
  236. return 0;
  237. ret = mt9p031_write(client, MT9P031_PLL_CONTROL,
  238. MT9P031_PLL_CONTROL_PWRON);
  239. if (ret < 0)
  240. return ret;
  241. ret = mt9p031_write(client, MT9P031_PLL_CONFIG_1,
  242. (mt9p031->pll.m << 8) | (mt9p031->pll.n - 1));
  243. if (ret < 0)
  244. return ret;
  245. ret = mt9p031_write(client, MT9P031_PLL_CONFIG_2, mt9p031->pll.p1 - 1);
  246. if (ret < 0)
  247. return ret;
  248. usleep_range(1000, 2000);
  249. ret = mt9p031_write(client, MT9P031_PLL_CONTROL,
  250. MT9P031_PLL_CONTROL_PWRON |
  251. MT9P031_PLL_CONTROL_USEPLL);
  252. return ret;
  253. }
  254. static inline int mt9p031_pll_disable(struct mt9p031 *mt9p031)
  255. {
  256. struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev);
  257. if (!mt9p031->use_pll)
  258. return 0;
  259. return mt9p031_write(client, MT9P031_PLL_CONTROL,
  260. MT9P031_PLL_CONTROL_PWROFF);
  261. }
  262. static int mt9p031_power_on(struct mt9p031 *mt9p031)
  263. {
  264. int ret;
  265. /* Ensure RESET_BAR is active */
  266. if (mt9p031->reset) {
  267. gpiod_set_value(mt9p031->reset, 1);
  268. usleep_range(1000, 2000);
  269. }
  270. /* Bring up the supplies */
  271. ret = regulator_bulk_enable(ARRAY_SIZE(mt9p031->regulators),
  272. mt9p031->regulators);
  273. if (ret < 0)
  274. return ret;
  275. /* Enable clock */
  276. if (mt9p031->clk) {
  277. ret = clk_prepare_enable(mt9p031->clk);
  278. if (ret) {
  279. regulator_bulk_disable(ARRAY_SIZE(mt9p031->regulators),
  280. mt9p031->regulators);
  281. return ret;
  282. }
  283. }
  284. /* Now RESET_BAR must be high */
  285. if (mt9p031->reset) {
  286. gpiod_set_value(mt9p031->reset, 0);
  287. usleep_range(1000, 2000);
  288. }
  289. return 0;
  290. }
  291. static void mt9p031_power_off(struct mt9p031 *mt9p031)
  292. {
  293. if (mt9p031->reset) {
  294. gpiod_set_value(mt9p031->reset, 1);
  295. usleep_range(1000, 2000);
  296. }
  297. regulator_bulk_disable(ARRAY_SIZE(mt9p031->regulators),
  298. mt9p031->regulators);
  299. if (mt9p031->clk)
  300. clk_disable_unprepare(mt9p031->clk);
  301. }
  302. static int __mt9p031_set_power(struct mt9p031 *mt9p031, bool on)
  303. {
  304. struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev);
  305. int ret;
  306. if (!on) {
  307. mt9p031_power_off(mt9p031);
  308. return 0;
  309. }
  310. ret = mt9p031_power_on(mt9p031);
  311. if (ret < 0)
  312. return ret;
  313. ret = mt9p031_reset(mt9p031);
  314. if (ret < 0) {
  315. dev_err(&client->dev, "Failed to reset the camera\n");
  316. return ret;
  317. }
  318. return v4l2_ctrl_handler_setup(&mt9p031->ctrls);
  319. }
  320. /* -----------------------------------------------------------------------------
  321. * V4L2 subdev video operations
  322. */
  323. static int mt9p031_set_params(struct mt9p031 *mt9p031)
  324. {
  325. struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev);
  326. struct v4l2_mbus_framefmt *format = &mt9p031->format;
  327. const struct v4l2_rect *crop = &mt9p031->crop;
  328. unsigned int hblank;
  329. unsigned int vblank;
  330. unsigned int xskip;
  331. unsigned int yskip;
  332. unsigned int xbin;
  333. unsigned int ybin;
  334. int ret;
  335. /* Windows position and size.
  336. *
  337. * TODO: Make sure the start coordinates and window size match the
  338. * skipping, binning and mirroring (see description of registers 2 and 4
  339. * in table 13, and Binning section on page 41).
  340. */
  341. ret = mt9p031_write(client, MT9P031_COLUMN_START, crop->left);
  342. if (ret < 0)
  343. return ret;
  344. ret = mt9p031_write(client, MT9P031_ROW_START, crop->top);
  345. if (ret < 0)
  346. return ret;
  347. ret = mt9p031_write(client, MT9P031_WINDOW_WIDTH, crop->width - 1);
  348. if (ret < 0)
  349. return ret;
  350. ret = mt9p031_write(client, MT9P031_WINDOW_HEIGHT, crop->height - 1);
  351. if (ret < 0)
  352. return ret;
  353. /* Row and column binning and skipping. Use the maximum binning value
  354. * compatible with the skipping settings.
  355. */
  356. xskip = DIV_ROUND_CLOSEST(crop->width, format->width);
  357. yskip = DIV_ROUND_CLOSEST(crop->height, format->height);
  358. xbin = 1 << (ffs(xskip) - 1);
  359. ybin = 1 << (ffs(yskip) - 1);
  360. ret = mt9p031_write(client, MT9P031_COLUMN_ADDRESS_MODE,
  361. ((xbin - 1) << 4) | (xskip - 1));
  362. if (ret < 0)
  363. return ret;
  364. ret = mt9p031_write(client, MT9P031_ROW_ADDRESS_MODE,
  365. ((ybin - 1) << 4) | (yskip - 1));
  366. if (ret < 0)
  367. return ret;
  368. /* Blanking - use minimum value for horizontal blanking and default
  369. * value for vertical blanking.
  370. */
  371. hblank = 346 * ybin + 64 + (80 >> min_t(unsigned int, xbin, 3));
  372. vblank = MT9P031_VERTICAL_BLANK_DEF;
  373. ret = mt9p031_write(client, MT9P031_HORIZONTAL_BLANK, hblank - 1);
  374. if (ret < 0)
  375. return ret;
  376. ret = mt9p031_write(client, MT9P031_VERTICAL_BLANK, vblank - 1);
  377. if (ret < 0)
  378. return ret;
  379. return ret;
  380. }
  381. static int mt9p031_s_stream(struct v4l2_subdev *subdev, int enable)
  382. {
  383. struct mt9p031 *mt9p031 = to_mt9p031(subdev);
  384. struct i2c_client *client = v4l2_get_subdevdata(subdev);
  385. int val;
  386. int ret;
  387. if (!enable) {
  388. /* enable pause restart */
  389. val = MT9P031_FRAME_PAUSE_RESTART;
  390. ret = mt9p031_write(client, MT9P031_RESTART, val);
  391. if (ret < 0)
  392. return ret;
  393. /* enable restart + keep pause restart set */
  394. val |= MT9P031_FRAME_RESTART;
  395. ret = mt9p031_write(client, MT9P031_RESTART, val);
  396. if (ret < 0)
  397. return ret;
  398. /* Stop sensor readout */
  399. ret = mt9p031_set_output_control(mt9p031,
  400. MT9P031_OUTPUT_CONTROL_CEN, 0);
  401. if (ret < 0)
  402. return ret;
  403. return mt9p031_pll_disable(mt9p031);
  404. }
  405. ret = mt9p031_set_params(mt9p031);
  406. if (ret < 0)
  407. return ret;
  408. /* Switch to master "normal" mode */
  409. ret = mt9p031_set_output_control(mt9p031, 0,
  410. MT9P031_OUTPUT_CONTROL_CEN);
  411. if (ret < 0)
  412. return ret;
  413. /*
  414. * - clear pause restart
  415. * - don't clear restart as clearing restart manually can cause
  416. * undefined behavior
  417. */
  418. val = MT9P031_FRAME_RESTART;
  419. ret = mt9p031_write(client, MT9P031_RESTART, val);
  420. if (ret < 0)
  421. return ret;
  422. return mt9p031_pll_enable(mt9p031);
  423. }
  424. static int mt9p031_enum_mbus_code(struct v4l2_subdev *subdev,
  425. struct v4l2_subdev_pad_config *cfg,
  426. struct v4l2_subdev_mbus_code_enum *code)
  427. {
  428. struct mt9p031 *mt9p031 = to_mt9p031(subdev);
  429. if (code->pad || code->index)
  430. return -EINVAL;
  431. code->code = mt9p031->format.code;
  432. return 0;
  433. }
  434. static int mt9p031_enum_frame_size(struct v4l2_subdev *subdev,
  435. struct v4l2_subdev_pad_config *cfg,
  436. struct v4l2_subdev_frame_size_enum *fse)
  437. {
  438. struct mt9p031 *mt9p031 = to_mt9p031(subdev);
  439. if (fse->index >= 8 || fse->code != mt9p031->format.code)
  440. return -EINVAL;
  441. fse->min_width = MT9P031_WINDOW_WIDTH_DEF
  442. / min_t(unsigned int, 7, fse->index + 1);
  443. fse->max_width = fse->min_width;
  444. fse->min_height = MT9P031_WINDOW_HEIGHT_DEF / (fse->index + 1);
  445. fse->max_height = fse->min_height;
  446. return 0;
  447. }
  448. static struct v4l2_mbus_framefmt *
  449. __mt9p031_get_pad_format(struct mt9p031 *mt9p031, struct v4l2_subdev_pad_config *cfg,
  450. unsigned int pad, u32 which)
  451. {
  452. switch (which) {
  453. case V4L2_SUBDEV_FORMAT_TRY:
  454. return v4l2_subdev_get_try_format(&mt9p031->subdev, cfg, pad);
  455. case V4L2_SUBDEV_FORMAT_ACTIVE:
  456. return &mt9p031->format;
  457. default:
  458. return NULL;
  459. }
  460. }
  461. static struct v4l2_rect *
  462. __mt9p031_get_pad_crop(struct mt9p031 *mt9p031, struct v4l2_subdev_pad_config *cfg,
  463. unsigned int pad, u32 which)
  464. {
  465. switch (which) {
  466. case V4L2_SUBDEV_FORMAT_TRY:
  467. return v4l2_subdev_get_try_crop(&mt9p031->subdev, cfg, pad);
  468. case V4L2_SUBDEV_FORMAT_ACTIVE:
  469. return &mt9p031->crop;
  470. default:
  471. return NULL;
  472. }
  473. }
  474. static int mt9p031_get_format(struct v4l2_subdev *subdev,
  475. struct v4l2_subdev_pad_config *cfg,
  476. struct v4l2_subdev_format *fmt)
  477. {
  478. struct mt9p031 *mt9p031 = to_mt9p031(subdev);
  479. fmt->format = *__mt9p031_get_pad_format(mt9p031, cfg, fmt->pad,
  480. fmt->which);
  481. return 0;
  482. }
  483. static int mt9p031_set_format(struct v4l2_subdev *subdev,
  484. struct v4l2_subdev_pad_config *cfg,
  485. struct v4l2_subdev_format *format)
  486. {
  487. struct mt9p031 *mt9p031 = to_mt9p031(subdev);
  488. struct v4l2_mbus_framefmt *__format;
  489. struct v4l2_rect *__crop;
  490. unsigned int width;
  491. unsigned int height;
  492. unsigned int hratio;
  493. unsigned int vratio;
  494. __crop = __mt9p031_get_pad_crop(mt9p031, cfg, format->pad,
  495. format->which);
  496. /* Clamp the width and height to avoid dividing by zero. */
  497. width = clamp_t(unsigned int, ALIGN(format->format.width, 2),
  498. max_t(unsigned int, __crop->width / 7,
  499. MT9P031_WINDOW_WIDTH_MIN),
  500. __crop->width);
  501. height = clamp_t(unsigned int, ALIGN(format->format.height, 2),
  502. max_t(unsigned int, __crop->height / 8,
  503. MT9P031_WINDOW_HEIGHT_MIN),
  504. __crop->height);
  505. hratio = DIV_ROUND_CLOSEST(__crop->width, width);
  506. vratio = DIV_ROUND_CLOSEST(__crop->height, height);
  507. __format = __mt9p031_get_pad_format(mt9p031, cfg, format->pad,
  508. format->which);
  509. __format->width = __crop->width / hratio;
  510. __format->height = __crop->height / vratio;
  511. format->format = *__format;
  512. return 0;
  513. }
  514. static int mt9p031_get_selection(struct v4l2_subdev *subdev,
  515. struct v4l2_subdev_pad_config *cfg,
  516. struct v4l2_subdev_selection *sel)
  517. {
  518. struct mt9p031 *mt9p031 = to_mt9p031(subdev);
  519. if (sel->target != V4L2_SEL_TGT_CROP)
  520. return -EINVAL;
  521. sel->r = *__mt9p031_get_pad_crop(mt9p031, cfg, sel->pad, sel->which);
  522. return 0;
  523. }
  524. static int mt9p031_set_selection(struct v4l2_subdev *subdev,
  525. struct v4l2_subdev_pad_config *cfg,
  526. struct v4l2_subdev_selection *sel)
  527. {
  528. struct mt9p031 *mt9p031 = to_mt9p031(subdev);
  529. struct v4l2_mbus_framefmt *__format;
  530. struct v4l2_rect *__crop;
  531. struct v4l2_rect rect;
  532. if (sel->target != V4L2_SEL_TGT_CROP)
  533. return -EINVAL;
  534. /* Clamp the crop rectangle boundaries and align them to a multiple of 2
  535. * pixels to ensure a GRBG Bayer pattern.
  536. */
  537. rect.left = clamp(ALIGN(sel->r.left, 2), MT9P031_COLUMN_START_MIN,
  538. MT9P031_COLUMN_START_MAX);
  539. rect.top = clamp(ALIGN(sel->r.top, 2), MT9P031_ROW_START_MIN,
  540. MT9P031_ROW_START_MAX);
  541. rect.width = clamp_t(unsigned int, ALIGN(sel->r.width, 2),
  542. MT9P031_WINDOW_WIDTH_MIN,
  543. MT9P031_WINDOW_WIDTH_MAX);
  544. rect.height = clamp_t(unsigned int, ALIGN(sel->r.height, 2),
  545. MT9P031_WINDOW_HEIGHT_MIN,
  546. MT9P031_WINDOW_HEIGHT_MAX);
  547. rect.width = min_t(unsigned int, rect.width,
  548. MT9P031_PIXEL_ARRAY_WIDTH - rect.left);
  549. rect.height = min_t(unsigned int, rect.height,
  550. MT9P031_PIXEL_ARRAY_HEIGHT - rect.top);
  551. __crop = __mt9p031_get_pad_crop(mt9p031, cfg, sel->pad, sel->which);
  552. if (rect.width != __crop->width || rect.height != __crop->height) {
  553. /* Reset the output image size if the crop rectangle size has
  554. * been modified.
  555. */
  556. __format = __mt9p031_get_pad_format(mt9p031, cfg, sel->pad,
  557. sel->which);
  558. __format->width = rect.width;
  559. __format->height = rect.height;
  560. }
  561. *__crop = rect;
  562. sel->r = rect;
  563. return 0;
  564. }
  565. /* -----------------------------------------------------------------------------
  566. * V4L2 subdev control operations
  567. */
  568. #define V4L2_CID_BLC_AUTO (V4L2_CID_USER_BASE | 0x1002)
  569. #define V4L2_CID_BLC_TARGET_LEVEL (V4L2_CID_USER_BASE | 0x1003)
  570. #define V4L2_CID_BLC_ANALOG_OFFSET (V4L2_CID_USER_BASE | 0x1004)
  571. #define V4L2_CID_BLC_DIGITAL_OFFSET (V4L2_CID_USER_BASE | 0x1005)
  572. static int mt9p031_restore_blc(struct mt9p031 *mt9p031)
  573. {
  574. struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev);
  575. int ret;
  576. if (mt9p031->blc_auto->cur.val != 0) {
  577. ret = mt9p031_set_mode2(mt9p031, 0,
  578. MT9P031_READ_MODE_2_ROW_BLC);
  579. if (ret < 0)
  580. return ret;
  581. }
  582. if (mt9p031->blc_offset->cur.val != 0) {
  583. ret = mt9p031_write(client, MT9P031_ROW_BLACK_TARGET,
  584. mt9p031->blc_offset->cur.val);
  585. if (ret < 0)
  586. return ret;
  587. }
  588. return 0;
  589. }
  590. static int mt9p031_s_ctrl(struct v4l2_ctrl *ctrl)
  591. {
  592. struct mt9p031 *mt9p031 =
  593. container_of(ctrl->handler, struct mt9p031, ctrls);
  594. struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev);
  595. u16 data;
  596. int ret;
  597. if (ctrl->flags & V4L2_CTRL_FLAG_INACTIVE)
  598. return 0;
  599. switch (ctrl->id) {
  600. case V4L2_CID_EXPOSURE:
  601. ret = mt9p031_write(client, MT9P031_SHUTTER_WIDTH_UPPER,
  602. (ctrl->val >> 16) & 0xffff);
  603. if (ret < 0)
  604. return ret;
  605. return mt9p031_write(client, MT9P031_SHUTTER_WIDTH_LOWER,
  606. ctrl->val & 0xffff);
  607. case V4L2_CID_GAIN:
  608. /* Gain is controlled by 2 analog stages and a digital stage.
  609. * Valid values for the 3 stages are
  610. *
  611. * Stage Min Max Step
  612. * ------------------------------------------
  613. * First analog stage x1 x2 1
  614. * Second analog stage x1 x4 0.125
  615. * Digital stage x1 x16 0.125
  616. *
  617. * To minimize noise, the gain stages should be used in the
  618. * second analog stage, first analog stage, digital stage order.
  619. * Gain from a previous stage should be pushed to its maximum
  620. * value before the next stage is used.
  621. */
  622. if (ctrl->val <= 32) {
  623. data = ctrl->val;
  624. } else if (ctrl->val <= 64) {
  625. ctrl->val &= ~1;
  626. data = (1 << 6) | (ctrl->val >> 1);
  627. } else {
  628. ctrl->val &= ~7;
  629. data = ((ctrl->val - 64) << 5) | (1 << 6) | 32;
  630. }
  631. return mt9p031_write(client, MT9P031_GLOBAL_GAIN, data);
  632. case V4L2_CID_HFLIP:
  633. if (ctrl->val)
  634. return mt9p031_set_mode2(mt9p031,
  635. 0, MT9P031_READ_MODE_2_COL_MIR);
  636. else
  637. return mt9p031_set_mode2(mt9p031,
  638. MT9P031_READ_MODE_2_COL_MIR, 0);
  639. case V4L2_CID_VFLIP:
  640. if (ctrl->val)
  641. return mt9p031_set_mode2(mt9p031,
  642. 0, MT9P031_READ_MODE_2_ROW_MIR);
  643. else
  644. return mt9p031_set_mode2(mt9p031,
  645. MT9P031_READ_MODE_2_ROW_MIR, 0);
  646. case V4L2_CID_TEST_PATTERN:
  647. /* The digital side of the Black Level Calibration function must
  648. * be disabled when generating a test pattern to avoid artifacts
  649. * in the image. Activate (deactivate) the BLC-related controls
  650. * when the test pattern is enabled (disabled).
  651. */
  652. v4l2_ctrl_activate(mt9p031->blc_auto, ctrl->val == 0);
  653. v4l2_ctrl_activate(mt9p031->blc_offset, ctrl->val == 0);
  654. if (!ctrl->val) {
  655. /* Restore the BLC settings. */
  656. ret = mt9p031_restore_blc(mt9p031);
  657. if (ret < 0)
  658. return ret;
  659. return mt9p031_write(client, MT9P031_TEST_PATTERN,
  660. MT9P031_TEST_PATTERN_DISABLE);
  661. }
  662. ret = mt9p031_write(client, MT9P031_TEST_PATTERN_GREEN, 0x05a0);
  663. if (ret < 0)
  664. return ret;
  665. ret = mt9p031_write(client, MT9P031_TEST_PATTERN_RED, 0x0a50);
  666. if (ret < 0)
  667. return ret;
  668. ret = mt9p031_write(client, MT9P031_TEST_PATTERN_BLUE, 0x0aa0);
  669. if (ret < 0)
  670. return ret;
  671. /* Disable digital BLC when generating a test pattern. */
  672. ret = mt9p031_set_mode2(mt9p031, MT9P031_READ_MODE_2_ROW_BLC,
  673. 0);
  674. if (ret < 0)
  675. return ret;
  676. ret = mt9p031_write(client, MT9P031_ROW_BLACK_DEF_OFFSET, 0);
  677. if (ret < 0)
  678. return ret;
  679. return mt9p031_write(client, MT9P031_TEST_PATTERN,
  680. ((ctrl->val - 1) << MT9P031_TEST_PATTERN_SHIFT)
  681. | MT9P031_TEST_PATTERN_ENABLE);
  682. case V4L2_CID_BLC_AUTO:
  683. ret = mt9p031_set_mode2(mt9p031,
  684. ctrl->val ? 0 : MT9P031_READ_MODE_2_ROW_BLC,
  685. ctrl->val ? MT9P031_READ_MODE_2_ROW_BLC : 0);
  686. if (ret < 0)
  687. return ret;
  688. return mt9p031_write(client, MT9P031_BLACK_LEVEL_CALIBRATION,
  689. ctrl->val ? 0 : MT9P031_BLC_MANUAL_BLC);
  690. case V4L2_CID_BLC_TARGET_LEVEL:
  691. return mt9p031_write(client, MT9P031_ROW_BLACK_TARGET,
  692. ctrl->val);
  693. case V4L2_CID_BLC_ANALOG_OFFSET:
  694. data = ctrl->val & ((1 << 9) - 1);
  695. ret = mt9p031_write(client, MT9P031_GREEN1_OFFSET, data);
  696. if (ret < 0)
  697. return ret;
  698. ret = mt9p031_write(client, MT9P031_GREEN2_OFFSET, data);
  699. if (ret < 0)
  700. return ret;
  701. ret = mt9p031_write(client, MT9P031_RED_OFFSET, data);
  702. if (ret < 0)
  703. return ret;
  704. return mt9p031_write(client, MT9P031_BLUE_OFFSET, data);
  705. case V4L2_CID_BLC_DIGITAL_OFFSET:
  706. return mt9p031_write(client, MT9P031_ROW_BLACK_DEF_OFFSET,
  707. ctrl->val & ((1 << 12) - 1));
  708. }
  709. return 0;
  710. }
  711. static const struct v4l2_ctrl_ops mt9p031_ctrl_ops = {
  712. .s_ctrl = mt9p031_s_ctrl,
  713. };
  714. static const char * const mt9p031_test_pattern_menu[] = {
  715. "Disabled",
  716. "Color Field",
  717. "Horizontal Gradient",
  718. "Vertical Gradient",
  719. "Diagonal Gradient",
  720. "Classic Test Pattern",
  721. "Walking 1s",
  722. "Monochrome Horizontal Bars",
  723. "Monochrome Vertical Bars",
  724. "Vertical Color Bars",
  725. };
  726. static const struct v4l2_ctrl_config mt9p031_ctrls[] = {
  727. {
  728. .ops = &mt9p031_ctrl_ops,
  729. .id = V4L2_CID_BLC_AUTO,
  730. .type = V4L2_CTRL_TYPE_BOOLEAN,
  731. .name = "BLC, Auto",
  732. .min = 0,
  733. .max = 1,
  734. .step = 1,
  735. .def = 1,
  736. .flags = 0,
  737. }, {
  738. .ops = &mt9p031_ctrl_ops,
  739. .id = V4L2_CID_BLC_TARGET_LEVEL,
  740. .type = V4L2_CTRL_TYPE_INTEGER,
  741. .name = "BLC Target Level",
  742. .min = 0,
  743. .max = 4095,
  744. .step = 1,
  745. .def = 168,
  746. .flags = 0,
  747. }, {
  748. .ops = &mt9p031_ctrl_ops,
  749. .id = V4L2_CID_BLC_ANALOG_OFFSET,
  750. .type = V4L2_CTRL_TYPE_INTEGER,
  751. .name = "BLC Analog Offset",
  752. .min = -255,
  753. .max = 255,
  754. .step = 1,
  755. .def = 32,
  756. .flags = 0,
  757. }, {
  758. .ops = &mt9p031_ctrl_ops,
  759. .id = V4L2_CID_BLC_DIGITAL_OFFSET,
  760. .type = V4L2_CTRL_TYPE_INTEGER,
  761. .name = "BLC Digital Offset",
  762. .min = -2048,
  763. .max = 2047,
  764. .step = 1,
  765. .def = 40,
  766. .flags = 0,
  767. }
  768. };
  769. /* -----------------------------------------------------------------------------
  770. * V4L2 subdev core operations
  771. */
  772. static int mt9p031_set_power(struct v4l2_subdev *subdev, int on)
  773. {
  774. struct mt9p031 *mt9p031 = to_mt9p031(subdev);
  775. int ret = 0;
  776. mutex_lock(&mt9p031->power_lock);
  777. /* If the power count is modified from 0 to != 0 or from != 0 to 0,
  778. * update the power state.
  779. */
  780. if (mt9p031->power_count == !on) {
  781. ret = __mt9p031_set_power(mt9p031, !!on);
  782. if (ret < 0)
  783. goto out;
  784. }
  785. /* Update the power count. */
  786. mt9p031->power_count += on ? 1 : -1;
  787. WARN_ON(mt9p031->power_count < 0);
  788. out:
  789. mutex_unlock(&mt9p031->power_lock);
  790. return ret;
  791. }
  792. /* -----------------------------------------------------------------------------
  793. * V4L2 subdev internal operations
  794. */
  795. static int mt9p031_registered(struct v4l2_subdev *subdev)
  796. {
  797. struct i2c_client *client = v4l2_get_subdevdata(subdev);
  798. struct mt9p031 *mt9p031 = to_mt9p031(subdev);
  799. s32 data;
  800. int ret;
  801. ret = mt9p031_power_on(mt9p031);
  802. if (ret < 0) {
  803. dev_err(&client->dev, "MT9P031 power up failed\n");
  804. return ret;
  805. }
  806. /* Read out the chip version register */
  807. data = mt9p031_read(client, MT9P031_CHIP_VERSION);
  808. mt9p031_power_off(mt9p031);
  809. if (data != MT9P031_CHIP_VERSION_VALUE) {
  810. dev_err(&client->dev, "MT9P031 not detected, wrong version "
  811. "0x%04x\n", data);
  812. return -ENODEV;
  813. }
  814. dev_info(&client->dev, "MT9P031 detected at address 0x%02x\n",
  815. client->addr);
  816. return 0;
  817. }
  818. static int mt9p031_open(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh)
  819. {
  820. struct mt9p031 *mt9p031 = to_mt9p031(subdev);
  821. struct v4l2_mbus_framefmt *format;
  822. struct v4l2_rect *crop;
  823. crop = v4l2_subdev_get_try_crop(subdev, fh->pad, 0);
  824. crop->left = MT9P031_COLUMN_START_DEF;
  825. crop->top = MT9P031_ROW_START_DEF;
  826. crop->width = MT9P031_WINDOW_WIDTH_DEF;
  827. crop->height = MT9P031_WINDOW_HEIGHT_DEF;
  828. format = v4l2_subdev_get_try_format(subdev, fh->pad, 0);
  829. if (mt9p031->model == MT9P031_MODEL_MONOCHROME)
  830. format->code = MEDIA_BUS_FMT_Y12_1X12;
  831. else
  832. format->code = MEDIA_BUS_FMT_SGRBG12_1X12;
  833. format->width = MT9P031_WINDOW_WIDTH_DEF;
  834. format->height = MT9P031_WINDOW_HEIGHT_DEF;
  835. format->field = V4L2_FIELD_NONE;
  836. format->colorspace = V4L2_COLORSPACE_SRGB;
  837. return mt9p031_set_power(subdev, 1);
  838. }
  839. static int mt9p031_close(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh)
  840. {
  841. return mt9p031_set_power(subdev, 0);
  842. }
  843. static const struct v4l2_subdev_core_ops mt9p031_subdev_core_ops = {
  844. .s_power = mt9p031_set_power,
  845. };
  846. static const struct v4l2_subdev_video_ops mt9p031_subdev_video_ops = {
  847. .s_stream = mt9p031_s_stream,
  848. };
  849. static const struct v4l2_subdev_pad_ops mt9p031_subdev_pad_ops = {
  850. .enum_mbus_code = mt9p031_enum_mbus_code,
  851. .enum_frame_size = mt9p031_enum_frame_size,
  852. .get_fmt = mt9p031_get_format,
  853. .set_fmt = mt9p031_set_format,
  854. .get_selection = mt9p031_get_selection,
  855. .set_selection = mt9p031_set_selection,
  856. };
  857. static const struct v4l2_subdev_ops mt9p031_subdev_ops = {
  858. .core = &mt9p031_subdev_core_ops,
  859. .video = &mt9p031_subdev_video_ops,
  860. .pad = &mt9p031_subdev_pad_ops,
  861. };
  862. static const struct v4l2_subdev_internal_ops mt9p031_subdev_internal_ops = {
  863. .registered = mt9p031_registered,
  864. .open = mt9p031_open,
  865. .close = mt9p031_close,
  866. };
  867. /* -----------------------------------------------------------------------------
  868. * Driver initialization and probing
  869. */
  870. static struct mt9p031_platform_data *
  871. mt9p031_get_pdata(struct i2c_client *client)
  872. {
  873. struct mt9p031_platform_data *pdata;
  874. struct device_node *np;
  875. if (!IS_ENABLED(CONFIG_OF) || !client->dev.of_node)
  876. return client->dev.platform_data;
  877. np = of_graph_get_next_endpoint(client->dev.of_node, NULL);
  878. if (!np)
  879. return NULL;
  880. pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL);
  881. if (!pdata)
  882. goto done;
  883. of_property_read_u32(np, "input-clock-frequency", &pdata->ext_freq);
  884. of_property_read_u32(np, "pixel-clock-frequency", &pdata->target_freq);
  885. done:
  886. of_node_put(np);
  887. return pdata;
  888. }
  889. static int mt9p031_probe(struct i2c_client *client,
  890. const struct i2c_device_id *did)
  891. {
  892. struct mt9p031_platform_data *pdata = mt9p031_get_pdata(client);
  893. struct i2c_adapter *adapter = client->adapter;
  894. struct mt9p031 *mt9p031;
  895. unsigned int i;
  896. int ret;
  897. if (pdata == NULL) {
  898. dev_err(&client->dev, "No platform data\n");
  899. return -EINVAL;
  900. }
  901. if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_WORD_DATA)) {
  902. dev_warn(&client->dev,
  903. "I2C-Adapter doesn't support I2C_FUNC_SMBUS_WORD\n");
  904. return -EIO;
  905. }
  906. mt9p031 = devm_kzalloc(&client->dev, sizeof(*mt9p031), GFP_KERNEL);
  907. if (mt9p031 == NULL)
  908. return -ENOMEM;
  909. mt9p031->pdata = pdata;
  910. mt9p031->output_control = MT9P031_OUTPUT_CONTROL_DEF;
  911. mt9p031->mode2 = MT9P031_READ_MODE_2_ROW_BLC;
  912. mt9p031->model = did->driver_data;
  913. mt9p031->regulators[0].supply = "vdd";
  914. mt9p031->regulators[1].supply = "vdd_io";
  915. mt9p031->regulators[2].supply = "vaa";
  916. ret = devm_regulator_bulk_get(&client->dev, 3, mt9p031->regulators);
  917. if (ret < 0) {
  918. dev_err(&client->dev, "Unable to get regulators\n");
  919. return ret;
  920. }
  921. mutex_init(&mt9p031->power_lock);
  922. v4l2_ctrl_handler_init(&mt9p031->ctrls, ARRAY_SIZE(mt9p031_ctrls) + 6);
  923. v4l2_ctrl_new_std(&mt9p031->ctrls, &mt9p031_ctrl_ops,
  924. V4L2_CID_EXPOSURE, MT9P031_SHUTTER_WIDTH_MIN,
  925. MT9P031_SHUTTER_WIDTH_MAX, 1,
  926. MT9P031_SHUTTER_WIDTH_DEF);
  927. v4l2_ctrl_new_std(&mt9p031->ctrls, &mt9p031_ctrl_ops,
  928. V4L2_CID_GAIN, MT9P031_GLOBAL_GAIN_MIN,
  929. MT9P031_GLOBAL_GAIN_MAX, 1, MT9P031_GLOBAL_GAIN_DEF);
  930. v4l2_ctrl_new_std(&mt9p031->ctrls, &mt9p031_ctrl_ops,
  931. V4L2_CID_HFLIP, 0, 1, 1, 0);
  932. v4l2_ctrl_new_std(&mt9p031->ctrls, &mt9p031_ctrl_ops,
  933. V4L2_CID_VFLIP, 0, 1, 1, 0);
  934. v4l2_ctrl_new_std(&mt9p031->ctrls, &mt9p031_ctrl_ops,
  935. V4L2_CID_PIXEL_RATE, pdata->target_freq,
  936. pdata->target_freq, 1, pdata->target_freq);
  937. v4l2_ctrl_new_std_menu_items(&mt9p031->ctrls, &mt9p031_ctrl_ops,
  938. V4L2_CID_TEST_PATTERN,
  939. ARRAY_SIZE(mt9p031_test_pattern_menu) - 1, 0,
  940. 0, mt9p031_test_pattern_menu);
  941. for (i = 0; i < ARRAY_SIZE(mt9p031_ctrls); ++i)
  942. v4l2_ctrl_new_custom(&mt9p031->ctrls, &mt9p031_ctrls[i], NULL);
  943. mt9p031->subdev.ctrl_handler = &mt9p031->ctrls;
  944. if (mt9p031->ctrls.error) {
  945. printk(KERN_INFO "%s: control initialization error %d\n",
  946. __func__, mt9p031->ctrls.error);
  947. ret = mt9p031->ctrls.error;
  948. goto done;
  949. }
  950. mt9p031->blc_auto = v4l2_ctrl_find(&mt9p031->ctrls, V4L2_CID_BLC_AUTO);
  951. mt9p031->blc_offset = v4l2_ctrl_find(&mt9p031->ctrls,
  952. V4L2_CID_BLC_DIGITAL_OFFSET);
  953. v4l2_i2c_subdev_init(&mt9p031->subdev, client, &mt9p031_subdev_ops);
  954. mt9p031->subdev.internal_ops = &mt9p031_subdev_internal_ops;
  955. mt9p031->subdev.entity.function = MEDIA_ENT_F_CAM_SENSOR;
  956. mt9p031->pad.flags = MEDIA_PAD_FL_SOURCE;
  957. ret = media_entity_pads_init(&mt9p031->subdev.entity, 1, &mt9p031->pad);
  958. if (ret < 0)
  959. goto done;
  960. mt9p031->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
  961. mt9p031->crop.width = MT9P031_WINDOW_WIDTH_DEF;
  962. mt9p031->crop.height = MT9P031_WINDOW_HEIGHT_DEF;
  963. mt9p031->crop.left = MT9P031_COLUMN_START_DEF;
  964. mt9p031->crop.top = MT9P031_ROW_START_DEF;
  965. if (mt9p031->model == MT9P031_MODEL_MONOCHROME)
  966. mt9p031->format.code = MEDIA_BUS_FMT_Y12_1X12;
  967. else
  968. mt9p031->format.code = MEDIA_BUS_FMT_SGRBG12_1X12;
  969. mt9p031->format.width = MT9P031_WINDOW_WIDTH_DEF;
  970. mt9p031->format.height = MT9P031_WINDOW_HEIGHT_DEF;
  971. mt9p031->format.field = V4L2_FIELD_NONE;
  972. mt9p031->format.colorspace = V4L2_COLORSPACE_SRGB;
  973. mt9p031->reset = devm_gpiod_get_optional(&client->dev, "reset",
  974. GPIOD_OUT_HIGH);
  975. ret = mt9p031_clk_setup(mt9p031);
  976. if (ret)
  977. goto done;
  978. ret = v4l2_async_register_subdev(&mt9p031->subdev);
  979. done:
  980. if (ret < 0) {
  981. v4l2_ctrl_handler_free(&mt9p031->ctrls);
  982. media_entity_cleanup(&mt9p031->subdev.entity);
  983. mutex_destroy(&mt9p031->power_lock);
  984. }
  985. return ret;
  986. }
  987. static int mt9p031_remove(struct i2c_client *client)
  988. {
  989. struct v4l2_subdev *subdev = i2c_get_clientdata(client);
  990. struct mt9p031 *mt9p031 = to_mt9p031(subdev);
  991. v4l2_ctrl_handler_free(&mt9p031->ctrls);
  992. v4l2_async_unregister_subdev(subdev);
  993. media_entity_cleanup(&subdev->entity);
  994. mutex_destroy(&mt9p031->power_lock);
  995. return 0;
  996. }
  997. static const struct i2c_device_id mt9p031_id[] = {
  998. { "mt9p031", MT9P031_MODEL_COLOR },
  999. { "mt9p031m", MT9P031_MODEL_MONOCHROME },
  1000. { }
  1001. };
  1002. MODULE_DEVICE_TABLE(i2c, mt9p031_id);
  1003. #if IS_ENABLED(CONFIG_OF)
  1004. static const struct of_device_id mt9p031_of_match[] = {
  1005. { .compatible = "aptina,mt9p031", },
  1006. { .compatible = "aptina,mt9p031m", },
  1007. { /* sentinel */ },
  1008. };
  1009. MODULE_DEVICE_TABLE(of, mt9p031_of_match);
  1010. #endif
  1011. static struct i2c_driver mt9p031_i2c_driver = {
  1012. .driver = {
  1013. .of_match_table = of_match_ptr(mt9p031_of_match),
  1014. .name = "mt9p031",
  1015. },
  1016. .probe = mt9p031_probe,
  1017. .remove = mt9p031_remove,
  1018. .id_table = mt9p031_id,
  1019. };
  1020. module_i2c_driver(mt9p031_i2c_driver);
  1021. MODULE_DESCRIPTION("Aptina MT9P031 Camera driver");
  1022. MODULE_AUTHOR("Bastian Hecht <hechtb@gmail.com>");
  1023. MODULE_LICENSE("GPL v2");