mt9m111.c 38 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Driver for MT9M111/MT9M112/MT9M131 CMOS Image Sensor from Micron/Aptina
  4. *
  5. * Copyright (C) 2008, Robert Jarzmik <robert.jarzmik@free.fr>
  6. */
  7. #include <linux/videodev2.h>
  8. #include <linux/slab.h>
  9. #include <linux/i2c.h>
  10. #include <linux/log2.h>
  11. #include <linux/gpio.h>
  12. #include <linux/delay.h>
  13. #include <linux/regulator/consumer.h>
  14. #include <linux/v4l2-mediabus.h>
  15. #include <linux/module.h>
  16. #include <linux/property.h>
  17. #include <media/v4l2-async.h>
  18. #include <media/v4l2-clk.h>
  19. #include <media/v4l2-common.h>
  20. #include <media/v4l2-ctrls.h>
  21. #include <media/v4l2-device.h>
  22. #include <media/v4l2-event.h>
  23. #include <media/v4l2-fwnode.h>
  24. /*
  25. * MT9M111, MT9M112 and MT9M131:
  26. * i2c address is 0x48 or 0x5d (depending on SADDR pin)
  27. * The platform has to define struct i2c_board_info objects and link to them
  28. * from struct soc_camera_host_desc
  29. */
  30. /*
  31. * Sensor core register addresses (0x000..0x0ff)
  32. */
  33. #define MT9M111_CHIP_VERSION 0x000
  34. #define MT9M111_ROW_START 0x001
  35. #define MT9M111_COLUMN_START 0x002
  36. #define MT9M111_WINDOW_HEIGHT 0x003
  37. #define MT9M111_WINDOW_WIDTH 0x004
  38. #define MT9M111_HORIZONTAL_BLANKING_B 0x005
  39. #define MT9M111_VERTICAL_BLANKING_B 0x006
  40. #define MT9M111_HORIZONTAL_BLANKING_A 0x007
  41. #define MT9M111_VERTICAL_BLANKING_A 0x008
  42. #define MT9M111_SHUTTER_WIDTH 0x009
  43. #define MT9M111_ROW_SPEED 0x00a
  44. #define MT9M111_EXTRA_DELAY 0x00b
  45. #define MT9M111_SHUTTER_DELAY 0x00c
  46. #define MT9M111_RESET 0x00d
  47. #define MT9M111_READ_MODE_B 0x020
  48. #define MT9M111_READ_MODE_A 0x021
  49. #define MT9M111_FLASH_CONTROL 0x023
  50. #define MT9M111_GREEN1_GAIN 0x02b
  51. #define MT9M111_BLUE_GAIN 0x02c
  52. #define MT9M111_RED_GAIN 0x02d
  53. #define MT9M111_GREEN2_GAIN 0x02e
  54. #define MT9M111_GLOBAL_GAIN 0x02f
  55. #define MT9M111_CONTEXT_CONTROL 0x0c8
  56. #define MT9M111_PAGE_MAP 0x0f0
  57. #define MT9M111_BYTE_WISE_ADDR 0x0f1
  58. #define MT9M111_RESET_SYNC_CHANGES (1 << 15)
  59. #define MT9M111_RESET_RESTART_BAD_FRAME (1 << 9)
  60. #define MT9M111_RESET_SHOW_BAD_FRAMES (1 << 8)
  61. #define MT9M111_RESET_RESET_SOC (1 << 5)
  62. #define MT9M111_RESET_OUTPUT_DISABLE (1 << 4)
  63. #define MT9M111_RESET_CHIP_ENABLE (1 << 3)
  64. #define MT9M111_RESET_ANALOG_STANDBY (1 << 2)
  65. #define MT9M111_RESET_RESTART_FRAME (1 << 1)
  66. #define MT9M111_RESET_RESET_MODE (1 << 0)
  67. #define MT9M111_RM_FULL_POWER_RD (0 << 10)
  68. #define MT9M111_RM_LOW_POWER_RD (1 << 10)
  69. #define MT9M111_RM_COL_SKIP_4X (1 << 5)
  70. #define MT9M111_RM_ROW_SKIP_4X (1 << 4)
  71. #define MT9M111_RM_COL_SKIP_2X (1 << 3)
  72. #define MT9M111_RM_ROW_SKIP_2X (1 << 2)
  73. #define MT9M111_RMB_MIRROR_COLS (1 << 1)
  74. #define MT9M111_RMB_MIRROR_ROWS (1 << 0)
  75. #define MT9M111_CTXT_CTRL_RESTART (1 << 15)
  76. #define MT9M111_CTXT_CTRL_DEFECTCOR_B (1 << 12)
  77. #define MT9M111_CTXT_CTRL_RESIZE_B (1 << 10)
  78. #define MT9M111_CTXT_CTRL_CTRL2_B (1 << 9)
  79. #define MT9M111_CTXT_CTRL_GAMMA_B (1 << 8)
  80. #define MT9M111_CTXT_CTRL_XENON_EN (1 << 7)
  81. #define MT9M111_CTXT_CTRL_READ_MODE_B (1 << 3)
  82. #define MT9M111_CTXT_CTRL_LED_FLASH_EN (1 << 2)
  83. #define MT9M111_CTXT_CTRL_VBLANK_SEL_B (1 << 1)
  84. #define MT9M111_CTXT_CTRL_HBLANK_SEL_B (1 << 0)
  85. /*
  86. * Colorpipe register addresses (0x100..0x1ff)
  87. */
  88. #define MT9M111_OPER_MODE_CTRL 0x106
  89. #define MT9M111_OUTPUT_FORMAT_CTRL 0x108
  90. #define MT9M111_TPG_CTRL 0x148
  91. #define MT9M111_REDUCER_XZOOM_B 0x1a0
  92. #define MT9M111_REDUCER_XSIZE_B 0x1a1
  93. #define MT9M111_REDUCER_YZOOM_B 0x1a3
  94. #define MT9M111_REDUCER_YSIZE_B 0x1a4
  95. #define MT9M111_REDUCER_XZOOM_A 0x1a6
  96. #define MT9M111_REDUCER_XSIZE_A 0x1a7
  97. #define MT9M111_REDUCER_YZOOM_A 0x1a9
  98. #define MT9M111_REDUCER_YSIZE_A 0x1aa
  99. #define MT9M111_EFFECTS_MODE 0x1e2
  100. #define MT9M111_OUTPUT_FORMAT_CTRL2_A 0x13a
  101. #define MT9M111_OUTPUT_FORMAT_CTRL2_B 0x19b
  102. #define MT9M111_OPMODE_AUTOEXPO_EN (1 << 14)
  103. #define MT9M111_OPMODE_AUTOWHITEBAL_EN (1 << 1)
  104. #define MT9M111_OUTFMT_FLIP_BAYER_COL (1 << 9)
  105. #define MT9M111_OUTFMT_FLIP_BAYER_ROW (1 << 8)
  106. #define MT9M111_OUTFMT_PROCESSED_BAYER (1 << 14)
  107. #define MT9M111_OUTFMT_BYPASS_IFP (1 << 10)
  108. #define MT9M111_OUTFMT_INV_PIX_CLOCK (1 << 9)
  109. #define MT9M111_OUTFMT_RGB (1 << 8)
  110. #define MT9M111_OUTFMT_RGB565 (0 << 6)
  111. #define MT9M111_OUTFMT_RGB555 (1 << 6)
  112. #define MT9M111_OUTFMT_RGB444x (2 << 6)
  113. #define MT9M111_OUTFMT_RGBx444 (3 << 6)
  114. #define MT9M111_OUTFMT_TST_RAMP_OFF (0 << 4)
  115. #define MT9M111_OUTFMT_TST_RAMP_COL (1 << 4)
  116. #define MT9M111_OUTFMT_TST_RAMP_ROW (2 << 4)
  117. #define MT9M111_OUTFMT_TST_RAMP_FRAME (3 << 4)
  118. #define MT9M111_OUTFMT_SHIFT_3_UP (1 << 3)
  119. #define MT9M111_OUTFMT_AVG_CHROMA (1 << 2)
  120. #define MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN (1 << 1)
  121. #define MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B (1 << 0)
  122. #define MT9M111_TPG_SEL_MASK GENMASK(2, 0)
  123. #define MT9M111_EFFECTS_MODE_MASK GENMASK(2, 0)
  124. #define MT9M111_RM_PWR_MASK BIT(10)
  125. #define MT9M111_RM_SKIP2_MASK GENMASK(3, 2)
  126. /*
  127. * Camera control register addresses (0x200..0x2ff not implemented)
  128. */
  129. #define reg_read(reg) mt9m111_reg_read(client, MT9M111_##reg)
  130. #define reg_write(reg, val) mt9m111_reg_write(client, MT9M111_##reg, (val))
  131. #define reg_set(reg, val) mt9m111_reg_set(client, MT9M111_##reg, (val))
  132. #define reg_clear(reg, val) mt9m111_reg_clear(client, MT9M111_##reg, (val))
  133. #define reg_mask(reg, val, mask) mt9m111_reg_mask(client, MT9M111_##reg, \
  134. (val), (mask))
  135. #define MT9M111_MIN_DARK_ROWS 8
  136. #define MT9M111_MIN_DARK_COLS 26
  137. #define MT9M111_MAX_HEIGHT 1024
  138. #define MT9M111_MAX_WIDTH 1280
  139. struct mt9m111_context {
  140. u16 read_mode;
  141. u16 blanking_h;
  142. u16 blanking_v;
  143. u16 reducer_xzoom;
  144. u16 reducer_yzoom;
  145. u16 reducer_xsize;
  146. u16 reducer_ysize;
  147. u16 output_fmt_ctrl2;
  148. u16 control;
  149. };
  150. static struct mt9m111_context context_a = {
  151. .read_mode = MT9M111_READ_MODE_A,
  152. .blanking_h = MT9M111_HORIZONTAL_BLANKING_A,
  153. .blanking_v = MT9M111_VERTICAL_BLANKING_A,
  154. .reducer_xzoom = MT9M111_REDUCER_XZOOM_A,
  155. .reducer_yzoom = MT9M111_REDUCER_YZOOM_A,
  156. .reducer_xsize = MT9M111_REDUCER_XSIZE_A,
  157. .reducer_ysize = MT9M111_REDUCER_YSIZE_A,
  158. .output_fmt_ctrl2 = MT9M111_OUTPUT_FORMAT_CTRL2_A,
  159. .control = MT9M111_CTXT_CTRL_RESTART,
  160. };
  161. static struct mt9m111_context context_b = {
  162. .read_mode = MT9M111_READ_MODE_B,
  163. .blanking_h = MT9M111_HORIZONTAL_BLANKING_B,
  164. .blanking_v = MT9M111_VERTICAL_BLANKING_B,
  165. .reducer_xzoom = MT9M111_REDUCER_XZOOM_B,
  166. .reducer_yzoom = MT9M111_REDUCER_YZOOM_B,
  167. .reducer_xsize = MT9M111_REDUCER_XSIZE_B,
  168. .reducer_ysize = MT9M111_REDUCER_YSIZE_B,
  169. .output_fmt_ctrl2 = MT9M111_OUTPUT_FORMAT_CTRL2_B,
  170. .control = MT9M111_CTXT_CTRL_RESTART |
  171. MT9M111_CTXT_CTRL_DEFECTCOR_B | MT9M111_CTXT_CTRL_RESIZE_B |
  172. MT9M111_CTXT_CTRL_CTRL2_B | MT9M111_CTXT_CTRL_GAMMA_B |
  173. MT9M111_CTXT_CTRL_READ_MODE_B | MT9M111_CTXT_CTRL_VBLANK_SEL_B |
  174. MT9M111_CTXT_CTRL_HBLANK_SEL_B,
  175. };
  176. /* MT9M111 has only one fixed colorspace per pixelcode */
  177. struct mt9m111_datafmt {
  178. u32 code;
  179. enum v4l2_colorspace colorspace;
  180. };
  181. static const struct mt9m111_datafmt mt9m111_colour_fmts[] = {
  182. {MEDIA_BUS_FMT_YUYV8_2X8, V4L2_COLORSPACE_SRGB},
  183. {MEDIA_BUS_FMT_YVYU8_2X8, V4L2_COLORSPACE_SRGB},
  184. {MEDIA_BUS_FMT_UYVY8_2X8, V4L2_COLORSPACE_SRGB},
  185. {MEDIA_BUS_FMT_VYUY8_2X8, V4L2_COLORSPACE_SRGB},
  186. {MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE, V4L2_COLORSPACE_SRGB},
  187. {MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE, V4L2_COLORSPACE_SRGB},
  188. {MEDIA_BUS_FMT_RGB565_2X8_LE, V4L2_COLORSPACE_SRGB},
  189. {MEDIA_BUS_FMT_RGB565_2X8_BE, V4L2_COLORSPACE_SRGB},
  190. {MEDIA_BUS_FMT_BGR565_2X8_LE, V4L2_COLORSPACE_SRGB},
  191. {MEDIA_BUS_FMT_BGR565_2X8_BE, V4L2_COLORSPACE_SRGB},
  192. {MEDIA_BUS_FMT_SBGGR8_1X8, V4L2_COLORSPACE_SRGB},
  193. {MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE, V4L2_COLORSPACE_SRGB},
  194. };
  195. enum mt9m111_mode_id {
  196. MT9M111_MODE_SXGA_8FPS,
  197. MT9M111_MODE_SXGA_15FPS,
  198. MT9M111_MODE_QSXGA_30FPS,
  199. MT9M111_NUM_MODES,
  200. };
  201. struct mt9m111_mode_info {
  202. unsigned int sensor_w;
  203. unsigned int sensor_h;
  204. unsigned int max_image_w;
  205. unsigned int max_image_h;
  206. unsigned int max_fps;
  207. unsigned int reg_val;
  208. unsigned int reg_mask;
  209. };
  210. struct mt9m111 {
  211. struct v4l2_subdev subdev;
  212. struct v4l2_ctrl_handler hdl;
  213. struct v4l2_ctrl *gain;
  214. struct mt9m111_context *ctx;
  215. struct v4l2_rect rect; /* cropping rectangle */
  216. struct v4l2_clk *clk;
  217. unsigned int width; /* output */
  218. unsigned int height; /* sizes */
  219. struct v4l2_fract frame_interval;
  220. const struct mt9m111_mode_info *current_mode;
  221. struct mutex power_lock; /* lock to protect power_count */
  222. int power_count;
  223. const struct mt9m111_datafmt *fmt;
  224. int lastpage; /* PageMap cache value */
  225. struct regulator *regulator;
  226. bool is_streaming;
  227. /* user point of view - 0: falling 1: rising edge */
  228. unsigned int pclk_sample:1;
  229. #ifdef CONFIG_MEDIA_CONTROLLER
  230. struct media_pad pad;
  231. #endif
  232. };
  233. static const struct mt9m111_mode_info mt9m111_mode_data[MT9M111_NUM_MODES] = {
  234. [MT9M111_MODE_SXGA_8FPS] = {
  235. .sensor_w = 1280,
  236. .sensor_h = 1024,
  237. .max_image_w = 1280,
  238. .max_image_h = 1024,
  239. .max_fps = 8,
  240. .reg_val = MT9M111_RM_LOW_POWER_RD,
  241. .reg_mask = MT9M111_RM_PWR_MASK | MT9M111_RM_SKIP2_MASK,
  242. },
  243. [MT9M111_MODE_SXGA_15FPS] = {
  244. .sensor_w = 1280,
  245. .sensor_h = 1024,
  246. .max_image_w = 1280,
  247. .max_image_h = 1024,
  248. .max_fps = 15,
  249. .reg_val = MT9M111_RM_FULL_POWER_RD,
  250. .reg_mask = MT9M111_RM_PWR_MASK | MT9M111_RM_SKIP2_MASK,
  251. },
  252. [MT9M111_MODE_QSXGA_30FPS] = {
  253. .sensor_w = 1280,
  254. .sensor_h = 1024,
  255. .max_image_w = 640,
  256. .max_image_h = 512,
  257. .max_fps = 30,
  258. .reg_val = MT9M111_RM_LOW_POWER_RD | MT9M111_RM_COL_SKIP_2X |
  259. MT9M111_RM_ROW_SKIP_2X,
  260. .reg_mask = MT9M111_RM_PWR_MASK | MT9M111_RM_SKIP2_MASK,
  261. },
  262. };
  263. /* Find a data format by a pixel code */
  264. static const struct mt9m111_datafmt *mt9m111_find_datafmt(struct mt9m111 *mt9m111,
  265. u32 code)
  266. {
  267. int i;
  268. for (i = 0; i < ARRAY_SIZE(mt9m111_colour_fmts); i++)
  269. if (mt9m111_colour_fmts[i].code == code)
  270. return mt9m111_colour_fmts + i;
  271. return mt9m111->fmt;
  272. }
  273. static struct mt9m111 *to_mt9m111(const struct i2c_client *client)
  274. {
  275. return container_of(i2c_get_clientdata(client), struct mt9m111, subdev);
  276. }
  277. static int reg_page_map_set(struct i2c_client *client, const u16 reg)
  278. {
  279. int ret;
  280. u16 page;
  281. struct mt9m111 *mt9m111 = to_mt9m111(client);
  282. page = (reg >> 8);
  283. if (page == mt9m111->lastpage)
  284. return 0;
  285. if (page > 2)
  286. return -EINVAL;
  287. ret = i2c_smbus_write_word_swapped(client, MT9M111_PAGE_MAP, page);
  288. if (!ret)
  289. mt9m111->lastpage = page;
  290. return ret;
  291. }
  292. static int mt9m111_reg_read(struct i2c_client *client, const u16 reg)
  293. {
  294. int ret;
  295. ret = reg_page_map_set(client, reg);
  296. if (!ret)
  297. ret = i2c_smbus_read_word_swapped(client, reg & 0xff);
  298. dev_dbg(&client->dev, "read reg.%03x -> %04x\n", reg, ret);
  299. return ret;
  300. }
  301. static int mt9m111_reg_write(struct i2c_client *client, const u16 reg,
  302. const u16 data)
  303. {
  304. int ret;
  305. ret = reg_page_map_set(client, reg);
  306. if (!ret)
  307. ret = i2c_smbus_write_word_swapped(client, reg & 0xff, data);
  308. dev_dbg(&client->dev, "write reg.%03x = %04x -> %d\n", reg, data, ret);
  309. return ret;
  310. }
  311. static int mt9m111_reg_set(struct i2c_client *client, const u16 reg,
  312. const u16 data)
  313. {
  314. int ret;
  315. ret = mt9m111_reg_read(client, reg);
  316. if (ret >= 0)
  317. ret = mt9m111_reg_write(client, reg, ret | data);
  318. return ret;
  319. }
  320. static int mt9m111_reg_clear(struct i2c_client *client, const u16 reg,
  321. const u16 data)
  322. {
  323. int ret;
  324. ret = mt9m111_reg_read(client, reg);
  325. if (ret >= 0)
  326. ret = mt9m111_reg_write(client, reg, ret & ~data);
  327. return ret;
  328. }
  329. static int mt9m111_reg_mask(struct i2c_client *client, const u16 reg,
  330. const u16 data, const u16 mask)
  331. {
  332. int ret;
  333. ret = mt9m111_reg_read(client, reg);
  334. if (ret >= 0)
  335. ret = mt9m111_reg_write(client, reg, (ret & ~mask) | data);
  336. return ret;
  337. }
  338. static int mt9m111_set_context(struct mt9m111 *mt9m111,
  339. struct mt9m111_context *ctx)
  340. {
  341. struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
  342. return reg_write(CONTEXT_CONTROL, ctx->control);
  343. }
  344. static int mt9m111_setup_rect_ctx(struct mt9m111 *mt9m111,
  345. struct mt9m111_context *ctx, struct v4l2_rect *rect,
  346. unsigned int width, unsigned int height)
  347. {
  348. struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
  349. int ret = mt9m111_reg_write(client, ctx->reducer_xzoom, rect->width);
  350. if (!ret)
  351. ret = mt9m111_reg_write(client, ctx->reducer_yzoom, rect->height);
  352. if (!ret)
  353. ret = mt9m111_reg_write(client, ctx->reducer_xsize, width);
  354. if (!ret)
  355. ret = mt9m111_reg_write(client, ctx->reducer_ysize, height);
  356. return ret;
  357. }
  358. static int mt9m111_setup_geometry(struct mt9m111 *mt9m111, struct v4l2_rect *rect,
  359. int width, int height, u32 code)
  360. {
  361. struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
  362. int ret;
  363. ret = reg_write(COLUMN_START, rect->left);
  364. if (!ret)
  365. ret = reg_write(ROW_START, rect->top);
  366. if (!ret)
  367. ret = reg_write(WINDOW_WIDTH, rect->width);
  368. if (!ret)
  369. ret = reg_write(WINDOW_HEIGHT, rect->height);
  370. if (code != MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE) {
  371. /* IFP in use, down-scaling possible */
  372. if (!ret)
  373. ret = mt9m111_setup_rect_ctx(mt9m111, &context_b,
  374. rect, width, height);
  375. if (!ret)
  376. ret = mt9m111_setup_rect_ctx(mt9m111, &context_a,
  377. rect, width, height);
  378. }
  379. dev_dbg(&client->dev, "%s(%x): %ux%u@%u:%u -> %ux%u = %d\n",
  380. __func__, code, rect->width, rect->height, rect->left, rect->top,
  381. width, height, ret);
  382. return ret;
  383. }
  384. static int mt9m111_enable(struct mt9m111 *mt9m111)
  385. {
  386. struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
  387. return reg_write(RESET, MT9M111_RESET_CHIP_ENABLE);
  388. }
  389. static int mt9m111_reset(struct mt9m111 *mt9m111)
  390. {
  391. struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
  392. int ret;
  393. ret = reg_set(RESET, MT9M111_RESET_RESET_MODE);
  394. if (!ret)
  395. ret = reg_set(RESET, MT9M111_RESET_RESET_SOC);
  396. if (!ret)
  397. ret = reg_clear(RESET, MT9M111_RESET_RESET_MODE
  398. | MT9M111_RESET_RESET_SOC);
  399. return ret;
  400. }
  401. static int mt9m111_set_selection(struct v4l2_subdev *sd,
  402. struct v4l2_subdev_pad_config *cfg,
  403. struct v4l2_subdev_selection *sel)
  404. {
  405. struct i2c_client *client = v4l2_get_subdevdata(sd);
  406. struct mt9m111 *mt9m111 = to_mt9m111(client);
  407. struct v4l2_rect rect = sel->r;
  408. int width, height;
  409. int ret, align = 0;
  410. if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE ||
  411. sel->target != V4L2_SEL_TGT_CROP)
  412. return -EINVAL;
  413. if (mt9m111->fmt->code == MEDIA_BUS_FMT_SBGGR8_1X8 ||
  414. mt9m111->fmt->code == MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE) {
  415. /* Bayer format - even size lengths */
  416. align = 1;
  417. /* Let the user play with the starting pixel */
  418. }
  419. /* FIXME: the datasheet doesn't specify minimum sizes */
  420. v4l_bound_align_image(&rect.width, 2, MT9M111_MAX_WIDTH, align,
  421. &rect.height, 2, MT9M111_MAX_HEIGHT, align, 0);
  422. rect.left = clamp(rect.left, MT9M111_MIN_DARK_COLS,
  423. MT9M111_MIN_DARK_COLS + MT9M111_MAX_WIDTH -
  424. (__s32)rect.width);
  425. rect.top = clamp(rect.top, MT9M111_MIN_DARK_ROWS,
  426. MT9M111_MIN_DARK_ROWS + MT9M111_MAX_HEIGHT -
  427. (__s32)rect.height);
  428. width = min(mt9m111->width, rect.width);
  429. height = min(mt9m111->height, rect.height);
  430. ret = mt9m111_setup_geometry(mt9m111, &rect, width, height, mt9m111->fmt->code);
  431. if (!ret) {
  432. mt9m111->rect = rect;
  433. mt9m111->width = width;
  434. mt9m111->height = height;
  435. }
  436. return ret;
  437. }
  438. static int mt9m111_get_selection(struct v4l2_subdev *sd,
  439. struct v4l2_subdev_pad_config *cfg,
  440. struct v4l2_subdev_selection *sel)
  441. {
  442. struct i2c_client *client = v4l2_get_subdevdata(sd);
  443. struct mt9m111 *mt9m111 = to_mt9m111(client);
  444. if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE)
  445. return -EINVAL;
  446. switch (sel->target) {
  447. case V4L2_SEL_TGT_CROP_BOUNDS:
  448. sel->r.left = MT9M111_MIN_DARK_COLS;
  449. sel->r.top = MT9M111_MIN_DARK_ROWS;
  450. sel->r.width = MT9M111_MAX_WIDTH;
  451. sel->r.height = MT9M111_MAX_HEIGHT;
  452. return 0;
  453. case V4L2_SEL_TGT_CROP:
  454. sel->r = mt9m111->rect;
  455. return 0;
  456. default:
  457. return -EINVAL;
  458. }
  459. }
  460. static int mt9m111_get_fmt(struct v4l2_subdev *sd,
  461. struct v4l2_subdev_pad_config *cfg,
  462. struct v4l2_subdev_format *format)
  463. {
  464. struct v4l2_mbus_framefmt *mf = &format->format;
  465. struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev);
  466. if (format->pad)
  467. return -EINVAL;
  468. if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
  469. #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
  470. mf = v4l2_subdev_get_try_format(sd, cfg, format->pad);
  471. format->format = *mf;
  472. return 0;
  473. #else
  474. return -EINVAL;
  475. #endif
  476. }
  477. mf->width = mt9m111->width;
  478. mf->height = mt9m111->height;
  479. mf->code = mt9m111->fmt->code;
  480. mf->colorspace = mt9m111->fmt->colorspace;
  481. mf->field = V4L2_FIELD_NONE;
  482. mf->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
  483. mf->quantization = V4L2_QUANTIZATION_DEFAULT;
  484. mf->xfer_func = V4L2_XFER_FUNC_DEFAULT;
  485. return 0;
  486. }
  487. static int mt9m111_set_pixfmt(struct mt9m111 *mt9m111,
  488. u32 code)
  489. {
  490. struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
  491. u16 data_outfmt2, mask_outfmt2 = MT9M111_OUTFMT_PROCESSED_BAYER |
  492. MT9M111_OUTFMT_BYPASS_IFP | MT9M111_OUTFMT_RGB |
  493. MT9M111_OUTFMT_RGB565 | MT9M111_OUTFMT_RGB555 |
  494. MT9M111_OUTFMT_RGB444x | MT9M111_OUTFMT_RGBx444 |
  495. MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN |
  496. MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B;
  497. int ret;
  498. switch (code) {
  499. case MEDIA_BUS_FMT_SBGGR8_1X8:
  500. data_outfmt2 = MT9M111_OUTFMT_PROCESSED_BAYER |
  501. MT9M111_OUTFMT_RGB;
  502. break;
  503. case MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE:
  504. data_outfmt2 = MT9M111_OUTFMT_BYPASS_IFP | MT9M111_OUTFMT_RGB;
  505. break;
  506. case MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE:
  507. data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB555 |
  508. MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN;
  509. break;
  510. case MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE:
  511. data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB555;
  512. break;
  513. case MEDIA_BUS_FMT_RGB565_2X8_LE:
  514. data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB565 |
  515. MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN;
  516. break;
  517. case MEDIA_BUS_FMT_RGB565_2X8_BE:
  518. data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB565;
  519. break;
  520. case MEDIA_BUS_FMT_BGR565_2X8_BE:
  521. data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB565 |
  522. MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B;
  523. break;
  524. case MEDIA_BUS_FMT_BGR565_2X8_LE:
  525. data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB565 |
  526. MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN |
  527. MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B;
  528. break;
  529. case MEDIA_BUS_FMT_UYVY8_2X8:
  530. data_outfmt2 = 0;
  531. break;
  532. case MEDIA_BUS_FMT_VYUY8_2X8:
  533. data_outfmt2 = MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B;
  534. break;
  535. case MEDIA_BUS_FMT_YUYV8_2X8:
  536. data_outfmt2 = MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN;
  537. break;
  538. case MEDIA_BUS_FMT_YVYU8_2X8:
  539. data_outfmt2 = MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN |
  540. MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B;
  541. break;
  542. default:
  543. dev_err(&client->dev, "Pixel format not handled: %x\n", code);
  544. return -EINVAL;
  545. }
  546. /* receiver samples on falling edge, chip-hw default is rising */
  547. if (mt9m111->pclk_sample == 0)
  548. mask_outfmt2 |= MT9M111_OUTFMT_INV_PIX_CLOCK;
  549. ret = mt9m111_reg_mask(client, context_a.output_fmt_ctrl2,
  550. data_outfmt2, mask_outfmt2);
  551. if (!ret)
  552. ret = mt9m111_reg_mask(client, context_b.output_fmt_ctrl2,
  553. data_outfmt2, mask_outfmt2);
  554. return ret;
  555. }
  556. static int mt9m111_set_fmt(struct v4l2_subdev *sd,
  557. struct v4l2_subdev_pad_config *cfg,
  558. struct v4l2_subdev_format *format)
  559. {
  560. struct v4l2_mbus_framefmt *mf = &format->format;
  561. struct i2c_client *client = v4l2_get_subdevdata(sd);
  562. struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev);
  563. const struct mt9m111_datafmt *fmt;
  564. struct v4l2_rect *rect = &mt9m111->rect;
  565. bool bayer;
  566. int ret;
  567. if (mt9m111->is_streaming)
  568. return -EBUSY;
  569. if (format->pad)
  570. return -EINVAL;
  571. fmt = mt9m111_find_datafmt(mt9m111, mf->code);
  572. bayer = fmt->code == MEDIA_BUS_FMT_SBGGR8_1X8 ||
  573. fmt->code == MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE;
  574. /*
  575. * With Bayer format enforce even side lengths, but let the user play
  576. * with the starting pixel
  577. */
  578. if (bayer) {
  579. rect->width = ALIGN(rect->width, 2);
  580. rect->height = ALIGN(rect->height, 2);
  581. }
  582. if (fmt->code == MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE) {
  583. /* IFP bypass mode, no scaling */
  584. mf->width = rect->width;
  585. mf->height = rect->height;
  586. } else {
  587. /* No upscaling */
  588. if (mf->width > rect->width)
  589. mf->width = rect->width;
  590. if (mf->height > rect->height)
  591. mf->height = rect->height;
  592. }
  593. dev_dbg(&client->dev, "%s(): %ux%u, code=%x\n", __func__,
  594. mf->width, mf->height, fmt->code);
  595. mf->code = fmt->code;
  596. mf->colorspace = fmt->colorspace;
  597. mf->field = V4L2_FIELD_NONE;
  598. mf->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
  599. mf->quantization = V4L2_QUANTIZATION_DEFAULT;
  600. mf->xfer_func = V4L2_XFER_FUNC_DEFAULT;
  601. if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
  602. cfg->try_fmt = *mf;
  603. return 0;
  604. }
  605. ret = mt9m111_setup_geometry(mt9m111, rect, mf->width, mf->height, mf->code);
  606. if (!ret)
  607. ret = mt9m111_set_pixfmt(mt9m111, mf->code);
  608. if (!ret) {
  609. mt9m111->width = mf->width;
  610. mt9m111->height = mf->height;
  611. mt9m111->fmt = fmt;
  612. }
  613. return ret;
  614. }
  615. static const struct mt9m111_mode_info *
  616. mt9m111_find_mode(struct mt9m111 *mt9m111, unsigned int req_fps,
  617. unsigned int width, unsigned int height)
  618. {
  619. const struct mt9m111_mode_info *mode;
  620. struct v4l2_rect *sensor_rect = &mt9m111->rect;
  621. unsigned int gap, gap_best = (unsigned int) -1;
  622. int i, best_gap_idx = MT9M111_MODE_SXGA_15FPS;
  623. bool skip_30fps = false;
  624. /*
  625. * The fps selection is based on the row, column skipping mechanism.
  626. * So ensure that the sensor window is set to default else the fps
  627. * aren't calculated correctly within the sensor hw.
  628. */
  629. if (sensor_rect->width != MT9M111_MAX_WIDTH ||
  630. sensor_rect->height != MT9M111_MAX_HEIGHT) {
  631. dev_info(mt9m111->subdev.dev,
  632. "Framerate selection is not supported for cropped "
  633. "images\n");
  634. return NULL;
  635. }
  636. /* 30fps only supported for images not exceeding 640x512 */
  637. if (width > MT9M111_MAX_WIDTH / 2 || height > MT9M111_MAX_HEIGHT / 2) {
  638. dev_dbg(mt9m111->subdev.dev,
  639. "Framerates > 15fps are supported only for images "
  640. "not exceeding 640x512\n");
  641. skip_30fps = true;
  642. }
  643. /* find best matched fps */
  644. for (i = 0; i < MT9M111_NUM_MODES; i++) {
  645. unsigned int fps = mt9m111_mode_data[i].max_fps;
  646. if (fps == 30 && skip_30fps)
  647. continue;
  648. gap = abs(fps - req_fps);
  649. if (gap < gap_best) {
  650. best_gap_idx = i;
  651. gap_best = gap;
  652. }
  653. }
  654. /*
  655. * Use context a/b default timing values instead of calculate blanking
  656. * timing values.
  657. */
  658. mode = &mt9m111_mode_data[best_gap_idx];
  659. mt9m111->ctx = (best_gap_idx == MT9M111_MODE_QSXGA_30FPS) ? &context_a :
  660. &context_b;
  661. return mode;
  662. }
  663. #ifdef CONFIG_VIDEO_ADV_DEBUG
  664. static int mt9m111_g_register(struct v4l2_subdev *sd,
  665. struct v4l2_dbg_register *reg)
  666. {
  667. struct i2c_client *client = v4l2_get_subdevdata(sd);
  668. int val;
  669. if (reg->reg > 0x2ff)
  670. return -EINVAL;
  671. val = mt9m111_reg_read(client, reg->reg);
  672. reg->size = 2;
  673. reg->val = (u64)val;
  674. if (reg->val > 0xffff)
  675. return -EIO;
  676. return 0;
  677. }
  678. static int mt9m111_s_register(struct v4l2_subdev *sd,
  679. const struct v4l2_dbg_register *reg)
  680. {
  681. struct i2c_client *client = v4l2_get_subdevdata(sd);
  682. if (reg->reg > 0x2ff)
  683. return -EINVAL;
  684. if (mt9m111_reg_write(client, reg->reg, reg->val) < 0)
  685. return -EIO;
  686. return 0;
  687. }
  688. #endif
  689. static int mt9m111_set_flip(struct mt9m111 *mt9m111, int flip, int mask)
  690. {
  691. struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
  692. int ret;
  693. if (flip)
  694. ret = mt9m111_reg_set(client, mt9m111->ctx->read_mode, mask);
  695. else
  696. ret = mt9m111_reg_clear(client, mt9m111->ctx->read_mode, mask);
  697. return ret;
  698. }
  699. static int mt9m111_get_global_gain(struct mt9m111 *mt9m111)
  700. {
  701. struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
  702. int data;
  703. data = reg_read(GLOBAL_GAIN);
  704. if (data >= 0)
  705. return (data & 0x2f) * (1 << ((data >> 10) & 1)) *
  706. (1 << ((data >> 9) & 1));
  707. return data;
  708. }
  709. static int mt9m111_set_global_gain(struct mt9m111 *mt9m111, int gain)
  710. {
  711. struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
  712. u16 val;
  713. if (gain > 63 * 2 * 2)
  714. return -EINVAL;
  715. if ((gain >= 64 * 2) && (gain < 63 * 2 * 2))
  716. val = (1 << 10) | (1 << 9) | (gain / 4);
  717. else if ((gain >= 64) && (gain < 64 * 2))
  718. val = (1 << 9) | (gain / 2);
  719. else
  720. val = gain;
  721. return reg_write(GLOBAL_GAIN, val);
  722. }
  723. static int mt9m111_set_autoexposure(struct mt9m111 *mt9m111, int val)
  724. {
  725. struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
  726. if (val == V4L2_EXPOSURE_AUTO)
  727. return reg_set(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOEXPO_EN);
  728. return reg_clear(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOEXPO_EN);
  729. }
  730. static int mt9m111_set_autowhitebalance(struct mt9m111 *mt9m111, int on)
  731. {
  732. struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
  733. if (on)
  734. return reg_set(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOWHITEBAL_EN);
  735. return reg_clear(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOWHITEBAL_EN);
  736. }
  737. static const char * const mt9m111_test_pattern_menu[] = {
  738. "Disabled",
  739. "Vertical monochrome gradient",
  740. "Flat color type 1",
  741. "Flat color type 2",
  742. "Flat color type 3",
  743. "Flat color type 4",
  744. "Flat color type 5",
  745. "Color bar",
  746. };
  747. static int mt9m111_set_test_pattern(struct mt9m111 *mt9m111, int val)
  748. {
  749. struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
  750. return mt9m111_reg_mask(client, MT9M111_TPG_CTRL, val,
  751. MT9M111_TPG_SEL_MASK);
  752. }
  753. static int mt9m111_set_colorfx(struct mt9m111 *mt9m111, int val)
  754. {
  755. struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
  756. static const struct v4l2_control colorfx[] = {
  757. { V4L2_COLORFX_NONE, 0 },
  758. { V4L2_COLORFX_BW, 1 },
  759. { V4L2_COLORFX_SEPIA, 2 },
  760. { V4L2_COLORFX_NEGATIVE, 3 },
  761. { V4L2_COLORFX_SOLARIZATION, 4 },
  762. };
  763. int i;
  764. for (i = 0; i < ARRAY_SIZE(colorfx); i++) {
  765. if (colorfx[i].id == val) {
  766. return mt9m111_reg_mask(client, MT9M111_EFFECTS_MODE,
  767. colorfx[i].value,
  768. MT9M111_EFFECTS_MODE_MASK);
  769. }
  770. }
  771. return -EINVAL;
  772. }
  773. static int mt9m111_s_ctrl(struct v4l2_ctrl *ctrl)
  774. {
  775. struct mt9m111 *mt9m111 = container_of(ctrl->handler,
  776. struct mt9m111, hdl);
  777. switch (ctrl->id) {
  778. case V4L2_CID_VFLIP:
  779. return mt9m111_set_flip(mt9m111, ctrl->val,
  780. MT9M111_RMB_MIRROR_ROWS);
  781. case V4L2_CID_HFLIP:
  782. return mt9m111_set_flip(mt9m111, ctrl->val,
  783. MT9M111_RMB_MIRROR_COLS);
  784. case V4L2_CID_GAIN:
  785. return mt9m111_set_global_gain(mt9m111, ctrl->val);
  786. case V4L2_CID_EXPOSURE_AUTO:
  787. return mt9m111_set_autoexposure(mt9m111, ctrl->val);
  788. case V4L2_CID_AUTO_WHITE_BALANCE:
  789. return mt9m111_set_autowhitebalance(mt9m111, ctrl->val);
  790. case V4L2_CID_TEST_PATTERN:
  791. return mt9m111_set_test_pattern(mt9m111, ctrl->val);
  792. case V4L2_CID_COLORFX:
  793. return mt9m111_set_colorfx(mt9m111, ctrl->val);
  794. }
  795. return -EINVAL;
  796. }
  797. static int mt9m111_suspend(struct mt9m111 *mt9m111)
  798. {
  799. struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
  800. int ret;
  801. v4l2_ctrl_s_ctrl(mt9m111->gain, mt9m111_get_global_gain(mt9m111));
  802. ret = reg_set(RESET, MT9M111_RESET_RESET_MODE);
  803. if (!ret)
  804. ret = reg_set(RESET, MT9M111_RESET_RESET_SOC |
  805. MT9M111_RESET_OUTPUT_DISABLE |
  806. MT9M111_RESET_ANALOG_STANDBY);
  807. if (!ret)
  808. ret = reg_clear(RESET, MT9M111_RESET_CHIP_ENABLE);
  809. return ret;
  810. }
  811. static void mt9m111_restore_state(struct mt9m111 *mt9m111)
  812. {
  813. struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
  814. mt9m111_set_context(mt9m111, mt9m111->ctx);
  815. mt9m111_set_pixfmt(mt9m111, mt9m111->fmt->code);
  816. mt9m111_setup_geometry(mt9m111, &mt9m111->rect,
  817. mt9m111->width, mt9m111->height, mt9m111->fmt->code);
  818. v4l2_ctrl_handler_setup(&mt9m111->hdl);
  819. mt9m111_reg_mask(client, mt9m111->ctx->read_mode,
  820. mt9m111->current_mode->reg_val,
  821. mt9m111->current_mode->reg_mask);
  822. }
  823. static int mt9m111_resume(struct mt9m111 *mt9m111)
  824. {
  825. int ret = mt9m111_enable(mt9m111);
  826. if (!ret)
  827. ret = mt9m111_reset(mt9m111);
  828. if (!ret)
  829. mt9m111_restore_state(mt9m111);
  830. return ret;
  831. }
  832. static int mt9m111_init(struct mt9m111 *mt9m111)
  833. {
  834. struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
  835. int ret;
  836. ret = mt9m111_enable(mt9m111);
  837. if (!ret)
  838. ret = mt9m111_reset(mt9m111);
  839. if (!ret)
  840. ret = mt9m111_set_context(mt9m111, mt9m111->ctx);
  841. if (ret)
  842. dev_err(&client->dev, "mt9m111 init failed: %d\n", ret);
  843. return ret;
  844. }
  845. static int mt9m111_power_on(struct mt9m111 *mt9m111)
  846. {
  847. struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
  848. int ret;
  849. ret = v4l2_clk_enable(mt9m111->clk);
  850. if (ret < 0)
  851. return ret;
  852. ret = regulator_enable(mt9m111->regulator);
  853. if (ret < 0)
  854. goto out_clk_disable;
  855. ret = mt9m111_resume(mt9m111);
  856. if (ret < 0)
  857. goto out_regulator_disable;
  858. return 0;
  859. out_regulator_disable:
  860. regulator_disable(mt9m111->regulator);
  861. out_clk_disable:
  862. v4l2_clk_disable(mt9m111->clk);
  863. dev_err(&client->dev, "Failed to resume the sensor: %d\n", ret);
  864. return ret;
  865. }
  866. static void mt9m111_power_off(struct mt9m111 *mt9m111)
  867. {
  868. mt9m111_suspend(mt9m111);
  869. regulator_disable(mt9m111->regulator);
  870. v4l2_clk_disable(mt9m111->clk);
  871. }
  872. static int mt9m111_s_power(struct v4l2_subdev *sd, int on)
  873. {
  874. struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev);
  875. int ret = 0;
  876. mutex_lock(&mt9m111->power_lock);
  877. /*
  878. * If the power count is modified from 0 to != 0 or from != 0 to 0,
  879. * update the power state.
  880. */
  881. if (mt9m111->power_count == !on) {
  882. if (on)
  883. ret = mt9m111_power_on(mt9m111);
  884. else
  885. mt9m111_power_off(mt9m111);
  886. }
  887. if (!ret) {
  888. /* Update the power count. */
  889. mt9m111->power_count += on ? 1 : -1;
  890. WARN_ON(mt9m111->power_count < 0);
  891. }
  892. mutex_unlock(&mt9m111->power_lock);
  893. return ret;
  894. }
  895. static const struct v4l2_ctrl_ops mt9m111_ctrl_ops = {
  896. .s_ctrl = mt9m111_s_ctrl,
  897. };
  898. static const struct v4l2_subdev_core_ops mt9m111_subdev_core_ops = {
  899. .s_power = mt9m111_s_power,
  900. .log_status = v4l2_ctrl_subdev_log_status,
  901. .subscribe_event = v4l2_ctrl_subdev_subscribe_event,
  902. .unsubscribe_event = v4l2_event_subdev_unsubscribe,
  903. #ifdef CONFIG_VIDEO_ADV_DEBUG
  904. .g_register = mt9m111_g_register,
  905. .s_register = mt9m111_s_register,
  906. #endif
  907. };
  908. static int mt9m111_g_frame_interval(struct v4l2_subdev *sd,
  909. struct v4l2_subdev_frame_interval *fi)
  910. {
  911. struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev);
  912. fi->interval = mt9m111->frame_interval;
  913. return 0;
  914. }
  915. static int mt9m111_s_frame_interval(struct v4l2_subdev *sd,
  916. struct v4l2_subdev_frame_interval *fi)
  917. {
  918. struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev);
  919. const struct mt9m111_mode_info *mode;
  920. struct v4l2_fract *fract = &fi->interval;
  921. int fps;
  922. if (mt9m111->is_streaming)
  923. return -EBUSY;
  924. if (fi->pad != 0)
  925. return -EINVAL;
  926. if (fract->numerator == 0) {
  927. fract->denominator = 30;
  928. fract->numerator = 1;
  929. }
  930. fps = DIV_ROUND_CLOSEST(fract->denominator, fract->numerator);
  931. /* Find best fitting mode. Do not update the mode if no one was found. */
  932. mode = mt9m111_find_mode(mt9m111, fps, mt9m111->width, mt9m111->height);
  933. if (!mode)
  934. return 0;
  935. if (mode->max_fps != fps) {
  936. fract->denominator = mode->max_fps;
  937. fract->numerator = 1;
  938. }
  939. mt9m111->current_mode = mode;
  940. mt9m111->frame_interval = fi->interval;
  941. return 0;
  942. }
  943. static int mt9m111_enum_mbus_code(struct v4l2_subdev *sd,
  944. struct v4l2_subdev_pad_config *cfg,
  945. struct v4l2_subdev_mbus_code_enum *code)
  946. {
  947. if (code->pad || code->index >= ARRAY_SIZE(mt9m111_colour_fmts))
  948. return -EINVAL;
  949. code->code = mt9m111_colour_fmts[code->index].code;
  950. return 0;
  951. }
  952. static int mt9m111_s_stream(struct v4l2_subdev *sd, int enable)
  953. {
  954. struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev);
  955. mt9m111->is_streaming = !!enable;
  956. return 0;
  957. }
  958. static int mt9m111_init_cfg(struct v4l2_subdev *sd,
  959. struct v4l2_subdev_pad_config *cfg)
  960. {
  961. #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
  962. struct v4l2_mbus_framefmt *format =
  963. v4l2_subdev_get_try_format(sd, cfg, 0);
  964. format->width = MT9M111_MAX_WIDTH;
  965. format->height = MT9M111_MAX_HEIGHT;
  966. format->code = mt9m111_colour_fmts[0].code;
  967. format->colorspace = mt9m111_colour_fmts[0].colorspace;
  968. format->field = V4L2_FIELD_NONE;
  969. format->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
  970. format->quantization = V4L2_QUANTIZATION_DEFAULT;
  971. format->xfer_func = V4L2_XFER_FUNC_DEFAULT;
  972. #endif
  973. return 0;
  974. }
  975. static int mt9m111_get_mbus_config(struct v4l2_subdev *sd,
  976. unsigned int pad,
  977. struct v4l2_mbus_config *cfg)
  978. {
  979. struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev);
  980. cfg->flags = V4L2_MBUS_MASTER |
  981. V4L2_MBUS_HSYNC_ACTIVE_HIGH | V4L2_MBUS_VSYNC_ACTIVE_HIGH |
  982. V4L2_MBUS_DATA_ACTIVE_HIGH;
  983. cfg->flags |= mt9m111->pclk_sample ? V4L2_MBUS_PCLK_SAMPLE_RISING :
  984. V4L2_MBUS_PCLK_SAMPLE_FALLING;
  985. cfg->type = V4L2_MBUS_PARALLEL;
  986. return 0;
  987. }
  988. static const struct v4l2_subdev_video_ops mt9m111_subdev_video_ops = {
  989. .s_stream = mt9m111_s_stream,
  990. .g_frame_interval = mt9m111_g_frame_interval,
  991. .s_frame_interval = mt9m111_s_frame_interval,
  992. };
  993. static const struct v4l2_subdev_pad_ops mt9m111_subdev_pad_ops = {
  994. .init_cfg = mt9m111_init_cfg,
  995. .enum_mbus_code = mt9m111_enum_mbus_code,
  996. .get_selection = mt9m111_get_selection,
  997. .set_selection = mt9m111_set_selection,
  998. .get_fmt = mt9m111_get_fmt,
  999. .set_fmt = mt9m111_set_fmt,
  1000. .get_mbus_config = mt9m111_get_mbus_config,
  1001. };
  1002. static const struct v4l2_subdev_ops mt9m111_subdev_ops = {
  1003. .core = &mt9m111_subdev_core_ops,
  1004. .video = &mt9m111_subdev_video_ops,
  1005. .pad = &mt9m111_subdev_pad_ops,
  1006. };
  1007. /*
  1008. * Interface active, can use i2c. If it fails, it can indeed mean, that
  1009. * this wasn't our capture interface, so, we wait for the right one
  1010. */
  1011. static int mt9m111_video_probe(struct i2c_client *client)
  1012. {
  1013. struct mt9m111 *mt9m111 = to_mt9m111(client);
  1014. s32 data;
  1015. int ret;
  1016. ret = mt9m111_s_power(&mt9m111->subdev, 1);
  1017. if (ret < 0)
  1018. return ret;
  1019. data = reg_read(CHIP_VERSION);
  1020. switch (data) {
  1021. case 0x143a: /* MT9M111 or MT9M131 */
  1022. dev_info(&client->dev,
  1023. "Detected a MT9M111/MT9M131 chip ID %x\n", data);
  1024. break;
  1025. case 0x148c: /* MT9M112 */
  1026. dev_info(&client->dev, "Detected a MT9M112 chip ID %x\n", data);
  1027. break;
  1028. default:
  1029. dev_err(&client->dev,
  1030. "No MT9M111/MT9M112/MT9M131 chip detected register read %x\n",
  1031. data);
  1032. ret = -ENODEV;
  1033. goto done;
  1034. }
  1035. ret = mt9m111_init(mt9m111);
  1036. if (ret)
  1037. goto done;
  1038. ret = v4l2_ctrl_handler_setup(&mt9m111->hdl);
  1039. done:
  1040. mt9m111_s_power(&mt9m111->subdev, 0);
  1041. return ret;
  1042. }
  1043. static int mt9m111_probe_fw(struct i2c_client *client, struct mt9m111 *mt9m111)
  1044. {
  1045. struct v4l2_fwnode_endpoint bus_cfg = {
  1046. .bus_type = V4L2_MBUS_PARALLEL
  1047. };
  1048. struct fwnode_handle *np;
  1049. int ret;
  1050. np = fwnode_graph_get_next_endpoint(dev_fwnode(&client->dev), NULL);
  1051. if (!np)
  1052. return -EINVAL;
  1053. ret = v4l2_fwnode_endpoint_parse(np, &bus_cfg);
  1054. if (ret)
  1055. goto out_put_fw;
  1056. mt9m111->pclk_sample = !!(bus_cfg.bus.parallel.flags &
  1057. V4L2_MBUS_PCLK_SAMPLE_RISING);
  1058. out_put_fw:
  1059. fwnode_handle_put(np);
  1060. return ret;
  1061. }
  1062. static int mt9m111_probe(struct i2c_client *client)
  1063. {
  1064. struct mt9m111 *mt9m111;
  1065. struct i2c_adapter *adapter = client->adapter;
  1066. int ret;
  1067. if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_WORD_DATA)) {
  1068. dev_warn(&adapter->dev,
  1069. "I2C-Adapter doesn't support I2C_FUNC_SMBUS_WORD\n");
  1070. return -EIO;
  1071. }
  1072. mt9m111 = devm_kzalloc(&client->dev, sizeof(struct mt9m111), GFP_KERNEL);
  1073. if (!mt9m111)
  1074. return -ENOMEM;
  1075. if (dev_fwnode(&client->dev)) {
  1076. ret = mt9m111_probe_fw(client, mt9m111);
  1077. if (ret)
  1078. return ret;
  1079. }
  1080. mt9m111->clk = v4l2_clk_get(&client->dev, "mclk");
  1081. if (IS_ERR(mt9m111->clk))
  1082. return PTR_ERR(mt9m111->clk);
  1083. mt9m111->regulator = devm_regulator_get(&client->dev, "vdd");
  1084. if (IS_ERR(mt9m111->regulator)) {
  1085. dev_err(&client->dev, "regulator not found: %ld\n",
  1086. PTR_ERR(mt9m111->regulator));
  1087. return PTR_ERR(mt9m111->regulator);
  1088. }
  1089. /* Default HIGHPOWER context */
  1090. mt9m111->ctx = &context_b;
  1091. v4l2_i2c_subdev_init(&mt9m111->subdev, client, &mt9m111_subdev_ops);
  1092. mt9m111->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
  1093. V4L2_SUBDEV_FL_HAS_EVENTS;
  1094. v4l2_ctrl_handler_init(&mt9m111->hdl, 7);
  1095. v4l2_ctrl_new_std(&mt9m111->hdl, &mt9m111_ctrl_ops,
  1096. V4L2_CID_VFLIP, 0, 1, 1, 0);
  1097. v4l2_ctrl_new_std(&mt9m111->hdl, &mt9m111_ctrl_ops,
  1098. V4L2_CID_HFLIP, 0, 1, 1, 0);
  1099. v4l2_ctrl_new_std(&mt9m111->hdl, &mt9m111_ctrl_ops,
  1100. V4L2_CID_AUTO_WHITE_BALANCE, 0, 1, 1, 1);
  1101. mt9m111->gain = v4l2_ctrl_new_std(&mt9m111->hdl, &mt9m111_ctrl_ops,
  1102. V4L2_CID_GAIN, 0, 63 * 2 * 2, 1, 32);
  1103. v4l2_ctrl_new_std_menu(&mt9m111->hdl,
  1104. &mt9m111_ctrl_ops, V4L2_CID_EXPOSURE_AUTO, 1, 0,
  1105. V4L2_EXPOSURE_AUTO);
  1106. v4l2_ctrl_new_std_menu_items(&mt9m111->hdl,
  1107. &mt9m111_ctrl_ops, V4L2_CID_TEST_PATTERN,
  1108. ARRAY_SIZE(mt9m111_test_pattern_menu) - 1, 0, 0,
  1109. mt9m111_test_pattern_menu);
  1110. v4l2_ctrl_new_std_menu(&mt9m111->hdl, &mt9m111_ctrl_ops,
  1111. V4L2_CID_COLORFX, V4L2_COLORFX_SOLARIZATION,
  1112. ~(BIT(V4L2_COLORFX_NONE) |
  1113. BIT(V4L2_COLORFX_BW) |
  1114. BIT(V4L2_COLORFX_SEPIA) |
  1115. BIT(V4L2_COLORFX_NEGATIVE) |
  1116. BIT(V4L2_COLORFX_SOLARIZATION)),
  1117. V4L2_COLORFX_NONE);
  1118. mt9m111->subdev.ctrl_handler = &mt9m111->hdl;
  1119. if (mt9m111->hdl.error) {
  1120. ret = mt9m111->hdl.error;
  1121. goto out_clkput;
  1122. }
  1123. #ifdef CONFIG_MEDIA_CONTROLLER
  1124. mt9m111->pad.flags = MEDIA_PAD_FL_SOURCE;
  1125. mt9m111->subdev.entity.function = MEDIA_ENT_F_CAM_SENSOR;
  1126. ret = media_entity_pads_init(&mt9m111->subdev.entity, 1, &mt9m111->pad);
  1127. if (ret < 0)
  1128. goto out_hdlfree;
  1129. #endif
  1130. mt9m111->current_mode = &mt9m111_mode_data[MT9M111_MODE_SXGA_15FPS];
  1131. mt9m111->frame_interval.numerator = 1;
  1132. mt9m111->frame_interval.denominator = mt9m111->current_mode->max_fps;
  1133. /* Second stage probe - when a capture adapter is there */
  1134. mt9m111->rect.left = MT9M111_MIN_DARK_COLS;
  1135. mt9m111->rect.top = MT9M111_MIN_DARK_ROWS;
  1136. mt9m111->rect.width = MT9M111_MAX_WIDTH;
  1137. mt9m111->rect.height = MT9M111_MAX_HEIGHT;
  1138. mt9m111->width = mt9m111->rect.width;
  1139. mt9m111->height = mt9m111->rect.height;
  1140. mt9m111->fmt = &mt9m111_colour_fmts[0];
  1141. mt9m111->lastpage = -1;
  1142. mutex_init(&mt9m111->power_lock);
  1143. ret = mt9m111_video_probe(client);
  1144. if (ret < 0)
  1145. goto out_entityclean;
  1146. mt9m111->subdev.dev = &client->dev;
  1147. ret = v4l2_async_register_subdev(&mt9m111->subdev);
  1148. if (ret < 0)
  1149. goto out_entityclean;
  1150. return 0;
  1151. out_entityclean:
  1152. #ifdef CONFIG_MEDIA_CONTROLLER
  1153. media_entity_cleanup(&mt9m111->subdev.entity);
  1154. out_hdlfree:
  1155. #endif
  1156. v4l2_ctrl_handler_free(&mt9m111->hdl);
  1157. out_clkput:
  1158. v4l2_clk_put(mt9m111->clk);
  1159. return ret;
  1160. }
  1161. static int mt9m111_remove(struct i2c_client *client)
  1162. {
  1163. struct mt9m111 *mt9m111 = to_mt9m111(client);
  1164. v4l2_async_unregister_subdev(&mt9m111->subdev);
  1165. media_entity_cleanup(&mt9m111->subdev.entity);
  1166. v4l2_clk_put(mt9m111->clk);
  1167. v4l2_ctrl_handler_free(&mt9m111->hdl);
  1168. return 0;
  1169. }
  1170. static const struct of_device_id mt9m111_of_match[] = {
  1171. { .compatible = "micron,mt9m111", },
  1172. {},
  1173. };
  1174. MODULE_DEVICE_TABLE(of, mt9m111_of_match);
  1175. static const struct i2c_device_id mt9m111_id[] = {
  1176. { "mt9m111", 0 },
  1177. { }
  1178. };
  1179. MODULE_DEVICE_TABLE(i2c, mt9m111_id);
  1180. static struct i2c_driver mt9m111_i2c_driver = {
  1181. .driver = {
  1182. .name = "mt9m111",
  1183. .of_match_table = of_match_ptr(mt9m111_of_match),
  1184. },
  1185. .probe_new = mt9m111_probe,
  1186. .remove = mt9m111_remove,
  1187. .id_table = mt9m111_id,
  1188. };
  1189. module_i2c_driver(mt9m111_i2c_driver);
  1190. MODULE_DESCRIPTION("Micron/Aptina MT9M111/MT9M112/MT9M131 Camera driver");
  1191. MODULE_AUTHOR("Robert Jarzmik");
  1192. MODULE_LICENSE("GPL");