ml86v7667.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * OKI Semiconductor ML86V7667 video decoder driver
  4. *
  5. * Author: Vladimir Barinov <source@cogentembedded.com>
  6. * Copyright (C) 2013 Cogent Embedded, Inc.
  7. * Copyright (C) 2013 Renesas Solutions Corp.
  8. */
  9. #include <linux/init.h>
  10. #include <linux/module.h>
  11. #include <linux/i2c.h>
  12. #include <linux/slab.h>
  13. #include <linux/videodev2.h>
  14. #include <media/v4l2-subdev.h>
  15. #include <media/v4l2-device.h>
  16. #include <media/v4l2-ioctl.h>
  17. #include <media/v4l2-ctrls.h>
  18. #define DRV_NAME "ml86v7667"
  19. /* Subaddresses */
  20. #define MRA_REG 0x00 /* Mode Register A */
  21. #define MRC_REG 0x02 /* Mode Register C */
  22. #define LUMC_REG 0x0C /* Luminance Control */
  23. #define CLC_REG 0x10 /* Contrast level control */
  24. #define SSEPL_REG 0x11 /* Sync separation level */
  25. #define CHRCA_REG 0x12 /* Chrominance Control A */
  26. #define ACCC_REG 0x14 /* ACC Loop filter & Chrominance control */
  27. #define ACCRC_REG 0x15 /* ACC Reference level control */
  28. #define HUE_REG 0x16 /* Hue control */
  29. #define ADC2_REG 0x1F /* ADC Register 2 */
  30. #define PLLR1_REG 0x20 /* PLL Register 1 */
  31. #define STATUS_REG 0x2C /* STATUS Register */
  32. /* Mode Register A register bits */
  33. #define MRA_OUTPUT_MODE_MASK (3 << 6)
  34. #define MRA_ITUR_BT601 (1 << 6)
  35. #define MRA_ITUR_BT656 (0 << 6)
  36. #define MRA_INPUT_MODE_MASK (7 << 3)
  37. #define MRA_PAL_BT601 (4 << 3)
  38. #define MRA_NTSC_BT601 (0 << 3)
  39. #define MRA_REGISTER_MODE (1 << 0)
  40. /* Mode Register C register bits */
  41. #define MRC_AUTOSELECT (1 << 7)
  42. /* Luminance Control register bits */
  43. #define LUMC_ONOFF_SHIFT 7
  44. #define LUMC_ONOFF_MASK (1 << 7)
  45. /* Contrast level control register bits */
  46. #define CLC_CONTRAST_ONOFF (1 << 7)
  47. #define CLC_CONTRAST_MASK 0x0F
  48. /* Sync separation level register bits */
  49. #define SSEPL_LUMINANCE_ONOFF (1 << 7)
  50. #define SSEPL_LUMINANCE_MASK 0x7F
  51. /* Chrominance Control A register bits */
  52. #define CHRCA_MODE_SHIFT 6
  53. #define CHRCA_MODE_MASK (1 << 6)
  54. /* ACC Loop filter & Chrominance control register bits */
  55. #define ACCC_CHROMA_CR_SHIFT 3
  56. #define ACCC_CHROMA_CR_MASK (7 << 3)
  57. #define ACCC_CHROMA_CB_SHIFT 0
  58. #define ACCC_CHROMA_CB_MASK (7 << 0)
  59. /* ACC Reference level control register bits */
  60. #define ACCRC_CHROMA_MASK 0xfc
  61. #define ACCRC_CHROMA_SHIFT 2
  62. /* ADC Register 2 register bits */
  63. #define ADC2_CLAMP_VOLTAGE_MASK (7 << 1)
  64. #define ADC2_CLAMP_VOLTAGE(n) ((n & 7) << 1)
  65. /* PLL Register 1 register bits */
  66. #define PLLR1_FIXED_CLOCK (1 << 7)
  67. /* STATUS Register register bits */
  68. #define STATUS_HLOCK_DETECT (1 << 3)
  69. #define STATUS_NTSCPAL (1 << 2)
  70. struct ml86v7667_priv {
  71. struct v4l2_subdev sd;
  72. struct v4l2_ctrl_handler hdl;
  73. v4l2_std_id std;
  74. };
  75. static inline struct ml86v7667_priv *to_ml86v7667(struct v4l2_subdev *subdev)
  76. {
  77. return container_of(subdev, struct ml86v7667_priv, sd);
  78. }
  79. static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
  80. {
  81. return &container_of(ctrl->handler, struct ml86v7667_priv, hdl)->sd;
  82. }
  83. static int ml86v7667_mask_set(struct i2c_client *client, const u8 reg,
  84. const u8 mask, const u8 data)
  85. {
  86. int val = i2c_smbus_read_byte_data(client, reg);
  87. if (val < 0)
  88. return val;
  89. val = (val & ~mask) | (data & mask);
  90. return i2c_smbus_write_byte_data(client, reg, val);
  91. }
  92. static int ml86v7667_s_ctrl(struct v4l2_ctrl *ctrl)
  93. {
  94. struct v4l2_subdev *sd = to_sd(ctrl);
  95. struct i2c_client *client = v4l2_get_subdevdata(sd);
  96. int ret = -EINVAL;
  97. switch (ctrl->id) {
  98. case V4L2_CID_BRIGHTNESS:
  99. ret = ml86v7667_mask_set(client, SSEPL_REG,
  100. SSEPL_LUMINANCE_MASK, ctrl->val);
  101. break;
  102. case V4L2_CID_CONTRAST:
  103. ret = ml86v7667_mask_set(client, CLC_REG,
  104. CLC_CONTRAST_MASK, ctrl->val);
  105. break;
  106. case V4L2_CID_CHROMA_GAIN:
  107. ret = ml86v7667_mask_set(client, ACCRC_REG, ACCRC_CHROMA_MASK,
  108. ctrl->val << ACCRC_CHROMA_SHIFT);
  109. break;
  110. case V4L2_CID_HUE:
  111. ret = ml86v7667_mask_set(client, HUE_REG, ~0, ctrl->val);
  112. break;
  113. case V4L2_CID_RED_BALANCE:
  114. ret = ml86v7667_mask_set(client, ACCC_REG,
  115. ACCC_CHROMA_CR_MASK,
  116. ctrl->val << ACCC_CHROMA_CR_SHIFT);
  117. break;
  118. case V4L2_CID_BLUE_BALANCE:
  119. ret = ml86v7667_mask_set(client, ACCC_REG,
  120. ACCC_CHROMA_CB_MASK,
  121. ctrl->val << ACCC_CHROMA_CB_SHIFT);
  122. break;
  123. case V4L2_CID_SHARPNESS:
  124. ret = ml86v7667_mask_set(client, LUMC_REG,
  125. LUMC_ONOFF_MASK,
  126. ctrl->val << LUMC_ONOFF_SHIFT);
  127. break;
  128. case V4L2_CID_COLOR_KILLER:
  129. ret = ml86v7667_mask_set(client, CHRCA_REG,
  130. CHRCA_MODE_MASK,
  131. ctrl->val << CHRCA_MODE_SHIFT);
  132. break;
  133. }
  134. return ret;
  135. }
  136. static int ml86v7667_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
  137. {
  138. struct i2c_client *client = v4l2_get_subdevdata(sd);
  139. int status;
  140. status = i2c_smbus_read_byte_data(client, STATUS_REG);
  141. if (status < 0)
  142. return status;
  143. if (status & STATUS_HLOCK_DETECT)
  144. *std &= status & STATUS_NTSCPAL ? V4L2_STD_625_50 : V4L2_STD_525_60;
  145. else
  146. *std = V4L2_STD_UNKNOWN;
  147. return 0;
  148. }
  149. static int ml86v7667_g_input_status(struct v4l2_subdev *sd, u32 *status)
  150. {
  151. struct i2c_client *client = v4l2_get_subdevdata(sd);
  152. int status_reg;
  153. status_reg = i2c_smbus_read_byte_data(client, STATUS_REG);
  154. if (status_reg < 0)
  155. return status_reg;
  156. *status = status_reg & STATUS_HLOCK_DETECT ? 0 : V4L2_IN_ST_NO_SIGNAL;
  157. return 0;
  158. }
  159. static int ml86v7667_enum_mbus_code(struct v4l2_subdev *sd,
  160. struct v4l2_subdev_pad_config *cfg,
  161. struct v4l2_subdev_mbus_code_enum *code)
  162. {
  163. if (code->pad || code->index > 0)
  164. return -EINVAL;
  165. code->code = MEDIA_BUS_FMT_YUYV8_2X8;
  166. return 0;
  167. }
  168. static int ml86v7667_fill_fmt(struct v4l2_subdev *sd,
  169. struct v4l2_subdev_pad_config *cfg,
  170. struct v4l2_subdev_format *format)
  171. {
  172. struct ml86v7667_priv *priv = to_ml86v7667(sd);
  173. struct v4l2_mbus_framefmt *fmt = &format->format;
  174. if (format->pad)
  175. return -EINVAL;
  176. fmt->code = MEDIA_BUS_FMT_YUYV8_2X8;
  177. fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
  178. /* The top field is always transferred first by the chip */
  179. fmt->field = V4L2_FIELD_INTERLACED_TB;
  180. fmt->width = 720;
  181. fmt->height = priv->std & V4L2_STD_525_60 ? 480 : 576;
  182. return 0;
  183. }
  184. static int ml86v7667_get_mbus_config(struct v4l2_subdev *sd,
  185. unsigned int pad,
  186. struct v4l2_mbus_config *cfg)
  187. {
  188. cfg->flags = V4L2_MBUS_MASTER | V4L2_MBUS_PCLK_SAMPLE_RISING |
  189. V4L2_MBUS_DATA_ACTIVE_HIGH;
  190. cfg->type = V4L2_MBUS_BT656;
  191. return 0;
  192. }
  193. static int ml86v7667_g_std(struct v4l2_subdev *sd, v4l2_std_id *std)
  194. {
  195. struct ml86v7667_priv *priv = to_ml86v7667(sd);
  196. *std = priv->std;
  197. return 0;
  198. }
  199. static int ml86v7667_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
  200. {
  201. struct ml86v7667_priv *priv = to_ml86v7667(sd);
  202. struct i2c_client *client = v4l2_get_subdevdata(&priv->sd);
  203. int ret;
  204. u8 mode;
  205. /* PAL/NTSC ITU-R BT.601 input mode */
  206. mode = std & V4L2_STD_525_60 ? MRA_NTSC_BT601 : MRA_PAL_BT601;
  207. ret = ml86v7667_mask_set(client, MRA_REG, MRA_INPUT_MODE_MASK, mode);
  208. if (ret < 0)
  209. return ret;
  210. priv->std = std;
  211. return 0;
  212. }
  213. #ifdef CONFIG_VIDEO_ADV_DEBUG
  214. static int ml86v7667_g_register(struct v4l2_subdev *sd,
  215. struct v4l2_dbg_register *reg)
  216. {
  217. struct i2c_client *client = v4l2_get_subdevdata(sd);
  218. int ret;
  219. ret = i2c_smbus_read_byte_data(client, (u8)reg->reg);
  220. if (ret < 0)
  221. return ret;
  222. reg->val = ret;
  223. reg->size = sizeof(u8);
  224. return 0;
  225. }
  226. static int ml86v7667_s_register(struct v4l2_subdev *sd,
  227. const struct v4l2_dbg_register *reg)
  228. {
  229. struct i2c_client *client = v4l2_get_subdevdata(sd);
  230. return i2c_smbus_write_byte_data(client, (u8)reg->reg, (u8)reg->val);
  231. }
  232. #endif
  233. static const struct v4l2_ctrl_ops ml86v7667_ctrl_ops = {
  234. .s_ctrl = ml86v7667_s_ctrl,
  235. };
  236. static const struct v4l2_subdev_video_ops ml86v7667_subdev_video_ops = {
  237. .g_std = ml86v7667_g_std,
  238. .s_std = ml86v7667_s_std,
  239. .querystd = ml86v7667_querystd,
  240. .g_input_status = ml86v7667_g_input_status,
  241. };
  242. static const struct v4l2_subdev_pad_ops ml86v7667_subdev_pad_ops = {
  243. .enum_mbus_code = ml86v7667_enum_mbus_code,
  244. .get_fmt = ml86v7667_fill_fmt,
  245. .set_fmt = ml86v7667_fill_fmt,
  246. .get_mbus_config = ml86v7667_get_mbus_config,
  247. };
  248. static const struct v4l2_subdev_core_ops ml86v7667_subdev_core_ops = {
  249. #ifdef CONFIG_VIDEO_ADV_DEBUG
  250. .g_register = ml86v7667_g_register,
  251. .s_register = ml86v7667_s_register,
  252. #endif
  253. };
  254. static const struct v4l2_subdev_ops ml86v7667_subdev_ops = {
  255. .core = &ml86v7667_subdev_core_ops,
  256. .video = &ml86v7667_subdev_video_ops,
  257. .pad = &ml86v7667_subdev_pad_ops,
  258. };
  259. static int ml86v7667_init(struct ml86v7667_priv *priv)
  260. {
  261. struct i2c_client *client = v4l2_get_subdevdata(&priv->sd);
  262. int val;
  263. int ret;
  264. /* BT.656-4 output mode, register mode */
  265. ret = ml86v7667_mask_set(client, MRA_REG,
  266. MRA_OUTPUT_MODE_MASK | MRA_REGISTER_MODE,
  267. MRA_ITUR_BT656 | MRA_REGISTER_MODE);
  268. /* PLL circuit fixed clock, 32MHz */
  269. ret |= ml86v7667_mask_set(client, PLLR1_REG, PLLR1_FIXED_CLOCK,
  270. PLLR1_FIXED_CLOCK);
  271. /* ADC2 clamping voltage maximum */
  272. ret |= ml86v7667_mask_set(client, ADC2_REG, ADC2_CLAMP_VOLTAGE_MASK,
  273. ADC2_CLAMP_VOLTAGE(7));
  274. /* enable luminance function */
  275. ret |= ml86v7667_mask_set(client, SSEPL_REG, SSEPL_LUMINANCE_ONOFF,
  276. SSEPL_LUMINANCE_ONOFF);
  277. /* enable contrast function */
  278. ret |= ml86v7667_mask_set(client, CLC_REG, CLC_CONTRAST_ONOFF, 0);
  279. /*
  280. * PAL/NTSC autodetection is enabled after reset,
  281. * set the autodetected std in manual std mode and
  282. * disable autodetection
  283. */
  284. val = i2c_smbus_read_byte_data(client, STATUS_REG);
  285. if (val < 0)
  286. return val;
  287. priv->std = val & STATUS_NTSCPAL ? V4L2_STD_625_50 : V4L2_STD_525_60;
  288. ret |= ml86v7667_mask_set(client, MRC_REG, MRC_AUTOSELECT, 0);
  289. val = priv->std & V4L2_STD_525_60 ? MRA_NTSC_BT601 : MRA_PAL_BT601;
  290. ret |= ml86v7667_mask_set(client, MRA_REG, MRA_INPUT_MODE_MASK, val);
  291. return ret;
  292. }
  293. static int ml86v7667_probe(struct i2c_client *client,
  294. const struct i2c_device_id *did)
  295. {
  296. struct ml86v7667_priv *priv;
  297. int ret;
  298. if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
  299. return -EIO;
  300. priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL);
  301. if (!priv)
  302. return -ENOMEM;
  303. v4l2_i2c_subdev_init(&priv->sd, client, &ml86v7667_subdev_ops);
  304. v4l2_ctrl_handler_init(&priv->hdl, 8);
  305. v4l2_ctrl_new_std(&priv->hdl, &ml86v7667_ctrl_ops,
  306. V4L2_CID_BRIGHTNESS, -64, 63, 1, 0);
  307. v4l2_ctrl_new_std(&priv->hdl, &ml86v7667_ctrl_ops,
  308. V4L2_CID_CONTRAST, -8, 7, 1, 0);
  309. v4l2_ctrl_new_std(&priv->hdl, &ml86v7667_ctrl_ops,
  310. V4L2_CID_CHROMA_GAIN, -32, 31, 1, 0);
  311. v4l2_ctrl_new_std(&priv->hdl, &ml86v7667_ctrl_ops,
  312. V4L2_CID_HUE, -128, 127, 1, 0);
  313. v4l2_ctrl_new_std(&priv->hdl, &ml86v7667_ctrl_ops,
  314. V4L2_CID_RED_BALANCE, -4, 3, 1, 0);
  315. v4l2_ctrl_new_std(&priv->hdl, &ml86v7667_ctrl_ops,
  316. V4L2_CID_BLUE_BALANCE, -4, 3, 1, 0);
  317. v4l2_ctrl_new_std(&priv->hdl, &ml86v7667_ctrl_ops,
  318. V4L2_CID_SHARPNESS, 0, 1, 1, 0);
  319. v4l2_ctrl_new_std(&priv->hdl, &ml86v7667_ctrl_ops,
  320. V4L2_CID_COLOR_KILLER, 0, 1, 1, 0);
  321. priv->sd.ctrl_handler = &priv->hdl;
  322. ret = priv->hdl.error;
  323. if (ret)
  324. goto cleanup;
  325. v4l2_ctrl_handler_setup(&priv->hdl);
  326. ret = ml86v7667_init(priv);
  327. if (ret)
  328. goto cleanup;
  329. v4l_info(client, "chip found @ 0x%02x (%s)\n",
  330. client->addr, client->adapter->name);
  331. return 0;
  332. cleanup:
  333. v4l2_ctrl_handler_free(&priv->hdl);
  334. v4l2_device_unregister_subdev(&priv->sd);
  335. v4l_err(client, "failed to probe @ 0x%02x (%s)\n",
  336. client->addr, client->adapter->name);
  337. return ret;
  338. }
  339. static int ml86v7667_remove(struct i2c_client *client)
  340. {
  341. struct v4l2_subdev *sd = i2c_get_clientdata(client);
  342. struct ml86v7667_priv *priv = to_ml86v7667(sd);
  343. v4l2_ctrl_handler_free(&priv->hdl);
  344. v4l2_device_unregister_subdev(&priv->sd);
  345. return 0;
  346. }
  347. static const struct i2c_device_id ml86v7667_id[] = {
  348. {DRV_NAME, 0},
  349. {},
  350. };
  351. MODULE_DEVICE_TABLE(i2c, ml86v7667_id);
  352. static struct i2c_driver ml86v7667_i2c_driver = {
  353. .driver = {
  354. .name = DRV_NAME,
  355. },
  356. .probe = ml86v7667_probe,
  357. .remove = ml86v7667_remove,
  358. .id_table = ml86v7667_id,
  359. };
  360. module_i2c_driver(ml86v7667_i2c_driver);
  361. MODULE_DESCRIPTION("OKI Semiconductor ML86V7667 video decoder driver");
  362. MODULE_AUTHOR("Vladimir Barinov");
  363. MODULE_LICENSE("GPL");