imx355.c 41 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. // Copyright (C) 2018 Intel Corporation
  3. #include <asm/unaligned.h>
  4. #include <linux/acpi.h>
  5. #include <linux/i2c.h>
  6. #include <linux/module.h>
  7. #include <linux/pm_runtime.h>
  8. #include <media/v4l2-ctrls.h>
  9. #include <media/v4l2-device.h>
  10. #include <media/v4l2-event.h>
  11. #include <media/v4l2-fwnode.h>
  12. #define IMX355_REG_MODE_SELECT 0x0100
  13. #define IMX355_MODE_STANDBY 0x00
  14. #define IMX355_MODE_STREAMING 0x01
  15. /* Chip ID */
  16. #define IMX355_REG_CHIP_ID 0x0016
  17. #define IMX355_CHIP_ID 0x0355
  18. /* V_TIMING internal */
  19. #define IMX355_REG_FLL 0x0340
  20. #define IMX355_FLL_MAX 0xffff
  21. /* Exposure control */
  22. #define IMX355_REG_EXPOSURE 0x0202
  23. #define IMX355_EXPOSURE_MIN 1
  24. #define IMX355_EXPOSURE_STEP 1
  25. #define IMX355_EXPOSURE_DEFAULT 0x0282
  26. /* Analog gain control */
  27. #define IMX355_REG_ANALOG_GAIN 0x0204
  28. #define IMX355_ANA_GAIN_MIN 0
  29. #define IMX355_ANA_GAIN_MAX 960
  30. #define IMX355_ANA_GAIN_STEP 1
  31. #define IMX355_ANA_GAIN_DEFAULT 0
  32. /* Digital gain control */
  33. #define IMX355_REG_DPGA_USE_GLOBAL_GAIN 0x3070
  34. #define IMX355_REG_DIG_GAIN_GLOBAL 0x020e
  35. #define IMX355_DGTL_GAIN_MIN 256
  36. #define IMX355_DGTL_GAIN_MAX 4095
  37. #define IMX355_DGTL_GAIN_STEP 1
  38. #define IMX355_DGTL_GAIN_DEFAULT 256
  39. /* Test Pattern Control */
  40. #define IMX355_REG_TEST_PATTERN 0x0600
  41. #define IMX355_TEST_PATTERN_DISABLED 0
  42. #define IMX355_TEST_PATTERN_SOLID_COLOR 1
  43. #define IMX355_TEST_PATTERN_COLOR_BARS 2
  44. #define IMX355_TEST_PATTERN_GRAY_COLOR_BARS 3
  45. #define IMX355_TEST_PATTERN_PN9 4
  46. /* Flip Control */
  47. #define IMX355_REG_ORIENTATION 0x0101
  48. /* default link frequency and external clock */
  49. #define IMX355_LINK_FREQ_DEFAULT 360000000
  50. #define IMX355_EXT_CLK 19200000
  51. #define IMX355_LINK_FREQ_INDEX 0
  52. struct imx355_reg {
  53. u16 address;
  54. u8 val;
  55. };
  56. struct imx355_reg_list {
  57. u32 num_of_regs;
  58. const struct imx355_reg *regs;
  59. };
  60. /* Mode : resolution and related config&values */
  61. struct imx355_mode {
  62. /* Frame width */
  63. u32 width;
  64. /* Frame height */
  65. u32 height;
  66. /* V-timing */
  67. u32 fll_def;
  68. u32 fll_min;
  69. /* H-timing */
  70. u32 llp;
  71. /* index of link frequency */
  72. u32 link_freq_index;
  73. /* Default register values */
  74. struct imx355_reg_list reg_list;
  75. };
  76. struct imx355_hwcfg {
  77. u32 ext_clk; /* sensor external clk */
  78. s64 *link_freqs; /* CSI-2 link frequencies */
  79. unsigned int nr_of_link_freqs;
  80. };
  81. struct imx355 {
  82. struct v4l2_subdev sd;
  83. struct media_pad pad;
  84. struct v4l2_ctrl_handler ctrl_handler;
  85. /* V4L2 Controls */
  86. struct v4l2_ctrl *link_freq;
  87. struct v4l2_ctrl *pixel_rate;
  88. struct v4l2_ctrl *vblank;
  89. struct v4l2_ctrl *hblank;
  90. struct v4l2_ctrl *exposure;
  91. struct v4l2_ctrl *vflip;
  92. struct v4l2_ctrl *hflip;
  93. /* Current mode */
  94. const struct imx355_mode *cur_mode;
  95. struct imx355_hwcfg *hwcfg;
  96. s64 link_def_freq; /* CSI-2 link default frequency */
  97. /*
  98. * Mutex for serialized access:
  99. * Protect sensor set pad format and start/stop streaming safely.
  100. * Protect access to sensor v4l2 controls.
  101. */
  102. struct mutex mutex;
  103. /* Streaming on/off */
  104. bool streaming;
  105. };
  106. static const struct imx355_reg imx355_global_regs[] = {
  107. { 0x0136, 0x13 },
  108. { 0x0137, 0x33 },
  109. { 0x304e, 0x03 },
  110. { 0x4348, 0x16 },
  111. { 0x4350, 0x19 },
  112. { 0x4408, 0x0a },
  113. { 0x440c, 0x0b },
  114. { 0x4411, 0x5f },
  115. { 0x4412, 0x2c },
  116. { 0x4623, 0x00 },
  117. { 0x462c, 0x0f },
  118. { 0x462d, 0x00 },
  119. { 0x462e, 0x00 },
  120. { 0x4684, 0x54 },
  121. { 0x480a, 0x07 },
  122. { 0x4908, 0x07 },
  123. { 0x4909, 0x07 },
  124. { 0x490d, 0x0a },
  125. { 0x491e, 0x0f },
  126. { 0x4921, 0x06 },
  127. { 0x4923, 0x28 },
  128. { 0x4924, 0x28 },
  129. { 0x4925, 0x29 },
  130. { 0x4926, 0x29 },
  131. { 0x4927, 0x1f },
  132. { 0x4928, 0x20 },
  133. { 0x4929, 0x20 },
  134. { 0x492a, 0x20 },
  135. { 0x492c, 0x05 },
  136. { 0x492d, 0x06 },
  137. { 0x492e, 0x06 },
  138. { 0x492f, 0x06 },
  139. { 0x4930, 0x03 },
  140. { 0x4931, 0x04 },
  141. { 0x4932, 0x04 },
  142. { 0x4933, 0x05 },
  143. { 0x595e, 0x01 },
  144. { 0x5963, 0x01 },
  145. { 0x3030, 0x01 },
  146. { 0x3031, 0x01 },
  147. { 0x3045, 0x01 },
  148. { 0x4010, 0x00 },
  149. { 0x4011, 0x00 },
  150. { 0x4012, 0x00 },
  151. { 0x4013, 0x01 },
  152. { 0x68a8, 0xfe },
  153. { 0x68a9, 0xff },
  154. { 0x6888, 0x00 },
  155. { 0x6889, 0x00 },
  156. { 0x68b0, 0x00 },
  157. { 0x3058, 0x00 },
  158. { 0x305a, 0x00 },
  159. };
  160. static const struct imx355_reg_list imx355_global_setting = {
  161. .num_of_regs = ARRAY_SIZE(imx355_global_regs),
  162. .regs = imx355_global_regs,
  163. };
  164. static const struct imx355_reg mode_3268x2448_regs[] = {
  165. { 0x0112, 0x0a },
  166. { 0x0113, 0x0a },
  167. { 0x0114, 0x03 },
  168. { 0x0342, 0x0e },
  169. { 0x0343, 0x58 },
  170. { 0x0340, 0x0a },
  171. { 0x0341, 0x37 },
  172. { 0x0344, 0x00 },
  173. { 0x0345, 0x08 },
  174. { 0x0346, 0x00 },
  175. { 0x0347, 0x08 },
  176. { 0x0348, 0x0c },
  177. { 0x0349, 0xcb },
  178. { 0x034a, 0x09 },
  179. { 0x034b, 0x97 },
  180. { 0x0220, 0x00 },
  181. { 0x0222, 0x01 },
  182. { 0x0900, 0x00 },
  183. { 0x0901, 0x11 },
  184. { 0x0902, 0x00 },
  185. { 0x034c, 0x0c },
  186. { 0x034d, 0xc4 },
  187. { 0x034e, 0x09 },
  188. { 0x034f, 0x90 },
  189. { 0x0301, 0x05 },
  190. { 0x0303, 0x01 },
  191. { 0x0305, 0x02 },
  192. { 0x0306, 0x00 },
  193. { 0x0307, 0x78 },
  194. { 0x030b, 0x01 },
  195. { 0x030d, 0x02 },
  196. { 0x030e, 0x00 },
  197. { 0x030f, 0x4b },
  198. { 0x0310, 0x00 },
  199. { 0x0700, 0x00 },
  200. { 0x0701, 0x10 },
  201. { 0x0820, 0x0b },
  202. { 0x0821, 0x40 },
  203. { 0x3088, 0x04 },
  204. { 0x6813, 0x02 },
  205. { 0x6835, 0x07 },
  206. { 0x6836, 0x01 },
  207. { 0x6837, 0x04 },
  208. { 0x684d, 0x07 },
  209. { 0x684e, 0x01 },
  210. { 0x684f, 0x04 },
  211. };
  212. static const struct imx355_reg mode_3264x2448_regs[] = {
  213. { 0x0112, 0x0a },
  214. { 0x0113, 0x0a },
  215. { 0x0114, 0x03 },
  216. { 0x0342, 0x0e },
  217. { 0x0343, 0x58 },
  218. { 0x0340, 0x0a },
  219. { 0x0341, 0x37 },
  220. { 0x0344, 0x00 },
  221. { 0x0345, 0x08 },
  222. { 0x0346, 0x00 },
  223. { 0x0347, 0x08 },
  224. { 0x0348, 0x0c },
  225. { 0x0349, 0xc7 },
  226. { 0x034a, 0x09 },
  227. { 0x034b, 0x97 },
  228. { 0x0220, 0x00 },
  229. { 0x0222, 0x01 },
  230. { 0x0900, 0x00 },
  231. { 0x0901, 0x11 },
  232. { 0x0902, 0x00 },
  233. { 0x034c, 0x0c },
  234. { 0x034d, 0xc0 },
  235. { 0x034e, 0x09 },
  236. { 0x034f, 0x90 },
  237. { 0x0301, 0x05 },
  238. { 0x0303, 0x01 },
  239. { 0x0305, 0x02 },
  240. { 0x0306, 0x00 },
  241. { 0x0307, 0x78 },
  242. { 0x030b, 0x01 },
  243. { 0x030d, 0x02 },
  244. { 0x030e, 0x00 },
  245. { 0x030f, 0x4b },
  246. { 0x0310, 0x00 },
  247. { 0x0700, 0x00 },
  248. { 0x0701, 0x10 },
  249. { 0x0820, 0x0b },
  250. { 0x0821, 0x40 },
  251. { 0x3088, 0x04 },
  252. { 0x6813, 0x02 },
  253. { 0x6835, 0x07 },
  254. { 0x6836, 0x01 },
  255. { 0x6837, 0x04 },
  256. { 0x684d, 0x07 },
  257. { 0x684e, 0x01 },
  258. { 0x684f, 0x04 },
  259. };
  260. static const struct imx355_reg mode_3280x2464_regs[] = {
  261. { 0x0112, 0x0a },
  262. { 0x0113, 0x0a },
  263. { 0x0114, 0x03 },
  264. { 0x0342, 0x0e },
  265. { 0x0343, 0x58 },
  266. { 0x0340, 0x0a },
  267. { 0x0341, 0x37 },
  268. { 0x0344, 0x00 },
  269. { 0x0345, 0x00 },
  270. { 0x0346, 0x00 },
  271. { 0x0347, 0x00 },
  272. { 0x0348, 0x0c },
  273. { 0x0349, 0xcf },
  274. { 0x034a, 0x09 },
  275. { 0x034b, 0x9f },
  276. { 0x0220, 0x00 },
  277. { 0x0222, 0x01 },
  278. { 0x0900, 0x00 },
  279. { 0x0901, 0x11 },
  280. { 0x0902, 0x00 },
  281. { 0x034c, 0x0c },
  282. { 0x034d, 0xd0 },
  283. { 0x034e, 0x09 },
  284. { 0x034f, 0xa0 },
  285. { 0x0301, 0x05 },
  286. { 0x0303, 0x01 },
  287. { 0x0305, 0x02 },
  288. { 0x0306, 0x00 },
  289. { 0x0307, 0x78 },
  290. { 0x030b, 0x01 },
  291. { 0x030d, 0x02 },
  292. { 0x030e, 0x00 },
  293. { 0x030f, 0x4b },
  294. { 0x0310, 0x00 },
  295. { 0x0700, 0x00 },
  296. { 0x0701, 0x10 },
  297. { 0x0820, 0x0b },
  298. { 0x0821, 0x40 },
  299. { 0x3088, 0x04 },
  300. { 0x6813, 0x02 },
  301. { 0x6835, 0x07 },
  302. { 0x6836, 0x01 },
  303. { 0x6837, 0x04 },
  304. { 0x684d, 0x07 },
  305. { 0x684e, 0x01 },
  306. { 0x684f, 0x04 },
  307. };
  308. static const struct imx355_reg mode_1940x1096_regs[] = {
  309. { 0x0112, 0x0a },
  310. { 0x0113, 0x0a },
  311. { 0x0114, 0x03 },
  312. { 0x0342, 0x0e },
  313. { 0x0343, 0x58 },
  314. { 0x0340, 0x05 },
  315. { 0x0341, 0x1a },
  316. { 0x0344, 0x02 },
  317. { 0x0345, 0xa0 },
  318. { 0x0346, 0x02 },
  319. { 0x0347, 0xac },
  320. { 0x0348, 0x0a },
  321. { 0x0349, 0x33 },
  322. { 0x034a, 0x06 },
  323. { 0x034b, 0xf3 },
  324. { 0x0220, 0x00 },
  325. { 0x0222, 0x01 },
  326. { 0x0900, 0x00 },
  327. { 0x0901, 0x11 },
  328. { 0x0902, 0x00 },
  329. { 0x034c, 0x07 },
  330. { 0x034d, 0x94 },
  331. { 0x034e, 0x04 },
  332. { 0x034f, 0x48 },
  333. { 0x0301, 0x05 },
  334. { 0x0303, 0x01 },
  335. { 0x0305, 0x02 },
  336. { 0x0306, 0x00 },
  337. { 0x0307, 0x78 },
  338. { 0x030b, 0x01 },
  339. { 0x030d, 0x02 },
  340. { 0x030e, 0x00 },
  341. { 0x030f, 0x4b },
  342. { 0x0310, 0x00 },
  343. { 0x0700, 0x00 },
  344. { 0x0701, 0x10 },
  345. { 0x0820, 0x0b },
  346. { 0x0821, 0x40 },
  347. { 0x3088, 0x04 },
  348. { 0x6813, 0x02 },
  349. { 0x6835, 0x07 },
  350. { 0x6836, 0x01 },
  351. { 0x6837, 0x04 },
  352. { 0x684d, 0x07 },
  353. { 0x684e, 0x01 },
  354. { 0x684f, 0x04 },
  355. };
  356. static const struct imx355_reg mode_1936x1096_regs[] = {
  357. { 0x0112, 0x0a },
  358. { 0x0113, 0x0a },
  359. { 0x0114, 0x03 },
  360. { 0x0342, 0x0e },
  361. { 0x0343, 0x58 },
  362. { 0x0340, 0x05 },
  363. { 0x0341, 0x1a },
  364. { 0x0344, 0x02 },
  365. { 0x0345, 0xa0 },
  366. { 0x0346, 0x02 },
  367. { 0x0347, 0xac },
  368. { 0x0348, 0x0a },
  369. { 0x0349, 0x2f },
  370. { 0x034a, 0x06 },
  371. { 0x034b, 0xf3 },
  372. { 0x0220, 0x00 },
  373. { 0x0222, 0x01 },
  374. { 0x0900, 0x00 },
  375. { 0x0901, 0x11 },
  376. { 0x0902, 0x00 },
  377. { 0x034c, 0x07 },
  378. { 0x034d, 0x90 },
  379. { 0x034e, 0x04 },
  380. { 0x034f, 0x48 },
  381. { 0x0301, 0x05 },
  382. { 0x0303, 0x01 },
  383. { 0x0305, 0x02 },
  384. { 0x0306, 0x00 },
  385. { 0x0307, 0x78 },
  386. { 0x030b, 0x01 },
  387. { 0x030d, 0x02 },
  388. { 0x030e, 0x00 },
  389. { 0x030f, 0x4b },
  390. { 0x0310, 0x00 },
  391. { 0x0700, 0x00 },
  392. { 0x0701, 0x10 },
  393. { 0x0820, 0x0b },
  394. { 0x0821, 0x40 },
  395. { 0x3088, 0x04 },
  396. { 0x6813, 0x02 },
  397. { 0x6835, 0x07 },
  398. { 0x6836, 0x01 },
  399. { 0x6837, 0x04 },
  400. { 0x684d, 0x07 },
  401. { 0x684e, 0x01 },
  402. { 0x684f, 0x04 },
  403. };
  404. static const struct imx355_reg mode_1924x1080_regs[] = {
  405. { 0x0112, 0x0a },
  406. { 0x0113, 0x0a },
  407. { 0x0114, 0x03 },
  408. { 0x0342, 0x0e },
  409. { 0x0343, 0x58 },
  410. { 0x0340, 0x05 },
  411. { 0x0341, 0x1a },
  412. { 0x0344, 0x02 },
  413. { 0x0345, 0xa8 },
  414. { 0x0346, 0x02 },
  415. { 0x0347, 0xb4 },
  416. { 0x0348, 0x0a },
  417. { 0x0349, 0x2b },
  418. { 0x034a, 0x06 },
  419. { 0x034b, 0xeb },
  420. { 0x0220, 0x00 },
  421. { 0x0222, 0x01 },
  422. { 0x0900, 0x00 },
  423. { 0x0901, 0x11 },
  424. { 0x0902, 0x00 },
  425. { 0x034c, 0x07 },
  426. { 0x034d, 0x84 },
  427. { 0x034e, 0x04 },
  428. { 0x034f, 0x38 },
  429. { 0x0301, 0x05 },
  430. { 0x0303, 0x01 },
  431. { 0x0305, 0x02 },
  432. { 0x0306, 0x00 },
  433. { 0x0307, 0x78 },
  434. { 0x030b, 0x01 },
  435. { 0x030d, 0x02 },
  436. { 0x030e, 0x00 },
  437. { 0x030f, 0x4b },
  438. { 0x0310, 0x00 },
  439. { 0x0700, 0x00 },
  440. { 0x0701, 0x10 },
  441. { 0x0820, 0x0b },
  442. { 0x0821, 0x40 },
  443. { 0x3088, 0x04 },
  444. { 0x6813, 0x02 },
  445. { 0x6835, 0x07 },
  446. { 0x6836, 0x01 },
  447. { 0x6837, 0x04 },
  448. { 0x684d, 0x07 },
  449. { 0x684e, 0x01 },
  450. { 0x684f, 0x04 },
  451. };
  452. static const struct imx355_reg mode_1920x1080_regs[] = {
  453. { 0x0112, 0x0a },
  454. { 0x0113, 0x0a },
  455. { 0x0114, 0x03 },
  456. { 0x0342, 0x0e },
  457. { 0x0343, 0x58 },
  458. { 0x0340, 0x05 },
  459. { 0x0341, 0x1a },
  460. { 0x0344, 0x02 },
  461. { 0x0345, 0xa8 },
  462. { 0x0346, 0x02 },
  463. { 0x0347, 0xb4 },
  464. { 0x0348, 0x0a },
  465. { 0x0349, 0x27 },
  466. { 0x034a, 0x06 },
  467. { 0x034b, 0xeb },
  468. { 0x0220, 0x00 },
  469. { 0x0222, 0x01 },
  470. { 0x0900, 0x00 },
  471. { 0x0901, 0x11 },
  472. { 0x0902, 0x00 },
  473. { 0x034c, 0x07 },
  474. { 0x034d, 0x80 },
  475. { 0x034e, 0x04 },
  476. { 0x034f, 0x38 },
  477. { 0x0301, 0x05 },
  478. { 0x0303, 0x01 },
  479. { 0x0305, 0x02 },
  480. { 0x0306, 0x00 },
  481. { 0x0307, 0x78 },
  482. { 0x030b, 0x01 },
  483. { 0x030d, 0x02 },
  484. { 0x030e, 0x00 },
  485. { 0x030f, 0x4b },
  486. { 0x0310, 0x00 },
  487. { 0x0700, 0x00 },
  488. { 0x0701, 0x10 },
  489. { 0x0820, 0x0b },
  490. { 0x0821, 0x40 },
  491. { 0x3088, 0x04 },
  492. { 0x6813, 0x02 },
  493. { 0x6835, 0x07 },
  494. { 0x6836, 0x01 },
  495. { 0x6837, 0x04 },
  496. { 0x684d, 0x07 },
  497. { 0x684e, 0x01 },
  498. { 0x684f, 0x04 },
  499. };
  500. static const struct imx355_reg mode_1640x1232_regs[] = {
  501. { 0x0112, 0x0a },
  502. { 0x0113, 0x0a },
  503. { 0x0114, 0x03 },
  504. { 0x0342, 0x07 },
  505. { 0x0343, 0x2c },
  506. { 0x0340, 0x05 },
  507. { 0x0341, 0x1a },
  508. { 0x0344, 0x00 },
  509. { 0x0345, 0x00 },
  510. { 0x0346, 0x00 },
  511. { 0x0347, 0x00 },
  512. { 0x0348, 0x0c },
  513. { 0x0349, 0xcf },
  514. { 0x034a, 0x09 },
  515. { 0x034b, 0x9f },
  516. { 0x0220, 0x00 },
  517. { 0x0222, 0x01 },
  518. { 0x0900, 0x01 },
  519. { 0x0901, 0x22 },
  520. { 0x0902, 0x00 },
  521. { 0x034c, 0x06 },
  522. { 0x034d, 0x68 },
  523. { 0x034e, 0x04 },
  524. { 0x034f, 0xd0 },
  525. { 0x0301, 0x05 },
  526. { 0x0303, 0x01 },
  527. { 0x0305, 0x02 },
  528. { 0x0306, 0x00 },
  529. { 0x0307, 0x78 },
  530. { 0x030b, 0x01 },
  531. { 0x030d, 0x02 },
  532. { 0x030e, 0x00 },
  533. { 0x030f, 0x4b },
  534. { 0x0310, 0x00 },
  535. { 0x0700, 0x00 },
  536. { 0x0701, 0x10 },
  537. { 0x0820, 0x0b },
  538. { 0x0821, 0x40 },
  539. { 0x3088, 0x04 },
  540. { 0x6813, 0x02 },
  541. { 0x6835, 0x07 },
  542. { 0x6836, 0x01 },
  543. { 0x6837, 0x04 },
  544. { 0x684d, 0x07 },
  545. { 0x684e, 0x01 },
  546. { 0x684f, 0x04 },
  547. };
  548. static const struct imx355_reg mode_1640x922_regs[] = {
  549. { 0x0112, 0x0a },
  550. { 0x0113, 0x0a },
  551. { 0x0114, 0x03 },
  552. { 0x0342, 0x07 },
  553. { 0x0343, 0x2c },
  554. { 0x0340, 0x05 },
  555. { 0x0341, 0x1a },
  556. { 0x0344, 0x00 },
  557. { 0x0345, 0x00 },
  558. { 0x0346, 0x01 },
  559. { 0x0347, 0x30 },
  560. { 0x0348, 0x0c },
  561. { 0x0349, 0xcf },
  562. { 0x034a, 0x08 },
  563. { 0x034b, 0x63 },
  564. { 0x0220, 0x00 },
  565. { 0x0222, 0x01 },
  566. { 0x0900, 0x01 },
  567. { 0x0901, 0x22 },
  568. { 0x0902, 0x00 },
  569. { 0x034c, 0x06 },
  570. { 0x034d, 0x68 },
  571. { 0x034e, 0x03 },
  572. { 0x034f, 0x9a },
  573. { 0x0301, 0x05 },
  574. { 0x0303, 0x01 },
  575. { 0x0305, 0x02 },
  576. { 0x0306, 0x00 },
  577. { 0x0307, 0x78 },
  578. { 0x030b, 0x01 },
  579. { 0x030d, 0x02 },
  580. { 0x030e, 0x00 },
  581. { 0x030f, 0x4b },
  582. { 0x0310, 0x00 },
  583. { 0x0700, 0x00 },
  584. { 0x0701, 0x10 },
  585. { 0x0820, 0x0b },
  586. { 0x0821, 0x40 },
  587. { 0x3088, 0x04 },
  588. { 0x6813, 0x02 },
  589. { 0x6835, 0x07 },
  590. { 0x6836, 0x01 },
  591. { 0x6837, 0x04 },
  592. { 0x684d, 0x07 },
  593. { 0x684e, 0x01 },
  594. { 0x684f, 0x04 },
  595. };
  596. static const struct imx355_reg mode_1300x736_regs[] = {
  597. { 0x0112, 0x0a },
  598. { 0x0113, 0x0a },
  599. { 0x0114, 0x03 },
  600. { 0x0342, 0x07 },
  601. { 0x0343, 0x2c },
  602. { 0x0340, 0x05 },
  603. { 0x0341, 0x1a },
  604. { 0x0344, 0x01 },
  605. { 0x0345, 0x58 },
  606. { 0x0346, 0x01 },
  607. { 0x0347, 0xf0 },
  608. { 0x0348, 0x0b },
  609. { 0x0349, 0x7f },
  610. { 0x034a, 0x07 },
  611. { 0x034b, 0xaf },
  612. { 0x0220, 0x00 },
  613. { 0x0222, 0x01 },
  614. { 0x0900, 0x01 },
  615. { 0x0901, 0x22 },
  616. { 0x0902, 0x00 },
  617. { 0x034c, 0x05 },
  618. { 0x034d, 0x14 },
  619. { 0x034e, 0x02 },
  620. { 0x034f, 0xe0 },
  621. { 0x0301, 0x05 },
  622. { 0x0303, 0x01 },
  623. { 0x0305, 0x02 },
  624. { 0x0306, 0x00 },
  625. { 0x0307, 0x78 },
  626. { 0x030b, 0x01 },
  627. { 0x030d, 0x02 },
  628. { 0x030e, 0x00 },
  629. { 0x030f, 0x4b },
  630. { 0x0310, 0x00 },
  631. { 0x0700, 0x00 },
  632. { 0x0701, 0x10 },
  633. { 0x0820, 0x0b },
  634. { 0x0821, 0x40 },
  635. { 0x3088, 0x04 },
  636. { 0x6813, 0x02 },
  637. { 0x6835, 0x07 },
  638. { 0x6836, 0x01 },
  639. { 0x6837, 0x04 },
  640. { 0x684d, 0x07 },
  641. { 0x684e, 0x01 },
  642. { 0x684f, 0x04 },
  643. };
  644. static const struct imx355_reg mode_1296x736_regs[] = {
  645. { 0x0112, 0x0a },
  646. { 0x0113, 0x0a },
  647. { 0x0114, 0x03 },
  648. { 0x0342, 0x07 },
  649. { 0x0343, 0x2c },
  650. { 0x0340, 0x05 },
  651. { 0x0341, 0x1a },
  652. { 0x0344, 0x01 },
  653. { 0x0345, 0x58 },
  654. { 0x0346, 0x01 },
  655. { 0x0347, 0xf0 },
  656. { 0x0348, 0x0b },
  657. { 0x0349, 0x77 },
  658. { 0x034a, 0x07 },
  659. { 0x034b, 0xaf },
  660. { 0x0220, 0x00 },
  661. { 0x0222, 0x01 },
  662. { 0x0900, 0x01 },
  663. { 0x0901, 0x22 },
  664. { 0x0902, 0x00 },
  665. { 0x034c, 0x05 },
  666. { 0x034d, 0x10 },
  667. { 0x034e, 0x02 },
  668. { 0x034f, 0xe0 },
  669. { 0x0301, 0x05 },
  670. { 0x0303, 0x01 },
  671. { 0x0305, 0x02 },
  672. { 0x0306, 0x00 },
  673. { 0x0307, 0x78 },
  674. { 0x030b, 0x01 },
  675. { 0x030d, 0x02 },
  676. { 0x030e, 0x00 },
  677. { 0x030f, 0x4b },
  678. { 0x0310, 0x00 },
  679. { 0x0700, 0x00 },
  680. { 0x0701, 0x10 },
  681. { 0x0820, 0x0b },
  682. { 0x0821, 0x40 },
  683. { 0x3088, 0x04 },
  684. { 0x6813, 0x02 },
  685. { 0x6835, 0x07 },
  686. { 0x6836, 0x01 },
  687. { 0x6837, 0x04 },
  688. { 0x684d, 0x07 },
  689. { 0x684e, 0x01 },
  690. { 0x684f, 0x04 },
  691. };
  692. static const struct imx355_reg mode_1284x720_regs[] = {
  693. { 0x0112, 0x0a },
  694. { 0x0113, 0x0a },
  695. { 0x0114, 0x03 },
  696. { 0x0342, 0x07 },
  697. { 0x0343, 0x2c },
  698. { 0x0340, 0x05 },
  699. { 0x0341, 0x1a },
  700. { 0x0344, 0x01 },
  701. { 0x0345, 0x68 },
  702. { 0x0346, 0x02 },
  703. { 0x0347, 0x00 },
  704. { 0x0348, 0x0b },
  705. { 0x0349, 0x6f },
  706. { 0x034a, 0x07 },
  707. { 0x034b, 0x9f },
  708. { 0x0220, 0x00 },
  709. { 0x0222, 0x01 },
  710. { 0x0900, 0x01 },
  711. { 0x0901, 0x22 },
  712. { 0x0902, 0x00 },
  713. { 0x034c, 0x05 },
  714. { 0x034d, 0x04 },
  715. { 0x034e, 0x02 },
  716. { 0x034f, 0xd0 },
  717. { 0x0301, 0x05 },
  718. { 0x0303, 0x01 },
  719. { 0x0305, 0x02 },
  720. { 0x0306, 0x00 },
  721. { 0x0307, 0x78 },
  722. { 0x030b, 0x01 },
  723. { 0x030d, 0x02 },
  724. { 0x030e, 0x00 },
  725. { 0x030f, 0x4b },
  726. { 0x0310, 0x00 },
  727. { 0x0700, 0x00 },
  728. { 0x0701, 0x10 },
  729. { 0x0820, 0x0b },
  730. { 0x0821, 0x40 },
  731. { 0x3088, 0x04 },
  732. { 0x6813, 0x02 },
  733. { 0x6835, 0x07 },
  734. { 0x6836, 0x01 },
  735. { 0x6837, 0x04 },
  736. { 0x684d, 0x07 },
  737. { 0x684e, 0x01 },
  738. { 0x684f, 0x04 },
  739. };
  740. static const struct imx355_reg mode_1280x720_regs[] = {
  741. { 0x0112, 0x0a },
  742. { 0x0113, 0x0a },
  743. { 0x0114, 0x03 },
  744. { 0x0342, 0x07 },
  745. { 0x0343, 0x2c },
  746. { 0x0340, 0x05 },
  747. { 0x0341, 0x1a },
  748. { 0x0344, 0x01 },
  749. { 0x0345, 0x68 },
  750. { 0x0346, 0x02 },
  751. { 0x0347, 0x00 },
  752. { 0x0348, 0x0b },
  753. { 0x0349, 0x67 },
  754. { 0x034a, 0x07 },
  755. { 0x034b, 0x9f },
  756. { 0x0220, 0x00 },
  757. { 0x0222, 0x01 },
  758. { 0x0900, 0x01 },
  759. { 0x0901, 0x22 },
  760. { 0x0902, 0x00 },
  761. { 0x034c, 0x05 },
  762. { 0x034d, 0x00 },
  763. { 0x034e, 0x02 },
  764. { 0x034f, 0xd0 },
  765. { 0x0301, 0x05 },
  766. { 0x0303, 0x01 },
  767. { 0x0305, 0x02 },
  768. { 0x0306, 0x00 },
  769. { 0x0307, 0x78 },
  770. { 0x030b, 0x01 },
  771. { 0x030d, 0x02 },
  772. { 0x030e, 0x00 },
  773. { 0x030f, 0x4b },
  774. { 0x0310, 0x00 },
  775. { 0x0700, 0x00 },
  776. { 0x0701, 0x10 },
  777. { 0x0820, 0x0b },
  778. { 0x0821, 0x40 },
  779. { 0x3088, 0x04 },
  780. { 0x6813, 0x02 },
  781. { 0x6835, 0x07 },
  782. { 0x6836, 0x01 },
  783. { 0x6837, 0x04 },
  784. { 0x684d, 0x07 },
  785. { 0x684e, 0x01 },
  786. { 0x684f, 0x04 },
  787. };
  788. static const struct imx355_reg mode_820x616_regs[] = {
  789. { 0x0112, 0x0a },
  790. { 0x0113, 0x0a },
  791. { 0x0114, 0x03 },
  792. { 0x0342, 0x0e },
  793. { 0x0343, 0x58 },
  794. { 0x0340, 0x02 },
  795. { 0x0341, 0x8c },
  796. { 0x0344, 0x00 },
  797. { 0x0345, 0x00 },
  798. { 0x0346, 0x00 },
  799. { 0x0347, 0x00 },
  800. { 0x0348, 0x0c },
  801. { 0x0349, 0xcf },
  802. { 0x034a, 0x09 },
  803. { 0x034b, 0x9f },
  804. { 0x0220, 0x00 },
  805. { 0x0222, 0x01 },
  806. { 0x0900, 0x01 },
  807. { 0x0901, 0x44 },
  808. { 0x0902, 0x00 },
  809. { 0x034c, 0x03 },
  810. { 0x034d, 0x34 },
  811. { 0x034e, 0x02 },
  812. { 0x034f, 0x68 },
  813. { 0x0301, 0x05 },
  814. { 0x0303, 0x01 },
  815. { 0x0305, 0x02 },
  816. { 0x0306, 0x00 },
  817. { 0x0307, 0x78 },
  818. { 0x030b, 0x01 },
  819. { 0x030d, 0x02 },
  820. { 0x030e, 0x00 },
  821. { 0x030f, 0x4b },
  822. { 0x0310, 0x00 },
  823. { 0x0700, 0x02 },
  824. { 0x0701, 0x78 },
  825. { 0x0820, 0x0b },
  826. { 0x0821, 0x40 },
  827. { 0x3088, 0x04 },
  828. { 0x6813, 0x02 },
  829. { 0x6835, 0x07 },
  830. { 0x6836, 0x01 },
  831. { 0x6837, 0x04 },
  832. { 0x684d, 0x07 },
  833. { 0x684e, 0x01 },
  834. { 0x684f, 0x04 },
  835. };
  836. static const char * const imx355_test_pattern_menu[] = {
  837. "Disabled",
  838. "Solid Colour",
  839. "Eight Vertical Colour Bars",
  840. "Colour Bars With Fade to Grey",
  841. "Pseudorandom Sequence (PN9)",
  842. };
  843. /* supported link frequencies */
  844. static const s64 link_freq_menu_items[] = {
  845. IMX355_LINK_FREQ_DEFAULT,
  846. };
  847. /* Mode configs */
  848. static const struct imx355_mode supported_modes[] = {
  849. {
  850. .width = 3280,
  851. .height = 2464,
  852. .fll_def = 2615,
  853. .fll_min = 2615,
  854. .llp = 3672,
  855. .link_freq_index = IMX355_LINK_FREQ_INDEX,
  856. .reg_list = {
  857. .num_of_regs = ARRAY_SIZE(mode_3280x2464_regs),
  858. .regs = mode_3280x2464_regs,
  859. },
  860. },
  861. {
  862. .width = 3268,
  863. .height = 2448,
  864. .fll_def = 2615,
  865. .fll_min = 2615,
  866. .llp = 3672,
  867. .link_freq_index = IMX355_LINK_FREQ_INDEX,
  868. .reg_list = {
  869. .num_of_regs = ARRAY_SIZE(mode_3268x2448_regs),
  870. .regs = mode_3268x2448_regs,
  871. },
  872. },
  873. {
  874. .width = 3264,
  875. .height = 2448,
  876. .fll_def = 2615,
  877. .fll_min = 2615,
  878. .llp = 3672,
  879. .link_freq_index = IMX355_LINK_FREQ_INDEX,
  880. .reg_list = {
  881. .num_of_regs = ARRAY_SIZE(mode_3264x2448_regs),
  882. .regs = mode_3264x2448_regs,
  883. },
  884. },
  885. {
  886. .width = 1940,
  887. .height = 1096,
  888. .fll_def = 1306,
  889. .fll_min = 1306,
  890. .llp = 3672,
  891. .link_freq_index = IMX355_LINK_FREQ_INDEX,
  892. .reg_list = {
  893. .num_of_regs = ARRAY_SIZE(mode_1940x1096_regs),
  894. .regs = mode_1940x1096_regs,
  895. },
  896. },
  897. {
  898. .width = 1936,
  899. .height = 1096,
  900. .fll_def = 1306,
  901. .fll_min = 1306,
  902. .llp = 3672,
  903. .link_freq_index = IMX355_LINK_FREQ_INDEX,
  904. .reg_list = {
  905. .num_of_regs = ARRAY_SIZE(mode_1936x1096_regs),
  906. .regs = mode_1936x1096_regs,
  907. },
  908. },
  909. {
  910. .width = 1924,
  911. .height = 1080,
  912. .fll_def = 1306,
  913. .fll_min = 1306,
  914. .llp = 3672,
  915. .link_freq_index = IMX355_LINK_FREQ_INDEX,
  916. .reg_list = {
  917. .num_of_regs = ARRAY_SIZE(mode_1924x1080_regs),
  918. .regs = mode_1924x1080_regs,
  919. },
  920. },
  921. {
  922. .width = 1920,
  923. .height = 1080,
  924. .fll_def = 1306,
  925. .fll_min = 1306,
  926. .llp = 3672,
  927. .link_freq_index = IMX355_LINK_FREQ_INDEX,
  928. .reg_list = {
  929. .num_of_regs = ARRAY_SIZE(mode_1920x1080_regs),
  930. .regs = mode_1920x1080_regs,
  931. },
  932. },
  933. {
  934. .width = 1640,
  935. .height = 1232,
  936. .fll_def = 1306,
  937. .fll_min = 1306,
  938. .llp = 1836,
  939. .link_freq_index = IMX355_LINK_FREQ_INDEX,
  940. .reg_list = {
  941. .num_of_regs = ARRAY_SIZE(mode_1640x1232_regs),
  942. .regs = mode_1640x1232_regs,
  943. },
  944. },
  945. {
  946. .width = 1640,
  947. .height = 922,
  948. .fll_def = 1306,
  949. .fll_min = 1306,
  950. .llp = 1836,
  951. .link_freq_index = IMX355_LINK_FREQ_INDEX,
  952. .reg_list = {
  953. .num_of_regs = ARRAY_SIZE(mode_1640x922_regs),
  954. .regs = mode_1640x922_regs,
  955. },
  956. },
  957. {
  958. .width = 1300,
  959. .height = 736,
  960. .fll_def = 1306,
  961. .fll_min = 1306,
  962. .llp = 1836,
  963. .link_freq_index = IMX355_LINK_FREQ_INDEX,
  964. .reg_list = {
  965. .num_of_regs = ARRAY_SIZE(mode_1300x736_regs),
  966. .regs = mode_1300x736_regs,
  967. },
  968. },
  969. {
  970. .width = 1296,
  971. .height = 736,
  972. .fll_def = 1306,
  973. .fll_min = 1306,
  974. .llp = 1836,
  975. .link_freq_index = IMX355_LINK_FREQ_INDEX,
  976. .reg_list = {
  977. .num_of_regs = ARRAY_SIZE(mode_1296x736_regs),
  978. .regs = mode_1296x736_regs,
  979. },
  980. },
  981. {
  982. .width = 1284,
  983. .height = 720,
  984. .fll_def = 1306,
  985. .fll_min = 1306,
  986. .llp = 1836,
  987. .link_freq_index = IMX355_LINK_FREQ_INDEX,
  988. .reg_list = {
  989. .num_of_regs = ARRAY_SIZE(mode_1284x720_regs),
  990. .regs = mode_1284x720_regs,
  991. },
  992. },
  993. {
  994. .width = 1280,
  995. .height = 720,
  996. .fll_def = 1306,
  997. .fll_min = 1306,
  998. .llp = 1836,
  999. .link_freq_index = IMX355_LINK_FREQ_INDEX,
  1000. .reg_list = {
  1001. .num_of_regs = ARRAY_SIZE(mode_1280x720_regs),
  1002. .regs = mode_1280x720_regs,
  1003. },
  1004. },
  1005. {
  1006. .width = 820,
  1007. .height = 616,
  1008. .fll_def = 652,
  1009. .fll_min = 652,
  1010. .llp = 3672,
  1011. .link_freq_index = IMX355_LINK_FREQ_INDEX,
  1012. .reg_list = {
  1013. .num_of_regs = ARRAY_SIZE(mode_820x616_regs),
  1014. .regs = mode_820x616_regs,
  1015. },
  1016. },
  1017. };
  1018. static inline struct imx355 *to_imx355(struct v4l2_subdev *_sd)
  1019. {
  1020. return container_of(_sd, struct imx355, sd);
  1021. }
  1022. /* Get bayer order based on flip setting. */
  1023. static u32 imx355_get_format_code(struct imx355 *imx355)
  1024. {
  1025. /*
  1026. * Only one bayer order is supported.
  1027. * It depends on the flip settings.
  1028. */
  1029. u32 code;
  1030. static const u32 codes[2][2] = {
  1031. { MEDIA_BUS_FMT_SRGGB10_1X10, MEDIA_BUS_FMT_SGRBG10_1X10, },
  1032. { MEDIA_BUS_FMT_SGBRG10_1X10, MEDIA_BUS_FMT_SBGGR10_1X10, },
  1033. };
  1034. lockdep_assert_held(&imx355->mutex);
  1035. code = codes[imx355->vflip->val][imx355->hflip->val];
  1036. return code;
  1037. }
  1038. /* Read registers up to 4 at a time */
  1039. static int imx355_read_reg(struct imx355 *imx355, u16 reg, u32 len, u32 *val)
  1040. {
  1041. struct i2c_client *client = v4l2_get_subdevdata(&imx355->sd);
  1042. struct i2c_msg msgs[2];
  1043. u8 addr_buf[2];
  1044. u8 data_buf[4] = { 0 };
  1045. int ret;
  1046. if (len > 4)
  1047. return -EINVAL;
  1048. put_unaligned_be16(reg, addr_buf);
  1049. /* Write register address */
  1050. msgs[0].addr = client->addr;
  1051. msgs[0].flags = 0;
  1052. msgs[0].len = ARRAY_SIZE(addr_buf);
  1053. msgs[0].buf = addr_buf;
  1054. /* Read data from register */
  1055. msgs[1].addr = client->addr;
  1056. msgs[1].flags = I2C_M_RD;
  1057. msgs[1].len = len;
  1058. msgs[1].buf = &data_buf[4 - len];
  1059. ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
  1060. if (ret != ARRAY_SIZE(msgs))
  1061. return -EIO;
  1062. *val = get_unaligned_be32(data_buf);
  1063. return 0;
  1064. }
  1065. /* Write registers up to 4 at a time */
  1066. static int imx355_write_reg(struct imx355 *imx355, u16 reg, u32 len, u32 val)
  1067. {
  1068. struct i2c_client *client = v4l2_get_subdevdata(&imx355->sd);
  1069. u8 buf[6];
  1070. if (len > 4)
  1071. return -EINVAL;
  1072. put_unaligned_be16(reg, buf);
  1073. put_unaligned_be32(val << (8 * (4 - len)), buf + 2);
  1074. if (i2c_master_send(client, buf, len + 2) != len + 2)
  1075. return -EIO;
  1076. return 0;
  1077. }
  1078. /* Write a list of registers */
  1079. static int imx355_write_regs(struct imx355 *imx355,
  1080. const struct imx355_reg *regs, u32 len)
  1081. {
  1082. struct i2c_client *client = v4l2_get_subdevdata(&imx355->sd);
  1083. int ret;
  1084. u32 i;
  1085. for (i = 0; i < len; i++) {
  1086. ret = imx355_write_reg(imx355, regs[i].address, 1, regs[i].val);
  1087. if (ret) {
  1088. dev_err_ratelimited(&client->dev,
  1089. "write reg 0x%4.4x return err %d",
  1090. regs[i].address, ret);
  1091. return ret;
  1092. }
  1093. }
  1094. return 0;
  1095. }
  1096. /* Open sub-device */
  1097. static int imx355_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
  1098. {
  1099. struct imx355 *imx355 = to_imx355(sd);
  1100. struct v4l2_mbus_framefmt *try_fmt =
  1101. v4l2_subdev_get_try_format(sd, fh->pad, 0);
  1102. mutex_lock(&imx355->mutex);
  1103. /* Initialize try_fmt */
  1104. try_fmt->width = imx355->cur_mode->width;
  1105. try_fmt->height = imx355->cur_mode->height;
  1106. try_fmt->code = imx355_get_format_code(imx355);
  1107. try_fmt->field = V4L2_FIELD_NONE;
  1108. mutex_unlock(&imx355->mutex);
  1109. return 0;
  1110. }
  1111. static int imx355_set_ctrl(struct v4l2_ctrl *ctrl)
  1112. {
  1113. struct imx355 *imx355 = container_of(ctrl->handler,
  1114. struct imx355, ctrl_handler);
  1115. struct i2c_client *client = v4l2_get_subdevdata(&imx355->sd);
  1116. s64 max;
  1117. int ret;
  1118. /* Propagate change of current control to all related controls */
  1119. switch (ctrl->id) {
  1120. case V4L2_CID_VBLANK:
  1121. /* Update max exposure while meeting expected vblanking */
  1122. max = imx355->cur_mode->height + ctrl->val - 10;
  1123. __v4l2_ctrl_modify_range(imx355->exposure,
  1124. imx355->exposure->minimum,
  1125. max, imx355->exposure->step, max);
  1126. break;
  1127. }
  1128. /*
  1129. * Applying V4L2 control value only happens
  1130. * when power is up for streaming
  1131. */
  1132. if (!pm_runtime_get_if_in_use(&client->dev))
  1133. return 0;
  1134. switch (ctrl->id) {
  1135. case V4L2_CID_ANALOGUE_GAIN:
  1136. /* Analog gain = 1024/(1024 - ctrl->val) times */
  1137. ret = imx355_write_reg(imx355, IMX355_REG_ANALOG_GAIN, 2,
  1138. ctrl->val);
  1139. break;
  1140. case V4L2_CID_DIGITAL_GAIN:
  1141. ret = imx355_write_reg(imx355, IMX355_REG_DIG_GAIN_GLOBAL, 2,
  1142. ctrl->val);
  1143. break;
  1144. case V4L2_CID_EXPOSURE:
  1145. ret = imx355_write_reg(imx355, IMX355_REG_EXPOSURE, 2,
  1146. ctrl->val);
  1147. break;
  1148. case V4L2_CID_VBLANK:
  1149. /* Update FLL that meets expected vertical blanking */
  1150. ret = imx355_write_reg(imx355, IMX355_REG_FLL, 2,
  1151. imx355->cur_mode->height + ctrl->val);
  1152. break;
  1153. case V4L2_CID_TEST_PATTERN:
  1154. ret = imx355_write_reg(imx355, IMX355_REG_TEST_PATTERN,
  1155. 2, ctrl->val);
  1156. break;
  1157. case V4L2_CID_HFLIP:
  1158. case V4L2_CID_VFLIP:
  1159. ret = imx355_write_reg(imx355, IMX355_REG_ORIENTATION, 1,
  1160. imx355->hflip->val |
  1161. imx355->vflip->val << 1);
  1162. break;
  1163. default:
  1164. ret = -EINVAL;
  1165. dev_info(&client->dev, "ctrl(id:0x%x,val:0x%x) is not handled",
  1166. ctrl->id, ctrl->val);
  1167. break;
  1168. }
  1169. pm_runtime_put(&client->dev);
  1170. return ret;
  1171. }
  1172. static const struct v4l2_ctrl_ops imx355_ctrl_ops = {
  1173. .s_ctrl = imx355_set_ctrl,
  1174. };
  1175. static int imx355_enum_mbus_code(struct v4l2_subdev *sd,
  1176. struct v4l2_subdev_pad_config *cfg,
  1177. struct v4l2_subdev_mbus_code_enum *code)
  1178. {
  1179. struct imx355 *imx355 = to_imx355(sd);
  1180. if (code->index > 0)
  1181. return -EINVAL;
  1182. mutex_lock(&imx355->mutex);
  1183. code->code = imx355_get_format_code(imx355);
  1184. mutex_unlock(&imx355->mutex);
  1185. return 0;
  1186. }
  1187. static int imx355_enum_frame_size(struct v4l2_subdev *sd,
  1188. struct v4l2_subdev_pad_config *cfg,
  1189. struct v4l2_subdev_frame_size_enum *fse)
  1190. {
  1191. struct imx355 *imx355 = to_imx355(sd);
  1192. if (fse->index >= ARRAY_SIZE(supported_modes))
  1193. return -EINVAL;
  1194. mutex_lock(&imx355->mutex);
  1195. if (fse->code != imx355_get_format_code(imx355)) {
  1196. mutex_unlock(&imx355->mutex);
  1197. return -EINVAL;
  1198. }
  1199. mutex_unlock(&imx355->mutex);
  1200. fse->min_width = supported_modes[fse->index].width;
  1201. fse->max_width = fse->min_width;
  1202. fse->min_height = supported_modes[fse->index].height;
  1203. fse->max_height = fse->min_height;
  1204. return 0;
  1205. }
  1206. static void imx355_update_pad_format(struct imx355 *imx355,
  1207. const struct imx355_mode *mode,
  1208. struct v4l2_subdev_format *fmt)
  1209. {
  1210. fmt->format.width = mode->width;
  1211. fmt->format.height = mode->height;
  1212. fmt->format.code = imx355_get_format_code(imx355);
  1213. fmt->format.field = V4L2_FIELD_NONE;
  1214. }
  1215. static int imx355_do_get_pad_format(struct imx355 *imx355,
  1216. struct v4l2_subdev_pad_config *cfg,
  1217. struct v4l2_subdev_format *fmt)
  1218. {
  1219. struct v4l2_mbus_framefmt *framefmt;
  1220. struct v4l2_subdev *sd = &imx355->sd;
  1221. if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
  1222. framefmt = v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
  1223. fmt->format = *framefmt;
  1224. } else {
  1225. imx355_update_pad_format(imx355, imx355->cur_mode, fmt);
  1226. }
  1227. return 0;
  1228. }
  1229. static int imx355_get_pad_format(struct v4l2_subdev *sd,
  1230. struct v4l2_subdev_pad_config *cfg,
  1231. struct v4l2_subdev_format *fmt)
  1232. {
  1233. struct imx355 *imx355 = to_imx355(sd);
  1234. int ret;
  1235. mutex_lock(&imx355->mutex);
  1236. ret = imx355_do_get_pad_format(imx355, cfg, fmt);
  1237. mutex_unlock(&imx355->mutex);
  1238. return ret;
  1239. }
  1240. static int
  1241. imx355_set_pad_format(struct v4l2_subdev *sd,
  1242. struct v4l2_subdev_pad_config *cfg,
  1243. struct v4l2_subdev_format *fmt)
  1244. {
  1245. struct imx355 *imx355 = to_imx355(sd);
  1246. const struct imx355_mode *mode;
  1247. struct v4l2_mbus_framefmt *framefmt;
  1248. s32 vblank_def;
  1249. s32 vblank_min;
  1250. s64 h_blank;
  1251. u64 pixel_rate;
  1252. u32 height;
  1253. mutex_lock(&imx355->mutex);
  1254. /*
  1255. * Only one bayer order is supported.
  1256. * It depends on the flip settings.
  1257. */
  1258. fmt->format.code = imx355_get_format_code(imx355);
  1259. mode = v4l2_find_nearest_size(supported_modes,
  1260. ARRAY_SIZE(supported_modes),
  1261. width, height,
  1262. fmt->format.width, fmt->format.height);
  1263. imx355_update_pad_format(imx355, mode, fmt);
  1264. if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
  1265. framefmt = v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
  1266. *framefmt = fmt->format;
  1267. } else {
  1268. imx355->cur_mode = mode;
  1269. pixel_rate = imx355->link_def_freq * 2 * 4;
  1270. do_div(pixel_rate, 10);
  1271. __v4l2_ctrl_s_ctrl_int64(imx355->pixel_rate, pixel_rate);
  1272. /* Update limits and set FPS to default */
  1273. height = imx355->cur_mode->height;
  1274. vblank_def = imx355->cur_mode->fll_def - height;
  1275. vblank_min = imx355->cur_mode->fll_min - height;
  1276. height = IMX355_FLL_MAX - height;
  1277. __v4l2_ctrl_modify_range(imx355->vblank, vblank_min, height, 1,
  1278. vblank_def);
  1279. __v4l2_ctrl_s_ctrl(imx355->vblank, vblank_def);
  1280. h_blank = mode->llp - imx355->cur_mode->width;
  1281. /*
  1282. * Currently hblank is not changeable.
  1283. * So FPS control is done only by vblank.
  1284. */
  1285. __v4l2_ctrl_modify_range(imx355->hblank, h_blank,
  1286. h_blank, 1, h_blank);
  1287. }
  1288. mutex_unlock(&imx355->mutex);
  1289. return 0;
  1290. }
  1291. /* Start streaming */
  1292. static int imx355_start_streaming(struct imx355 *imx355)
  1293. {
  1294. struct i2c_client *client = v4l2_get_subdevdata(&imx355->sd);
  1295. const struct imx355_reg_list *reg_list;
  1296. int ret;
  1297. /* Global Setting */
  1298. reg_list = &imx355_global_setting;
  1299. ret = imx355_write_regs(imx355, reg_list->regs, reg_list->num_of_regs);
  1300. if (ret) {
  1301. dev_err(&client->dev, "failed to set global settings");
  1302. return ret;
  1303. }
  1304. /* Apply default values of current mode */
  1305. reg_list = &imx355->cur_mode->reg_list;
  1306. ret = imx355_write_regs(imx355, reg_list->regs, reg_list->num_of_regs);
  1307. if (ret) {
  1308. dev_err(&client->dev, "failed to set mode");
  1309. return ret;
  1310. }
  1311. /* set digital gain control to all color mode */
  1312. ret = imx355_write_reg(imx355, IMX355_REG_DPGA_USE_GLOBAL_GAIN, 1, 1);
  1313. if (ret)
  1314. return ret;
  1315. /* Apply customized values from user */
  1316. ret = __v4l2_ctrl_handler_setup(imx355->sd.ctrl_handler);
  1317. if (ret)
  1318. return ret;
  1319. return imx355_write_reg(imx355, IMX355_REG_MODE_SELECT,
  1320. 1, IMX355_MODE_STREAMING);
  1321. }
  1322. /* Stop streaming */
  1323. static int imx355_stop_streaming(struct imx355 *imx355)
  1324. {
  1325. return imx355_write_reg(imx355, IMX355_REG_MODE_SELECT,
  1326. 1, IMX355_MODE_STANDBY);
  1327. }
  1328. static int imx355_set_stream(struct v4l2_subdev *sd, int enable)
  1329. {
  1330. struct imx355 *imx355 = to_imx355(sd);
  1331. struct i2c_client *client = v4l2_get_subdevdata(sd);
  1332. int ret = 0;
  1333. mutex_lock(&imx355->mutex);
  1334. if (imx355->streaming == enable) {
  1335. mutex_unlock(&imx355->mutex);
  1336. return 0;
  1337. }
  1338. if (enable) {
  1339. ret = pm_runtime_get_sync(&client->dev);
  1340. if (ret < 0) {
  1341. pm_runtime_put_noidle(&client->dev);
  1342. goto err_unlock;
  1343. }
  1344. /*
  1345. * Apply default & customized values
  1346. * and then start streaming.
  1347. */
  1348. ret = imx355_start_streaming(imx355);
  1349. if (ret)
  1350. goto err_rpm_put;
  1351. } else {
  1352. imx355_stop_streaming(imx355);
  1353. pm_runtime_put(&client->dev);
  1354. }
  1355. imx355->streaming = enable;
  1356. /* vflip and hflip cannot change during streaming */
  1357. __v4l2_ctrl_grab(imx355->vflip, enable);
  1358. __v4l2_ctrl_grab(imx355->hflip, enable);
  1359. mutex_unlock(&imx355->mutex);
  1360. return ret;
  1361. err_rpm_put:
  1362. pm_runtime_put(&client->dev);
  1363. err_unlock:
  1364. mutex_unlock(&imx355->mutex);
  1365. return ret;
  1366. }
  1367. static int __maybe_unused imx355_suspend(struct device *dev)
  1368. {
  1369. struct i2c_client *client = to_i2c_client(dev);
  1370. struct v4l2_subdev *sd = i2c_get_clientdata(client);
  1371. struct imx355 *imx355 = to_imx355(sd);
  1372. if (imx355->streaming)
  1373. imx355_stop_streaming(imx355);
  1374. return 0;
  1375. }
  1376. static int __maybe_unused imx355_resume(struct device *dev)
  1377. {
  1378. struct i2c_client *client = to_i2c_client(dev);
  1379. struct v4l2_subdev *sd = i2c_get_clientdata(client);
  1380. struct imx355 *imx355 = to_imx355(sd);
  1381. int ret;
  1382. if (imx355->streaming) {
  1383. ret = imx355_start_streaming(imx355);
  1384. if (ret)
  1385. goto error;
  1386. }
  1387. return 0;
  1388. error:
  1389. imx355_stop_streaming(imx355);
  1390. imx355->streaming = 0;
  1391. return ret;
  1392. }
  1393. /* Verify chip ID */
  1394. static int imx355_identify_module(struct imx355 *imx355)
  1395. {
  1396. struct i2c_client *client = v4l2_get_subdevdata(&imx355->sd);
  1397. int ret;
  1398. u32 val;
  1399. ret = imx355_read_reg(imx355, IMX355_REG_CHIP_ID, 2, &val);
  1400. if (ret)
  1401. return ret;
  1402. if (val != IMX355_CHIP_ID) {
  1403. dev_err(&client->dev, "chip id mismatch: %x!=%x",
  1404. IMX355_CHIP_ID, val);
  1405. return -EIO;
  1406. }
  1407. return 0;
  1408. }
  1409. static const struct v4l2_subdev_core_ops imx355_subdev_core_ops = {
  1410. .subscribe_event = v4l2_ctrl_subdev_subscribe_event,
  1411. .unsubscribe_event = v4l2_event_subdev_unsubscribe,
  1412. };
  1413. static const struct v4l2_subdev_video_ops imx355_video_ops = {
  1414. .s_stream = imx355_set_stream,
  1415. };
  1416. static const struct v4l2_subdev_pad_ops imx355_pad_ops = {
  1417. .enum_mbus_code = imx355_enum_mbus_code,
  1418. .get_fmt = imx355_get_pad_format,
  1419. .set_fmt = imx355_set_pad_format,
  1420. .enum_frame_size = imx355_enum_frame_size,
  1421. };
  1422. static const struct v4l2_subdev_ops imx355_subdev_ops = {
  1423. .core = &imx355_subdev_core_ops,
  1424. .video = &imx355_video_ops,
  1425. .pad = &imx355_pad_ops,
  1426. };
  1427. static const struct media_entity_operations imx355_subdev_entity_ops = {
  1428. .link_validate = v4l2_subdev_link_validate,
  1429. };
  1430. static const struct v4l2_subdev_internal_ops imx355_internal_ops = {
  1431. .open = imx355_open,
  1432. };
  1433. /* Initialize control handlers */
  1434. static int imx355_init_controls(struct imx355 *imx355)
  1435. {
  1436. struct i2c_client *client = v4l2_get_subdevdata(&imx355->sd);
  1437. struct v4l2_ctrl_handler *ctrl_hdlr;
  1438. s64 exposure_max;
  1439. s64 vblank_def;
  1440. s64 vblank_min;
  1441. s64 hblank;
  1442. u64 pixel_rate;
  1443. const struct imx355_mode *mode;
  1444. u32 max;
  1445. int ret;
  1446. ctrl_hdlr = &imx355->ctrl_handler;
  1447. ret = v4l2_ctrl_handler_init(ctrl_hdlr, 10);
  1448. if (ret)
  1449. return ret;
  1450. ctrl_hdlr->lock = &imx355->mutex;
  1451. max = ARRAY_SIZE(link_freq_menu_items) - 1;
  1452. imx355->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, &imx355_ctrl_ops,
  1453. V4L2_CID_LINK_FREQ, max, 0,
  1454. link_freq_menu_items);
  1455. if (imx355->link_freq)
  1456. imx355->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
  1457. /* pixel_rate = link_freq * 2 * nr_of_lanes / bits_per_sample */
  1458. pixel_rate = imx355->link_def_freq * 2 * 4;
  1459. do_div(pixel_rate, 10);
  1460. /* By default, PIXEL_RATE is read only */
  1461. imx355->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &imx355_ctrl_ops,
  1462. V4L2_CID_PIXEL_RATE, pixel_rate,
  1463. pixel_rate, 1, pixel_rate);
  1464. /* Initialize vblank/hblank/exposure parameters based on current mode */
  1465. mode = imx355->cur_mode;
  1466. vblank_def = mode->fll_def - mode->height;
  1467. vblank_min = mode->fll_min - mode->height;
  1468. imx355->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &imx355_ctrl_ops,
  1469. V4L2_CID_VBLANK, vblank_min,
  1470. IMX355_FLL_MAX - mode->height,
  1471. 1, vblank_def);
  1472. hblank = mode->llp - mode->width;
  1473. imx355->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &imx355_ctrl_ops,
  1474. V4L2_CID_HBLANK, hblank, hblank,
  1475. 1, hblank);
  1476. if (imx355->hblank)
  1477. imx355->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
  1478. /* fll >= exposure time + adjust parameter (default value is 10) */
  1479. exposure_max = mode->fll_def - 10;
  1480. imx355->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &imx355_ctrl_ops,
  1481. V4L2_CID_EXPOSURE,
  1482. IMX355_EXPOSURE_MIN, exposure_max,
  1483. IMX355_EXPOSURE_STEP,
  1484. IMX355_EXPOSURE_DEFAULT);
  1485. imx355->hflip = v4l2_ctrl_new_std(ctrl_hdlr, &imx355_ctrl_ops,
  1486. V4L2_CID_HFLIP, 0, 1, 1, 0);
  1487. imx355->vflip = v4l2_ctrl_new_std(ctrl_hdlr, &imx355_ctrl_ops,
  1488. V4L2_CID_VFLIP, 0, 1, 1, 0);
  1489. v4l2_ctrl_new_std(ctrl_hdlr, &imx355_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
  1490. IMX355_ANA_GAIN_MIN, IMX355_ANA_GAIN_MAX,
  1491. IMX355_ANA_GAIN_STEP, IMX355_ANA_GAIN_DEFAULT);
  1492. /* Digital gain */
  1493. v4l2_ctrl_new_std(ctrl_hdlr, &imx355_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
  1494. IMX355_DGTL_GAIN_MIN, IMX355_DGTL_GAIN_MAX,
  1495. IMX355_DGTL_GAIN_STEP, IMX355_DGTL_GAIN_DEFAULT);
  1496. v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &imx355_ctrl_ops,
  1497. V4L2_CID_TEST_PATTERN,
  1498. ARRAY_SIZE(imx355_test_pattern_menu) - 1,
  1499. 0, 0, imx355_test_pattern_menu);
  1500. if (ctrl_hdlr->error) {
  1501. ret = ctrl_hdlr->error;
  1502. dev_err(&client->dev, "control init failed: %d", ret);
  1503. goto error;
  1504. }
  1505. imx355->sd.ctrl_handler = ctrl_hdlr;
  1506. return 0;
  1507. error:
  1508. v4l2_ctrl_handler_free(ctrl_hdlr);
  1509. return ret;
  1510. }
  1511. static struct imx355_hwcfg *imx355_get_hwcfg(struct device *dev)
  1512. {
  1513. struct imx355_hwcfg *cfg;
  1514. struct v4l2_fwnode_endpoint bus_cfg = {
  1515. .bus_type = V4L2_MBUS_CSI2_DPHY
  1516. };
  1517. struct fwnode_handle *ep;
  1518. struct fwnode_handle *fwnode = dev_fwnode(dev);
  1519. unsigned int i;
  1520. int ret;
  1521. if (!fwnode)
  1522. return NULL;
  1523. ep = fwnode_graph_get_next_endpoint(fwnode, NULL);
  1524. if (!ep)
  1525. return NULL;
  1526. ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
  1527. if (ret)
  1528. goto out_err;
  1529. cfg = devm_kzalloc(dev, sizeof(*cfg), GFP_KERNEL);
  1530. if (!cfg)
  1531. goto out_err;
  1532. ret = fwnode_property_read_u32(dev_fwnode(dev), "clock-frequency",
  1533. &cfg->ext_clk);
  1534. if (ret) {
  1535. dev_err(dev, "can't get clock frequency");
  1536. goto out_err;
  1537. }
  1538. dev_dbg(dev, "ext clk: %d", cfg->ext_clk);
  1539. if (cfg->ext_clk != IMX355_EXT_CLK) {
  1540. dev_err(dev, "external clock %d is not supported",
  1541. cfg->ext_clk);
  1542. goto out_err;
  1543. }
  1544. dev_dbg(dev, "num of link freqs: %d", bus_cfg.nr_of_link_frequencies);
  1545. if (!bus_cfg.nr_of_link_frequencies) {
  1546. dev_warn(dev, "no link frequencies defined");
  1547. goto out_err;
  1548. }
  1549. cfg->nr_of_link_freqs = bus_cfg.nr_of_link_frequencies;
  1550. cfg->link_freqs = devm_kcalloc(dev,
  1551. bus_cfg.nr_of_link_frequencies + 1,
  1552. sizeof(*cfg->link_freqs), GFP_KERNEL);
  1553. if (!cfg->link_freqs)
  1554. goto out_err;
  1555. for (i = 0; i < bus_cfg.nr_of_link_frequencies; i++) {
  1556. cfg->link_freqs[i] = bus_cfg.link_frequencies[i];
  1557. dev_dbg(dev, "link_freq[%d] = %lld", i, cfg->link_freqs[i]);
  1558. }
  1559. v4l2_fwnode_endpoint_free(&bus_cfg);
  1560. fwnode_handle_put(ep);
  1561. return cfg;
  1562. out_err:
  1563. v4l2_fwnode_endpoint_free(&bus_cfg);
  1564. fwnode_handle_put(ep);
  1565. return NULL;
  1566. }
  1567. static int imx355_probe(struct i2c_client *client)
  1568. {
  1569. struct imx355 *imx355;
  1570. int ret;
  1571. u32 i;
  1572. imx355 = devm_kzalloc(&client->dev, sizeof(*imx355), GFP_KERNEL);
  1573. if (!imx355)
  1574. return -ENOMEM;
  1575. mutex_init(&imx355->mutex);
  1576. /* Initialize subdev */
  1577. v4l2_i2c_subdev_init(&imx355->sd, client, &imx355_subdev_ops);
  1578. /* Check module identity */
  1579. ret = imx355_identify_module(imx355);
  1580. if (ret) {
  1581. dev_err(&client->dev, "failed to find sensor: %d", ret);
  1582. goto error_probe;
  1583. }
  1584. imx355->hwcfg = imx355_get_hwcfg(&client->dev);
  1585. if (!imx355->hwcfg) {
  1586. dev_err(&client->dev, "failed to get hwcfg");
  1587. ret = -ENODEV;
  1588. goto error_probe;
  1589. }
  1590. imx355->link_def_freq = link_freq_menu_items[IMX355_LINK_FREQ_INDEX];
  1591. for (i = 0; i < imx355->hwcfg->nr_of_link_freqs; i++) {
  1592. if (imx355->hwcfg->link_freqs[i] == imx355->link_def_freq) {
  1593. dev_dbg(&client->dev, "link freq index %d matched", i);
  1594. break;
  1595. }
  1596. }
  1597. if (i == imx355->hwcfg->nr_of_link_freqs) {
  1598. dev_err(&client->dev, "no link frequency supported");
  1599. ret = -EINVAL;
  1600. goto error_probe;
  1601. }
  1602. /* Set default mode to max resolution */
  1603. imx355->cur_mode = &supported_modes[0];
  1604. ret = imx355_init_controls(imx355);
  1605. if (ret) {
  1606. dev_err(&client->dev, "failed to init controls: %d", ret);
  1607. goto error_probe;
  1608. }
  1609. /* Initialize subdev */
  1610. imx355->sd.internal_ops = &imx355_internal_ops;
  1611. imx355->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
  1612. V4L2_SUBDEV_FL_HAS_EVENTS;
  1613. imx355->sd.entity.ops = &imx355_subdev_entity_ops;
  1614. imx355->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
  1615. /* Initialize source pad */
  1616. imx355->pad.flags = MEDIA_PAD_FL_SOURCE;
  1617. ret = media_entity_pads_init(&imx355->sd.entity, 1, &imx355->pad);
  1618. if (ret) {
  1619. dev_err(&client->dev, "failed to init entity pads: %d", ret);
  1620. goto error_handler_free;
  1621. }
  1622. ret = v4l2_async_register_subdev_sensor_common(&imx355->sd);
  1623. if (ret < 0)
  1624. goto error_media_entity;
  1625. /*
  1626. * Device is already turned on by i2c-core with ACPI domain PM.
  1627. * Enable runtime PM and turn off the device.
  1628. */
  1629. pm_runtime_set_active(&client->dev);
  1630. pm_runtime_enable(&client->dev);
  1631. pm_runtime_idle(&client->dev);
  1632. return 0;
  1633. error_media_entity:
  1634. media_entity_cleanup(&imx355->sd.entity);
  1635. error_handler_free:
  1636. v4l2_ctrl_handler_free(imx355->sd.ctrl_handler);
  1637. error_probe:
  1638. mutex_destroy(&imx355->mutex);
  1639. return ret;
  1640. }
  1641. static int imx355_remove(struct i2c_client *client)
  1642. {
  1643. struct v4l2_subdev *sd = i2c_get_clientdata(client);
  1644. struct imx355 *imx355 = to_imx355(sd);
  1645. v4l2_async_unregister_subdev(sd);
  1646. media_entity_cleanup(&sd->entity);
  1647. v4l2_ctrl_handler_free(sd->ctrl_handler);
  1648. pm_runtime_disable(&client->dev);
  1649. pm_runtime_set_suspended(&client->dev);
  1650. mutex_destroy(&imx355->mutex);
  1651. return 0;
  1652. }
  1653. static const struct dev_pm_ops imx355_pm_ops = {
  1654. SET_SYSTEM_SLEEP_PM_OPS(imx355_suspend, imx355_resume)
  1655. };
  1656. static const struct acpi_device_id imx355_acpi_ids[] = {
  1657. { "SONY355A" },
  1658. { /* sentinel */ }
  1659. };
  1660. MODULE_DEVICE_TABLE(acpi, imx355_acpi_ids);
  1661. static struct i2c_driver imx355_i2c_driver = {
  1662. .driver = {
  1663. .name = "imx355",
  1664. .pm = &imx355_pm_ops,
  1665. .acpi_match_table = ACPI_PTR(imx355_acpi_ids),
  1666. },
  1667. .probe_new = imx355_probe,
  1668. .remove = imx355_remove,
  1669. };
  1670. module_i2c_driver(imx355_i2c_driver);
  1671. MODULE_AUTHOR("Qiu, Tianshu <tian.shu.qiu@intel.com>");
  1672. MODULE_AUTHOR("Rapolu, Chiranjeevi <chiranjeevi.rapolu@intel.com>");
  1673. MODULE_AUTHOR("Bingbu Cao <bingbu.cao@intel.com>");
  1674. MODULE_AUTHOR("Yang, Hyungwoo <hyungwoo.yang@intel.com>");
  1675. MODULE_DESCRIPTION("Sony imx355 sensor driver");
  1676. MODULE_LICENSE("GPL v2");