adv7180.c 41 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * adv7180.c Analog Devices ADV7180 video decoder driver
  4. * Copyright (c) 2009 Intel Corporation
  5. * Copyright (C) 2013 Cogent Embedded, Inc.
  6. * Copyright (C) 2013 Renesas Solutions Corp.
  7. */
  8. #include <linux/module.h>
  9. #include <linux/init.h>
  10. #include <linux/errno.h>
  11. #include <linux/kernel.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/i2c.h>
  14. #include <linux/slab.h>
  15. #include <linux/of.h>
  16. #include <linux/gpio/consumer.h>
  17. #include <linux/videodev2.h>
  18. #include <media/v4l2-ioctl.h>
  19. #include <media/v4l2-event.h>
  20. #include <media/v4l2-device.h>
  21. #include <media/v4l2-ctrls.h>
  22. #include <linux/mutex.h>
  23. #include <linux/delay.h>
  24. #define ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM 0x0
  25. #define ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM_PED 0x1
  26. #define ADV7180_STD_AD_PAL_N_NTSC_J_SECAM 0x2
  27. #define ADV7180_STD_AD_PAL_N_NTSC_M_SECAM 0x3
  28. #define ADV7180_STD_NTSC_J 0x4
  29. #define ADV7180_STD_NTSC_M 0x5
  30. #define ADV7180_STD_PAL60 0x6
  31. #define ADV7180_STD_NTSC_443 0x7
  32. #define ADV7180_STD_PAL_BG 0x8
  33. #define ADV7180_STD_PAL_N 0x9
  34. #define ADV7180_STD_PAL_M 0xa
  35. #define ADV7180_STD_PAL_M_PED 0xb
  36. #define ADV7180_STD_PAL_COMB_N 0xc
  37. #define ADV7180_STD_PAL_COMB_N_PED 0xd
  38. #define ADV7180_STD_PAL_SECAM 0xe
  39. #define ADV7180_STD_PAL_SECAM_PED 0xf
  40. #define ADV7180_REG_INPUT_CONTROL 0x0000
  41. #define ADV7180_INPUT_CONTROL_INSEL_MASK 0x0f
  42. #define ADV7182_REG_INPUT_VIDSEL 0x0002
  43. #define ADV7180_REG_OUTPUT_CONTROL 0x0003
  44. #define ADV7180_REG_EXTENDED_OUTPUT_CONTROL 0x0004
  45. #define ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS 0xC5
  46. #define ADV7180_REG_AUTODETECT_ENABLE 0x0007
  47. #define ADV7180_AUTODETECT_DEFAULT 0x7f
  48. /* Contrast */
  49. #define ADV7180_REG_CON 0x0008 /*Unsigned */
  50. #define ADV7180_CON_MIN 0
  51. #define ADV7180_CON_DEF 128
  52. #define ADV7180_CON_MAX 255
  53. /* Brightness*/
  54. #define ADV7180_REG_BRI 0x000a /*Signed */
  55. #define ADV7180_BRI_MIN -128
  56. #define ADV7180_BRI_DEF 0
  57. #define ADV7180_BRI_MAX 127
  58. /* Hue */
  59. #define ADV7180_REG_HUE 0x000b /*Signed, inverted */
  60. #define ADV7180_HUE_MIN -127
  61. #define ADV7180_HUE_DEF 0
  62. #define ADV7180_HUE_MAX 128
  63. #define ADV7180_REG_CTRL 0x000e
  64. #define ADV7180_CTRL_IRQ_SPACE 0x20
  65. #define ADV7180_REG_PWR_MAN 0x0f
  66. #define ADV7180_PWR_MAN_ON 0x04
  67. #define ADV7180_PWR_MAN_OFF 0x24
  68. #define ADV7180_PWR_MAN_RES 0x80
  69. #define ADV7180_REG_STATUS1 0x0010
  70. #define ADV7180_STATUS1_IN_LOCK 0x01
  71. #define ADV7180_STATUS1_AUTOD_MASK 0x70
  72. #define ADV7180_STATUS1_AUTOD_NTSM_M_J 0x00
  73. #define ADV7180_STATUS1_AUTOD_NTSC_4_43 0x10
  74. #define ADV7180_STATUS1_AUTOD_PAL_M 0x20
  75. #define ADV7180_STATUS1_AUTOD_PAL_60 0x30
  76. #define ADV7180_STATUS1_AUTOD_PAL_B_G 0x40
  77. #define ADV7180_STATUS1_AUTOD_SECAM 0x50
  78. #define ADV7180_STATUS1_AUTOD_PAL_COMB 0x60
  79. #define ADV7180_STATUS1_AUTOD_SECAM_525 0x70
  80. #define ADV7180_REG_IDENT 0x0011
  81. #define ADV7180_ID_7180 0x18
  82. #define ADV7180_REG_STATUS3 0x0013
  83. #define ADV7180_REG_ANALOG_CLAMP_CTL 0x0014
  84. #define ADV7180_REG_SHAP_FILTER_CTL_1 0x0017
  85. #define ADV7180_REG_CTRL_2 0x001d
  86. #define ADV7180_REG_VSYNC_FIELD_CTL_1 0x0031
  87. #define ADV7180_REG_MANUAL_WIN_CTL_1 0x003d
  88. #define ADV7180_REG_MANUAL_WIN_CTL_2 0x003e
  89. #define ADV7180_REG_MANUAL_WIN_CTL_3 0x003f
  90. #define ADV7180_REG_LOCK_CNT 0x0051
  91. #define ADV7180_REG_CVBS_TRIM 0x0052
  92. #define ADV7180_REG_CLAMP_ADJ 0x005a
  93. #define ADV7180_REG_RES_CIR 0x005f
  94. #define ADV7180_REG_DIFF_MODE 0x0060
  95. #define ADV7180_REG_ICONF1 0x2040
  96. #define ADV7180_ICONF1_ACTIVE_LOW 0x01
  97. #define ADV7180_ICONF1_PSYNC_ONLY 0x10
  98. #define ADV7180_ICONF1_ACTIVE_TO_CLR 0xC0
  99. /* Saturation */
  100. #define ADV7180_REG_SD_SAT_CB 0x00e3 /*Unsigned */
  101. #define ADV7180_REG_SD_SAT_CR 0x00e4 /*Unsigned */
  102. #define ADV7180_SAT_MIN 0
  103. #define ADV7180_SAT_DEF 128
  104. #define ADV7180_SAT_MAX 255
  105. #define ADV7180_IRQ1_LOCK 0x01
  106. #define ADV7180_IRQ1_UNLOCK 0x02
  107. #define ADV7180_REG_ISR1 0x2042
  108. #define ADV7180_REG_ICR1 0x2043
  109. #define ADV7180_REG_IMR1 0x2044
  110. #define ADV7180_REG_IMR2 0x2048
  111. #define ADV7180_IRQ3_AD_CHANGE 0x08
  112. #define ADV7180_REG_ISR3 0x204A
  113. #define ADV7180_REG_ICR3 0x204B
  114. #define ADV7180_REG_IMR3 0x204C
  115. #define ADV7180_REG_IMR4 0x2050
  116. #define ADV7180_REG_NTSC_V_BIT_END 0x00E6
  117. #define ADV7180_NTSC_V_BIT_END_MANUAL_NVEND 0x4F
  118. #define ADV7180_REG_VPP_SLAVE_ADDR 0xFD
  119. #define ADV7180_REG_CSI_SLAVE_ADDR 0xFE
  120. #define ADV7180_REG_ACE_CTRL1 0x4080
  121. #define ADV7180_REG_ACE_CTRL5 0x4084
  122. #define ADV7180_REG_FLCONTROL 0x40e0
  123. #define ADV7180_FLCONTROL_FL_ENABLE 0x1
  124. #define ADV7180_REG_RST_CLAMP 0x809c
  125. #define ADV7180_REG_AGC_ADJ1 0x80b6
  126. #define ADV7180_REG_AGC_ADJ2 0x80c0
  127. #define ADV7180_CSI_REG_PWRDN 0x00
  128. #define ADV7180_CSI_PWRDN 0x80
  129. #define ADV7180_INPUT_CVBS_AIN1 0x00
  130. #define ADV7180_INPUT_CVBS_AIN2 0x01
  131. #define ADV7180_INPUT_CVBS_AIN3 0x02
  132. #define ADV7180_INPUT_CVBS_AIN4 0x03
  133. #define ADV7180_INPUT_CVBS_AIN5 0x04
  134. #define ADV7180_INPUT_CVBS_AIN6 0x05
  135. #define ADV7180_INPUT_SVIDEO_AIN1_AIN2 0x06
  136. #define ADV7180_INPUT_SVIDEO_AIN3_AIN4 0x07
  137. #define ADV7180_INPUT_SVIDEO_AIN5_AIN6 0x08
  138. #define ADV7180_INPUT_YPRPB_AIN1_AIN2_AIN3 0x09
  139. #define ADV7180_INPUT_YPRPB_AIN4_AIN5_AIN6 0x0a
  140. #define ADV7182_INPUT_CVBS_AIN1 0x00
  141. #define ADV7182_INPUT_CVBS_AIN2 0x01
  142. #define ADV7182_INPUT_CVBS_AIN3 0x02
  143. #define ADV7182_INPUT_CVBS_AIN4 0x03
  144. #define ADV7182_INPUT_CVBS_AIN5 0x04
  145. #define ADV7182_INPUT_CVBS_AIN6 0x05
  146. #define ADV7182_INPUT_CVBS_AIN7 0x06
  147. #define ADV7182_INPUT_CVBS_AIN8 0x07
  148. #define ADV7182_INPUT_SVIDEO_AIN1_AIN2 0x08
  149. #define ADV7182_INPUT_SVIDEO_AIN3_AIN4 0x09
  150. #define ADV7182_INPUT_SVIDEO_AIN5_AIN6 0x0a
  151. #define ADV7182_INPUT_SVIDEO_AIN7_AIN8 0x0b
  152. #define ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3 0x0c
  153. #define ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6 0x0d
  154. #define ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2 0x0e
  155. #define ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4 0x0f
  156. #define ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6 0x10
  157. #define ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8 0x11
  158. #define ADV7180_DEFAULT_CSI_I2C_ADDR 0x44
  159. #define ADV7180_DEFAULT_VPP_I2C_ADDR 0x42
  160. #define V4L2_CID_ADV_FAST_SWITCH (V4L2_CID_USER_ADV7180_BASE + 0x00)
  161. /* Initial number of frames to skip to avoid possible garbage */
  162. #define ADV7180_NUM_OF_SKIP_FRAMES 2
  163. struct adv7180_state;
  164. #define ADV7180_FLAG_RESET_POWERED BIT(0)
  165. #define ADV7180_FLAG_V2 BIT(1)
  166. #define ADV7180_FLAG_MIPI_CSI2 BIT(2)
  167. #define ADV7180_FLAG_I2P BIT(3)
  168. struct adv7180_chip_info {
  169. unsigned int flags;
  170. unsigned int valid_input_mask;
  171. int (*set_std)(struct adv7180_state *st, unsigned int std);
  172. int (*select_input)(struct adv7180_state *st, unsigned int input);
  173. int (*init)(struct adv7180_state *state);
  174. };
  175. struct adv7180_state {
  176. struct v4l2_ctrl_handler ctrl_hdl;
  177. struct v4l2_subdev sd;
  178. struct media_pad pad;
  179. struct mutex mutex; /* mutual excl. when accessing chip */
  180. int irq;
  181. struct gpio_desc *pwdn_gpio;
  182. v4l2_std_id curr_norm;
  183. bool powered;
  184. bool streaming;
  185. u8 input;
  186. struct i2c_client *client;
  187. unsigned int register_page;
  188. struct i2c_client *csi_client;
  189. struct i2c_client *vpp_client;
  190. const struct adv7180_chip_info *chip_info;
  191. enum v4l2_field field;
  192. };
  193. #define to_adv7180_sd(_ctrl) (&container_of(_ctrl->handler, \
  194. struct adv7180_state, \
  195. ctrl_hdl)->sd)
  196. static int adv7180_select_page(struct adv7180_state *state, unsigned int page)
  197. {
  198. if (state->register_page != page) {
  199. i2c_smbus_write_byte_data(state->client, ADV7180_REG_CTRL,
  200. page);
  201. state->register_page = page;
  202. }
  203. return 0;
  204. }
  205. static int adv7180_write(struct adv7180_state *state, unsigned int reg,
  206. unsigned int value)
  207. {
  208. lockdep_assert_held(&state->mutex);
  209. adv7180_select_page(state, reg >> 8);
  210. return i2c_smbus_write_byte_data(state->client, reg & 0xff, value);
  211. }
  212. static int adv7180_read(struct adv7180_state *state, unsigned int reg)
  213. {
  214. lockdep_assert_held(&state->mutex);
  215. adv7180_select_page(state, reg >> 8);
  216. return i2c_smbus_read_byte_data(state->client, reg & 0xff);
  217. }
  218. static int adv7180_csi_write(struct adv7180_state *state, unsigned int reg,
  219. unsigned int value)
  220. {
  221. return i2c_smbus_write_byte_data(state->csi_client, reg, value);
  222. }
  223. static int adv7180_set_video_standard(struct adv7180_state *state,
  224. unsigned int std)
  225. {
  226. return state->chip_info->set_std(state, std);
  227. }
  228. static int adv7180_vpp_write(struct adv7180_state *state, unsigned int reg,
  229. unsigned int value)
  230. {
  231. return i2c_smbus_write_byte_data(state->vpp_client, reg, value);
  232. }
  233. static v4l2_std_id adv7180_std_to_v4l2(u8 status1)
  234. {
  235. /* in case V4L2_IN_ST_NO_SIGNAL */
  236. if (!(status1 & ADV7180_STATUS1_IN_LOCK))
  237. return V4L2_STD_UNKNOWN;
  238. switch (status1 & ADV7180_STATUS1_AUTOD_MASK) {
  239. case ADV7180_STATUS1_AUTOD_NTSM_M_J:
  240. return V4L2_STD_NTSC;
  241. case ADV7180_STATUS1_AUTOD_NTSC_4_43:
  242. return V4L2_STD_NTSC_443;
  243. case ADV7180_STATUS1_AUTOD_PAL_M:
  244. return V4L2_STD_PAL_M;
  245. case ADV7180_STATUS1_AUTOD_PAL_60:
  246. return V4L2_STD_PAL_60;
  247. case ADV7180_STATUS1_AUTOD_PAL_B_G:
  248. return V4L2_STD_PAL;
  249. case ADV7180_STATUS1_AUTOD_SECAM:
  250. return V4L2_STD_SECAM;
  251. case ADV7180_STATUS1_AUTOD_PAL_COMB:
  252. return V4L2_STD_PAL_Nc | V4L2_STD_PAL_N;
  253. case ADV7180_STATUS1_AUTOD_SECAM_525:
  254. return V4L2_STD_SECAM;
  255. default:
  256. return V4L2_STD_UNKNOWN;
  257. }
  258. }
  259. static int v4l2_std_to_adv7180(v4l2_std_id std)
  260. {
  261. if (std == V4L2_STD_PAL_60)
  262. return ADV7180_STD_PAL60;
  263. if (std == V4L2_STD_NTSC_443)
  264. return ADV7180_STD_NTSC_443;
  265. if (std == V4L2_STD_PAL_N)
  266. return ADV7180_STD_PAL_N;
  267. if (std == V4L2_STD_PAL_M)
  268. return ADV7180_STD_PAL_M;
  269. if (std == V4L2_STD_PAL_Nc)
  270. return ADV7180_STD_PAL_COMB_N;
  271. if (std & V4L2_STD_PAL)
  272. return ADV7180_STD_PAL_BG;
  273. if (std & V4L2_STD_NTSC)
  274. return ADV7180_STD_NTSC_M;
  275. if (std & V4L2_STD_SECAM)
  276. return ADV7180_STD_PAL_SECAM;
  277. return -EINVAL;
  278. }
  279. static u32 adv7180_status_to_v4l2(u8 status1)
  280. {
  281. if (!(status1 & ADV7180_STATUS1_IN_LOCK))
  282. return V4L2_IN_ST_NO_SIGNAL;
  283. return 0;
  284. }
  285. static int __adv7180_status(struct adv7180_state *state, u32 *status,
  286. v4l2_std_id *std)
  287. {
  288. int status1 = adv7180_read(state, ADV7180_REG_STATUS1);
  289. if (status1 < 0)
  290. return status1;
  291. if (status)
  292. *status = adv7180_status_to_v4l2(status1);
  293. if (std)
  294. *std = adv7180_std_to_v4l2(status1);
  295. return 0;
  296. }
  297. static inline struct adv7180_state *to_state(struct v4l2_subdev *sd)
  298. {
  299. return container_of(sd, struct adv7180_state, sd);
  300. }
  301. static int adv7180_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
  302. {
  303. struct adv7180_state *state = to_state(sd);
  304. int err = mutex_lock_interruptible(&state->mutex);
  305. if (err)
  306. return err;
  307. if (state->streaming) {
  308. err = -EBUSY;
  309. goto unlock;
  310. }
  311. err = adv7180_set_video_standard(state,
  312. ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM);
  313. if (err)
  314. goto unlock;
  315. msleep(100);
  316. __adv7180_status(state, NULL, std);
  317. err = v4l2_std_to_adv7180(state->curr_norm);
  318. if (err < 0)
  319. goto unlock;
  320. err = adv7180_set_video_standard(state, err);
  321. unlock:
  322. mutex_unlock(&state->mutex);
  323. return err;
  324. }
  325. static int adv7180_s_routing(struct v4l2_subdev *sd, u32 input,
  326. u32 output, u32 config)
  327. {
  328. struct adv7180_state *state = to_state(sd);
  329. int ret = mutex_lock_interruptible(&state->mutex);
  330. if (ret)
  331. return ret;
  332. if (input > 31 || !(BIT(input) & state->chip_info->valid_input_mask)) {
  333. ret = -EINVAL;
  334. goto out;
  335. }
  336. ret = state->chip_info->select_input(state, input);
  337. if (ret == 0)
  338. state->input = input;
  339. out:
  340. mutex_unlock(&state->mutex);
  341. return ret;
  342. }
  343. static int adv7180_g_input_status(struct v4l2_subdev *sd, u32 *status)
  344. {
  345. struct adv7180_state *state = to_state(sd);
  346. int ret = mutex_lock_interruptible(&state->mutex);
  347. if (ret)
  348. return ret;
  349. ret = __adv7180_status(state, status, NULL);
  350. mutex_unlock(&state->mutex);
  351. return ret;
  352. }
  353. static int adv7180_program_std(struct adv7180_state *state)
  354. {
  355. int ret;
  356. ret = v4l2_std_to_adv7180(state->curr_norm);
  357. if (ret < 0)
  358. return ret;
  359. ret = adv7180_set_video_standard(state, ret);
  360. if (ret < 0)
  361. return ret;
  362. return 0;
  363. }
  364. static int adv7180_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
  365. {
  366. struct adv7180_state *state = to_state(sd);
  367. int ret = mutex_lock_interruptible(&state->mutex);
  368. if (ret)
  369. return ret;
  370. /* Make sure we can support this std */
  371. ret = v4l2_std_to_adv7180(std);
  372. if (ret < 0)
  373. goto out;
  374. state->curr_norm = std;
  375. ret = adv7180_program_std(state);
  376. out:
  377. mutex_unlock(&state->mutex);
  378. return ret;
  379. }
  380. static int adv7180_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm)
  381. {
  382. struct adv7180_state *state = to_state(sd);
  383. *norm = state->curr_norm;
  384. return 0;
  385. }
  386. static int adv7180_g_frame_interval(struct v4l2_subdev *sd,
  387. struct v4l2_subdev_frame_interval *fi)
  388. {
  389. struct adv7180_state *state = to_state(sd);
  390. if (state->curr_norm & V4L2_STD_525_60) {
  391. fi->interval.numerator = 1001;
  392. fi->interval.denominator = 30000;
  393. } else {
  394. fi->interval.numerator = 1;
  395. fi->interval.denominator = 25;
  396. }
  397. return 0;
  398. }
  399. static void adv7180_set_power_pin(struct adv7180_state *state, bool on)
  400. {
  401. if (!state->pwdn_gpio)
  402. return;
  403. if (on) {
  404. gpiod_set_value_cansleep(state->pwdn_gpio, 0);
  405. usleep_range(5000, 10000);
  406. } else {
  407. gpiod_set_value_cansleep(state->pwdn_gpio, 1);
  408. }
  409. }
  410. static int adv7180_set_power(struct adv7180_state *state, bool on)
  411. {
  412. u8 val;
  413. int ret;
  414. if (on)
  415. val = ADV7180_PWR_MAN_ON;
  416. else
  417. val = ADV7180_PWR_MAN_OFF;
  418. ret = adv7180_write(state, ADV7180_REG_PWR_MAN, val);
  419. if (ret)
  420. return ret;
  421. if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
  422. if (on) {
  423. adv7180_csi_write(state, 0xDE, 0x02);
  424. adv7180_csi_write(state, 0xD2, 0xF7);
  425. adv7180_csi_write(state, 0xD8, 0x65);
  426. adv7180_csi_write(state, 0xE0, 0x09);
  427. adv7180_csi_write(state, 0x2C, 0x00);
  428. if (state->field == V4L2_FIELD_NONE)
  429. adv7180_csi_write(state, 0x1D, 0x80);
  430. adv7180_csi_write(state, 0x00, 0x00);
  431. } else {
  432. adv7180_csi_write(state, 0x00, 0x80);
  433. }
  434. }
  435. return 0;
  436. }
  437. static int adv7180_s_power(struct v4l2_subdev *sd, int on)
  438. {
  439. struct adv7180_state *state = to_state(sd);
  440. int ret;
  441. ret = mutex_lock_interruptible(&state->mutex);
  442. if (ret)
  443. return ret;
  444. ret = adv7180_set_power(state, on);
  445. if (ret == 0)
  446. state->powered = on;
  447. mutex_unlock(&state->mutex);
  448. return ret;
  449. }
  450. static int adv7180_s_ctrl(struct v4l2_ctrl *ctrl)
  451. {
  452. struct v4l2_subdev *sd = to_adv7180_sd(ctrl);
  453. struct adv7180_state *state = to_state(sd);
  454. int ret = mutex_lock_interruptible(&state->mutex);
  455. int val;
  456. if (ret)
  457. return ret;
  458. val = ctrl->val;
  459. switch (ctrl->id) {
  460. case V4L2_CID_BRIGHTNESS:
  461. ret = adv7180_write(state, ADV7180_REG_BRI, val);
  462. break;
  463. case V4L2_CID_HUE:
  464. /*Hue is inverted according to HSL chart */
  465. ret = adv7180_write(state, ADV7180_REG_HUE, -val);
  466. break;
  467. case V4L2_CID_CONTRAST:
  468. ret = adv7180_write(state, ADV7180_REG_CON, val);
  469. break;
  470. case V4L2_CID_SATURATION:
  471. /*
  472. *This could be V4L2_CID_BLUE_BALANCE/V4L2_CID_RED_BALANCE
  473. *Let's not confuse the user, everybody understands saturation
  474. */
  475. ret = adv7180_write(state, ADV7180_REG_SD_SAT_CB, val);
  476. if (ret < 0)
  477. break;
  478. ret = adv7180_write(state, ADV7180_REG_SD_SAT_CR, val);
  479. break;
  480. case V4L2_CID_ADV_FAST_SWITCH:
  481. if (ctrl->val) {
  482. /* ADI required write */
  483. adv7180_write(state, 0x80d9, 0x44);
  484. adv7180_write(state, ADV7180_REG_FLCONTROL,
  485. ADV7180_FLCONTROL_FL_ENABLE);
  486. } else {
  487. /* ADI required write */
  488. adv7180_write(state, 0x80d9, 0xc4);
  489. adv7180_write(state, ADV7180_REG_FLCONTROL, 0x00);
  490. }
  491. break;
  492. default:
  493. ret = -EINVAL;
  494. }
  495. mutex_unlock(&state->mutex);
  496. return ret;
  497. }
  498. static const struct v4l2_ctrl_ops adv7180_ctrl_ops = {
  499. .s_ctrl = adv7180_s_ctrl,
  500. };
  501. static const struct v4l2_ctrl_config adv7180_ctrl_fast_switch = {
  502. .ops = &adv7180_ctrl_ops,
  503. .id = V4L2_CID_ADV_FAST_SWITCH,
  504. .name = "Fast Switching",
  505. .type = V4L2_CTRL_TYPE_BOOLEAN,
  506. .min = 0,
  507. .max = 1,
  508. .step = 1,
  509. };
  510. static int adv7180_init_controls(struct adv7180_state *state)
  511. {
  512. v4l2_ctrl_handler_init(&state->ctrl_hdl, 4);
  513. v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
  514. V4L2_CID_BRIGHTNESS, ADV7180_BRI_MIN,
  515. ADV7180_BRI_MAX, 1, ADV7180_BRI_DEF);
  516. v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
  517. V4L2_CID_CONTRAST, ADV7180_CON_MIN,
  518. ADV7180_CON_MAX, 1, ADV7180_CON_DEF);
  519. v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
  520. V4L2_CID_SATURATION, ADV7180_SAT_MIN,
  521. ADV7180_SAT_MAX, 1, ADV7180_SAT_DEF);
  522. v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
  523. V4L2_CID_HUE, ADV7180_HUE_MIN,
  524. ADV7180_HUE_MAX, 1, ADV7180_HUE_DEF);
  525. v4l2_ctrl_new_custom(&state->ctrl_hdl, &adv7180_ctrl_fast_switch, NULL);
  526. state->sd.ctrl_handler = &state->ctrl_hdl;
  527. if (state->ctrl_hdl.error) {
  528. int err = state->ctrl_hdl.error;
  529. v4l2_ctrl_handler_free(&state->ctrl_hdl);
  530. return err;
  531. }
  532. v4l2_ctrl_handler_setup(&state->ctrl_hdl);
  533. return 0;
  534. }
  535. static void adv7180_exit_controls(struct adv7180_state *state)
  536. {
  537. v4l2_ctrl_handler_free(&state->ctrl_hdl);
  538. }
  539. static int adv7180_enum_mbus_code(struct v4l2_subdev *sd,
  540. struct v4l2_subdev_pad_config *cfg,
  541. struct v4l2_subdev_mbus_code_enum *code)
  542. {
  543. if (code->index != 0)
  544. return -EINVAL;
  545. code->code = MEDIA_BUS_FMT_UYVY8_2X8;
  546. return 0;
  547. }
  548. static int adv7180_mbus_fmt(struct v4l2_subdev *sd,
  549. struct v4l2_mbus_framefmt *fmt)
  550. {
  551. struct adv7180_state *state = to_state(sd);
  552. fmt->code = MEDIA_BUS_FMT_UYVY8_2X8;
  553. fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
  554. fmt->width = 720;
  555. fmt->height = state->curr_norm & V4L2_STD_525_60 ? 480 : 576;
  556. if (state->field == V4L2_FIELD_ALTERNATE)
  557. fmt->height /= 2;
  558. return 0;
  559. }
  560. static int adv7180_set_field_mode(struct adv7180_state *state)
  561. {
  562. if (!(state->chip_info->flags & ADV7180_FLAG_I2P))
  563. return 0;
  564. if (state->field == V4L2_FIELD_NONE) {
  565. if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
  566. adv7180_csi_write(state, 0x01, 0x20);
  567. adv7180_csi_write(state, 0x02, 0x28);
  568. adv7180_csi_write(state, 0x03, 0x38);
  569. adv7180_csi_write(state, 0x04, 0x30);
  570. adv7180_csi_write(state, 0x05, 0x30);
  571. adv7180_csi_write(state, 0x06, 0x80);
  572. adv7180_csi_write(state, 0x07, 0x70);
  573. adv7180_csi_write(state, 0x08, 0x50);
  574. }
  575. adv7180_vpp_write(state, 0xa3, 0x00);
  576. adv7180_vpp_write(state, 0x5b, 0x00);
  577. adv7180_vpp_write(state, 0x55, 0x80);
  578. } else {
  579. if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
  580. adv7180_csi_write(state, 0x01, 0x18);
  581. adv7180_csi_write(state, 0x02, 0x18);
  582. adv7180_csi_write(state, 0x03, 0x30);
  583. adv7180_csi_write(state, 0x04, 0x20);
  584. adv7180_csi_write(state, 0x05, 0x28);
  585. adv7180_csi_write(state, 0x06, 0x40);
  586. adv7180_csi_write(state, 0x07, 0x58);
  587. adv7180_csi_write(state, 0x08, 0x30);
  588. }
  589. adv7180_vpp_write(state, 0xa3, 0x70);
  590. adv7180_vpp_write(state, 0x5b, 0x80);
  591. adv7180_vpp_write(state, 0x55, 0x00);
  592. }
  593. return 0;
  594. }
  595. static int adv7180_get_pad_format(struct v4l2_subdev *sd,
  596. struct v4l2_subdev_pad_config *cfg,
  597. struct v4l2_subdev_format *format)
  598. {
  599. struct adv7180_state *state = to_state(sd);
  600. if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
  601. format->format = *v4l2_subdev_get_try_format(sd, cfg, 0);
  602. } else {
  603. adv7180_mbus_fmt(sd, &format->format);
  604. format->format.field = state->field;
  605. }
  606. return 0;
  607. }
  608. static int adv7180_set_pad_format(struct v4l2_subdev *sd,
  609. struct v4l2_subdev_pad_config *cfg,
  610. struct v4l2_subdev_format *format)
  611. {
  612. struct adv7180_state *state = to_state(sd);
  613. struct v4l2_mbus_framefmt *framefmt;
  614. int ret;
  615. switch (format->format.field) {
  616. case V4L2_FIELD_NONE:
  617. if (state->chip_info->flags & ADV7180_FLAG_I2P)
  618. break;
  619. fallthrough;
  620. default:
  621. format->format.field = V4L2_FIELD_ALTERNATE;
  622. break;
  623. }
  624. ret = adv7180_mbus_fmt(sd, &format->format);
  625. if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
  626. if (state->field != format->format.field) {
  627. state->field = format->format.field;
  628. adv7180_set_power(state, false);
  629. adv7180_set_field_mode(state);
  630. adv7180_set_power(state, true);
  631. }
  632. } else {
  633. framefmt = v4l2_subdev_get_try_format(sd, cfg, 0);
  634. *framefmt = format->format;
  635. }
  636. return ret;
  637. }
  638. static int adv7180_init_cfg(struct v4l2_subdev *sd,
  639. struct v4l2_subdev_pad_config *cfg)
  640. {
  641. struct v4l2_subdev_format fmt = {
  642. .which = cfg ? V4L2_SUBDEV_FORMAT_TRY
  643. : V4L2_SUBDEV_FORMAT_ACTIVE,
  644. };
  645. return adv7180_set_pad_format(sd, cfg, &fmt);
  646. }
  647. static int adv7180_get_mbus_config(struct v4l2_subdev *sd,
  648. unsigned int pad,
  649. struct v4l2_mbus_config *cfg)
  650. {
  651. struct adv7180_state *state = to_state(sd);
  652. if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
  653. cfg->type = V4L2_MBUS_CSI2_DPHY;
  654. cfg->flags = V4L2_MBUS_CSI2_1_LANE |
  655. V4L2_MBUS_CSI2_CHANNEL_0 |
  656. V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
  657. } else {
  658. /*
  659. * The ADV7180 sensor supports BT.601/656 output modes.
  660. * The BT.656 is default and not yet configurable by s/w.
  661. */
  662. cfg->flags = V4L2_MBUS_MASTER | V4L2_MBUS_PCLK_SAMPLE_RISING |
  663. V4L2_MBUS_DATA_ACTIVE_HIGH;
  664. cfg->type = V4L2_MBUS_BT656;
  665. }
  666. return 0;
  667. }
  668. static int adv7180_get_skip_frames(struct v4l2_subdev *sd, u32 *frames)
  669. {
  670. *frames = ADV7180_NUM_OF_SKIP_FRAMES;
  671. return 0;
  672. }
  673. static int adv7180_g_pixelaspect(struct v4l2_subdev *sd, struct v4l2_fract *aspect)
  674. {
  675. struct adv7180_state *state = to_state(sd);
  676. if (state->curr_norm & V4L2_STD_525_60) {
  677. aspect->numerator = 11;
  678. aspect->denominator = 10;
  679. } else {
  680. aspect->numerator = 54;
  681. aspect->denominator = 59;
  682. }
  683. return 0;
  684. }
  685. static int adv7180_g_tvnorms(struct v4l2_subdev *sd, v4l2_std_id *norm)
  686. {
  687. *norm = V4L2_STD_ALL;
  688. return 0;
  689. }
  690. static int adv7180_s_stream(struct v4l2_subdev *sd, int enable)
  691. {
  692. struct adv7180_state *state = to_state(sd);
  693. int ret;
  694. /* It's always safe to stop streaming, no need to take the lock */
  695. if (!enable) {
  696. state->streaming = enable;
  697. return 0;
  698. }
  699. /* Must wait until querystd released the lock */
  700. ret = mutex_lock_interruptible(&state->mutex);
  701. if (ret)
  702. return ret;
  703. state->streaming = enable;
  704. mutex_unlock(&state->mutex);
  705. return 0;
  706. }
  707. static int adv7180_subscribe_event(struct v4l2_subdev *sd,
  708. struct v4l2_fh *fh,
  709. struct v4l2_event_subscription *sub)
  710. {
  711. switch (sub->type) {
  712. case V4L2_EVENT_SOURCE_CHANGE:
  713. return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
  714. case V4L2_EVENT_CTRL:
  715. return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
  716. default:
  717. return -EINVAL;
  718. }
  719. }
  720. static const struct v4l2_subdev_video_ops adv7180_video_ops = {
  721. .s_std = adv7180_s_std,
  722. .g_std = adv7180_g_std,
  723. .g_frame_interval = adv7180_g_frame_interval,
  724. .querystd = adv7180_querystd,
  725. .g_input_status = adv7180_g_input_status,
  726. .s_routing = adv7180_s_routing,
  727. .g_pixelaspect = adv7180_g_pixelaspect,
  728. .g_tvnorms = adv7180_g_tvnorms,
  729. .s_stream = adv7180_s_stream,
  730. };
  731. static const struct v4l2_subdev_core_ops adv7180_core_ops = {
  732. .s_power = adv7180_s_power,
  733. .subscribe_event = adv7180_subscribe_event,
  734. .unsubscribe_event = v4l2_event_subdev_unsubscribe,
  735. };
  736. static const struct v4l2_subdev_pad_ops adv7180_pad_ops = {
  737. .init_cfg = adv7180_init_cfg,
  738. .enum_mbus_code = adv7180_enum_mbus_code,
  739. .set_fmt = adv7180_set_pad_format,
  740. .get_fmt = adv7180_get_pad_format,
  741. .get_mbus_config = adv7180_get_mbus_config,
  742. };
  743. static const struct v4l2_subdev_sensor_ops adv7180_sensor_ops = {
  744. .g_skip_frames = adv7180_get_skip_frames,
  745. };
  746. static const struct v4l2_subdev_ops adv7180_ops = {
  747. .core = &adv7180_core_ops,
  748. .video = &adv7180_video_ops,
  749. .pad = &adv7180_pad_ops,
  750. .sensor = &adv7180_sensor_ops,
  751. };
  752. static irqreturn_t adv7180_irq(int irq, void *devid)
  753. {
  754. struct adv7180_state *state = devid;
  755. u8 isr3;
  756. mutex_lock(&state->mutex);
  757. isr3 = adv7180_read(state, ADV7180_REG_ISR3);
  758. /* clear */
  759. adv7180_write(state, ADV7180_REG_ICR3, isr3);
  760. if (isr3 & ADV7180_IRQ3_AD_CHANGE) {
  761. static const struct v4l2_event src_ch = {
  762. .type = V4L2_EVENT_SOURCE_CHANGE,
  763. .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
  764. };
  765. v4l2_subdev_notify_event(&state->sd, &src_ch);
  766. }
  767. mutex_unlock(&state->mutex);
  768. return IRQ_HANDLED;
  769. }
  770. static int adv7180_init(struct adv7180_state *state)
  771. {
  772. int ret;
  773. /* ITU-R BT.656-4 compatible */
  774. ret = adv7180_write(state, ADV7180_REG_EXTENDED_OUTPUT_CONTROL,
  775. ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS);
  776. if (ret < 0)
  777. return ret;
  778. /* Manually set V bit end position in NTSC mode */
  779. return adv7180_write(state, ADV7180_REG_NTSC_V_BIT_END,
  780. ADV7180_NTSC_V_BIT_END_MANUAL_NVEND);
  781. }
  782. static int adv7180_set_std(struct adv7180_state *state, unsigned int std)
  783. {
  784. return adv7180_write(state, ADV7180_REG_INPUT_CONTROL,
  785. (std << 4) | state->input);
  786. }
  787. static int adv7180_select_input(struct adv7180_state *state, unsigned int input)
  788. {
  789. int ret;
  790. ret = adv7180_read(state, ADV7180_REG_INPUT_CONTROL);
  791. if (ret < 0)
  792. return ret;
  793. ret &= ~ADV7180_INPUT_CONTROL_INSEL_MASK;
  794. ret |= input;
  795. return adv7180_write(state, ADV7180_REG_INPUT_CONTROL, ret);
  796. }
  797. static int adv7182_init(struct adv7180_state *state)
  798. {
  799. if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2)
  800. adv7180_write(state, ADV7180_REG_CSI_SLAVE_ADDR,
  801. ADV7180_DEFAULT_CSI_I2C_ADDR << 1);
  802. if (state->chip_info->flags & ADV7180_FLAG_I2P)
  803. adv7180_write(state, ADV7180_REG_VPP_SLAVE_ADDR,
  804. ADV7180_DEFAULT_VPP_I2C_ADDR << 1);
  805. if (state->chip_info->flags & ADV7180_FLAG_V2) {
  806. /* ADI recommended writes for improved video quality */
  807. adv7180_write(state, 0x0080, 0x51);
  808. adv7180_write(state, 0x0081, 0x51);
  809. adv7180_write(state, 0x0082, 0x68);
  810. }
  811. /* ADI required writes */
  812. if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
  813. adv7180_write(state, ADV7180_REG_OUTPUT_CONTROL, 0x4e);
  814. adv7180_write(state, ADV7180_REG_EXTENDED_OUTPUT_CONTROL, 0x57);
  815. adv7180_write(state, ADV7180_REG_CTRL_2, 0xc0);
  816. } else {
  817. if (state->chip_info->flags & ADV7180_FLAG_V2)
  818. adv7180_write(state,
  819. ADV7180_REG_EXTENDED_OUTPUT_CONTROL,
  820. 0x17);
  821. else
  822. adv7180_write(state,
  823. ADV7180_REG_EXTENDED_OUTPUT_CONTROL,
  824. 0x07);
  825. adv7180_write(state, ADV7180_REG_OUTPUT_CONTROL, 0x0c);
  826. adv7180_write(state, ADV7180_REG_CTRL_2, 0x40);
  827. }
  828. adv7180_write(state, 0x0013, 0x00);
  829. return 0;
  830. }
  831. static int adv7182_set_std(struct adv7180_state *state, unsigned int std)
  832. {
  833. return adv7180_write(state, ADV7182_REG_INPUT_VIDSEL, std << 4);
  834. }
  835. enum adv7182_input_type {
  836. ADV7182_INPUT_TYPE_CVBS,
  837. ADV7182_INPUT_TYPE_DIFF_CVBS,
  838. ADV7182_INPUT_TYPE_SVIDEO,
  839. ADV7182_INPUT_TYPE_YPBPR,
  840. };
  841. static enum adv7182_input_type adv7182_get_input_type(unsigned int input)
  842. {
  843. switch (input) {
  844. case ADV7182_INPUT_CVBS_AIN1:
  845. case ADV7182_INPUT_CVBS_AIN2:
  846. case ADV7182_INPUT_CVBS_AIN3:
  847. case ADV7182_INPUT_CVBS_AIN4:
  848. case ADV7182_INPUT_CVBS_AIN5:
  849. case ADV7182_INPUT_CVBS_AIN6:
  850. case ADV7182_INPUT_CVBS_AIN7:
  851. case ADV7182_INPUT_CVBS_AIN8:
  852. return ADV7182_INPUT_TYPE_CVBS;
  853. case ADV7182_INPUT_SVIDEO_AIN1_AIN2:
  854. case ADV7182_INPUT_SVIDEO_AIN3_AIN4:
  855. case ADV7182_INPUT_SVIDEO_AIN5_AIN6:
  856. case ADV7182_INPUT_SVIDEO_AIN7_AIN8:
  857. return ADV7182_INPUT_TYPE_SVIDEO;
  858. case ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3:
  859. case ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6:
  860. return ADV7182_INPUT_TYPE_YPBPR;
  861. case ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2:
  862. case ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4:
  863. case ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6:
  864. case ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8:
  865. return ADV7182_INPUT_TYPE_DIFF_CVBS;
  866. default: /* Will never happen */
  867. return 0;
  868. }
  869. }
  870. /* ADI recommended writes to registers 0x52, 0x53, 0x54 */
  871. static unsigned int adv7182_lbias_settings[][3] = {
  872. [ADV7182_INPUT_TYPE_CVBS] = { 0xCB, 0x4E, 0x80 },
  873. [ADV7182_INPUT_TYPE_DIFF_CVBS] = { 0xC0, 0x4E, 0x80 },
  874. [ADV7182_INPUT_TYPE_SVIDEO] = { 0x0B, 0xCE, 0x80 },
  875. [ADV7182_INPUT_TYPE_YPBPR] = { 0x0B, 0x4E, 0xC0 },
  876. };
  877. static unsigned int adv7280_lbias_settings[][3] = {
  878. [ADV7182_INPUT_TYPE_CVBS] = { 0xCD, 0x4E, 0x80 },
  879. [ADV7182_INPUT_TYPE_DIFF_CVBS] = { 0xC0, 0x4E, 0x80 },
  880. [ADV7182_INPUT_TYPE_SVIDEO] = { 0x0B, 0xCE, 0x80 },
  881. [ADV7182_INPUT_TYPE_YPBPR] = { 0x0B, 0x4E, 0xC0 },
  882. };
  883. static int adv7182_select_input(struct adv7180_state *state, unsigned int input)
  884. {
  885. enum adv7182_input_type input_type;
  886. unsigned int *lbias;
  887. unsigned int i;
  888. int ret;
  889. ret = adv7180_write(state, ADV7180_REG_INPUT_CONTROL, input);
  890. if (ret)
  891. return ret;
  892. /* Reset clamp circuitry - ADI recommended writes */
  893. adv7180_write(state, ADV7180_REG_RST_CLAMP, 0x00);
  894. adv7180_write(state, ADV7180_REG_RST_CLAMP, 0xff);
  895. input_type = adv7182_get_input_type(input);
  896. switch (input_type) {
  897. case ADV7182_INPUT_TYPE_CVBS:
  898. case ADV7182_INPUT_TYPE_DIFF_CVBS:
  899. /* ADI recommends to use the SH1 filter */
  900. adv7180_write(state, ADV7180_REG_SHAP_FILTER_CTL_1, 0x41);
  901. break;
  902. default:
  903. adv7180_write(state, ADV7180_REG_SHAP_FILTER_CTL_1, 0x01);
  904. break;
  905. }
  906. if (state->chip_info->flags & ADV7180_FLAG_V2)
  907. lbias = adv7280_lbias_settings[input_type];
  908. else
  909. lbias = adv7182_lbias_settings[input_type];
  910. for (i = 0; i < ARRAY_SIZE(adv7182_lbias_settings[0]); i++)
  911. adv7180_write(state, ADV7180_REG_CVBS_TRIM + i, lbias[i]);
  912. if (input_type == ADV7182_INPUT_TYPE_DIFF_CVBS) {
  913. /* ADI required writes to make differential CVBS work */
  914. adv7180_write(state, ADV7180_REG_RES_CIR, 0xa8);
  915. adv7180_write(state, ADV7180_REG_CLAMP_ADJ, 0x90);
  916. adv7180_write(state, ADV7180_REG_DIFF_MODE, 0xb0);
  917. adv7180_write(state, ADV7180_REG_AGC_ADJ1, 0x08);
  918. adv7180_write(state, ADV7180_REG_AGC_ADJ2, 0xa0);
  919. } else {
  920. adv7180_write(state, ADV7180_REG_RES_CIR, 0xf0);
  921. adv7180_write(state, ADV7180_REG_CLAMP_ADJ, 0xd0);
  922. adv7180_write(state, ADV7180_REG_DIFF_MODE, 0x10);
  923. adv7180_write(state, ADV7180_REG_AGC_ADJ1, 0x9c);
  924. adv7180_write(state, ADV7180_REG_AGC_ADJ2, 0x00);
  925. }
  926. return 0;
  927. }
  928. static const struct adv7180_chip_info adv7180_info = {
  929. .flags = ADV7180_FLAG_RESET_POWERED,
  930. /* We cannot discriminate between LQFP and 40-pin LFCSP, so accept
  931. * all inputs and let the card driver take care of validation
  932. */
  933. .valid_input_mask = BIT(ADV7180_INPUT_CVBS_AIN1) |
  934. BIT(ADV7180_INPUT_CVBS_AIN2) |
  935. BIT(ADV7180_INPUT_CVBS_AIN3) |
  936. BIT(ADV7180_INPUT_CVBS_AIN4) |
  937. BIT(ADV7180_INPUT_CVBS_AIN5) |
  938. BIT(ADV7180_INPUT_CVBS_AIN6) |
  939. BIT(ADV7180_INPUT_SVIDEO_AIN1_AIN2) |
  940. BIT(ADV7180_INPUT_SVIDEO_AIN3_AIN4) |
  941. BIT(ADV7180_INPUT_SVIDEO_AIN5_AIN6) |
  942. BIT(ADV7180_INPUT_YPRPB_AIN1_AIN2_AIN3) |
  943. BIT(ADV7180_INPUT_YPRPB_AIN4_AIN5_AIN6),
  944. .init = adv7180_init,
  945. .set_std = adv7180_set_std,
  946. .select_input = adv7180_select_input,
  947. };
  948. static const struct adv7180_chip_info adv7182_info = {
  949. .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
  950. BIT(ADV7182_INPUT_CVBS_AIN2) |
  951. BIT(ADV7182_INPUT_CVBS_AIN3) |
  952. BIT(ADV7182_INPUT_CVBS_AIN4) |
  953. BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
  954. BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
  955. BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
  956. BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
  957. BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4),
  958. .init = adv7182_init,
  959. .set_std = adv7182_set_std,
  960. .select_input = adv7182_select_input,
  961. };
  962. static const struct adv7180_chip_info adv7280_info = {
  963. .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_I2P,
  964. .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
  965. BIT(ADV7182_INPUT_CVBS_AIN2) |
  966. BIT(ADV7182_INPUT_CVBS_AIN3) |
  967. BIT(ADV7182_INPUT_CVBS_AIN4) |
  968. BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
  969. BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
  970. BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3),
  971. .init = adv7182_init,
  972. .set_std = adv7182_set_std,
  973. .select_input = adv7182_select_input,
  974. };
  975. static const struct adv7180_chip_info adv7280_m_info = {
  976. .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 | ADV7180_FLAG_I2P,
  977. .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
  978. BIT(ADV7182_INPUT_CVBS_AIN2) |
  979. BIT(ADV7182_INPUT_CVBS_AIN3) |
  980. BIT(ADV7182_INPUT_CVBS_AIN4) |
  981. BIT(ADV7182_INPUT_CVBS_AIN5) |
  982. BIT(ADV7182_INPUT_CVBS_AIN6) |
  983. BIT(ADV7182_INPUT_CVBS_AIN7) |
  984. BIT(ADV7182_INPUT_CVBS_AIN8) |
  985. BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
  986. BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
  987. BIT(ADV7182_INPUT_SVIDEO_AIN5_AIN6) |
  988. BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
  989. BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
  990. BIT(ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6),
  991. .init = adv7182_init,
  992. .set_std = adv7182_set_std,
  993. .select_input = adv7182_select_input,
  994. };
  995. static const struct adv7180_chip_info adv7281_info = {
  996. .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2,
  997. .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
  998. BIT(ADV7182_INPUT_CVBS_AIN2) |
  999. BIT(ADV7182_INPUT_CVBS_AIN7) |
  1000. BIT(ADV7182_INPUT_CVBS_AIN8) |
  1001. BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
  1002. BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
  1003. BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
  1004. BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
  1005. .init = adv7182_init,
  1006. .set_std = adv7182_set_std,
  1007. .select_input = adv7182_select_input,
  1008. };
  1009. static const struct adv7180_chip_info adv7281_m_info = {
  1010. .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2,
  1011. .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
  1012. BIT(ADV7182_INPUT_CVBS_AIN2) |
  1013. BIT(ADV7182_INPUT_CVBS_AIN3) |
  1014. BIT(ADV7182_INPUT_CVBS_AIN4) |
  1015. BIT(ADV7182_INPUT_CVBS_AIN7) |
  1016. BIT(ADV7182_INPUT_CVBS_AIN8) |
  1017. BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
  1018. BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
  1019. BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
  1020. BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
  1021. BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
  1022. BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) |
  1023. BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
  1024. .init = adv7182_init,
  1025. .set_std = adv7182_set_std,
  1026. .select_input = adv7182_select_input,
  1027. };
  1028. static const struct adv7180_chip_info adv7281_ma_info = {
  1029. .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2,
  1030. .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
  1031. BIT(ADV7182_INPUT_CVBS_AIN2) |
  1032. BIT(ADV7182_INPUT_CVBS_AIN3) |
  1033. BIT(ADV7182_INPUT_CVBS_AIN4) |
  1034. BIT(ADV7182_INPUT_CVBS_AIN5) |
  1035. BIT(ADV7182_INPUT_CVBS_AIN6) |
  1036. BIT(ADV7182_INPUT_CVBS_AIN7) |
  1037. BIT(ADV7182_INPUT_CVBS_AIN8) |
  1038. BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
  1039. BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
  1040. BIT(ADV7182_INPUT_SVIDEO_AIN5_AIN6) |
  1041. BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
  1042. BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
  1043. BIT(ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6) |
  1044. BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
  1045. BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) |
  1046. BIT(ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6) |
  1047. BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
  1048. .init = adv7182_init,
  1049. .set_std = adv7182_set_std,
  1050. .select_input = adv7182_select_input,
  1051. };
  1052. static const struct adv7180_chip_info adv7282_info = {
  1053. .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_I2P,
  1054. .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
  1055. BIT(ADV7182_INPUT_CVBS_AIN2) |
  1056. BIT(ADV7182_INPUT_CVBS_AIN7) |
  1057. BIT(ADV7182_INPUT_CVBS_AIN8) |
  1058. BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
  1059. BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
  1060. BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
  1061. BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
  1062. .init = adv7182_init,
  1063. .set_std = adv7182_set_std,
  1064. .select_input = adv7182_select_input,
  1065. };
  1066. static const struct adv7180_chip_info adv7282_m_info = {
  1067. .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 | ADV7180_FLAG_I2P,
  1068. .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
  1069. BIT(ADV7182_INPUT_CVBS_AIN2) |
  1070. BIT(ADV7182_INPUT_CVBS_AIN3) |
  1071. BIT(ADV7182_INPUT_CVBS_AIN4) |
  1072. BIT(ADV7182_INPUT_CVBS_AIN7) |
  1073. BIT(ADV7182_INPUT_CVBS_AIN8) |
  1074. BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
  1075. BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
  1076. BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
  1077. BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
  1078. BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) |
  1079. BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
  1080. .init = adv7182_init,
  1081. .set_std = adv7182_set_std,
  1082. .select_input = adv7182_select_input,
  1083. };
  1084. static int init_device(struct adv7180_state *state)
  1085. {
  1086. int ret;
  1087. mutex_lock(&state->mutex);
  1088. adv7180_set_power_pin(state, true);
  1089. adv7180_write(state, ADV7180_REG_PWR_MAN, ADV7180_PWR_MAN_RES);
  1090. usleep_range(5000, 10000);
  1091. ret = state->chip_info->init(state);
  1092. if (ret)
  1093. goto out_unlock;
  1094. ret = adv7180_program_std(state);
  1095. if (ret)
  1096. goto out_unlock;
  1097. adv7180_set_field_mode(state);
  1098. /* register for interrupts */
  1099. if (state->irq > 0) {
  1100. /* config the Interrupt pin to be active low */
  1101. ret = adv7180_write(state, ADV7180_REG_ICONF1,
  1102. ADV7180_ICONF1_ACTIVE_LOW |
  1103. ADV7180_ICONF1_PSYNC_ONLY);
  1104. if (ret < 0)
  1105. goto out_unlock;
  1106. ret = adv7180_write(state, ADV7180_REG_IMR1, 0);
  1107. if (ret < 0)
  1108. goto out_unlock;
  1109. ret = adv7180_write(state, ADV7180_REG_IMR2, 0);
  1110. if (ret < 0)
  1111. goto out_unlock;
  1112. /* enable AD change interrupts interrupts */
  1113. ret = adv7180_write(state, ADV7180_REG_IMR3,
  1114. ADV7180_IRQ3_AD_CHANGE);
  1115. if (ret < 0)
  1116. goto out_unlock;
  1117. ret = adv7180_write(state, ADV7180_REG_IMR4, 0);
  1118. if (ret < 0)
  1119. goto out_unlock;
  1120. }
  1121. out_unlock:
  1122. mutex_unlock(&state->mutex);
  1123. return ret;
  1124. }
  1125. static int adv7180_probe(struct i2c_client *client,
  1126. const struct i2c_device_id *id)
  1127. {
  1128. struct adv7180_state *state;
  1129. struct v4l2_subdev *sd;
  1130. int ret;
  1131. /* Check if the adapter supports the needed features */
  1132. if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
  1133. return -EIO;
  1134. state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
  1135. if (state == NULL)
  1136. return -ENOMEM;
  1137. state->client = client;
  1138. state->field = V4L2_FIELD_ALTERNATE;
  1139. state->chip_info = (struct adv7180_chip_info *)id->driver_data;
  1140. state->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "powerdown",
  1141. GPIOD_OUT_HIGH);
  1142. if (IS_ERR(state->pwdn_gpio)) {
  1143. ret = PTR_ERR(state->pwdn_gpio);
  1144. v4l_err(client, "request for power pin failed: %d\n", ret);
  1145. return ret;
  1146. }
  1147. if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
  1148. state->csi_client = i2c_new_dummy_device(client->adapter,
  1149. ADV7180_DEFAULT_CSI_I2C_ADDR);
  1150. if (IS_ERR(state->csi_client))
  1151. return PTR_ERR(state->csi_client);
  1152. }
  1153. if (state->chip_info->flags & ADV7180_FLAG_I2P) {
  1154. state->vpp_client = i2c_new_dummy_device(client->adapter,
  1155. ADV7180_DEFAULT_VPP_I2C_ADDR);
  1156. if (IS_ERR(state->vpp_client)) {
  1157. ret = PTR_ERR(state->vpp_client);
  1158. goto err_unregister_csi_client;
  1159. }
  1160. }
  1161. state->irq = client->irq;
  1162. mutex_init(&state->mutex);
  1163. state->curr_norm = V4L2_STD_NTSC;
  1164. if (state->chip_info->flags & ADV7180_FLAG_RESET_POWERED)
  1165. state->powered = true;
  1166. else
  1167. state->powered = false;
  1168. state->input = 0;
  1169. sd = &state->sd;
  1170. v4l2_i2c_subdev_init(sd, client, &adv7180_ops);
  1171. sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
  1172. ret = adv7180_init_controls(state);
  1173. if (ret)
  1174. goto err_unregister_vpp_client;
  1175. state->pad.flags = MEDIA_PAD_FL_SOURCE;
  1176. sd->entity.function = MEDIA_ENT_F_ATV_DECODER;
  1177. ret = media_entity_pads_init(&sd->entity, 1, &state->pad);
  1178. if (ret)
  1179. goto err_free_ctrl;
  1180. ret = init_device(state);
  1181. if (ret)
  1182. goto err_media_entity_cleanup;
  1183. if (state->irq) {
  1184. ret = request_threaded_irq(client->irq, NULL, adv7180_irq,
  1185. IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
  1186. KBUILD_MODNAME, state);
  1187. if (ret)
  1188. goto err_media_entity_cleanup;
  1189. }
  1190. ret = v4l2_async_register_subdev(sd);
  1191. if (ret)
  1192. goto err_free_irq;
  1193. v4l_info(client, "chip found @ 0x%02x (%s)\n",
  1194. client->addr, client->adapter->name);
  1195. return 0;
  1196. err_free_irq:
  1197. if (state->irq > 0)
  1198. free_irq(client->irq, state);
  1199. err_media_entity_cleanup:
  1200. media_entity_cleanup(&sd->entity);
  1201. err_free_ctrl:
  1202. adv7180_exit_controls(state);
  1203. err_unregister_vpp_client:
  1204. i2c_unregister_device(state->vpp_client);
  1205. err_unregister_csi_client:
  1206. i2c_unregister_device(state->csi_client);
  1207. mutex_destroy(&state->mutex);
  1208. return ret;
  1209. }
  1210. static int adv7180_remove(struct i2c_client *client)
  1211. {
  1212. struct v4l2_subdev *sd = i2c_get_clientdata(client);
  1213. struct adv7180_state *state = to_state(sd);
  1214. v4l2_async_unregister_subdev(sd);
  1215. if (state->irq > 0)
  1216. free_irq(client->irq, state);
  1217. media_entity_cleanup(&sd->entity);
  1218. adv7180_exit_controls(state);
  1219. i2c_unregister_device(state->vpp_client);
  1220. i2c_unregister_device(state->csi_client);
  1221. adv7180_set_power_pin(state, false);
  1222. mutex_destroy(&state->mutex);
  1223. return 0;
  1224. }
  1225. static const struct i2c_device_id adv7180_id[] = {
  1226. { "adv7180", (kernel_ulong_t)&adv7180_info },
  1227. { "adv7180cp", (kernel_ulong_t)&adv7180_info },
  1228. { "adv7180st", (kernel_ulong_t)&adv7180_info },
  1229. { "adv7182", (kernel_ulong_t)&adv7182_info },
  1230. { "adv7280", (kernel_ulong_t)&adv7280_info },
  1231. { "adv7280-m", (kernel_ulong_t)&adv7280_m_info },
  1232. { "adv7281", (kernel_ulong_t)&adv7281_info },
  1233. { "adv7281-m", (kernel_ulong_t)&adv7281_m_info },
  1234. { "adv7281-ma", (kernel_ulong_t)&adv7281_ma_info },
  1235. { "adv7282", (kernel_ulong_t)&adv7282_info },
  1236. { "adv7282-m", (kernel_ulong_t)&adv7282_m_info },
  1237. {},
  1238. };
  1239. MODULE_DEVICE_TABLE(i2c, adv7180_id);
  1240. #ifdef CONFIG_PM_SLEEP
  1241. static int adv7180_suspend(struct device *dev)
  1242. {
  1243. struct i2c_client *client = to_i2c_client(dev);
  1244. struct v4l2_subdev *sd = i2c_get_clientdata(client);
  1245. struct adv7180_state *state = to_state(sd);
  1246. return adv7180_set_power(state, false);
  1247. }
  1248. static int adv7180_resume(struct device *dev)
  1249. {
  1250. struct i2c_client *client = to_i2c_client(dev);
  1251. struct v4l2_subdev *sd = i2c_get_clientdata(client);
  1252. struct adv7180_state *state = to_state(sd);
  1253. int ret;
  1254. ret = init_device(state);
  1255. if (ret < 0)
  1256. return ret;
  1257. ret = adv7180_set_power(state, state->powered);
  1258. if (ret)
  1259. return ret;
  1260. return 0;
  1261. }
  1262. static SIMPLE_DEV_PM_OPS(adv7180_pm_ops, adv7180_suspend, adv7180_resume);
  1263. #define ADV7180_PM_OPS (&adv7180_pm_ops)
  1264. #else
  1265. #define ADV7180_PM_OPS NULL
  1266. #endif
  1267. #ifdef CONFIG_OF
  1268. static const struct of_device_id adv7180_of_id[] = {
  1269. { .compatible = "adi,adv7180", },
  1270. { .compatible = "adi,adv7180cp", },
  1271. { .compatible = "adi,adv7180st", },
  1272. { .compatible = "adi,adv7182", },
  1273. { .compatible = "adi,adv7280", },
  1274. { .compatible = "adi,adv7280-m", },
  1275. { .compatible = "adi,adv7281", },
  1276. { .compatible = "adi,adv7281-m", },
  1277. { .compatible = "adi,adv7281-ma", },
  1278. { .compatible = "adi,adv7282", },
  1279. { .compatible = "adi,adv7282-m", },
  1280. { },
  1281. };
  1282. MODULE_DEVICE_TABLE(of, adv7180_of_id);
  1283. #endif
  1284. static struct i2c_driver adv7180_driver = {
  1285. .driver = {
  1286. .name = KBUILD_MODNAME,
  1287. .pm = ADV7180_PM_OPS,
  1288. .of_match_table = of_match_ptr(adv7180_of_id),
  1289. },
  1290. .probe = adv7180_probe,
  1291. .remove = adv7180_remove,
  1292. .id_table = adv7180_id,
  1293. };
  1294. module_i2c_driver(adv7180_driver);
  1295. MODULE_DESCRIPTION("Analog Devices ADV7180 video decoder driver");
  1296. MODULE_AUTHOR("Mocean Laboratories");
  1297. MODULE_LICENSE("GPL v2");