tda10048.c 28 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. NXP TDA10048HN DVB OFDM demodulator driver
  4. Copyright (C) 2009 Steven Toth <stoth@kernellabs.com>
  5. */
  6. #include <linux/kernel.h>
  7. #include <linux/init.h>
  8. #include <linux/module.h>
  9. #include <linux/string.h>
  10. #include <linux/slab.h>
  11. #include <linux/delay.h>
  12. #include <linux/math64.h>
  13. #include <asm/div64.h>
  14. #include <media/dvb_frontend.h>
  15. #include <media/dvb_math.h>
  16. #include "tda10048.h"
  17. #define TDA10048_DEFAULT_FIRMWARE "dvb-fe-tda10048-1.0.fw"
  18. #define TDA10048_DEFAULT_FIRMWARE_SIZE 24878
  19. /* Register name definitions */
  20. #define TDA10048_IDENTITY 0x00
  21. #define TDA10048_VERSION 0x01
  22. #define TDA10048_DSP_CODE_CPT 0x0C
  23. #define TDA10048_DSP_CODE_IN 0x0E
  24. #define TDA10048_IN_CONF1 0x10
  25. #define TDA10048_IN_CONF2 0x11
  26. #define TDA10048_IN_CONF3 0x12
  27. #define TDA10048_OUT_CONF1 0x14
  28. #define TDA10048_OUT_CONF2 0x15
  29. #define TDA10048_OUT_CONF3 0x16
  30. #define TDA10048_AUTO 0x18
  31. #define TDA10048_SYNC_STATUS 0x1A
  32. #define TDA10048_CONF_C4_1 0x1E
  33. #define TDA10048_CONF_C4_2 0x1F
  34. #define TDA10048_CODE_IN_RAM 0x20
  35. #define TDA10048_CHANNEL_INFO1_R 0x22
  36. #define TDA10048_CHANNEL_INFO2_R 0x23
  37. #define TDA10048_CHANNEL_INFO1 0x24
  38. #define TDA10048_CHANNEL_INFO2 0x25
  39. #define TDA10048_TIME_ERROR_R 0x26
  40. #define TDA10048_TIME_ERROR 0x27
  41. #define TDA10048_FREQ_ERROR_LSB_R 0x28
  42. #define TDA10048_FREQ_ERROR_MSB_R 0x29
  43. #define TDA10048_FREQ_ERROR_LSB 0x2A
  44. #define TDA10048_FREQ_ERROR_MSB 0x2B
  45. #define TDA10048_IT_SEL 0x30
  46. #define TDA10048_IT_STAT 0x32
  47. #define TDA10048_DSP_AD_LSB 0x3C
  48. #define TDA10048_DSP_AD_MSB 0x3D
  49. #define TDA10048_DSP_REG_LSB 0x3E
  50. #define TDA10048_DSP_REG_MSB 0x3F
  51. #define TDA10048_CONF_TRISTATE1 0x44
  52. #define TDA10048_CONF_TRISTATE2 0x45
  53. #define TDA10048_CONF_POLARITY 0x46
  54. #define TDA10048_GPIO_SP_DS0 0x48
  55. #define TDA10048_GPIO_SP_DS1 0x49
  56. #define TDA10048_GPIO_SP_DS2 0x4A
  57. #define TDA10048_GPIO_SP_DS3 0x4B
  58. #define TDA10048_GPIO_OUT_SEL 0x4C
  59. #define TDA10048_GPIO_SELECT 0x4D
  60. #define TDA10048_IC_MODE 0x4E
  61. #define TDA10048_CONF_XO 0x50
  62. #define TDA10048_CONF_PLL1 0x51
  63. #define TDA10048_CONF_PLL2 0x52
  64. #define TDA10048_CONF_PLL3 0x53
  65. #define TDA10048_CONF_ADC 0x54
  66. #define TDA10048_CONF_ADC_2 0x55
  67. #define TDA10048_CONF_C1_1 0x60
  68. #define TDA10048_CONF_C1_3 0x62
  69. #define TDA10048_AGC_CONF 0x70
  70. #define TDA10048_AGC_THRESHOLD_LSB 0x72
  71. #define TDA10048_AGC_THRESHOLD_MSB 0x73
  72. #define TDA10048_AGC_RENORM 0x74
  73. #define TDA10048_AGC_GAINS 0x76
  74. #define TDA10048_AGC_TUN_MIN 0x78
  75. #define TDA10048_AGC_TUN_MAX 0x79
  76. #define TDA10048_AGC_IF_MIN 0x7A
  77. #define TDA10048_AGC_IF_MAX 0x7B
  78. #define TDA10048_AGC_TUN_LEVEL 0x7E
  79. #define TDA10048_AGC_IF_LEVEL 0x7F
  80. #define TDA10048_DIG_AGC_LEVEL 0x81
  81. #define TDA10048_FREQ_PHY2_LSB 0x86
  82. #define TDA10048_FREQ_PHY2_MSB 0x87
  83. #define TDA10048_TIME_INVWREF_LSB 0x88
  84. #define TDA10048_TIME_INVWREF_MSB 0x89
  85. #define TDA10048_TIME_WREF_LSB 0x8A
  86. #define TDA10048_TIME_WREF_MID1 0x8B
  87. #define TDA10048_TIME_WREF_MID2 0x8C
  88. #define TDA10048_TIME_WREF_MSB 0x8D
  89. #define TDA10048_NP_OUT 0xA2
  90. #define TDA10048_CELL_ID_LSB 0xA4
  91. #define TDA10048_CELL_ID_MSB 0xA5
  92. #define TDA10048_EXTTPS_ODD 0xAA
  93. #define TDA10048_EXTTPS_EVEN 0xAB
  94. #define TDA10048_TPS_LENGTH 0xAC
  95. #define TDA10048_FREE_REG_1 0xB2
  96. #define TDA10048_FREE_REG_2 0xB3
  97. #define TDA10048_CONF_C3_1 0xC0
  98. #define TDA10048_CVBER_CTRL 0xC2
  99. #define TDA10048_CBER_NMAX_LSB 0xC4
  100. #define TDA10048_CBER_NMAX_MSB 0xC5
  101. #define TDA10048_CBER_LSB 0xC6
  102. #define TDA10048_CBER_MSB 0xC7
  103. #define TDA10048_VBER_LSB 0xC8
  104. #define TDA10048_VBER_MID 0xC9
  105. #define TDA10048_VBER_MSB 0xCA
  106. #define TDA10048_CVBER_LUT 0xCC
  107. #define TDA10048_UNCOR_CTRL 0xCD
  108. #define TDA10048_UNCOR_CPT_LSB 0xCE
  109. #define TDA10048_UNCOR_CPT_MSB 0xCF
  110. #define TDA10048_SOFT_IT_C3 0xD6
  111. #define TDA10048_CONF_TS2 0xE0
  112. #define TDA10048_CONF_TS1 0xE1
  113. static unsigned int debug;
  114. #define dprintk(level, fmt, arg...)\
  115. do { if (debug >= level)\
  116. printk(KERN_DEBUG "tda10048: " fmt, ## arg);\
  117. } while (0)
  118. struct tda10048_state {
  119. struct i2c_adapter *i2c;
  120. /* We'll cache and update the attach config settings */
  121. struct tda10048_config config;
  122. struct dvb_frontend frontend;
  123. int fwloaded;
  124. u32 freq_if_hz;
  125. u32 xtal_hz;
  126. u32 pll_mfactor;
  127. u32 pll_nfactor;
  128. u32 pll_pfactor;
  129. u32 sample_freq;
  130. u32 bandwidth;
  131. };
  132. static struct init_tab {
  133. u8 reg;
  134. u16 data;
  135. } init_tab[] = {
  136. { TDA10048_CONF_PLL1, 0x08 },
  137. { TDA10048_CONF_ADC_2, 0x00 },
  138. { TDA10048_CONF_C4_1, 0x00 },
  139. { TDA10048_CONF_PLL1, 0x0f },
  140. { TDA10048_CONF_PLL2, 0x0a },
  141. { TDA10048_CONF_PLL3, 0x43 },
  142. { TDA10048_FREQ_PHY2_LSB, 0x02 },
  143. { TDA10048_FREQ_PHY2_MSB, 0x0a },
  144. { TDA10048_TIME_WREF_LSB, 0xbd },
  145. { TDA10048_TIME_WREF_MID1, 0xe4 },
  146. { TDA10048_TIME_WREF_MID2, 0xa8 },
  147. { TDA10048_TIME_WREF_MSB, 0x02 },
  148. { TDA10048_TIME_INVWREF_LSB, 0x04 },
  149. { TDA10048_TIME_INVWREF_MSB, 0x06 },
  150. { TDA10048_CONF_C4_1, 0x00 },
  151. { TDA10048_CONF_C1_1, 0xa8 },
  152. { TDA10048_AGC_CONF, 0x16 },
  153. { TDA10048_CONF_C1_3, 0x0b },
  154. { TDA10048_AGC_TUN_MIN, 0x00 },
  155. { TDA10048_AGC_TUN_MAX, 0xff },
  156. { TDA10048_AGC_IF_MIN, 0x00 },
  157. { TDA10048_AGC_IF_MAX, 0xff },
  158. { TDA10048_AGC_THRESHOLD_MSB, 0x00 },
  159. { TDA10048_AGC_THRESHOLD_LSB, 0x70 },
  160. { TDA10048_CVBER_CTRL, 0x38 },
  161. { TDA10048_AGC_GAINS, 0x12 },
  162. { TDA10048_CONF_XO, 0x00 },
  163. { TDA10048_CONF_TS1, 0x07 },
  164. { TDA10048_IC_MODE, 0x00 },
  165. { TDA10048_CONF_TS2, 0xc0 },
  166. { TDA10048_CONF_TRISTATE1, 0x21 },
  167. { TDA10048_CONF_TRISTATE2, 0x00 },
  168. { TDA10048_CONF_POLARITY, 0x00 },
  169. { TDA10048_CONF_C4_2, 0x04 },
  170. { TDA10048_CONF_ADC, 0x60 },
  171. { TDA10048_CONF_ADC_2, 0x10 },
  172. { TDA10048_CONF_ADC, 0x60 },
  173. { TDA10048_CONF_ADC_2, 0x00 },
  174. { TDA10048_CONF_C1_1, 0xa8 },
  175. { TDA10048_UNCOR_CTRL, 0x00 },
  176. { TDA10048_CONF_C4_2, 0x04 },
  177. };
  178. static struct pll_tab {
  179. u32 clk_freq_khz;
  180. u32 if_freq_khz;
  181. } pll_tab[] = {
  182. { TDA10048_CLK_4000, TDA10048_IF_36130 },
  183. { TDA10048_CLK_16000, TDA10048_IF_3300 },
  184. { TDA10048_CLK_16000, TDA10048_IF_3500 },
  185. { TDA10048_CLK_16000, TDA10048_IF_3800 },
  186. { TDA10048_CLK_16000, TDA10048_IF_4000 },
  187. { TDA10048_CLK_16000, TDA10048_IF_4300 },
  188. { TDA10048_CLK_16000, TDA10048_IF_4500 },
  189. { TDA10048_CLK_16000, TDA10048_IF_5000 },
  190. { TDA10048_CLK_16000, TDA10048_IF_36130 },
  191. };
  192. static int tda10048_writereg(struct tda10048_state *state, u8 reg, u8 data)
  193. {
  194. struct tda10048_config *config = &state->config;
  195. int ret;
  196. u8 buf[] = { reg, data };
  197. struct i2c_msg msg = {
  198. .addr = config->demod_address,
  199. .flags = 0, .buf = buf, .len = 2 };
  200. dprintk(2, "%s(reg = 0x%02x, data = 0x%02x)\n", __func__, reg, data);
  201. ret = i2c_transfer(state->i2c, &msg, 1);
  202. if (ret != 1)
  203. printk("%s: writereg error (ret == %i)\n", __func__, ret);
  204. return (ret != 1) ? -1 : 0;
  205. }
  206. static u8 tda10048_readreg(struct tda10048_state *state, u8 reg)
  207. {
  208. struct tda10048_config *config = &state->config;
  209. int ret;
  210. u8 b0[] = { reg };
  211. u8 b1[] = { 0 };
  212. struct i2c_msg msg[] = {
  213. { .addr = config->demod_address,
  214. .flags = 0, .buf = b0, .len = 1 },
  215. { .addr = config->demod_address,
  216. .flags = I2C_M_RD, .buf = b1, .len = 1 } };
  217. dprintk(2, "%s(reg = 0x%02x)\n", __func__, reg);
  218. ret = i2c_transfer(state->i2c, msg, 2);
  219. if (ret != 2)
  220. printk(KERN_ERR "%s: readreg error (ret == %i)\n",
  221. __func__, ret);
  222. return b1[0];
  223. }
  224. static int tda10048_writeregbulk(struct tda10048_state *state, u8 reg,
  225. const u8 *data, u16 len)
  226. {
  227. struct tda10048_config *config = &state->config;
  228. int ret = -EREMOTEIO;
  229. struct i2c_msg msg;
  230. u8 *buf;
  231. dprintk(2, "%s(%d, ?, len = %d)\n", __func__, reg, len);
  232. buf = kmalloc(len + 1, GFP_KERNEL);
  233. if (buf == NULL) {
  234. ret = -ENOMEM;
  235. goto error;
  236. }
  237. *buf = reg;
  238. memcpy(buf + 1, data, len);
  239. msg.addr = config->demod_address;
  240. msg.flags = 0;
  241. msg.buf = buf;
  242. msg.len = len + 1;
  243. dprintk(2, "%s(): write len = %d\n",
  244. __func__, msg.len);
  245. ret = i2c_transfer(state->i2c, &msg, 1);
  246. if (ret != 1) {
  247. printk(KERN_ERR "%s(): writereg error err %i\n",
  248. __func__, ret);
  249. ret = -EREMOTEIO;
  250. }
  251. error:
  252. kfree(buf);
  253. return ret;
  254. }
  255. static int tda10048_set_phy2(struct dvb_frontend *fe, u32 sample_freq_hz,
  256. u32 if_hz)
  257. {
  258. struct tda10048_state *state = fe->demodulator_priv;
  259. u64 t;
  260. dprintk(1, "%s()\n", __func__);
  261. if (sample_freq_hz == 0)
  262. return -EINVAL;
  263. if (if_hz < (sample_freq_hz / 2)) {
  264. /* PHY2 = (if2/fs) * 2^15 */
  265. t = if_hz;
  266. t *= 10;
  267. t *= 32768;
  268. do_div(t, sample_freq_hz);
  269. t += 5;
  270. do_div(t, 10);
  271. } else {
  272. /* PHY2 = ((IF1-fs)/fs) * 2^15 */
  273. t = sample_freq_hz - if_hz;
  274. t *= 10;
  275. t *= 32768;
  276. do_div(t, sample_freq_hz);
  277. t += 5;
  278. do_div(t, 10);
  279. t = ~t + 1;
  280. }
  281. tda10048_writereg(state, TDA10048_FREQ_PHY2_LSB, (u8)t);
  282. tda10048_writereg(state, TDA10048_FREQ_PHY2_MSB, (u8)(t >> 8));
  283. return 0;
  284. }
  285. static int tda10048_set_wref(struct dvb_frontend *fe, u32 sample_freq_hz,
  286. u32 bw)
  287. {
  288. struct tda10048_state *state = fe->demodulator_priv;
  289. u64 t, z;
  290. dprintk(1, "%s()\n", __func__);
  291. if (sample_freq_hz == 0)
  292. return -EINVAL;
  293. /* WREF = (B / (7 * fs)) * 2^31 */
  294. t = bw * 10;
  295. /* avoid warning: this decimal constant is unsigned only in ISO C90 */
  296. /* t *= 2147483648 on 32bit platforms */
  297. t *= (2048 * 1024);
  298. t *= 1024;
  299. z = 7 * sample_freq_hz;
  300. do_div(t, z);
  301. t += 5;
  302. do_div(t, 10);
  303. tda10048_writereg(state, TDA10048_TIME_WREF_LSB, (u8)t);
  304. tda10048_writereg(state, TDA10048_TIME_WREF_MID1, (u8)(t >> 8));
  305. tda10048_writereg(state, TDA10048_TIME_WREF_MID2, (u8)(t >> 16));
  306. tda10048_writereg(state, TDA10048_TIME_WREF_MSB, (u8)(t >> 24));
  307. return 0;
  308. }
  309. static int tda10048_set_invwref(struct dvb_frontend *fe, u32 sample_freq_hz,
  310. u32 bw)
  311. {
  312. struct tda10048_state *state = fe->demodulator_priv;
  313. u64 t;
  314. dprintk(1, "%s()\n", __func__);
  315. if (sample_freq_hz == 0)
  316. return -EINVAL;
  317. /* INVWREF = ((7 * fs) / B) * 2^5 */
  318. t = sample_freq_hz;
  319. t *= 7;
  320. t *= 32;
  321. t *= 10;
  322. do_div(t, bw);
  323. t += 5;
  324. do_div(t, 10);
  325. tda10048_writereg(state, TDA10048_TIME_INVWREF_LSB, (u8)t);
  326. tda10048_writereg(state, TDA10048_TIME_INVWREF_MSB, (u8)(t >> 8));
  327. return 0;
  328. }
  329. static int tda10048_set_bandwidth(struct dvb_frontend *fe,
  330. u32 bw)
  331. {
  332. struct tda10048_state *state = fe->demodulator_priv;
  333. dprintk(1, "%s(bw=%d)\n", __func__, bw);
  334. /* Bandwidth setting may need to be adjusted */
  335. switch (bw) {
  336. case 6000000:
  337. case 7000000:
  338. case 8000000:
  339. tda10048_set_wref(fe, state->sample_freq, bw);
  340. tda10048_set_invwref(fe, state->sample_freq, bw);
  341. break;
  342. default:
  343. printk(KERN_ERR "%s() invalid bandwidth\n", __func__);
  344. return -EINVAL;
  345. }
  346. state->bandwidth = bw;
  347. return 0;
  348. }
  349. static int tda10048_set_if(struct dvb_frontend *fe, u32 bw)
  350. {
  351. struct tda10048_state *state = fe->demodulator_priv;
  352. struct tda10048_config *config = &state->config;
  353. int i;
  354. u32 if_freq_khz;
  355. dprintk(1, "%s(bw = %d)\n", __func__, bw);
  356. /* based on target bandwidth and clk we calculate pll factors */
  357. switch (bw) {
  358. case 6000000:
  359. if_freq_khz = config->dtv6_if_freq_khz;
  360. break;
  361. case 7000000:
  362. if_freq_khz = config->dtv7_if_freq_khz;
  363. break;
  364. case 8000000:
  365. if_freq_khz = config->dtv8_if_freq_khz;
  366. break;
  367. default:
  368. printk(KERN_ERR "%s() no default\n", __func__);
  369. return -EINVAL;
  370. }
  371. for (i = 0; i < ARRAY_SIZE(pll_tab); i++) {
  372. if ((pll_tab[i].clk_freq_khz == config->clk_freq_khz) &&
  373. (pll_tab[i].if_freq_khz == if_freq_khz)) {
  374. state->freq_if_hz = pll_tab[i].if_freq_khz * 1000;
  375. state->xtal_hz = pll_tab[i].clk_freq_khz * 1000;
  376. break;
  377. }
  378. }
  379. if (i == ARRAY_SIZE(pll_tab)) {
  380. printk(KERN_ERR "%s() Incorrect attach settings\n",
  381. __func__);
  382. return -EINVAL;
  383. }
  384. dprintk(1, "- freq_if_hz = %d\n", state->freq_if_hz);
  385. dprintk(1, "- xtal_hz = %d\n", state->xtal_hz);
  386. dprintk(1, "- pll_mfactor = %d\n", state->pll_mfactor);
  387. dprintk(1, "- pll_nfactor = %d\n", state->pll_nfactor);
  388. dprintk(1, "- pll_pfactor = %d\n", state->pll_pfactor);
  389. /* Calculate the sample frequency */
  390. state->sample_freq = state->xtal_hz * (state->pll_mfactor + 45);
  391. state->sample_freq /= (state->pll_nfactor + 1);
  392. state->sample_freq /= (state->pll_pfactor + 4);
  393. dprintk(1, "- sample_freq = %d\n", state->sample_freq);
  394. /* Update the I/F */
  395. tda10048_set_phy2(fe, state->sample_freq, state->freq_if_hz);
  396. return 0;
  397. }
  398. static int tda10048_firmware_upload(struct dvb_frontend *fe)
  399. {
  400. struct tda10048_state *state = fe->demodulator_priv;
  401. struct tda10048_config *config = &state->config;
  402. const struct firmware *fw;
  403. int ret;
  404. int pos = 0;
  405. int cnt;
  406. u8 wlen = config->fwbulkwritelen;
  407. if ((wlen != TDA10048_BULKWRITE_200) && (wlen != TDA10048_BULKWRITE_50))
  408. wlen = TDA10048_BULKWRITE_200;
  409. /* request the firmware, this will block and timeout */
  410. printk(KERN_INFO "%s: waiting for firmware upload (%s)...\n",
  411. __func__,
  412. TDA10048_DEFAULT_FIRMWARE);
  413. ret = request_firmware(&fw, TDA10048_DEFAULT_FIRMWARE,
  414. state->i2c->dev.parent);
  415. if (ret) {
  416. printk(KERN_ERR "%s: Upload failed. (file not found?)\n",
  417. __func__);
  418. return -EIO;
  419. } else {
  420. printk(KERN_INFO "%s: firmware read %zu bytes.\n",
  421. __func__,
  422. fw->size);
  423. ret = 0;
  424. }
  425. if (fw->size != TDA10048_DEFAULT_FIRMWARE_SIZE) {
  426. printk(KERN_ERR "%s: firmware incorrect size\n", __func__);
  427. ret = -EIO;
  428. } else {
  429. printk(KERN_INFO "%s: firmware uploading\n", __func__);
  430. /* Soft reset */
  431. tda10048_writereg(state, TDA10048_CONF_TRISTATE1,
  432. tda10048_readreg(state, TDA10048_CONF_TRISTATE1)
  433. & 0xfe);
  434. tda10048_writereg(state, TDA10048_CONF_TRISTATE1,
  435. tda10048_readreg(state, TDA10048_CONF_TRISTATE1)
  436. | 0x01);
  437. /* Put the demod into host download mode */
  438. tda10048_writereg(state, TDA10048_CONF_C4_1,
  439. tda10048_readreg(state, TDA10048_CONF_C4_1) & 0xf9);
  440. /* Boot the DSP */
  441. tda10048_writereg(state, TDA10048_CONF_C4_1,
  442. tda10048_readreg(state, TDA10048_CONF_C4_1) | 0x08);
  443. /* Prepare for download */
  444. tda10048_writereg(state, TDA10048_DSP_CODE_CPT, 0);
  445. /* Download the firmware payload */
  446. while (pos < fw->size) {
  447. if ((fw->size - pos) > wlen)
  448. cnt = wlen;
  449. else
  450. cnt = fw->size - pos;
  451. tda10048_writeregbulk(state, TDA10048_DSP_CODE_IN,
  452. &fw->data[pos], cnt);
  453. pos += cnt;
  454. }
  455. ret = -EIO;
  456. /* Wait up to 250ms for the DSP to boot */
  457. for (cnt = 0; cnt < 250 ; cnt += 10) {
  458. msleep(10);
  459. if (tda10048_readreg(state, TDA10048_SYNC_STATUS)
  460. & 0x40) {
  461. ret = 0;
  462. break;
  463. }
  464. }
  465. }
  466. release_firmware(fw);
  467. if (ret == 0) {
  468. printk(KERN_INFO "%s: firmware uploaded\n", __func__);
  469. state->fwloaded = 1;
  470. } else
  471. printk(KERN_ERR "%s: firmware upload failed\n", __func__);
  472. return ret;
  473. }
  474. static int tda10048_set_inversion(struct dvb_frontend *fe, int inversion)
  475. {
  476. struct tda10048_state *state = fe->demodulator_priv;
  477. dprintk(1, "%s(%d)\n", __func__, inversion);
  478. if (inversion == TDA10048_INVERSION_ON)
  479. tda10048_writereg(state, TDA10048_CONF_C1_1,
  480. tda10048_readreg(state, TDA10048_CONF_C1_1) | 0x20);
  481. else
  482. tda10048_writereg(state, TDA10048_CONF_C1_1,
  483. tda10048_readreg(state, TDA10048_CONF_C1_1) & 0xdf);
  484. return 0;
  485. }
  486. /* Retrieve the demod settings */
  487. static int tda10048_get_tps(struct tda10048_state *state,
  488. struct dtv_frontend_properties *p)
  489. {
  490. u8 val;
  491. /* Make sure the TPS regs are valid */
  492. if (!(tda10048_readreg(state, TDA10048_AUTO) & 0x01))
  493. return -EAGAIN;
  494. val = tda10048_readreg(state, TDA10048_OUT_CONF2);
  495. switch ((val & 0x60) >> 5) {
  496. case 0:
  497. p->modulation = QPSK;
  498. break;
  499. case 1:
  500. p->modulation = QAM_16;
  501. break;
  502. case 2:
  503. p->modulation = QAM_64;
  504. break;
  505. }
  506. switch ((val & 0x18) >> 3) {
  507. case 0:
  508. p->hierarchy = HIERARCHY_NONE;
  509. break;
  510. case 1:
  511. p->hierarchy = HIERARCHY_1;
  512. break;
  513. case 2:
  514. p->hierarchy = HIERARCHY_2;
  515. break;
  516. case 3:
  517. p->hierarchy = HIERARCHY_4;
  518. break;
  519. }
  520. switch (val & 0x07) {
  521. case 0:
  522. p->code_rate_HP = FEC_1_2;
  523. break;
  524. case 1:
  525. p->code_rate_HP = FEC_2_3;
  526. break;
  527. case 2:
  528. p->code_rate_HP = FEC_3_4;
  529. break;
  530. case 3:
  531. p->code_rate_HP = FEC_5_6;
  532. break;
  533. case 4:
  534. p->code_rate_HP = FEC_7_8;
  535. break;
  536. }
  537. val = tda10048_readreg(state, TDA10048_OUT_CONF3);
  538. switch (val & 0x07) {
  539. case 0:
  540. p->code_rate_LP = FEC_1_2;
  541. break;
  542. case 1:
  543. p->code_rate_LP = FEC_2_3;
  544. break;
  545. case 2:
  546. p->code_rate_LP = FEC_3_4;
  547. break;
  548. case 3:
  549. p->code_rate_LP = FEC_5_6;
  550. break;
  551. case 4:
  552. p->code_rate_LP = FEC_7_8;
  553. break;
  554. }
  555. val = tda10048_readreg(state, TDA10048_OUT_CONF1);
  556. switch ((val & 0x0c) >> 2) {
  557. case 0:
  558. p->guard_interval = GUARD_INTERVAL_1_32;
  559. break;
  560. case 1:
  561. p->guard_interval = GUARD_INTERVAL_1_16;
  562. break;
  563. case 2:
  564. p->guard_interval = GUARD_INTERVAL_1_8;
  565. break;
  566. case 3:
  567. p->guard_interval = GUARD_INTERVAL_1_4;
  568. break;
  569. }
  570. switch (val & 0x03) {
  571. case 0:
  572. p->transmission_mode = TRANSMISSION_MODE_2K;
  573. break;
  574. case 1:
  575. p->transmission_mode = TRANSMISSION_MODE_8K;
  576. break;
  577. }
  578. return 0;
  579. }
  580. static int tda10048_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
  581. {
  582. struct tda10048_state *state = fe->demodulator_priv;
  583. struct tda10048_config *config = &state->config;
  584. dprintk(1, "%s(%d)\n", __func__, enable);
  585. if (config->disable_gate_access)
  586. return 0;
  587. if (enable)
  588. return tda10048_writereg(state, TDA10048_CONF_C4_1,
  589. tda10048_readreg(state, TDA10048_CONF_C4_1) | 0x02);
  590. else
  591. return tda10048_writereg(state, TDA10048_CONF_C4_1,
  592. tda10048_readreg(state, TDA10048_CONF_C4_1) & 0xfd);
  593. }
  594. static int tda10048_output_mode(struct dvb_frontend *fe, int serial)
  595. {
  596. struct tda10048_state *state = fe->demodulator_priv;
  597. dprintk(1, "%s(%d)\n", __func__, serial);
  598. /* Ensure pins are out of tri-state */
  599. tda10048_writereg(state, TDA10048_CONF_TRISTATE1, 0x21);
  600. tda10048_writereg(state, TDA10048_CONF_TRISTATE2, 0x00);
  601. if (serial) {
  602. tda10048_writereg(state, TDA10048_IC_MODE, 0x80 | 0x20);
  603. tda10048_writereg(state, TDA10048_CONF_TS2, 0xc0);
  604. } else {
  605. tda10048_writereg(state, TDA10048_IC_MODE, 0x00);
  606. tda10048_writereg(state, TDA10048_CONF_TS2, 0x01);
  607. }
  608. return 0;
  609. }
  610. /* Talk to the demod, set the FEC, GUARD, QAM settings etc */
  611. /* TODO: Support manual tuning with specific params */
  612. static int tda10048_set_frontend(struct dvb_frontend *fe)
  613. {
  614. struct dtv_frontend_properties *p = &fe->dtv_property_cache;
  615. struct tda10048_state *state = fe->demodulator_priv;
  616. dprintk(1, "%s(frequency=%d)\n", __func__, p->frequency);
  617. /* Update the I/F pll's if the bandwidth changes */
  618. if (p->bandwidth_hz != state->bandwidth) {
  619. tda10048_set_if(fe, p->bandwidth_hz);
  620. tda10048_set_bandwidth(fe, p->bandwidth_hz);
  621. }
  622. if (fe->ops.tuner_ops.set_params) {
  623. if (fe->ops.i2c_gate_ctrl)
  624. fe->ops.i2c_gate_ctrl(fe, 1);
  625. fe->ops.tuner_ops.set_params(fe);
  626. if (fe->ops.i2c_gate_ctrl)
  627. fe->ops.i2c_gate_ctrl(fe, 0);
  628. }
  629. /* Enable demod TPS auto detection and begin acquisition */
  630. tda10048_writereg(state, TDA10048_AUTO, 0x57);
  631. /* trigger cber and vber acquisition */
  632. tda10048_writereg(state, TDA10048_CVBER_CTRL, 0x3B);
  633. return 0;
  634. }
  635. /* Establish sane defaults and load firmware. */
  636. static int tda10048_init(struct dvb_frontend *fe)
  637. {
  638. struct tda10048_state *state = fe->demodulator_priv;
  639. struct tda10048_config *config = &state->config;
  640. int ret = 0, i;
  641. dprintk(1, "%s()\n", __func__);
  642. /* PLL */
  643. init_tab[4].data = (u8)(state->pll_mfactor);
  644. init_tab[5].data = (u8)(state->pll_nfactor) | 0x40;
  645. /* Apply register defaults */
  646. for (i = 0; i < ARRAY_SIZE(init_tab); i++)
  647. tda10048_writereg(state, init_tab[i].reg, init_tab[i].data);
  648. if (state->fwloaded == 0)
  649. ret = tda10048_firmware_upload(fe);
  650. /* Set either serial or parallel */
  651. tda10048_output_mode(fe, config->output_mode);
  652. /* Set inversion */
  653. tda10048_set_inversion(fe, config->inversion);
  654. /* Establish default RF values */
  655. tda10048_set_if(fe, 8000000);
  656. tda10048_set_bandwidth(fe, 8000000);
  657. /* Ensure we leave the gate closed */
  658. tda10048_i2c_gate_ctrl(fe, 0);
  659. return ret;
  660. }
  661. static int tda10048_read_status(struct dvb_frontend *fe, enum fe_status *status)
  662. {
  663. struct tda10048_state *state = fe->demodulator_priv;
  664. u8 reg;
  665. *status = 0;
  666. reg = tda10048_readreg(state, TDA10048_SYNC_STATUS);
  667. dprintk(1, "%s() status =0x%02x\n", __func__, reg);
  668. if (reg & 0x02)
  669. *status |= FE_HAS_CARRIER;
  670. if (reg & 0x04)
  671. *status |= FE_HAS_SIGNAL;
  672. if (reg & 0x08) {
  673. *status |= FE_HAS_LOCK;
  674. *status |= FE_HAS_VITERBI;
  675. *status |= FE_HAS_SYNC;
  676. }
  677. return 0;
  678. }
  679. static int tda10048_read_ber(struct dvb_frontend *fe, u32 *ber)
  680. {
  681. struct tda10048_state *state = fe->demodulator_priv;
  682. static u32 cber_current;
  683. u32 cber_nmax;
  684. u64 cber_tmp;
  685. dprintk(1, "%s()\n", __func__);
  686. /* update cber on interrupt */
  687. if (tda10048_readreg(state, TDA10048_SOFT_IT_C3) & 0x01) {
  688. cber_tmp = tda10048_readreg(state, TDA10048_CBER_MSB) << 8 |
  689. tda10048_readreg(state, TDA10048_CBER_LSB);
  690. cber_nmax = tda10048_readreg(state, TDA10048_CBER_NMAX_MSB) << 8 |
  691. tda10048_readreg(state, TDA10048_CBER_NMAX_LSB);
  692. cber_tmp *= 100000000;
  693. cber_tmp *= 2;
  694. cber_tmp = div_u64(cber_tmp, (cber_nmax * 32) + 1);
  695. cber_current = (u32)cber_tmp;
  696. /* retrigger cber acquisition */
  697. tda10048_writereg(state, TDA10048_CVBER_CTRL, 0x39);
  698. }
  699. /* actual cber is (*ber)/1e8 */
  700. *ber = cber_current;
  701. return 0;
  702. }
  703. static int tda10048_read_signal_strength(struct dvb_frontend *fe,
  704. u16 *signal_strength)
  705. {
  706. struct tda10048_state *state = fe->demodulator_priv;
  707. u8 v;
  708. dprintk(1, "%s()\n", __func__);
  709. *signal_strength = 65535;
  710. v = tda10048_readreg(state, TDA10048_NP_OUT);
  711. if (v > 0)
  712. *signal_strength -= (v << 8) | v;
  713. return 0;
  714. }
  715. /* SNR lookup table */
  716. static struct snr_tab {
  717. u8 val;
  718. u8 data;
  719. } snr_tab[] = {
  720. { 0, 0 },
  721. { 1, 246 },
  722. { 2, 215 },
  723. { 3, 198 },
  724. { 4, 185 },
  725. { 5, 176 },
  726. { 6, 168 },
  727. { 7, 161 },
  728. { 8, 155 },
  729. { 9, 150 },
  730. { 10, 146 },
  731. { 11, 141 },
  732. { 12, 138 },
  733. { 13, 134 },
  734. { 14, 131 },
  735. { 15, 128 },
  736. { 16, 125 },
  737. { 17, 122 },
  738. { 18, 120 },
  739. { 19, 118 },
  740. { 20, 115 },
  741. { 21, 113 },
  742. { 22, 111 },
  743. { 23, 109 },
  744. { 24, 107 },
  745. { 25, 106 },
  746. { 26, 104 },
  747. { 27, 102 },
  748. { 28, 101 },
  749. { 29, 99 },
  750. { 30, 98 },
  751. { 31, 96 },
  752. { 32, 95 },
  753. { 33, 94 },
  754. { 34, 92 },
  755. { 35, 91 },
  756. { 36, 90 },
  757. { 37, 89 },
  758. { 38, 88 },
  759. { 39, 86 },
  760. { 40, 85 },
  761. { 41, 84 },
  762. { 42, 83 },
  763. { 43, 82 },
  764. { 44, 81 },
  765. { 45, 80 },
  766. { 46, 79 },
  767. { 47, 78 },
  768. { 48, 77 },
  769. { 49, 76 },
  770. { 50, 76 },
  771. { 51, 75 },
  772. { 52, 74 },
  773. { 53, 73 },
  774. { 54, 72 },
  775. { 56, 71 },
  776. { 57, 70 },
  777. { 58, 69 },
  778. { 60, 68 },
  779. { 61, 67 },
  780. { 63, 66 },
  781. { 64, 65 },
  782. { 66, 64 },
  783. { 67, 63 },
  784. { 68, 62 },
  785. { 69, 62 },
  786. { 70, 61 },
  787. { 72, 60 },
  788. { 74, 59 },
  789. { 75, 58 },
  790. { 77, 57 },
  791. { 79, 56 },
  792. { 81, 55 },
  793. { 83, 54 },
  794. { 85, 53 },
  795. { 87, 52 },
  796. { 89, 51 },
  797. { 91, 50 },
  798. { 93, 49 },
  799. { 95, 48 },
  800. { 97, 47 },
  801. { 100, 46 },
  802. { 102, 45 },
  803. { 104, 44 },
  804. { 107, 43 },
  805. { 109, 42 },
  806. { 112, 41 },
  807. { 114, 40 },
  808. { 117, 39 },
  809. { 120, 38 },
  810. { 123, 37 },
  811. { 125, 36 },
  812. { 128, 35 },
  813. { 131, 34 },
  814. { 134, 33 },
  815. { 138, 32 },
  816. { 141, 31 },
  817. { 144, 30 },
  818. { 147, 29 },
  819. { 151, 28 },
  820. { 154, 27 },
  821. { 158, 26 },
  822. { 162, 25 },
  823. { 165, 24 },
  824. { 169, 23 },
  825. { 173, 22 },
  826. { 177, 21 },
  827. { 181, 20 },
  828. { 186, 19 },
  829. { 190, 18 },
  830. { 194, 17 },
  831. { 199, 16 },
  832. { 204, 15 },
  833. { 208, 14 },
  834. { 213, 13 },
  835. { 218, 12 },
  836. { 223, 11 },
  837. { 229, 10 },
  838. { 234, 9 },
  839. { 239, 8 },
  840. { 245, 7 },
  841. { 251, 6 },
  842. { 255, 5 },
  843. };
  844. static int tda10048_read_snr(struct dvb_frontend *fe, u16 *snr)
  845. {
  846. struct tda10048_state *state = fe->demodulator_priv;
  847. u8 v;
  848. int i, ret = -EINVAL;
  849. dprintk(1, "%s()\n", __func__);
  850. v = tda10048_readreg(state, TDA10048_NP_OUT);
  851. for (i = 0; i < ARRAY_SIZE(snr_tab); i++) {
  852. if (v <= snr_tab[i].val) {
  853. *snr = snr_tab[i].data;
  854. ret = 0;
  855. break;
  856. }
  857. }
  858. return ret;
  859. }
  860. static int tda10048_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
  861. {
  862. struct tda10048_state *state = fe->demodulator_priv;
  863. dprintk(1, "%s()\n", __func__);
  864. *ucblocks = tda10048_readreg(state, TDA10048_UNCOR_CPT_MSB) << 8 |
  865. tda10048_readreg(state, TDA10048_UNCOR_CPT_LSB);
  866. /* clear the uncorrected TS packets counter when saturated */
  867. if (*ucblocks == 0xFFFF)
  868. tda10048_writereg(state, TDA10048_UNCOR_CTRL, 0x80);
  869. return 0;
  870. }
  871. static int tda10048_get_frontend(struct dvb_frontend *fe,
  872. struct dtv_frontend_properties *p)
  873. {
  874. struct tda10048_state *state = fe->demodulator_priv;
  875. dprintk(1, "%s()\n", __func__);
  876. p->inversion = tda10048_readreg(state, TDA10048_CONF_C1_1)
  877. & 0x20 ? INVERSION_ON : INVERSION_OFF;
  878. return tda10048_get_tps(state, p);
  879. }
  880. static int tda10048_get_tune_settings(struct dvb_frontend *fe,
  881. struct dvb_frontend_tune_settings *tune)
  882. {
  883. tune->min_delay_ms = 1000;
  884. return 0;
  885. }
  886. static void tda10048_release(struct dvb_frontend *fe)
  887. {
  888. struct tda10048_state *state = fe->demodulator_priv;
  889. dprintk(1, "%s()\n", __func__);
  890. kfree(state);
  891. }
  892. static void tda10048_establish_defaults(struct dvb_frontend *fe)
  893. {
  894. struct tda10048_state *state = fe->demodulator_priv;
  895. struct tda10048_config *config = &state->config;
  896. /* Validate/default the config */
  897. if (config->dtv6_if_freq_khz == 0) {
  898. config->dtv6_if_freq_khz = TDA10048_IF_4300;
  899. printk(KERN_WARNING "%s() tda10048_config.dtv6_if_freq_khz is not set (defaulting to %d)\n",
  900. __func__,
  901. config->dtv6_if_freq_khz);
  902. }
  903. if (config->dtv7_if_freq_khz == 0) {
  904. config->dtv7_if_freq_khz = TDA10048_IF_4300;
  905. printk(KERN_WARNING "%s() tda10048_config.dtv7_if_freq_khz is not set (defaulting to %d)\n",
  906. __func__,
  907. config->dtv7_if_freq_khz);
  908. }
  909. if (config->dtv8_if_freq_khz == 0) {
  910. config->dtv8_if_freq_khz = TDA10048_IF_4300;
  911. printk(KERN_WARNING "%s() tda10048_config.dtv8_if_freq_khz is not set (defaulting to %d)\n",
  912. __func__,
  913. config->dtv8_if_freq_khz);
  914. }
  915. if (config->clk_freq_khz == 0) {
  916. config->clk_freq_khz = TDA10048_CLK_16000;
  917. printk(KERN_WARNING "%s() tda10048_config.clk_freq_khz is not set (defaulting to %d)\n",
  918. __func__,
  919. config->clk_freq_khz);
  920. }
  921. }
  922. static const struct dvb_frontend_ops tda10048_ops;
  923. struct dvb_frontend *tda10048_attach(const struct tda10048_config *config,
  924. struct i2c_adapter *i2c)
  925. {
  926. struct tda10048_state *state = NULL;
  927. dprintk(1, "%s()\n", __func__);
  928. /* allocate memory for the internal state */
  929. state = kzalloc(sizeof(struct tda10048_state), GFP_KERNEL);
  930. if (state == NULL)
  931. goto error;
  932. /* setup the state and clone the config */
  933. memcpy(&state->config, config, sizeof(*config));
  934. state->i2c = i2c;
  935. state->fwloaded = config->no_firmware;
  936. state->bandwidth = 8000000;
  937. /* check if the demod is present */
  938. if (tda10048_readreg(state, TDA10048_IDENTITY) != 0x048)
  939. goto error;
  940. /* create dvb_frontend */
  941. memcpy(&state->frontend.ops, &tda10048_ops,
  942. sizeof(struct dvb_frontend_ops));
  943. state->frontend.demodulator_priv = state;
  944. /* set pll */
  945. if (config->set_pll) {
  946. state->pll_mfactor = config->pll_m;
  947. state->pll_nfactor = config->pll_n;
  948. state->pll_pfactor = config->pll_p;
  949. } else {
  950. state->pll_mfactor = 10;
  951. state->pll_nfactor = 3;
  952. state->pll_pfactor = 0;
  953. }
  954. /* Establish any defaults the the user didn't pass */
  955. tda10048_establish_defaults(&state->frontend);
  956. /* Set the xtal and freq defaults */
  957. if (tda10048_set_if(&state->frontend, 8000000) != 0)
  958. goto error;
  959. /* Default bandwidth */
  960. if (tda10048_set_bandwidth(&state->frontend, 8000000) != 0)
  961. goto error;
  962. /* Leave the gate closed */
  963. tda10048_i2c_gate_ctrl(&state->frontend, 0);
  964. return &state->frontend;
  965. error:
  966. kfree(state);
  967. return NULL;
  968. }
  969. EXPORT_SYMBOL(tda10048_attach);
  970. static const struct dvb_frontend_ops tda10048_ops = {
  971. .delsys = { SYS_DVBT },
  972. .info = {
  973. .name = "NXP TDA10048HN DVB-T",
  974. .frequency_min_hz = 177 * MHz,
  975. .frequency_max_hz = 858 * MHz,
  976. .frequency_stepsize_hz = 166666,
  977. .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
  978. FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
  979. FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
  980. FE_CAN_HIERARCHY_AUTO | FE_CAN_GUARD_INTERVAL_AUTO |
  981. FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER
  982. },
  983. .release = tda10048_release,
  984. .init = tda10048_init,
  985. .i2c_gate_ctrl = tda10048_i2c_gate_ctrl,
  986. .set_frontend = tda10048_set_frontend,
  987. .get_frontend = tda10048_get_frontend,
  988. .get_tune_settings = tda10048_get_tune_settings,
  989. .read_status = tda10048_read_status,
  990. .read_ber = tda10048_read_ber,
  991. .read_signal_strength = tda10048_read_signal_strength,
  992. .read_snr = tda10048_read_snr,
  993. .read_ucblocks = tda10048_read_ucblocks,
  994. };
  995. module_param(debug, int, 0644);
  996. MODULE_PARM_DESC(debug, "Enable verbose debug messages");
  997. MODULE_DESCRIPTION("NXP TDA10048HN DVB-T Demodulator driver");
  998. MODULE_AUTHOR("Steven Toth");
  999. MODULE_LICENSE("GPL");