stv0900_sw.c 50 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * stv0900_sw.c
  4. *
  5. * Driver for ST STV0900 satellite demodulator IC.
  6. *
  7. * Copyright (C) ST Microelectronics.
  8. * Copyright (C) 2009 NetUP Inc.
  9. * Copyright (C) 2009 Igor M. Liplianin <liplianin@netup.ru>
  10. */
  11. #include "stv0900.h"
  12. #include "stv0900_reg.h"
  13. #include "stv0900_priv.h"
  14. s32 shiftx(s32 x, int demod, s32 shift)
  15. {
  16. if (demod == 1)
  17. return x - shift;
  18. return x;
  19. }
  20. int stv0900_check_signal_presence(struct stv0900_internal *intp,
  21. enum fe_stv0900_demod_num demod)
  22. {
  23. s32 carr_offset,
  24. agc2_integr,
  25. max_carrier;
  26. int no_signal = FALSE;
  27. carr_offset = (stv0900_read_reg(intp, CFR2) << 8)
  28. | stv0900_read_reg(intp, CFR1);
  29. carr_offset = ge2comp(carr_offset, 16);
  30. agc2_integr = (stv0900_read_reg(intp, AGC2I1) << 8)
  31. | stv0900_read_reg(intp, AGC2I0);
  32. max_carrier = intp->srch_range[demod] / 1000;
  33. max_carrier += (max_carrier / 10);
  34. max_carrier = 65536 * (max_carrier / 2);
  35. max_carrier /= intp->mclk / 1000;
  36. if (max_carrier > 0x4000)
  37. max_carrier = 0x4000;
  38. if ((agc2_integr > 0x2000)
  39. || (carr_offset > (2 * max_carrier))
  40. || (carr_offset < (-2 * max_carrier)))
  41. no_signal = TRUE;
  42. return no_signal;
  43. }
  44. static void stv0900_get_sw_loop_params(struct stv0900_internal *intp,
  45. s32 *frequency_inc, s32 *sw_timeout,
  46. s32 *steps,
  47. enum fe_stv0900_demod_num demod)
  48. {
  49. s32 timeout, freq_inc, max_steps, srate, max_carrier;
  50. enum fe_stv0900_search_standard standard;
  51. srate = intp->symbol_rate[demod];
  52. max_carrier = intp->srch_range[demod] / 1000;
  53. max_carrier += max_carrier / 10;
  54. standard = intp->srch_standard[demod];
  55. max_carrier = 65536 * (max_carrier / 2);
  56. max_carrier /= intp->mclk / 1000;
  57. if (max_carrier > 0x4000)
  58. max_carrier = 0x4000;
  59. freq_inc = srate;
  60. freq_inc /= intp->mclk >> 10;
  61. freq_inc = freq_inc << 6;
  62. switch (standard) {
  63. case STV0900_SEARCH_DVBS1:
  64. case STV0900_SEARCH_DSS:
  65. freq_inc *= 3;
  66. timeout = 20;
  67. break;
  68. case STV0900_SEARCH_DVBS2:
  69. freq_inc *= 4;
  70. timeout = 25;
  71. break;
  72. case STV0900_AUTO_SEARCH:
  73. default:
  74. freq_inc *= 3;
  75. timeout = 25;
  76. break;
  77. }
  78. freq_inc /= 100;
  79. if ((freq_inc > max_carrier) || (freq_inc < 0))
  80. freq_inc = max_carrier / 2;
  81. timeout *= 27500;
  82. if (srate > 0)
  83. timeout /= srate / 1000;
  84. if ((timeout > 100) || (timeout < 0))
  85. timeout = 100;
  86. max_steps = (max_carrier / freq_inc) + 1;
  87. if ((max_steps > 100) || (max_steps < 0)) {
  88. max_steps = 100;
  89. freq_inc = max_carrier / max_steps;
  90. }
  91. *frequency_inc = freq_inc;
  92. *sw_timeout = timeout;
  93. *steps = max_steps;
  94. }
  95. static int stv0900_search_carr_sw_loop(struct stv0900_internal *intp,
  96. s32 FreqIncr, s32 Timeout, int zigzag,
  97. s32 MaxStep, enum fe_stv0900_demod_num demod)
  98. {
  99. int no_signal,
  100. lock = FALSE;
  101. s32 stepCpt,
  102. freqOffset,
  103. max_carrier;
  104. max_carrier = intp->srch_range[demod] / 1000;
  105. max_carrier += (max_carrier / 10);
  106. max_carrier = 65536 * (max_carrier / 2);
  107. max_carrier /= intp->mclk / 1000;
  108. if (max_carrier > 0x4000)
  109. max_carrier = 0x4000;
  110. if (zigzag == TRUE)
  111. freqOffset = 0;
  112. else
  113. freqOffset = -max_carrier + FreqIncr;
  114. stepCpt = 0;
  115. do {
  116. stv0900_write_reg(intp, DMDISTATE, 0x1c);
  117. stv0900_write_reg(intp, CFRINIT1, (freqOffset / 256) & 0xff);
  118. stv0900_write_reg(intp, CFRINIT0, freqOffset & 0xff);
  119. stv0900_write_reg(intp, DMDISTATE, 0x18);
  120. stv0900_write_bits(intp, ALGOSWRST, 1);
  121. if (intp->chip_id == 0x12) {
  122. stv0900_write_bits(intp, RST_HWARE, 1);
  123. stv0900_write_bits(intp, RST_HWARE, 0);
  124. }
  125. if (zigzag == TRUE) {
  126. if (freqOffset >= 0)
  127. freqOffset = -freqOffset - 2 * FreqIncr;
  128. else
  129. freqOffset = -freqOffset;
  130. } else
  131. freqOffset += + 2 * FreqIncr;
  132. stepCpt++;
  133. lock = stv0900_get_demod_lock(intp, demod, Timeout);
  134. no_signal = stv0900_check_signal_presence(intp, demod);
  135. } while ((lock == FALSE)
  136. && (no_signal == FALSE)
  137. && ((freqOffset - FreqIncr) < max_carrier)
  138. && ((freqOffset + FreqIncr) > -max_carrier)
  139. && (stepCpt < MaxStep));
  140. stv0900_write_bits(intp, ALGOSWRST, 0);
  141. return lock;
  142. }
  143. static int stv0900_sw_algo(struct stv0900_internal *intp,
  144. enum fe_stv0900_demod_num demod)
  145. {
  146. int lock = FALSE,
  147. no_signal,
  148. zigzag;
  149. s32 s2fw,
  150. fqc_inc,
  151. sft_stp_tout,
  152. trial_cntr,
  153. max_steps;
  154. stv0900_get_sw_loop_params(intp, &fqc_inc, &sft_stp_tout,
  155. &max_steps, demod);
  156. switch (intp->srch_standard[demod]) {
  157. case STV0900_SEARCH_DVBS1:
  158. case STV0900_SEARCH_DSS:
  159. if (intp->chip_id >= 0x20)
  160. stv0900_write_reg(intp, CARFREQ, 0x3b);
  161. else
  162. stv0900_write_reg(intp, CARFREQ, 0xef);
  163. stv0900_write_reg(intp, DMDCFGMD, 0x49);
  164. zigzag = FALSE;
  165. break;
  166. case STV0900_SEARCH_DVBS2:
  167. if (intp->chip_id >= 0x20)
  168. stv0900_write_reg(intp, CORRELABS, 0x79);
  169. else
  170. stv0900_write_reg(intp, CORRELABS, 0x68);
  171. stv0900_write_reg(intp, DMDCFGMD, 0x89);
  172. zigzag = TRUE;
  173. break;
  174. case STV0900_AUTO_SEARCH:
  175. default:
  176. if (intp->chip_id >= 0x20) {
  177. stv0900_write_reg(intp, CARFREQ, 0x3b);
  178. stv0900_write_reg(intp, CORRELABS, 0x79);
  179. } else {
  180. stv0900_write_reg(intp, CARFREQ, 0xef);
  181. stv0900_write_reg(intp, CORRELABS, 0x68);
  182. }
  183. stv0900_write_reg(intp, DMDCFGMD, 0xc9);
  184. zigzag = FALSE;
  185. break;
  186. }
  187. trial_cntr = 0;
  188. do {
  189. lock = stv0900_search_carr_sw_loop(intp,
  190. fqc_inc,
  191. sft_stp_tout,
  192. zigzag,
  193. max_steps,
  194. demod);
  195. no_signal = stv0900_check_signal_presence(intp, demod);
  196. trial_cntr++;
  197. if ((lock == TRUE)
  198. || (no_signal == TRUE)
  199. || (trial_cntr == 2)) {
  200. if (intp->chip_id >= 0x20) {
  201. stv0900_write_reg(intp, CARFREQ, 0x49);
  202. stv0900_write_reg(intp, CORRELABS, 0x9e);
  203. } else {
  204. stv0900_write_reg(intp, CARFREQ, 0xed);
  205. stv0900_write_reg(intp, CORRELABS, 0x88);
  206. }
  207. if ((stv0900_get_bits(intp, HEADER_MODE) ==
  208. STV0900_DVBS2_FOUND) &&
  209. (lock == TRUE)) {
  210. msleep(sft_stp_tout);
  211. s2fw = stv0900_get_bits(intp, FLYWHEEL_CPT);
  212. if (s2fw < 0xd) {
  213. msleep(sft_stp_tout);
  214. s2fw = stv0900_get_bits(intp,
  215. FLYWHEEL_CPT);
  216. }
  217. if (s2fw < 0xd) {
  218. lock = FALSE;
  219. if (trial_cntr < 2) {
  220. if (intp->chip_id >= 0x20)
  221. stv0900_write_reg(intp,
  222. CORRELABS,
  223. 0x79);
  224. else
  225. stv0900_write_reg(intp,
  226. CORRELABS,
  227. 0x68);
  228. stv0900_write_reg(intp,
  229. DMDCFGMD,
  230. 0x89);
  231. }
  232. }
  233. }
  234. }
  235. } while ((lock == FALSE)
  236. && (trial_cntr < 2)
  237. && (no_signal == FALSE));
  238. return lock;
  239. }
  240. static u32 stv0900_get_symbol_rate(struct stv0900_internal *intp,
  241. u32 mclk,
  242. enum fe_stv0900_demod_num demod)
  243. {
  244. s32 rem1, rem2, intval1, intval2, srate;
  245. srate = (stv0900_get_bits(intp, SYMB_FREQ3) << 24) +
  246. (stv0900_get_bits(intp, SYMB_FREQ2) << 16) +
  247. (stv0900_get_bits(intp, SYMB_FREQ1) << 8) +
  248. (stv0900_get_bits(intp, SYMB_FREQ0));
  249. dprintk("lock: srate=%d r0=0x%x r1=0x%x r2=0x%x r3=0x%x \n",
  250. srate, stv0900_get_bits(intp, SYMB_FREQ0),
  251. stv0900_get_bits(intp, SYMB_FREQ1),
  252. stv0900_get_bits(intp, SYMB_FREQ2),
  253. stv0900_get_bits(intp, SYMB_FREQ3));
  254. intval1 = (mclk) >> 16;
  255. intval2 = (srate) >> 16;
  256. rem1 = (mclk) % 0x10000;
  257. rem2 = (srate) % 0x10000;
  258. srate = (intval1 * intval2) +
  259. ((intval1 * rem2) >> 16) +
  260. ((intval2 * rem1) >> 16);
  261. return srate;
  262. }
  263. static void stv0900_set_symbol_rate(struct stv0900_internal *intp,
  264. u32 mclk, u32 srate,
  265. enum fe_stv0900_demod_num demod)
  266. {
  267. u32 symb;
  268. dprintk("%s: Mclk %d, SR %d, Dmd %d\n", __func__, mclk,
  269. srate, demod);
  270. if (srate > 60000000) {
  271. symb = srate << 4;
  272. symb /= (mclk >> 12);
  273. } else if (srate > 6000000) {
  274. symb = srate << 6;
  275. symb /= (mclk >> 10);
  276. } else {
  277. symb = srate << 9;
  278. symb /= (mclk >> 7);
  279. }
  280. stv0900_write_reg(intp, SFRINIT1, (symb >> 8) & 0x7f);
  281. stv0900_write_reg(intp, SFRINIT1 + 1, (symb & 0xff));
  282. }
  283. static void stv0900_set_max_symbol_rate(struct stv0900_internal *intp,
  284. u32 mclk, u32 srate,
  285. enum fe_stv0900_demod_num demod)
  286. {
  287. u32 symb;
  288. srate = 105 * (srate / 100);
  289. if (srate > 60000000) {
  290. symb = srate << 4;
  291. symb /= (mclk >> 12);
  292. } else if (srate > 6000000) {
  293. symb = srate << 6;
  294. symb /= (mclk >> 10);
  295. } else {
  296. symb = srate << 9;
  297. symb /= (mclk >> 7);
  298. }
  299. if (symb < 0x7fff) {
  300. stv0900_write_reg(intp, SFRUP1, (symb >> 8) & 0x7f);
  301. stv0900_write_reg(intp, SFRUP1 + 1, (symb & 0xff));
  302. } else {
  303. stv0900_write_reg(intp, SFRUP1, 0x7f);
  304. stv0900_write_reg(intp, SFRUP1 + 1, 0xff);
  305. }
  306. }
  307. static void stv0900_set_min_symbol_rate(struct stv0900_internal *intp,
  308. u32 mclk, u32 srate,
  309. enum fe_stv0900_demod_num demod)
  310. {
  311. u32 symb;
  312. srate = 95 * (srate / 100);
  313. if (srate > 60000000) {
  314. symb = srate << 4;
  315. symb /= (mclk >> 12);
  316. } else if (srate > 6000000) {
  317. symb = srate << 6;
  318. symb /= (mclk >> 10);
  319. } else {
  320. symb = srate << 9;
  321. symb /= (mclk >> 7);
  322. }
  323. stv0900_write_reg(intp, SFRLOW1, (symb >> 8) & 0xff);
  324. stv0900_write_reg(intp, SFRLOW1 + 1, (symb & 0xff));
  325. }
  326. static s32 stv0900_get_timing_offst(struct stv0900_internal *intp,
  327. u32 srate,
  328. enum fe_stv0900_demod_num demod)
  329. {
  330. s32 timingoffset;
  331. timingoffset = (stv0900_read_reg(intp, TMGREG2) << 16) +
  332. (stv0900_read_reg(intp, TMGREG2 + 1) << 8) +
  333. (stv0900_read_reg(intp, TMGREG2 + 2));
  334. timingoffset = ge2comp(timingoffset, 24);
  335. if (timingoffset == 0)
  336. timingoffset = 1;
  337. timingoffset = ((s32)srate * 10) / ((s32)0x1000000 / timingoffset);
  338. timingoffset /= 320;
  339. return timingoffset;
  340. }
  341. static void stv0900_set_dvbs2_rolloff(struct stv0900_internal *intp,
  342. enum fe_stv0900_demod_num demod)
  343. {
  344. s32 rolloff;
  345. if (intp->chip_id == 0x10) {
  346. stv0900_write_bits(intp, MANUALSX_ROLLOFF, 1);
  347. rolloff = stv0900_read_reg(intp, MATSTR1) & 0x03;
  348. stv0900_write_bits(intp, ROLLOFF_CONTROL, rolloff);
  349. } else if (intp->chip_id <= 0x20)
  350. stv0900_write_bits(intp, MANUALSX_ROLLOFF, 0);
  351. else /* cut 3.0 */
  352. stv0900_write_bits(intp, MANUALS2_ROLLOFF, 0);
  353. }
  354. static u32 stv0900_carrier_width(u32 srate, enum fe_stv0900_rolloff ro)
  355. {
  356. u32 rolloff;
  357. switch (ro) {
  358. case STV0900_20:
  359. rolloff = 20;
  360. break;
  361. case STV0900_25:
  362. rolloff = 25;
  363. break;
  364. case STV0900_35:
  365. default:
  366. rolloff = 35;
  367. break;
  368. }
  369. return srate + (srate * rolloff) / 100;
  370. }
  371. static int stv0900_check_timing_lock(struct stv0900_internal *intp,
  372. enum fe_stv0900_demod_num demod)
  373. {
  374. int timingLock = FALSE;
  375. s32 i,
  376. timingcpt = 0;
  377. u8 car_freq,
  378. tmg_th_high,
  379. tmg_th_low;
  380. car_freq = stv0900_read_reg(intp, CARFREQ);
  381. tmg_th_high = stv0900_read_reg(intp, TMGTHRISE);
  382. tmg_th_low = stv0900_read_reg(intp, TMGTHFALL);
  383. stv0900_write_reg(intp, TMGTHRISE, 0x20);
  384. stv0900_write_reg(intp, TMGTHFALL, 0x0);
  385. stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
  386. stv0900_write_reg(intp, RTC, 0x80);
  387. stv0900_write_reg(intp, RTCS2, 0x40);
  388. stv0900_write_reg(intp, CARFREQ, 0x0);
  389. stv0900_write_reg(intp, CFRINIT1, 0x0);
  390. stv0900_write_reg(intp, CFRINIT0, 0x0);
  391. stv0900_write_reg(intp, AGC2REF, 0x65);
  392. stv0900_write_reg(intp, DMDISTATE, 0x18);
  393. msleep(7);
  394. for (i = 0; i < 10; i++) {
  395. if (stv0900_get_bits(intp, TMGLOCK_QUALITY) >= 2)
  396. timingcpt++;
  397. msleep(1);
  398. }
  399. if (timingcpt >= 3)
  400. timingLock = TRUE;
  401. stv0900_write_reg(intp, AGC2REF, 0x38);
  402. stv0900_write_reg(intp, RTC, 0x88);
  403. stv0900_write_reg(intp, RTCS2, 0x68);
  404. stv0900_write_reg(intp, CARFREQ, car_freq);
  405. stv0900_write_reg(intp, TMGTHRISE, tmg_th_high);
  406. stv0900_write_reg(intp, TMGTHFALL, tmg_th_low);
  407. return timingLock;
  408. }
  409. static int stv0900_get_demod_cold_lock(struct dvb_frontend *fe,
  410. s32 demod_timeout)
  411. {
  412. struct stv0900_state *state = fe->demodulator_priv;
  413. struct stv0900_internal *intp = state->internal;
  414. enum fe_stv0900_demod_num demod = state->demod;
  415. int lock = FALSE,
  416. d = demod;
  417. s32 srate,
  418. search_range,
  419. locktimeout,
  420. currier_step,
  421. nb_steps,
  422. current_step,
  423. direction,
  424. tuner_freq,
  425. timeout,
  426. freq;
  427. srate = intp->symbol_rate[d];
  428. search_range = intp->srch_range[d];
  429. if (srate >= 10000000)
  430. locktimeout = demod_timeout / 3;
  431. else
  432. locktimeout = demod_timeout / 2;
  433. lock = stv0900_get_demod_lock(intp, d, locktimeout);
  434. if (lock != FALSE)
  435. return lock;
  436. if (srate >= 10000000) {
  437. if (stv0900_check_timing_lock(intp, d) == TRUE) {
  438. stv0900_write_reg(intp, DMDISTATE, 0x1f);
  439. stv0900_write_reg(intp, DMDISTATE, 0x15);
  440. lock = stv0900_get_demod_lock(intp, d, demod_timeout);
  441. } else
  442. lock = FALSE;
  443. return lock;
  444. }
  445. if (intp->chip_id <= 0x20) {
  446. if (srate <= 1000000)
  447. currier_step = 500;
  448. else if (srate <= 4000000)
  449. currier_step = 1000;
  450. else if (srate <= 7000000)
  451. currier_step = 2000;
  452. else if (srate <= 10000000)
  453. currier_step = 3000;
  454. else
  455. currier_step = 5000;
  456. if (srate >= 2000000) {
  457. timeout = (demod_timeout / 3);
  458. if (timeout > 1000)
  459. timeout = 1000;
  460. } else
  461. timeout = (demod_timeout / 2);
  462. } else {
  463. /*cut 3.0 */
  464. currier_step = srate / 4000;
  465. timeout = (demod_timeout * 3) / 4;
  466. }
  467. nb_steps = ((search_range / 1000) / currier_step);
  468. if ((nb_steps % 2) != 0)
  469. nb_steps += 1;
  470. if (nb_steps <= 0)
  471. nb_steps = 2;
  472. else if (nb_steps > 12)
  473. nb_steps = 12;
  474. current_step = 1;
  475. direction = 1;
  476. if (intp->chip_id <= 0x20) {
  477. tuner_freq = intp->freq[d];
  478. intp->bw[d] = stv0900_carrier_width(intp->symbol_rate[d],
  479. intp->rolloff) + intp->symbol_rate[d];
  480. } else
  481. tuner_freq = 0;
  482. while ((current_step <= nb_steps) && (lock == FALSE)) {
  483. if (direction > 0)
  484. tuner_freq += (current_step * currier_step);
  485. else
  486. tuner_freq -= (current_step * currier_step);
  487. if (intp->chip_id <= 0x20) {
  488. if (intp->tuner_type[d] == 3)
  489. stv0900_set_tuner_auto(intp, tuner_freq,
  490. intp->bw[d], demod);
  491. else
  492. stv0900_set_tuner(fe, tuner_freq, intp->bw[d]);
  493. stv0900_write_reg(intp, DMDISTATE, 0x1c);
  494. stv0900_write_reg(intp, CFRINIT1, 0);
  495. stv0900_write_reg(intp, CFRINIT0, 0);
  496. stv0900_write_reg(intp, DMDISTATE, 0x1f);
  497. stv0900_write_reg(intp, DMDISTATE, 0x15);
  498. } else {
  499. stv0900_write_reg(intp, DMDISTATE, 0x1c);
  500. freq = (tuner_freq * 65536) / (intp->mclk / 1000);
  501. stv0900_write_bits(intp, CFR_INIT1, MSB(freq));
  502. stv0900_write_bits(intp, CFR_INIT0, LSB(freq));
  503. stv0900_write_reg(intp, DMDISTATE, 0x1f);
  504. stv0900_write_reg(intp, DMDISTATE, 0x05);
  505. }
  506. lock = stv0900_get_demod_lock(intp, d, timeout);
  507. direction *= -1;
  508. current_step++;
  509. }
  510. return lock;
  511. }
  512. static void stv0900_get_lock_timeout(s32 *demod_timeout, s32 *fec_timeout,
  513. s32 srate,
  514. enum fe_stv0900_search_algo algo)
  515. {
  516. switch (algo) {
  517. case STV0900_BLIND_SEARCH:
  518. if (srate <= 1500000) {
  519. (*demod_timeout) = 1500;
  520. (*fec_timeout) = 400;
  521. } else if (srate <= 5000000) {
  522. (*demod_timeout) = 1000;
  523. (*fec_timeout) = 300;
  524. } else {
  525. (*demod_timeout) = 700;
  526. (*fec_timeout) = 100;
  527. }
  528. break;
  529. case STV0900_COLD_START:
  530. case STV0900_WARM_START:
  531. default:
  532. if (srate <= 1000000) {
  533. (*demod_timeout) = 3000;
  534. (*fec_timeout) = 1700;
  535. } else if (srate <= 2000000) {
  536. (*demod_timeout) = 2500;
  537. (*fec_timeout) = 1100;
  538. } else if (srate <= 5000000) {
  539. (*demod_timeout) = 1000;
  540. (*fec_timeout) = 550;
  541. } else if (srate <= 10000000) {
  542. (*demod_timeout) = 700;
  543. (*fec_timeout) = 250;
  544. } else if (srate <= 20000000) {
  545. (*demod_timeout) = 400;
  546. (*fec_timeout) = 130;
  547. } else {
  548. (*demod_timeout) = 300;
  549. (*fec_timeout) = 100;
  550. }
  551. break;
  552. }
  553. if (algo == STV0900_WARM_START)
  554. (*demod_timeout) /= 2;
  555. }
  556. static void stv0900_set_viterbi_tracq(struct stv0900_internal *intp,
  557. enum fe_stv0900_demod_num demod)
  558. {
  559. s32 vth_reg = VTH12;
  560. dprintk("%s\n", __func__);
  561. stv0900_write_reg(intp, vth_reg++, 0xd0);
  562. stv0900_write_reg(intp, vth_reg++, 0x7d);
  563. stv0900_write_reg(intp, vth_reg++, 0x53);
  564. stv0900_write_reg(intp, vth_reg++, 0x2f);
  565. stv0900_write_reg(intp, vth_reg++, 0x24);
  566. stv0900_write_reg(intp, vth_reg++, 0x1f);
  567. }
  568. static void stv0900_set_viterbi_standard(struct stv0900_internal *intp,
  569. enum fe_stv0900_search_standard standard,
  570. enum fe_stv0900_fec fec,
  571. enum fe_stv0900_demod_num demod)
  572. {
  573. dprintk("%s: ViterbiStandard = ", __func__);
  574. switch (standard) {
  575. case STV0900_AUTO_SEARCH:
  576. dprintk("Auto\n");
  577. stv0900_write_reg(intp, FECM, 0x10);
  578. stv0900_write_reg(intp, PRVIT, 0x3f);
  579. break;
  580. case STV0900_SEARCH_DVBS1:
  581. dprintk("DVBS1\n");
  582. stv0900_write_reg(intp, FECM, 0x00);
  583. switch (fec) {
  584. case STV0900_FEC_UNKNOWN:
  585. default:
  586. stv0900_write_reg(intp, PRVIT, 0x2f);
  587. break;
  588. case STV0900_FEC_1_2:
  589. stv0900_write_reg(intp, PRVIT, 0x01);
  590. break;
  591. case STV0900_FEC_2_3:
  592. stv0900_write_reg(intp, PRVIT, 0x02);
  593. break;
  594. case STV0900_FEC_3_4:
  595. stv0900_write_reg(intp, PRVIT, 0x04);
  596. break;
  597. case STV0900_FEC_5_6:
  598. stv0900_write_reg(intp, PRVIT, 0x08);
  599. break;
  600. case STV0900_FEC_7_8:
  601. stv0900_write_reg(intp, PRVIT, 0x20);
  602. break;
  603. }
  604. break;
  605. case STV0900_SEARCH_DSS:
  606. dprintk("DSS\n");
  607. stv0900_write_reg(intp, FECM, 0x80);
  608. switch (fec) {
  609. case STV0900_FEC_UNKNOWN:
  610. default:
  611. stv0900_write_reg(intp, PRVIT, 0x13);
  612. break;
  613. case STV0900_FEC_1_2:
  614. stv0900_write_reg(intp, PRVIT, 0x01);
  615. break;
  616. case STV0900_FEC_2_3:
  617. stv0900_write_reg(intp, PRVIT, 0x02);
  618. break;
  619. case STV0900_FEC_6_7:
  620. stv0900_write_reg(intp, PRVIT, 0x10);
  621. break;
  622. }
  623. break;
  624. default:
  625. break;
  626. }
  627. }
  628. static enum fe_stv0900_fec stv0900_get_vit_fec(struct stv0900_internal *intp,
  629. enum fe_stv0900_demod_num demod)
  630. {
  631. enum fe_stv0900_fec prate;
  632. s32 rate_fld = stv0900_get_bits(intp, VIT_CURPUN);
  633. switch (rate_fld) {
  634. case 13:
  635. prate = STV0900_FEC_1_2;
  636. break;
  637. case 18:
  638. prate = STV0900_FEC_2_3;
  639. break;
  640. case 21:
  641. prate = STV0900_FEC_3_4;
  642. break;
  643. case 24:
  644. prate = STV0900_FEC_5_6;
  645. break;
  646. case 25:
  647. prate = STV0900_FEC_6_7;
  648. break;
  649. case 26:
  650. prate = STV0900_FEC_7_8;
  651. break;
  652. default:
  653. prate = STV0900_FEC_UNKNOWN;
  654. break;
  655. }
  656. return prate;
  657. }
  658. static void stv0900_set_dvbs1_track_car_loop(struct stv0900_internal *intp,
  659. enum fe_stv0900_demod_num demod,
  660. u32 srate)
  661. {
  662. if (intp->chip_id >= 0x30) {
  663. if (srate >= 15000000) {
  664. stv0900_write_reg(intp, ACLC, 0x2b);
  665. stv0900_write_reg(intp, BCLC, 0x1a);
  666. } else if ((srate >= 7000000) && (15000000 > srate)) {
  667. stv0900_write_reg(intp, ACLC, 0x0c);
  668. stv0900_write_reg(intp, BCLC, 0x1b);
  669. } else if (srate < 7000000) {
  670. stv0900_write_reg(intp, ACLC, 0x2c);
  671. stv0900_write_reg(intp, BCLC, 0x1c);
  672. }
  673. } else { /*cut 2.0 and 1.x*/
  674. stv0900_write_reg(intp, ACLC, 0x1a);
  675. stv0900_write_reg(intp, BCLC, 0x09);
  676. }
  677. }
  678. static void stv0900_track_optimization(struct dvb_frontend *fe)
  679. {
  680. struct stv0900_state *state = fe->demodulator_priv;
  681. struct stv0900_internal *intp = state->internal;
  682. enum fe_stv0900_demod_num demod = state->demod;
  683. s32 srate,
  684. pilots,
  685. aclc,
  686. freq1,
  687. freq0,
  688. i = 0,
  689. timed,
  690. timef,
  691. blind_tun_sw = 0,
  692. modulation;
  693. enum fe_stv0900_modcode foundModcod;
  694. dprintk("%s\n", __func__);
  695. srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
  696. srate += stv0900_get_timing_offst(intp, srate, demod);
  697. switch (intp->result[demod].standard) {
  698. case STV0900_DVBS1_STANDARD:
  699. case STV0900_DSS_STANDARD:
  700. dprintk("%s: found DVB-S or DSS\n", __func__);
  701. if (intp->srch_standard[demod] == STV0900_AUTO_SEARCH) {
  702. stv0900_write_bits(intp, DVBS1_ENABLE, 1);
  703. stv0900_write_bits(intp, DVBS2_ENABLE, 0);
  704. }
  705. stv0900_write_bits(intp, ROLLOFF_CONTROL, intp->rolloff);
  706. stv0900_write_bits(intp, MANUALSX_ROLLOFF, 1);
  707. if (intp->chip_id < 0x30) {
  708. stv0900_write_reg(intp, ERRCTRL1, 0x75);
  709. break;
  710. }
  711. if (stv0900_get_vit_fec(intp, demod) == STV0900_FEC_1_2) {
  712. stv0900_write_reg(intp, GAUSSR0, 0x98);
  713. stv0900_write_reg(intp, CCIR0, 0x18);
  714. } else {
  715. stv0900_write_reg(intp, GAUSSR0, 0x18);
  716. stv0900_write_reg(intp, CCIR0, 0x18);
  717. }
  718. stv0900_write_reg(intp, ERRCTRL1, 0x75);
  719. break;
  720. case STV0900_DVBS2_STANDARD:
  721. dprintk("%s: found DVB-S2\n", __func__);
  722. stv0900_write_bits(intp, DVBS1_ENABLE, 0);
  723. stv0900_write_bits(intp, DVBS2_ENABLE, 1);
  724. stv0900_write_reg(intp, ACLC, 0);
  725. stv0900_write_reg(intp, BCLC, 0);
  726. if (intp->result[demod].frame_len == STV0900_LONG_FRAME) {
  727. foundModcod = stv0900_get_bits(intp, DEMOD_MODCOD);
  728. pilots = stv0900_get_bits(intp, DEMOD_TYPE) & 0x01;
  729. aclc = stv0900_get_optim_carr_loop(srate,
  730. foundModcod,
  731. pilots,
  732. intp->chip_id);
  733. if (foundModcod <= STV0900_QPSK_910)
  734. stv0900_write_reg(intp, ACLC2S2Q, aclc);
  735. else if (foundModcod <= STV0900_8PSK_910) {
  736. stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
  737. stv0900_write_reg(intp, ACLC2S28, aclc);
  738. }
  739. if ((intp->demod_mode == STV0900_SINGLE) &&
  740. (foundModcod > STV0900_8PSK_910)) {
  741. if (foundModcod <= STV0900_16APSK_910) {
  742. stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
  743. stv0900_write_reg(intp, ACLC2S216A,
  744. aclc);
  745. } else if (foundModcod <= STV0900_32APSK_910) {
  746. stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
  747. stv0900_write_reg(intp, ACLC2S232A,
  748. aclc);
  749. }
  750. }
  751. } else {
  752. modulation = intp->result[demod].modulation;
  753. aclc = stv0900_get_optim_short_carr_loop(srate,
  754. modulation, intp->chip_id);
  755. if (modulation == STV0900_QPSK)
  756. stv0900_write_reg(intp, ACLC2S2Q, aclc);
  757. else if (modulation == STV0900_8PSK) {
  758. stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
  759. stv0900_write_reg(intp, ACLC2S28, aclc);
  760. } else if (modulation == STV0900_16APSK) {
  761. stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
  762. stv0900_write_reg(intp, ACLC2S216A, aclc);
  763. } else if (modulation == STV0900_32APSK) {
  764. stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
  765. stv0900_write_reg(intp, ACLC2S232A, aclc);
  766. }
  767. }
  768. if (intp->chip_id <= 0x11) {
  769. if (intp->demod_mode != STV0900_SINGLE)
  770. stv0900_activate_s2_modcod(intp, demod);
  771. }
  772. stv0900_write_reg(intp, ERRCTRL1, 0x67);
  773. break;
  774. case STV0900_UNKNOWN_STANDARD:
  775. default:
  776. dprintk("%s: found unknown standard\n", __func__);
  777. stv0900_write_bits(intp, DVBS1_ENABLE, 1);
  778. stv0900_write_bits(intp, DVBS2_ENABLE, 1);
  779. break;
  780. }
  781. freq1 = stv0900_read_reg(intp, CFR2);
  782. freq0 = stv0900_read_reg(intp, CFR1);
  783. if (intp->srch_algo[demod] == STV0900_BLIND_SEARCH) {
  784. stv0900_write_reg(intp, SFRSTEP, 0x00);
  785. stv0900_write_bits(intp, SCAN_ENABLE, 0);
  786. stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
  787. stv0900_write_reg(intp, TMGCFG2, 0xc1);
  788. stv0900_set_symbol_rate(intp, intp->mclk, srate, demod);
  789. blind_tun_sw = 1;
  790. if (intp->result[demod].standard != STV0900_DVBS2_STANDARD)
  791. stv0900_set_dvbs1_track_car_loop(intp, demod, srate);
  792. }
  793. if (intp->chip_id >= 0x20) {
  794. if ((intp->srch_standard[demod] == STV0900_SEARCH_DVBS1) ||
  795. (intp->srch_standard[demod] ==
  796. STV0900_SEARCH_DSS) ||
  797. (intp->srch_standard[demod] ==
  798. STV0900_AUTO_SEARCH)) {
  799. stv0900_write_reg(intp, VAVSRVIT, 0x0a);
  800. stv0900_write_reg(intp, VITSCALE, 0x0);
  801. }
  802. }
  803. if (intp->chip_id < 0x20)
  804. stv0900_write_reg(intp, CARHDR, 0x08);
  805. if (intp->chip_id == 0x10)
  806. stv0900_write_reg(intp, CORRELEXP, 0x0a);
  807. stv0900_write_reg(intp, AGC2REF, 0x38);
  808. if ((intp->chip_id >= 0x20) ||
  809. (blind_tun_sw == 1) ||
  810. (intp->symbol_rate[demod] < 10000000)) {
  811. stv0900_write_reg(intp, CFRINIT1, freq1);
  812. stv0900_write_reg(intp, CFRINIT0, freq0);
  813. intp->bw[demod] = stv0900_carrier_width(srate,
  814. intp->rolloff) + 10000000;
  815. if ((intp->chip_id >= 0x20) || (blind_tun_sw == 1)) {
  816. if (intp->srch_algo[demod] != STV0900_WARM_START) {
  817. if (intp->tuner_type[demod] == 3)
  818. stv0900_set_tuner_auto(intp,
  819. intp->freq[demod],
  820. intp->bw[demod],
  821. demod);
  822. else
  823. stv0900_set_bandwidth(fe,
  824. intp->bw[demod]);
  825. }
  826. }
  827. if ((intp->srch_algo[demod] == STV0900_BLIND_SEARCH) ||
  828. (intp->symbol_rate[demod] < 10000000))
  829. msleep(50);
  830. else
  831. msleep(5);
  832. stv0900_get_lock_timeout(&timed, &timef, srate,
  833. STV0900_WARM_START);
  834. if (stv0900_get_demod_lock(intp, demod, timed / 2) == FALSE) {
  835. stv0900_write_reg(intp, DMDISTATE, 0x1f);
  836. stv0900_write_reg(intp, CFRINIT1, freq1);
  837. stv0900_write_reg(intp, CFRINIT0, freq0);
  838. stv0900_write_reg(intp, DMDISTATE, 0x18);
  839. i = 0;
  840. while ((stv0900_get_demod_lock(intp,
  841. demod,
  842. timed / 2) == FALSE) &&
  843. (i <= 2)) {
  844. stv0900_write_reg(intp, DMDISTATE, 0x1f);
  845. stv0900_write_reg(intp, CFRINIT1, freq1);
  846. stv0900_write_reg(intp, CFRINIT0, freq0);
  847. stv0900_write_reg(intp, DMDISTATE, 0x18);
  848. i++;
  849. }
  850. }
  851. }
  852. if (intp->chip_id >= 0x20)
  853. stv0900_write_reg(intp, CARFREQ, 0x49);
  854. if ((intp->result[demod].standard == STV0900_DVBS1_STANDARD) ||
  855. (intp->result[demod].standard == STV0900_DSS_STANDARD))
  856. stv0900_set_viterbi_tracq(intp, demod);
  857. }
  858. static int stv0900_get_fec_lock(struct stv0900_internal *intp,
  859. enum fe_stv0900_demod_num demod, s32 time_out)
  860. {
  861. s32 timer = 0, lock = 0;
  862. enum fe_stv0900_search_state dmd_state;
  863. dprintk("%s\n", __func__);
  864. dmd_state = stv0900_get_bits(intp, HEADER_MODE);
  865. while ((timer < time_out) && (lock == 0)) {
  866. switch (dmd_state) {
  867. case STV0900_SEARCH:
  868. case STV0900_PLH_DETECTED:
  869. default:
  870. lock = 0;
  871. break;
  872. case STV0900_DVBS2_FOUND:
  873. lock = stv0900_get_bits(intp, PKTDELIN_LOCK);
  874. break;
  875. case STV0900_DVBS_FOUND:
  876. lock = stv0900_get_bits(intp, LOCKEDVIT);
  877. break;
  878. }
  879. if (lock == 0) {
  880. msleep(10);
  881. timer += 10;
  882. }
  883. }
  884. if (lock)
  885. dprintk("%s: DEMOD FEC LOCK OK\n", __func__);
  886. else
  887. dprintk("%s: DEMOD FEC LOCK FAIL\n", __func__);
  888. return lock;
  889. }
  890. static int stv0900_wait_for_lock(struct stv0900_internal *intp,
  891. enum fe_stv0900_demod_num demod,
  892. s32 dmd_timeout, s32 fec_timeout)
  893. {
  894. s32 timer = 0, lock = 0;
  895. dprintk("%s\n", __func__);
  896. lock = stv0900_get_demod_lock(intp, demod, dmd_timeout);
  897. if (lock)
  898. lock = stv0900_get_fec_lock(intp, demod, fec_timeout);
  899. if (lock) {
  900. lock = 0;
  901. dprintk("%s: Timer = %d, time_out = %d\n",
  902. __func__, timer, fec_timeout);
  903. while ((timer < fec_timeout) && (lock == 0)) {
  904. lock = stv0900_get_bits(intp, TSFIFO_LINEOK);
  905. msleep(1);
  906. timer++;
  907. }
  908. }
  909. if (lock)
  910. dprintk("%s: DEMOD LOCK OK\n", __func__);
  911. else
  912. dprintk("%s: DEMOD LOCK FAIL\n", __func__);
  913. if (lock)
  914. return TRUE;
  915. else
  916. return FALSE;
  917. }
  918. enum fe_stv0900_tracking_standard stv0900_get_standard(struct dvb_frontend *fe,
  919. enum fe_stv0900_demod_num demod)
  920. {
  921. struct stv0900_state *state = fe->demodulator_priv;
  922. struct stv0900_internal *intp = state->internal;
  923. enum fe_stv0900_tracking_standard fnd_standard;
  924. int hdr_mode = stv0900_get_bits(intp, HEADER_MODE);
  925. switch (hdr_mode) {
  926. case 2:
  927. fnd_standard = STV0900_DVBS2_STANDARD;
  928. break;
  929. case 3:
  930. if (stv0900_get_bits(intp, DSS_DVB) == 1)
  931. fnd_standard = STV0900_DSS_STANDARD;
  932. else
  933. fnd_standard = STV0900_DVBS1_STANDARD;
  934. break;
  935. default:
  936. fnd_standard = STV0900_UNKNOWN_STANDARD;
  937. }
  938. dprintk("%s: standard %d\n", __func__, fnd_standard);
  939. return fnd_standard;
  940. }
  941. static s32 stv0900_get_carr_freq(struct stv0900_internal *intp, u32 mclk,
  942. enum fe_stv0900_demod_num demod)
  943. {
  944. s32 derot,
  945. rem1,
  946. rem2,
  947. intval1,
  948. intval2;
  949. derot = (stv0900_get_bits(intp, CAR_FREQ2) << 16) +
  950. (stv0900_get_bits(intp, CAR_FREQ1) << 8) +
  951. (stv0900_get_bits(intp, CAR_FREQ0));
  952. derot = ge2comp(derot, 24);
  953. intval1 = mclk >> 12;
  954. intval2 = derot >> 12;
  955. rem1 = mclk % 0x1000;
  956. rem2 = derot % 0x1000;
  957. derot = (intval1 * intval2) +
  958. ((intval1 * rem2) >> 12) +
  959. ((intval2 * rem1) >> 12);
  960. return derot;
  961. }
  962. static u32 stv0900_get_tuner_freq(struct dvb_frontend *fe)
  963. {
  964. struct dvb_frontend_ops *frontend_ops = NULL;
  965. struct dvb_tuner_ops *tuner_ops = NULL;
  966. u32 freq = 0;
  967. frontend_ops = &fe->ops;
  968. tuner_ops = &frontend_ops->tuner_ops;
  969. if (tuner_ops->get_frequency) {
  970. if ((tuner_ops->get_frequency(fe, &freq)) < 0)
  971. dprintk("%s: Invalid parameter\n", __func__);
  972. else
  973. dprintk("%s: Frequency=%d\n", __func__, freq);
  974. }
  975. return freq;
  976. }
  977. static enum
  978. fe_stv0900_signal_type stv0900_get_signal_params(struct dvb_frontend *fe)
  979. {
  980. struct stv0900_state *state = fe->demodulator_priv;
  981. struct stv0900_internal *intp = state->internal;
  982. enum fe_stv0900_demod_num demod = state->demod;
  983. enum fe_stv0900_signal_type range = STV0900_OUTOFRANGE;
  984. struct stv0900_signal_info *result = &intp->result[demod];
  985. s32 offsetFreq,
  986. srate_offset;
  987. int i = 0,
  988. d = demod;
  989. u8 timing;
  990. msleep(5);
  991. if (intp->srch_algo[d] == STV0900_BLIND_SEARCH) {
  992. timing = stv0900_read_reg(intp, TMGREG2);
  993. i = 0;
  994. stv0900_write_reg(intp, SFRSTEP, 0x5c);
  995. while ((i <= 50) && (timing != 0) && (timing != 0xff)) {
  996. timing = stv0900_read_reg(intp, TMGREG2);
  997. msleep(5);
  998. i += 5;
  999. }
  1000. }
  1001. result->standard = stv0900_get_standard(fe, d);
  1002. if (intp->tuner_type[demod] == 3)
  1003. result->frequency = stv0900_get_freq_auto(intp, d);
  1004. else
  1005. result->frequency = stv0900_get_tuner_freq(fe);
  1006. offsetFreq = stv0900_get_carr_freq(intp, intp->mclk, d) / 1000;
  1007. result->frequency += offsetFreq;
  1008. result->symbol_rate = stv0900_get_symbol_rate(intp, intp->mclk, d);
  1009. srate_offset = stv0900_get_timing_offst(intp, result->symbol_rate, d);
  1010. result->symbol_rate += srate_offset;
  1011. result->fec = stv0900_get_vit_fec(intp, d);
  1012. result->modcode = stv0900_get_bits(intp, DEMOD_MODCOD);
  1013. result->pilot = stv0900_get_bits(intp, DEMOD_TYPE) & 0x01;
  1014. result->frame_len = ((u32)stv0900_get_bits(intp, DEMOD_TYPE)) >> 1;
  1015. result->rolloff = stv0900_get_bits(intp, ROLLOFF_STATUS);
  1016. dprintk("%s: modcode=0x%x \n", __func__, result->modcode);
  1017. switch (result->standard) {
  1018. case STV0900_DVBS2_STANDARD:
  1019. result->spectrum = stv0900_get_bits(intp, SPECINV_DEMOD);
  1020. if (result->modcode <= STV0900_QPSK_910)
  1021. result->modulation = STV0900_QPSK;
  1022. else if (result->modcode <= STV0900_8PSK_910)
  1023. result->modulation = STV0900_8PSK;
  1024. else if (result->modcode <= STV0900_16APSK_910)
  1025. result->modulation = STV0900_16APSK;
  1026. else if (result->modcode <= STV0900_32APSK_910)
  1027. result->modulation = STV0900_32APSK;
  1028. else
  1029. result->modulation = STV0900_UNKNOWN;
  1030. break;
  1031. case STV0900_DVBS1_STANDARD:
  1032. case STV0900_DSS_STANDARD:
  1033. result->spectrum = stv0900_get_bits(intp, IQINV);
  1034. result->modulation = STV0900_QPSK;
  1035. break;
  1036. default:
  1037. break;
  1038. }
  1039. if ((intp->srch_algo[d] == STV0900_BLIND_SEARCH) ||
  1040. (intp->symbol_rate[d] < 10000000)) {
  1041. offsetFreq = result->frequency - intp->freq[d];
  1042. if (intp->tuner_type[demod] == 3)
  1043. intp->freq[d] = stv0900_get_freq_auto(intp, d);
  1044. else
  1045. intp->freq[d] = stv0900_get_tuner_freq(fe);
  1046. if (abs(offsetFreq) <= ((intp->srch_range[d] / 2000) + 500))
  1047. range = STV0900_RANGEOK;
  1048. else if (abs(offsetFreq) <=
  1049. (stv0900_carrier_width(result->symbol_rate,
  1050. result->rolloff) / 2000))
  1051. range = STV0900_RANGEOK;
  1052. } else if (abs(offsetFreq) <= ((intp->srch_range[d] / 2000) + 500))
  1053. range = STV0900_RANGEOK;
  1054. dprintk("%s: range %d\n", __func__, range);
  1055. return range;
  1056. }
  1057. static enum
  1058. fe_stv0900_signal_type stv0900_dvbs1_acq_workaround(struct dvb_frontend *fe)
  1059. {
  1060. struct stv0900_state *state = fe->demodulator_priv;
  1061. struct stv0900_internal *intp = state->internal;
  1062. enum fe_stv0900_demod_num demod = state->demod;
  1063. enum fe_stv0900_signal_type signal_type = STV0900_NODATA;
  1064. s32 srate,
  1065. demod_timeout,
  1066. fec_timeout,
  1067. freq1,
  1068. freq0;
  1069. intp->result[demod].locked = FALSE;
  1070. if (stv0900_get_bits(intp, HEADER_MODE) == STV0900_DVBS_FOUND) {
  1071. srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
  1072. srate += stv0900_get_timing_offst(intp, srate, demod);
  1073. if (intp->srch_algo[demod] == STV0900_BLIND_SEARCH)
  1074. stv0900_set_symbol_rate(intp, intp->mclk, srate, demod);
  1075. stv0900_get_lock_timeout(&demod_timeout, &fec_timeout,
  1076. srate, STV0900_WARM_START);
  1077. freq1 = stv0900_read_reg(intp, CFR2);
  1078. freq0 = stv0900_read_reg(intp, CFR1);
  1079. stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
  1080. stv0900_write_bits(intp, SPECINV_CONTROL,
  1081. STV0900_IQ_FORCE_SWAPPED);
  1082. stv0900_write_reg(intp, DMDISTATE, 0x1c);
  1083. stv0900_write_reg(intp, CFRINIT1, freq1);
  1084. stv0900_write_reg(intp, CFRINIT0, freq0);
  1085. stv0900_write_reg(intp, DMDISTATE, 0x18);
  1086. if (stv0900_wait_for_lock(intp, demod,
  1087. demod_timeout, fec_timeout) == TRUE) {
  1088. intp->result[demod].locked = TRUE;
  1089. signal_type = stv0900_get_signal_params(fe);
  1090. stv0900_track_optimization(fe);
  1091. } else {
  1092. stv0900_write_bits(intp, SPECINV_CONTROL,
  1093. STV0900_IQ_FORCE_NORMAL);
  1094. stv0900_write_reg(intp, DMDISTATE, 0x1c);
  1095. stv0900_write_reg(intp, CFRINIT1, freq1);
  1096. stv0900_write_reg(intp, CFRINIT0, freq0);
  1097. stv0900_write_reg(intp, DMDISTATE, 0x18);
  1098. if (stv0900_wait_for_lock(intp, demod,
  1099. demod_timeout, fec_timeout) == TRUE) {
  1100. intp->result[demod].locked = TRUE;
  1101. signal_type = stv0900_get_signal_params(fe);
  1102. stv0900_track_optimization(fe);
  1103. }
  1104. }
  1105. } else
  1106. intp->result[demod].locked = FALSE;
  1107. return signal_type;
  1108. }
  1109. static u16 stv0900_blind_check_agc2_min_level(struct stv0900_internal *intp,
  1110. enum fe_stv0900_demod_num demod)
  1111. {
  1112. u32 minagc2level = 0xffff,
  1113. agc2level,
  1114. init_freq, freq_step;
  1115. s32 i, j, nb_steps, direction;
  1116. dprintk("%s\n", __func__);
  1117. stv0900_write_reg(intp, AGC2REF, 0x38);
  1118. stv0900_write_bits(intp, SCAN_ENABLE, 0);
  1119. stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
  1120. stv0900_write_bits(intp, AUTO_GUP, 1);
  1121. stv0900_write_bits(intp, AUTO_GLOW, 1);
  1122. stv0900_write_reg(intp, DMDT0M, 0x0);
  1123. stv0900_set_symbol_rate(intp, intp->mclk, 1000000, demod);
  1124. nb_steps = -1 + (intp->srch_range[demod] / 1000000);
  1125. nb_steps /= 2;
  1126. nb_steps = (2 * nb_steps) + 1;
  1127. if (nb_steps < 0)
  1128. nb_steps = 1;
  1129. direction = 1;
  1130. freq_step = (1000000 << 8) / (intp->mclk >> 8);
  1131. init_freq = 0;
  1132. for (i = 0; i < nb_steps; i++) {
  1133. if (direction > 0)
  1134. init_freq = init_freq + (freq_step * i);
  1135. else
  1136. init_freq = init_freq - (freq_step * i);
  1137. direction *= -1;
  1138. stv0900_write_reg(intp, DMDISTATE, 0x5C);
  1139. stv0900_write_reg(intp, CFRINIT1, (init_freq >> 8) & 0xff);
  1140. stv0900_write_reg(intp, CFRINIT0, init_freq & 0xff);
  1141. stv0900_write_reg(intp, DMDISTATE, 0x58);
  1142. msleep(10);
  1143. agc2level = 0;
  1144. for (j = 0; j < 10; j++)
  1145. agc2level += (stv0900_read_reg(intp, AGC2I1) << 8)
  1146. | stv0900_read_reg(intp, AGC2I0);
  1147. agc2level /= 10;
  1148. if (agc2level < minagc2level)
  1149. minagc2level = agc2level;
  1150. }
  1151. return (u16)minagc2level;
  1152. }
  1153. static u32 stv0900_search_srate_coarse(struct dvb_frontend *fe)
  1154. {
  1155. struct stv0900_state *state = fe->demodulator_priv;
  1156. struct stv0900_internal *intp = state->internal;
  1157. enum fe_stv0900_demod_num demod = state->demod;
  1158. int timing_lck = FALSE;
  1159. s32 i, timingcpt = 0,
  1160. direction = 1,
  1161. nb_steps,
  1162. current_step = 0,
  1163. tuner_freq;
  1164. u32 agc2_th,
  1165. coarse_srate = 0,
  1166. agc2_integr = 0,
  1167. currier_step = 1200;
  1168. if (intp->chip_id >= 0x30)
  1169. agc2_th = 0x2e00;
  1170. else
  1171. agc2_th = 0x1f00;
  1172. stv0900_write_bits(intp, DEMOD_MODE, 0x1f);
  1173. stv0900_write_reg(intp, TMGCFG, 0x12);
  1174. stv0900_write_reg(intp, TMGTHRISE, 0xf0);
  1175. stv0900_write_reg(intp, TMGTHFALL, 0xe0);
  1176. stv0900_write_bits(intp, SCAN_ENABLE, 1);
  1177. stv0900_write_bits(intp, CFR_AUTOSCAN, 1);
  1178. stv0900_write_reg(intp, SFRUP1, 0x83);
  1179. stv0900_write_reg(intp, SFRUP0, 0xc0);
  1180. stv0900_write_reg(intp, SFRLOW1, 0x82);
  1181. stv0900_write_reg(intp, SFRLOW0, 0xa0);
  1182. stv0900_write_reg(intp, DMDT0M, 0x0);
  1183. stv0900_write_reg(intp, AGC2REF, 0x50);
  1184. if (intp->chip_id >= 0x30) {
  1185. stv0900_write_reg(intp, CARFREQ, 0x99);
  1186. stv0900_write_reg(intp, SFRSTEP, 0x98);
  1187. } else if (intp->chip_id >= 0x20) {
  1188. stv0900_write_reg(intp, CARFREQ, 0x6a);
  1189. stv0900_write_reg(intp, SFRSTEP, 0x95);
  1190. } else {
  1191. stv0900_write_reg(intp, CARFREQ, 0xed);
  1192. stv0900_write_reg(intp, SFRSTEP, 0x73);
  1193. }
  1194. if (intp->symbol_rate[demod] <= 2000000)
  1195. currier_step = 1000;
  1196. else if (intp->symbol_rate[demod] <= 5000000)
  1197. currier_step = 2000;
  1198. else if (intp->symbol_rate[demod] <= 12000000)
  1199. currier_step = 3000;
  1200. else
  1201. currier_step = 5000;
  1202. nb_steps = -1 + ((intp->srch_range[demod] / 1000) / currier_step);
  1203. nb_steps /= 2;
  1204. nb_steps = (2 * nb_steps) + 1;
  1205. if (nb_steps < 0)
  1206. nb_steps = 1;
  1207. else if (nb_steps > 10) {
  1208. nb_steps = 11;
  1209. currier_step = (intp->srch_range[demod] / 1000) / 10;
  1210. }
  1211. current_step = 0;
  1212. direction = 1;
  1213. tuner_freq = intp->freq[demod];
  1214. while ((timing_lck == FALSE) && (current_step < nb_steps)) {
  1215. stv0900_write_reg(intp, DMDISTATE, 0x5f);
  1216. stv0900_write_bits(intp, DEMOD_MODE, 0);
  1217. msleep(50);
  1218. for (i = 0; i < 10; i++) {
  1219. if (stv0900_get_bits(intp, TMGLOCK_QUALITY) >= 2)
  1220. timingcpt++;
  1221. agc2_integr += (stv0900_read_reg(intp, AGC2I1) << 8) |
  1222. stv0900_read_reg(intp, AGC2I0);
  1223. }
  1224. agc2_integr /= 10;
  1225. coarse_srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
  1226. current_step++;
  1227. direction *= -1;
  1228. dprintk("lock: I2C_DEMOD_MODE_FIELD =0. Search started. tuner freq=%d agc2=0x%x srate_coarse=%d tmg_cpt=%d\n",
  1229. tuner_freq, agc2_integr, coarse_srate, timingcpt);
  1230. if ((timingcpt >= 5) &&
  1231. (agc2_integr < agc2_th) &&
  1232. (coarse_srate < 55000000) &&
  1233. (coarse_srate > 850000))
  1234. timing_lck = TRUE;
  1235. else if (current_step < nb_steps) {
  1236. if (direction > 0)
  1237. tuner_freq += (current_step * currier_step);
  1238. else
  1239. tuner_freq -= (current_step * currier_step);
  1240. if (intp->tuner_type[demod] == 3)
  1241. stv0900_set_tuner_auto(intp, tuner_freq,
  1242. intp->bw[demod], demod);
  1243. else
  1244. stv0900_set_tuner(fe, tuner_freq,
  1245. intp->bw[demod]);
  1246. }
  1247. }
  1248. if (timing_lck == FALSE)
  1249. coarse_srate = 0;
  1250. else
  1251. coarse_srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
  1252. return coarse_srate;
  1253. }
  1254. static u32 stv0900_search_srate_fine(struct dvb_frontend *fe)
  1255. {
  1256. struct stv0900_state *state = fe->demodulator_priv;
  1257. struct stv0900_internal *intp = state->internal;
  1258. enum fe_stv0900_demod_num demod = state->demod;
  1259. u32 coarse_srate,
  1260. coarse_freq,
  1261. symb,
  1262. symbmax,
  1263. symbmin,
  1264. symbcomp;
  1265. coarse_srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
  1266. if (coarse_srate > 3000000) {
  1267. symbmax = 13 * (coarse_srate / 10);
  1268. symbmax = (symbmax / 1000) * 65536;
  1269. symbmax /= (intp->mclk / 1000);
  1270. symbmin = 10 * (coarse_srate / 13);
  1271. symbmin = (symbmin / 1000)*65536;
  1272. symbmin /= (intp->mclk / 1000);
  1273. symb = (coarse_srate / 1000) * 65536;
  1274. symb /= (intp->mclk / 1000);
  1275. } else {
  1276. symbmax = 13 * (coarse_srate / 10);
  1277. symbmax = (symbmax / 100) * 65536;
  1278. symbmax /= (intp->mclk / 100);
  1279. symbmin = 10 * (coarse_srate / 14);
  1280. symbmin = (symbmin / 100) * 65536;
  1281. symbmin /= (intp->mclk / 100);
  1282. symb = (coarse_srate / 100) * 65536;
  1283. symb /= (intp->mclk / 100);
  1284. }
  1285. symbcomp = 13 * (coarse_srate / 10);
  1286. coarse_freq = (stv0900_read_reg(intp, CFR2) << 8)
  1287. | stv0900_read_reg(intp, CFR1);
  1288. if (symbcomp < intp->symbol_rate[demod])
  1289. coarse_srate = 0;
  1290. else {
  1291. stv0900_write_reg(intp, DMDISTATE, 0x1f);
  1292. stv0900_write_reg(intp, TMGCFG2, 0xc1);
  1293. stv0900_write_reg(intp, TMGTHRISE, 0x20);
  1294. stv0900_write_reg(intp, TMGTHFALL, 0x00);
  1295. stv0900_write_reg(intp, TMGCFG, 0xd2);
  1296. stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
  1297. stv0900_write_reg(intp, AGC2REF, 0x38);
  1298. if (intp->chip_id >= 0x30)
  1299. stv0900_write_reg(intp, CARFREQ, 0x79);
  1300. else if (intp->chip_id >= 0x20)
  1301. stv0900_write_reg(intp, CARFREQ, 0x49);
  1302. else
  1303. stv0900_write_reg(intp, CARFREQ, 0xed);
  1304. stv0900_write_reg(intp, SFRUP1, (symbmax >> 8) & 0x7f);
  1305. stv0900_write_reg(intp, SFRUP0, (symbmax & 0xff));
  1306. stv0900_write_reg(intp, SFRLOW1, (symbmin >> 8) & 0x7f);
  1307. stv0900_write_reg(intp, SFRLOW0, (symbmin & 0xff));
  1308. stv0900_write_reg(intp, SFRINIT1, (symb >> 8) & 0xff);
  1309. stv0900_write_reg(intp, SFRINIT0, (symb & 0xff));
  1310. stv0900_write_reg(intp, DMDT0M, 0x20);
  1311. stv0900_write_reg(intp, CFRINIT1, (coarse_freq >> 8) & 0xff);
  1312. stv0900_write_reg(intp, CFRINIT0, coarse_freq & 0xff);
  1313. stv0900_write_reg(intp, DMDISTATE, 0x15);
  1314. }
  1315. return coarse_srate;
  1316. }
  1317. static int stv0900_blind_search_algo(struct dvb_frontend *fe)
  1318. {
  1319. struct stv0900_state *state = fe->demodulator_priv;
  1320. struct stv0900_internal *intp = state->internal;
  1321. enum fe_stv0900_demod_num demod = state->demod;
  1322. u8 k_ref_tmg,
  1323. k_ref_tmg_max,
  1324. k_ref_tmg_min;
  1325. u32 coarse_srate,
  1326. agc2_th;
  1327. int lock = FALSE,
  1328. coarse_fail = FALSE;
  1329. s32 demod_timeout = 500,
  1330. fec_timeout = 50,
  1331. fail_cpt,
  1332. i,
  1333. agc2_overflow;
  1334. u16 agc2_int;
  1335. u8 dstatus2;
  1336. dprintk("%s\n", __func__);
  1337. if (intp->chip_id < 0x20) {
  1338. k_ref_tmg_max = 233;
  1339. k_ref_tmg_min = 143;
  1340. } else {
  1341. k_ref_tmg_max = 110;
  1342. k_ref_tmg_min = 10;
  1343. }
  1344. if (intp->chip_id <= 0x20)
  1345. agc2_th = STV0900_BLIND_SEARCH_AGC2_TH;
  1346. else
  1347. agc2_th = STV0900_BLIND_SEARCH_AGC2_TH_CUT30;
  1348. agc2_int = stv0900_blind_check_agc2_min_level(intp, demod);
  1349. dprintk("%s agc2_int=%d agc2_th=%d \n", __func__, agc2_int, agc2_th);
  1350. if (agc2_int > agc2_th)
  1351. return FALSE;
  1352. if (intp->chip_id == 0x10)
  1353. stv0900_write_reg(intp, CORRELEXP, 0xaa);
  1354. if (intp->chip_id < 0x20)
  1355. stv0900_write_reg(intp, CARHDR, 0x55);
  1356. else
  1357. stv0900_write_reg(intp, CARHDR, 0x20);
  1358. if (intp->chip_id <= 0x20)
  1359. stv0900_write_reg(intp, CARCFG, 0xc4);
  1360. else
  1361. stv0900_write_reg(intp, CARCFG, 0x6);
  1362. stv0900_write_reg(intp, RTCS2, 0x44);
  1363. if (intp->chip_id >= 0x20) {
  1364. stv0900_write_reg(intp, EQUALCFG, 0x41);
  1365. stv0900_write_reg(intp, FFECFG, 0x41);
  1366. stv0900_write_reg(intp, VITSCALE, 0x82);
  1367. stv0900_write_reg(intp, VAVSRVIT, 0x0);
  1368. }
  1369. k_ref_tmg = k_ref_tmg_max;
  1370. do {
  1371. stv0900_write_reg(intp, KREFTMG, k_ref_tmg);
  1372. if (stv0900_search_srate_coarse(fe) != 0) {
  1373. coarse_srate = stv0900_search_srate_fine(fe);
  1374. if (coarse_srate != 0) {
  1375. stv0900_get_lock_timeout(&demod_timeout,
  1376. &fec_timeout,
  1377. coarse_srate,
  1378. STV0900_BLIND_SEARCH);
  1379. lock = stv0900_get_demod_lock(intp,
  1380. demod,
  1381. demod_timeout);
  1382. } else
  1383. lock = FALSE;
  1384. } else {
  1385. fail_cpt = 0;
  1386. agc2_overflow = 0;
  1387. for (i = 0; i < 10; i++) {
  1388. agc2_int = (stv0900_read_reg(intp, AGC2I1) << 8)
  1389. | stv0900_read_reg(intp, AGC2I0);
  1390. if (agc2_int >= 0xff00)
  1391. agc2_overflow++;
  1392. dstatus2 = stv0900_read_reg(intp, DSTATUS2);
  1393. if (((dstatus2 & 0x1) == 0x1) &&
  1394. ((dstatus2 >> 7) == 1))
  1395. fail_cpt++;
  1396. }
  1397. if ((fail_cpt > 7) || (agc2_overflow > 7))
  1398. coarse_fail = TRUE;
  1399. lock = FALSE;
  1400. }
  1401. k_ref_tmg -= 30;
  1402. } while ((k_ref_tmg >= k_ref_tmg_min) &&
  1403. (lock == FALSE) &&
  1404. (coarse_fail == FALSE));
  1405. return lock;
  1406. }
  1407. static void stv0900_set_viterbi_acq(struct stv0900_internal *intp,
  1408. enum fe_stv0900_demod_num demod)
  1409. {
  1410. s32 vth_reg = VTH12;
  1411. dprintk("%s\n", __func__);
  1412. stv0900_write_reg(intp, vth_reg++, 0x96);
  1413. stv0900_write_reg(intp, vth_reg++, 0x64);
  1414. stv0900_write_reg(intp, vth_reg++, 0x36);
  1415. stv0900_write_reg(intp, vth_reg++, 0x23);
  1416. stv0900_write_reg(intp, vth_reg++, 0x1e);
  1417. stv0900_write_reg(intp, vth_reg++, 0x19);
  1418. }
  1419. static void stv0900_set_search_standard(struct stv0900_internal *intp,
  1420. enum fe_stv0900_demod_num demod)
  1421. {
  1422. dprintk("%s\n", __func__);
  1423. switch (intp->srch_standard[demod]) {
  1424. case STV0900_SEARCH_DVBS1:
  1425. dprintk("Search Standard = DVBS1\n");
  1426. break;
  1427. case STV0900_SEARCH_DSS:
  1428. dprintk("Search Standard = DSS\n");
  1429. break;
  1430. case STV0900_SEARCH_DVBS2:
  1431. dprintk("Search Standard = DVBS2\n");
  1432. break;
  1433. case STV0900_AUTO_SEARCH:
  1434. default:
  1435. dprintk("Search Standard = AUTO\n");
  1436. break;
  1437. }
  1438. switch (intp->srch_standard[demod]) {
  1439. case STV0900_SEARCH_DVBS1:
  1440. case STV0900_SEARCH_DSS:
  1441. stv0900_write_bits(intp, DVBS1_ENABLE, 1);
  1442. stv0900_write_bits(intp, DVBS2_ENABLE, 0);
  1443. stv0900_write_bits(intp, STOP_CLKVIT, 0);
  1444. stv0900_set_dvbs1_track_car_loop(intp,
  1445. demod,
  1446. intp->symbol_rate[demod]);
  1447. stv0900_write_reg(intp, CAR2CFG, 0x22);
  1448. stv0900_set_viterbi_acq(intp, demod);
  1449. stv0900_set_viterbi_standard(intp,
  1450. intp->srch_standard[demod],
  1451. intp->fec[demod], demod);
  1452. break;
  1453. case STV0900_SEARCH_DVBS2:
  1454. stv0900_write_bits(intp, DVBS1_ENABLE, 0);
  1455. stv0900_write_bits(intp, DVBS2_ENABLE, 1);
  1456. stv0900_write_bits(intp, STOP_CLKVIT, 1);
  1457. stv0900_write_reg(intp, ACLC, 0x1a);
  1458. stv0900_write_reg(intp, BCLC, 0x09);
  1459. if (intp->chip_id <= 0x20) /*cut 1.x and 2.0*/
  1460. stv0900_write_reg(intp, CAR2CFG, 0x26);
  1461. else
  1462. stv0900_write_reg(intp, CAR2CFG, 0x66);
  1463. if (intp->demod_mode != STV0900_SINGLE) {
  1464. if (intp->chip_id <= 0x11)
  1465. stv0900_stop_all_s2_modcod(intp, demod);
  1466. else
  1467. stv0900_activate_s2_modcod(intp, demod);
  1468. } else
  1469. stv0900_activate_s2_modcod_single(intp, demod);
  1470. stv0900_set_viterbi_tracq(intp, demod);
  1471. break;
  1472. case STV0900_AUTO_SEARCH:
  1473. default:
  1474. stv0900_write_bits(intp, DVBS1_ENABLE, 1);
  1475. stv0900_write_bits(intp, DVBS2_ENABLE, 1);
  1476. stv0900_write_bits(intp, STOP_CLKVIT, 0);
  1477. stv0900_write_reg(intp, ACLC, 0x1a);
  1478. stv0900_write_reg(intp, BCLC, 0x09);
  1479. stv0900_set_dvbs1_track_car_loop(intp,
  1480. demod,
  1481. intp->symbol_rate[demod]);
  1482. if (intp->chip_id <= 0x20) /*cut 1.x and 2.0*/
  1483. stv0900_write_reg(intp, CAR2CFG, 0x26);
  1484. else
  1485. stv0900_write_reg(intp, CAR2CFG, 0x66);
  1486. if (intp->demod_mode != STV0900_SINGLE) {
  1487. if (intp->chip_id <= 0x11)
  1488. stv0900_stop_all_s2_modcod(intp, demod);
  1489. else
  1490. stv0900_activate_s2_modcod(intp, demod);
  1491. } else
  1492. stv0900_activate_s2_modcod_single(intp, demod);
  1493. stv0900_set_viterbi_tracq(intp, demod);
  1494. stv0900_set_viterbi_standard(intp,
  1495. intp->srch_standard[demod],
  1496. intp->fec[demod], demod);
  1497. break;
  1498. }
  1499. }
  1500. enum fe_stv0900_signal_type stv0900_algo(struct dvb_frontend *fe)
  1501. {
  1502. struct stv0900_state *state = fe->demodulator_priv;
  1503. struct stv0900_internal *intp = state->internal;
  1504. enum fe_stv0900_demod_num demod = state->demod;
  1505. s32 demod_timeout = 500, fec_timeout = 50;
  1506. s32 aq_power, agc1_power, i;
  1507. int lock = FALSE, low_sr = FALSE;
  1508. enum fe_stv0900_signal_type signal_type = STV0900_NOCARRIER;
  1509. enum fe_stv0900_search_algo algo;
  1510. int no_signal = FALSE;
  1511. dprintk("%s\n", __func__);
  1512. algo = intp->srch_algo[demod];
  1513. stv0900_write_bits(intp, RST_HWARE, 1);
  1514. stv0900_write_reg(intp, DMDISTATE, 0x5c);
  1515. if (intp->chip_id >= 0x20) {
  1516. if (intp->symbol_rate[demod] > 5000000)
  1517. stv0900_write_reg(intp, CORRELABS, 0x9e);
  1518. else
  1519. stv0900_write_reg(intp, CORRELABS, 0x82);
  1520. } else
  1521. stv0900_write_reg(intp, CORRELABS, 0x88);
  1522. stv0900_get_lock_timeout(&demod_timeout, &fec_timeout,
  1523. intp->symbol_rate[demod],
  1524. intp->srch_algo[demod]);
  1525. if (intp->srch_algo[demod] == STV0900_BLIND_SEARCH) {
  1526. intp->bw[demod] = 2 * 36000000;
  1527. stv0900_write_reg(intp, TMGCFG2, 0xc0);
  1528. stv0900_write_reg(intp, CORRELMANT, 0x70);
  1529. stv0900_set_symbol_rate(intp, intp->mclk, 1000000, demod);
  1530. } else {
  1531. stv0900_write_reg(intp, DMDT0M, 0x20);
  1532. stv0900_write_reg(intp, TMGCFG, 0xd2);
  1533. if (intp->symbol_rate[demod] < 2000000)
  1534. stv0900_write_reg(intp, CORRELMANT, 0x63);
  1535. else
  1536. stv0900_write_reg(intp, CORRELMANT, 0x70);
  1537. stv0900_write_reg(intp, AGC2REF, 0x38);
  1538. intp->bw[demod] =
  1539. stv0900_carrier_width(intp->symbol_rate[demod],
  1540. intp->rolloff);
  1541. if (intp->chip_id >= 0x20) {
  1542. stv0900_write_reg(intp, KREFTMG, 0x5a);
  1543. if (intp->srch_algo[demod] == STV0900_COLD_START) {
  1544. intp->bw[demod] += 10000000;
  1545. intp->bw[demod] *= 15;
  1546. intp->bw[demod] /= 10;
  1547. } else if (intp->srch_algo[demod] == STV0900_WARM_START)
  1548. intp->bw[demod] += 10000000;
  1549. } else {
  1550. stv0900_write_reg(intp, KREFTMG, 0xc1);
  1551. intp->bw[demod] += 10000000;
  1552. intp->bw[demod] *= 15;
  1553. intp->bw[demod] /= 10;
  1554. }
  1555. stv0900_write_reg(intp, TMGCFG2, 0xc1);
  1556. stv0900_set_symbol_rate(intp, intp->mclk,
  1557. intp->symbol_rate[demod], demod);
  1558. stv0900_set_max_symbol_rate(intp, intp->mclk,
  1559. intp->symbol_rate[demod], demod);
  1560. stv0900_set_min_symbol_rate(intp, intp->mclk,
  1561. intp->symbol_rate[demod], demod);
  1562. if (intp->symbol_rate[demod] >= 10000000)
  1563. low_sr = FALSE;
  1564. else
  1565. low_sr = TRUE;
  1566. }
  1567. if (intp->tuner_type[demod] == 3)
  1568. stv0900_set_tuner_auto(intp, intp->freq[demod],
  1569. intp->bw[demod], demod);
  1570. else
  1571. stv0900_set_tuner(fe, intp->freq[demod], intp->bw[demod]);
  1572. agc1_power = MAKEWORD(stv0900_get_bits(intp, AGCIQ_VALUE1),
  1573. stv0900_get_bits(intp, AGCIQ_VALUE0));
  1574. aq_power = 0;
  1575. if (agc1_power == 0) {
  1576. for (i = 0; i < 5; i++)
  1577. aq_power += (stv0900_get_bits(intp, POWER_I) +
  1578. stv0900_get_bits(intp, POWER_Q)) / 2;
  1579. aq_power /= 5;
  1580. }
  1581. if ((agc1_power == 0) && (aq_power < IQPOWER_THRESHOLD)) {
  1582. intp->result[demod].locked = FALSE;
  1583. signal_type = STV0900_NOAGC1;
  1584. dprintk("%s: NO AGC1, POWERI, POWERQ\n", __func__);
  1585. } else {
  1586. stv0900_write_bits(intp, SPECINV_CONTROL,
  1587. intp->srch_iq_inv[demod]);
  1588. if (intp->chip_id <= 0x20) /*cut 2.0*/
  1589. stv0900_write_bits(intp, MANUALSX_ROLLOFF, 1);
  1590. else /*cut 3.0*/
  1591. stv0900_write_bits(intp, MANUALS2_ROLLOFF, 1);
  1592. stv0900_set_search_standard(intp, demod);
  1593. if (intp->srch_algo[demod] != STV0900_BLIND_SEARCH)
  1594. stv0900_start_search(intp, demod);
  1595. }
  1596. if (signal_type == STV0900_NOAGC1)
  1597. return signal_type;
  1598. if (intp->chip_id == 0x12) {
  1599. stv0900_write_bits(intp, RST_HWARE, 0);
  1600. msleep(3);
  1601. stv0900_write_bits(intp, RST_HWARE, 1);
  1602. stv0900_write_bits(intp, RST_HWARE, 0);
  1603. }
  1604. if (algo == STV0900_BLIND_SEARCH)
  1605. lock = stv0900_blind_search_algo(fe);
  1606. else if (algo == STV0900_COLD_START)
  1607. lock = stv0900_get_demod_cold_lock(fe, demod_timeout);
  1608. else if (algo == STV0900_WARM_START)
  1609. lock = stv0900_get_demod_lock(intp, demod, demod_timeout);
  1610. if ((lock == FALSE) && (algo == STV0900_COLD_START)) {
  1611. if (low_sr == FALSE) {
  1612. if (stv0900_check_timing_lock(intp, demod) == TRUE)
  1613. lock = stv0900_sw_algo(intp, demod);
  1614. }
  1615. }
  1616. if (lock == TRUE)
  1617. signal_type = stv0900_get_signal_params(fe);
  1618. if ((lock == TRUE) && (signal_type == STV0900_RANGEOK)) {
  1619. stv0900_track_optimization(fe);
  1620. if (intp->chip_id <= 0x11) {
  1621. if ((stv0900_get_standard(fe, 0) ==
  1622. STV0900_DVBS1_STANDARD) &&
  1623. (stv0900_get_standard(fe, 1) ==
  1624. STV0900_DVBS1_STANDARD)) {
  1625. msleep(20);
  1626. stv0900_write_bits(intp, RST_HWARE, 0);
  1627. } else {
  1628. stv0900_write_bits(intp, RST_HWARE, 0);
  1629. msleep(3);
  1630. stv0900_write_bits(intp, RST_HWARE, 1);
  1631. stv0900_write_bits(intp, RST_HWARE, 0);
  1632. }
  1633. } else if (intp->chip_id >= 0x20) {
  1634. stv0900_write_bits(intp, RST_HWARE, 0);
  1635. msleep(3);
  1636. stv0900_write_bits(intp, RST_HWARE, 1);
  1637. stv0900_write_bits(intp, RST_HWARE, 0);
  1638. }
  1639. if (stv0900_wait_for_lock(intp, demod,
  1640. fec_timeout, fec_timeout) == TRUE) {
  1641. lock = TRUE;
  1642. intp->result[demod].locked = TRUE;
  1643. if (intp->result[demod].standard ==
  1644. STV0900_DVBS2_STANDARD) {
  1645. stv0900_set_dvbs2_rolloff(intp, demod);
  1646. stv0900_write_bits(intp, RESET_UPKO_COUNT, 1);
  1647. stv0900_write_bits(intp, RESET_UPKO_COUNT, 0);
  1648. stv0900_write_reg(intp, ERRCTRL1, 0x67);
  1649. } else {
  1650. stv0900_write_reg(intp, ERRCTRL1, 0x75);
  1651. }
  1652. stv0900_write_reg(intp, FBERCPT4, 0);
  1653. stv0900_write_reg(intp, ERRCTRL2, 0xc1);
  1654. } else {
  1655. lock = FALSE;
  1656. signal_type = STV0900_NODATA;
  1657. no_signal = stv0900_check_signal_presence(intp, demod);
  1658. intp->result[demod].locked = FALSE;
  1659. }
  1660. }
  1661. if ((signal_type != STV0900_NODATA) || (no_signal != FALSE))
  1662. return signal_type;
  1663. if (intp->chip_id > 0x11) {
  1664. intp->result[demod].locked = FALSE;
  1665. return signal_type;
  1666. }
  1667. if ((stv0900_get_bits(intp, HEADER_MODE) == STV0900_DVBS_FOUND) &&
  1668. (intp->srch_iq_inv[demod] <= STV0900_IQ_AUTO_NORMAL_FIRST))
  1669. signal_type = stv0900_dvbs1_acq_workaround(fe);
  1670. return signal_type;
  1671. }