s5h1409.c 23 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. Samsung S5H1409 VSB/QAM demodulator driver
  4. Copyright (C) 2006 Steven Toth <stoth@linuxtv.org>
  5. */
  6. #include <linux/kernel.h>
  7. #include <linux/init.h>
  8. #include <linux/module.h>
  9. #include <linux/string.h>
  10. #include <linux/slab.h>
  11. #include <linux/delay.h>
  12. #include <media/dvb_frontend.h>
  13. #include "s5h1409.h"
  14. struct s5h1409_state {
  15. struct i2c_adapter *i2c;
  16. /* configuration settings */
  17. const struct s5h1409_config *config;
  18. struct dvb_frontend frontend;
  19. /* previous uncorrected block counter */
  20. enum fe_modulation current_modulation;
  21. u32 current_frequency;
  22. int if_freq;
  23. u32 is_qam_locked;
  24. /* QAM tuning state goes through the following state transitions */
  25. #define QAM_STATE_UNTUNED 0
  26. #define QAM_STATE_TUNING_STARTED 1
  27. #define QAM_STATE_INTERLEAVE_SET 2
  28. #define QAM_STATE_QAM_OPTIMIZED_L1 3
  29. #define QAM_STATE_QAM_OPTIMIZED_L2 4
  30. #define QAM_STATE_QAM_OPTIMIZED_L3 5
  31. u8 qam_state;
  32. };
  33. static int debug;
  34. module_param(debug, int, 0644);
  35. MODULE_PARM_DESC(debug, "Enable verbose debug messages");
  36. #define dprintk if (debug) printk
  37. /* Register values to initialise the demod, this will set VSB by default */
  38. static struct init_tab {
  39. u8 reg;
  40. u16 data;
  41. } init_tab[] = {
  42. { 0x00, 0x0071, },
  43. { 0x01, 0x3213, },
  44. { 0x09, 0x0025, },
  45. { 0x1c, 0x001d, },
  46. { 0x1f, 0x002d, },
  47. { 0x20, 0x001d, },
  48. { 0x22, 0x0022, },
  49. { 0x23, 0x0020, },
  50. { 0x29, 0x110f, },
  51. { 0x2a, 0x10b4, },
  52. { 0x2b, 0x10ae, },
  53. { 0x2c, 0x0031, },
  54. { 0x31, 0x010d, },
  55. { 0x32, 0x0100, },
  56. { 0x44, 0x0510, },
  57. { 0x54, 0x0104, },
  58. { 0x58, 0x2222, },
  59. { 0x59, 0x1162, },
  60. { 0x5a, 0x3211, },
  61. { 0x5d, 0x0370, },
  62. { 0x5e, 0x0296, },
  63. { 0x61, 0x0010, },
  64. { 0x63, 0x4a00, },
  65. { 0x65, 0x0800, },
  66. { 0x71, 0x0003, },
  67. { 0x72, 0x0470, },
  68. { 0x81, 0x0002, },
  69. { 0x82, 0x0600, },
  70. { 0x86, 0x0002, },
  71. { 0x8a, 0x2c38, },
  72. { 0x8b, 0x2a37, },
  73. { 0x92, 0x302f, },
  74. { 0x93, 0x3332, },
  75. { 0x96, 0x000c, },
  76. { 0x99, 0x0101, },
  77. { 0x9c, 0x2e37, },
  78. { 0x9d, 0x2c37, },
  79. { 0x9e, 0x2c37, },
  80. { 0xab, 0x0100, },
  81. { 0xac, 0x1003, },
  82. { 0xad, 0x103f, },
  83. { 0xe2, 0x0100, },
  84. { 0xe3, 0x1000, },
  85. { 0x28, 0x1010, },
  86. { 0xb1, 0x000e, },
  87. };
  88. /* VSB SNR lookup table */
  89. static struct vsb_snr_tab {
  90. u16 val;
  91. u16 data;
  92. } vsb_snr_tab[] = {
  93. { 924, 300, },
  94. { 923, 300, },
  95. { 918, 295, },
  96. { 915, 290, },
  97. { 911, 285, },
  98. { 906, 280, },
  99. { 901, 275, },
  100. { 896, 270, },
  101. { 891, 265, },
  102. { 885, 260, },
  103. { 879, 255, },
  104. { 873, 250, },
  105. { 864, 245, },
  106. { 858, 240, },
  107. { 850, 235, },
  108. { 841, 230, },
  109. { 832, 225, },
  110. { 823, 220, },
  111. { 812, 215, },
  112. { 802, 210, },
  113. { 788, 205, },
  114. { 778, 200, },
  115. { 767, 195, },
  116. { 753, 190, },
  117. { 740, 185, },
  118. { 725, 180, },
  119. { 707, 175, },
  120. { 689, 170, },
  121. { 671, 165, },
  122. { 656, 160, },
  123. { 637, 155, },
  124. { 616, 150, },
  125. { 542, 145, },
  126. { 519, 140, },
  127. { 507, 135, },
  128. { 497, 130, },
  129. { 492, 125, },
  130. { 474, 120, },
  131. { 300, 111, },
  132. { 0, 0, },
  133. };
  134. /* QAM64 SNR lookup table */
  135. static struct qam64_snr_tab {
  136. u16 val;
  137. u16 data;
  138. } qam64_snr_tab[] = {
  139. { 1, 0, },
  140. { 12, 300, },
  141. { 15, 290, },
  142. { 18, 280, },
  143. { 22, 270, },
  144. { 23, 268, },
  145. { 24, 266, },
  146. { 25, 264, },
  147. { 27, 262, },
  148. { 28, 260, },
  149. { 29, 258, },
  150. { 30, 256, },
  151. { 32, 254, },
  152. { 33, 252, },
  153. { 34, 250, },
  154. { 35, 249, },
  155. { 36, 248, },
  156. { 37, 247, },
  157. { 38, 246, },
  158. { 39, 245, },
  159. { 40, 244, },
  160. { 41, 243, },
  161. { 42, 241, },
  162. { 43, 240, },
  163. { 44, 239, },
  164. { 45, 238, },
  165. { 46, 237, },
  166. { 47, 236, },
  167. { 48, 235, },
  168. { 49, 234, },
  169. { 50, 233, },
  170. { 51, 232, },
  171. { 52, 231, },
  172. { 53, 230, },
  173. { 55, 229, },
  174. { 56, 228, },
  175. { 57, 227, },
  176. { 58, 226, },
  177. { 59, 225, },
  178. { 60, 224, },
  179. { 62, 223, },
  180. { 63, 222, },
  181. { 65, 221, },
  182. { 66, 220, },
  183. { 68, 219, },
  184. { 69, 218, },
  185. { 70, 217, },
  186. { 72, 216, },
  187. { 73, 215, },
  188. { 75, 214, },
  189. { 76, 213, },
  190. { 78, 212, },
  191. { 80, 211, },
  192. { 81, 210, },
  193. { 83, 209, },
  194. { 84, 208, },
  195. { 85, 207, },
  196. { 87, 206, },
  197. { 89, 205, },
  198. { 91, 204, },
  199. { 93, 203, },
  200. { 95, 202, },
  201. { 96, 201, },
  202. { 104, 200, },
  203. { 255, 0, },
  204. };
  205. /* QAM256 SNR lookup table */
  206. static struct qam256_snr_tab {
  207. u16 val;
  208. u16 data;
  209. } qam256_snr_tab[] = {
  210. { 1, 0, },
  211. { 12, 400, },
  212. { 13, 390, },
  213. { 15, 380, },
  214. { 17, 360, },
  215. { 19, 350, },
  216. { 22, 348, },
  217. { 23, 346, },
  218. { 24, 344, },
  219. { 25, 342, },
  220. { 26, 340, },
  221. { 27, 336, },
  222. { 28, 334, },
  223. { 29, 332, },
  224. { 30, 330, },
  225. { 31, 328, },
  226. { 32, 326, },
  227. { 33, 325, },
  228. { 34, 322, },
  229. { 35, 320, },
  230. { 37, 318, },
  231. { 39, 316, },
  232. { 40, 314, },
  233. { 41, 312, },
  234. { 42, 310, },
  235. { 43, 308, },
  236. { 46, 306, },
  237. { 47, 304, },
  238. { 49, 302, },
  239. { 51, 300, },
  240. { 53, 298, },
  241. { 54, 297, },
  242. { 55, 296, },
  243. { 56, 295, },
  244. { 57, 294, },
  245. { 59, 293, },
  246. { 60, 292, },
  247. { 61, 291, },
  248. { 63, 290, },
  249. { 64, 289, },
  250. { 65, 288, },
  251. { 66, 287, },
  252. { 68, 286, },
  253. { 69, 285, },
  254. { 71, 284, },
  255. { 72, 283, },
  256. { 74, 282, },
  257. { 75, 281, },
  258. { 76, 280, },
  259. { 77, 279, },
  260. { 78, 278, },
  261. { 81, 277, },
  262. { 83, 276, },
  263. { 84, 275, },
  264. { 86, 274, },
  265. { 87, 273, },
  266. { 89, 272, },
  267. { 90, 271, },
  268. { 92, 270, },
  269. { 93, 269, },
  270. { 95, 268, },
  271. { 96, 267, },
  272. { 98, 266, },
  273. { 100, 265, },
  274. { 102, 264, },
  275. { 104, 263, },
  276. { 105, 262, },
  277. { 106, 261, },
  278. { 110, 260, },
  279. { 255, 0, },
  280. };
  281. /* 8 bit registers, 16 bit values */
  282. static int s5h1409_writereg(struct s5h1409_state *state, u8 reg, u16 data)
  283. {
  284. int ret;
  285. u8 buf[] = { reg, data >> 8, data & 0xff };
  286. struct i2c_msg msg = { .addr = state->config->demod_address,
  287. .flags = 0, .buf = buf, .len = 3 };
  288. ret = i2c_transfer(state->i2c, &msg, 1);
  289. if (ret != 1)
  290. printk(KERN_ERR "%s: error (reg == 0x%02x, val == 0x%04x, ret == %i)\n",
  291. __func__, reg, data, ret);
  292. return (ret != 1) ? -1 : 0;
  293. }
  294. static u16 s5h1409_readreg(struct s5h1409_state *state, u8 reg)
  295. {
  296. int ret;
  297. u8 b0[] = { reg };
  298. u8 b1[] = { 0, 0 };
  299. struct i2c_msg msg[] = {
  300. { .addr = state->config->demod_address, .flags = 0,
  301. .buf = b0, .len = 1 },
  302. { .addr = state->config->demod_address, .flags = I2C_M_RD,
  303. .buf = b1, .len = 2 } };
  304. ret = i2c_transfer(state->i2c, msg, 2);
  305. if (ret != 2)
  306. printk("%s: readreg error (ret == %i)\n", __func__, ret);
  307. return (b1[0] << 8) | b1[1];
  308. }
  309. static int s5h1409_softreset(struct dvb_frontend *fe)
  310. {
  311. struct s5h1409_state *state = fe->demodulator_priv;
  312. dprintk("%s()\n", __func__);
  313. s5h1409_writereg(state, 0xf5, 0);
  314. s5h1409_writereg(state, 0xf5, 1);
  315. state->is_qam_locked = 0;
  316. state->qam_state = QAM_STATE_UNTUNED;
  317. return 0;
  318. }
  319. #define S5H1409_VSB_IF_FREQ 5380
  320. #define S5H1409_QAM_IF_FREQ (state->config->qam_if)
  321. static int s5h1409_set_if_freq(struct dvb_frontend *fe, int KHz)
  322. {
  323. struct s5h1409_state *state = fe->demodulator_priv;
  324. dprintk("%s(%d KHz)\n", __func__, KHz);
  325. switch (KHz) {
  326. case 4000:
  327. s5h1409_writereg(state, 0x87, 0x014b);
  328. s5h1409_writereg(state, 0x88, 0x0cb5);
  329. s5h1409_writereg(state, 0x89, 0x03e2);
  330. break;
  331. case 5380:
  332. case 44000:
  333. default:
  334. s5h1409_writereg(state, 0x87, 0x01be);
  335. s5h1409_writereg(state, 0x88, 0x0436);
  336. s5h1409_writereg(state, 0x89, 0x054d);
  337. break;
  338. }
  339. state->if_freq = KHz;
  340. return 0;
  341. }
  342. static int s5h1409_set_spectralinversion(struct dvb_frontend *fe, int inverted)
  343. {
  344. struct s5h1409_state *state = fe->demodulator_priv;
  345. dprintk("%s(%d)\n", __func__, inverted);
  346. if (inverted == 1)
  347. return s5h1409_writereg(state, 0x1b, 0x1101); /* Inverted */
  348. else
  349. return s5h1409_writereg(state, 0x1b, 0x0110); /* Normal */
  350. }
  351. static int s5h1409_enable_modulation(struct dvb_frontend *fe,
  352. enum fe_modulation m)
  353. {
  354. struct s5h1409_state *state = fe->demodulator_priv;
  355. dprintk("%s(0x%08x)\n", __func__, m);
  356. switch (m) {
  357. case VSB_8:
  358. dprintk("%s() VSB_8\n", __func__);
  359. if (state->if_freq != S5H1409_VSB_IF_FREQ)
  360. s5h1409_set_if_freq(fe, S5H1409_VSB_IF_FREQ);
  361. s5h1409_writereg(state, 0xf4, 0);
  362. break;
  363. case QAM_64:
  364. case QAM_256:
  365. case QAM_AUTO:
  366. dprintk("%s() QAM_AUTO (64/256)\n", __func__);
  367. if (state->if_freq != S5H1409_QAM_IF_FREQ)
  368. s5h1409_set_if_freq(fe, S5H1409_QAM_IF_FREQ);
  369. s5h1409_writereg(state, 0xf4, 1);
  370. s5h1409_writereg(state, 0x85, 0x110);
  371. break;
  372. default:
  373. dprintk("%s() Invalid modulation\n", __func__);
  374. return -EINVAL;
  375. }
  376. state->current_modulation = m;
  377. s5h1409_softreset(fe);
  378. return 0;
  379. }
  380. static int s5h1409_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
  381. {
  382. struct s5h1409_state *state = fe->demodulator_priv;
  383. dprintk("%s(%d)\n", __func__, enable);
  384. if (enable)
  385. return s5h1409_writereg(state, 0xf3, 1);
  386. else
  387. return s5h1409_writereg(state, 0xf3, 0);
  388. }
  389. static int s5h1409_set_gpio(struct dvb_frontend *fe, int enable)
  390. {
  391. struct s5h1409_state *state = fe->demodulator_priv;
  392. dprintk("%s(%d)\n", __func__, enable);
  393. if (enable)
  394. return s5h1409_writereg(state, 0xe3,
  395. s5h1409_readreg(state, 0xe3) | 0x1100);
  396. else
  397. return s5h1409_writereg(state, 0xe3,
  398. s5h1409_readreg(state, 0xe3) & 0xfeff);
  399. }
  400. static int s5h1409_sleep(struct dvb_frontend *fe, int enable)
  401. {
  402. struct s5h1409_state *state = fe->demodulator_priv;
  403. dprintk("%s(%d)\n", __func__, enable);
  404. return s5h1409_writereg(state, 0xf2, enable);
  405. }
  406. static int s5h1409_register_reset(struct dvb_frontend *fe)
  407. {
  408. struct s5h1409_state *state = fe->demodulator_priv;
  409. dprintk("%s()\n", __func__);
  410. return s5h1409_writereg(state, 0xfa, 0);
  411. }
  412. static void s5h1409_set_qam_amhum_mode(struct dvb_frontend *fe)
  413. {
  414. struct s5h1409_state *state = fe->demodulator_priv;
  415. u16 reg;
  416. if (state->qam_state < QAM_STATE_INTERLEAVE_SET) {
  417. /* We should not perform amhum optimization until
  418. the interleave mode has been configured */
  419. return;
  420. }
  421. if (state->qam_state == QAM_STATE_QAM_OPTIMIZED_L3) {
  422. /* We've already reached the maximum optimization level, so
  423. don't bother banging on the status registers */
  424. return;
  425. }
  426. /* QAM EQ lock check */
  427. reg = s5h1409_readreg(state, 0xf0);
  428. if ((reg >> 13) & 0x1) {
  429. reg &= 0xff;
  430. s5h1409_writereg(state, 0x96, 0x000c);
  431. if (reg < 0x68) {
  432. if (state->qam_state < QAM_STATE_QAM_OPTIMIZED_L3) {
  433. dprintk("%s() setting QAM state to OPT_L3\n",
  434. __func__);
  435. s5h1409_writereg(state, 0x93, 0x3130);
  436. s5h1409_writereg(state, 0x9e, 0x2836);
  437. state->qam_state = QAM_STATE_QAM_OPTIMIZED_L3;
  438. }
  439. } else {
  440. if (state->qam_state < QAM_STATE_QAM_OPTIMIZED_L2) {
  441. dprintk("%s() setting QAM state to OPT_L2\n",
  442. __func__);
  443. s5h1409_writereg(state, 0x93, 0x3332);
  444. s5h1409_writereg(state, 0x9e, 0x2c37);
  445. state->qam_state = QAM_STATE_QAM_OPTIMIZED_L2;
  446. }
  447. }
  448. } else {
  449. if (state->qam_state < QAM_STATE_QAM_OPTIMIZED_L1) {
  450. dprintk("%s() setting QAM state to OPT_L1\n", __func__);
  451. s5h1409_writereg(state, 0x96, 0x0008);
  452. s5h1409_writereg(state, 0x93, 0x3332);
  453. s5h1409_writereg(state, 0x9e, 0x2c37);
  454. state->qam_state = QAM_STATE_QAM_OPTIMIZED_L1;
  455. }
  456. }
  457. }
  458. static void s5h1409_set_qam_amhum_mode_legacy(struct dvb_frontend *fe)
  459. {
  460. struct s5h1409_state *state = fe->demodulator_priv;
  461. u16 reg;
  462. if (state->is_qam_locked)
  463. return;
  464. /* QAM EQ lock check */
  465. reg = s5h1409_readreg(state, 0xf0);
  466. if ((reg >> 13) & 0x1) {
  467. state->is_qam_locked = 1;
  468. reg &= 0xff;
  469. s5h1409_writereg(state, 0x96, 0x00c);
  470. if ((reg < 0x38) || (reg > 0x68)) {
  471. s5h1409_writereg(state, 0x93, 0x3332);
  472. s5h1409_writereg(state, 0x9e, 0x2c37);
  473. } else {
  474. s5h1409_writereg(state, 0x93, 0x3130);
  475. s5h1409_writereg(state, 0x9e, 0x2836);
  476. }
  477. } else {
  478. s5h1409_writereg(state, 0x96, 0x0008);
  479. s5h1409_writereg(state, 0x93, 0x3332);
  480. s5h1409_writereg(state, 0x9e, 0x2c37);
  481. }
  482. }
  483. static void s5h1409_set_qam_interleave_mode(struct dvb_frontend *fe)
  484. {
  485. struct s5h1409_state *state = fe->demodulator_priv;
  486. u16 reg, reg1, reg2;
  487. if (state->qam_state >= QAM_STATE_INTERLEAVE_SET) {
  488. /* We've done the optimization already */
  489. return;
  490. }
  491. reg = s5h1409_readreg(state, 0xf1);
  492. /* Master lock */
  493. if ((reg >> 15) & 0x1) {
  494. if (state->qam_state == QAM_STATE_UNTUNED ||
  495. state->qam_state == QAM_STATE_TUNING_STARTED) {
  496. dprintk("%s() setting QAM state to INTERLEAVE_SET\n",
  497. __func__);
  498. reg1 = s5h1409_readreg(state, 0xb2);
  499. reg2 = s5h1409_readreg(state, 0xad);
  500. s5h1409_writereg(state, 0x96, 0x0020);
  501. s5h1409_writereg(state, 0xad,
  502. (((reg1 & 0xf000) >> 4) | (reg2 & 0xf0ff)));
  503. state->qam_state = QAM_STATE_INTERLEAVE_SET;
  504. }
  505. } else {
  506. if (state->qam_state == QAM_STATE_UNTUNED) {
  507. dprintk("%s() setting QAM state to TUNING_STARTED\n",
  508. __func__);
  509. s5h1409_writereg(state, 0x96, 0x08);
  510. s5h1409_writereg(state, 0xab,
  511. s5h1409_readreg(state, 0xab) | 0x1001);
  512. state->qam_state = QAM_STATE_TUNING_STARTED;
  513. }
  514. }
  515. }
  516. static void s5h1409_set_qam_interleave_mode_legacy(struct dvb_frontend *fe)
  517. {
  518. struct s5h1409_state *state = fe->demodulator_priv;
  519. u16 reg, reg1, reg2;
  520. reg = s5h1409_readreg(state, 0xf1);
  521. /* Master lock */
  522. if ((reg >> 15) & 0x1) {
  523. if (state->qam_state != 2) {
  524. state->qam_state = 2;
  525. reg1 = s5h1409_readreg(state, 0xb2);
  526. reg2 = s5h1409_readreg(state, 0xad);
  527. s5h1409_writereg(state, 0x96, 0x20);
  528. s5h1409_writereg(state, 0xad,
  529. (((reg1 & 0xf000) >> 4) | (reg2 & 0xf0ff)));
  530. s5h1409_writereg(state, 0xab,
  531. s5h1409_readreg(state, 0xab) & 0xeffe);
  532. }
  533. } else {
  534. if (state->qam_state != 1) {
  535. state->qam_state = 1;
  536. s5h1409_writereg(state, 0x96, 0x08);
  537. s5h1409_writereg(state, 0xab,
  538. s5h1409_readreg(state, 0xab) | 0x1001);
  539. }
  540. }
  541. }
  542. /* Talk to the demod, set the FEC, GUARD, QAM settings etc */
  543. static int s5h1409_set_frontend(struct dvb_frontend *fe)
  544. {
  545. struct dtv_frontend_properties *p = &fe->dtv_property_cache;
  546. struct s5h1409_state *state = fe->demodulator_priv;
  547. dprintk("%s(frequency=%d)\n", __func__, p->frequency);
  548. s5h1409_softreset(fe);
  549. state->current_frequency = p->frequency;
  550. s5h1409_enable_modulation(fe, p->modulation);
  551. if (fe->ops.tuner_ops.set_params) {
  552. if (fe->ops.i2c_gate_ctrl)
  553. fe->ops.i2c_gate_ctrl(fe, 1);
  554. fe->ops.tuner_ops.set_params(fe);
  555. if (fe->ops.i2c_gate_ctrl)
  556. fe->ops.i2c_gate_ctrl(fe, 0);
  557. }
  558. /* Issue a reset to the demod so it knows to resync against the
  559. newly tuned frequency */
  560. s5h1409_softreset(fe);
  561. /* Optimize the demod for QAM */
  562. if (state->current_modulation != VSB_8) {
  563. /* This almost certainly applies to all boards, but for now
  564. only do it for the HVR-1600. Once the other boards are
  565. tested, the "legacy" versions can just go away */
  566. if (state->config->hvr1600_opt == S5H1409_HVR1600_OPTIMIZE) {
  567. s5h1409_set_qam_interleave_mode(fe);
  568. s5h1409_set_qam_amhum_mode(fe);
  569. } else {
  570. s5h1409_set_qam_amhum_mode_legacy(fe);
  571. s5h1409_set_qam_interleave_mode_legacy(fe);
  572. }
  573. }
  574. return 0;
  575. }
  576. static int s5h1409_set_mpeg_timing(struct dvb_frontend *fe, int mode)
  577. {
  578. struct s5h1409_state *state = fe->demodulator_priv;
  579. u16 val;
  580. dprintk("%s(%d)\n", __func__, mode);
  581. val = s5h1409_readreg(state, 0xac) & 0xcfff;
  582. switch (mode) {
  583. case S5H1409_MPEGTIMING_CONTINUOUS_INVERTING_CLOCK:
  584. val |= 0x0000;
  585. break;
  586. case S5H1409_MPEGTIMING_CONTINUOUS_NONINVERTING_CLOCK:
  587. dprintk("%s(%d) Mode1 or Defaulting\n", __func__, mode);
  588. val |= 0x1000;
  589. break;
  590. case S5H1409_MPEGTIMING_NONCONTINUOUS_INVERTING_CLOCK:
  591. val |= 0x2000;
  592. break;
  593. case S5H1409_MPEGTIMING_NONCONTINUOUS_NONINVERTING_CLOCK:
  594. val |= 0x3000;
  595. break;
  596. default:
  597. return -EINVAL;
  598. }
  599. /* Configure MPEG Signal Timing charactistics */
  600. return s5h1409_writereg(state, 0xac, val);
  601. }
  602. /* Reset the demod hardware and reset all of the configuration registers
  603. to a default state. */
  604. static int s5h1409_init(struct dvb_frontend *fe)
  605. {
  606. int i;
  607. struct s5h1409_state *state = fe->demodulator_priv;
  608. dprintk("%s()\n", __func__);
  609. s5h1409_sleep(fe, 0);
  610. s5h1409_register_reset(fe);
  611. for (i = 0; i < ARRAY_SIZE(init_tab); i++)
  612. s5h1409_writereg(state, init_tab[i].reg, init_tab[i].data);
  613. /* The datasheet says that after initialisation, VSB is default */
  614. state->current_modulation = VSB_8;
  615. /* Optimize for the HVR-1600 if appropriate. Note that some of these
  616. may get folded into the generic case after testing with other
  617. devices */
  618. if (state->config->hvr1600_opt == S5H1409_HVR1600_OPTIMIZE) {
  619. /* VSB AGC REF */
  620. s5h1409_writereg(state, 0x09, 0x0050);
  621. /* Unknown but Windows driver does it... */
  622. s5h1409_writereg(state, 0x21, 0x0001);
  623. s5h1409_writereg(state, 0x50, 0x030e);
  624. /* QAM AGC REF */
  625. s5h1409_writereg(state, 0x82, 0x0800);
  626. }
  627. if (state->config->output_mode == S5H1409_SERIAL_OUTPUT)
  628. s5h1409_writereg(state, 0xab,
  629. s5h1409_readreg(state, 0xab) | 0x100); /* Serial */
  630. else
  631. s5h1409_writereg(state, 0xab,
  632. s5h1409_readreg(state, 0xab) & 0xfeff); /* Parallel */
  633. s5h1409_set_spectralinversion(fe, state->config->inversion);
  634. s5h1409_set_if_freq(fe, state->if_freq);
  635. s5h1409_set_gpio(fe, state->config->gpio);
  636. s5h1409_set_mpeg_timing(fe, state->config->mpeg_timing);
  637. s5h1409_softreset(fe);
  638. /* Note: Leaving the I2C gate closed. */
  639. s5h1409_i2c_gate_ctrl(fe, 0);
  640. return 0;
  641. }
  642. static int s5h1409_read_status(struct dvb_frontend *fe, enum fe_status *status)
  643. {
  644. struct s5h1409_state *state = fe->demodulator_priv;
  645. u16 reg;
  646. u32 tuner_status = 0;
  647. *status = 0;
  648. /* Optimize the demod for QAM */
  649. if (state->current_modulation != VSB_8) {
  650. /* This almost certainly applies to all boards, but for now
  651. only do it for the HVR-1600. Once the other boards are
  652. tested, the "legacy" versions can just go away */
  653. if (state->config->hvr1600_opt == S5H1409_HVR1600_OPTIMIZE) {
  654. s5h1409_set_qam_interleave_mode(fe);
  655. s5h1409_set_qam_amhum_mode(fe);
  656. }
  657. }
  658. /* Get the demodulator status */
  659. reg = s5h1409_readreg(state, 0xf1);
  660. if (reg & 0x1000)
  661. *status |= FE_HAS_VITERBI;
  662. if (reg & 0x8000)
  663. *status |= FE_HAS_LOCK | FE_HAS_SYNC;
  664. switch (state->config->status_mode) {
  665. case S5H1409_DEMODLOCKING:
  666. if (*status & FE_HAS_VITERBI)
  667. *status |= FE_HAS_CARRIER | FE_HAS_SIGNAL;
  668. break;
  669. case S5H1409_TUNERLOCKING:
  670. /* Get the tuner status */
  671. if (fe->ops.tuner_ops.get_status) {
  672. if (fe->ops.i2c_gate_ctrl)
  673. fe->ops.i2c_gate_ctrl(fe, 1);
  674. fe->ops.tuner_ops.get_status(fe, &tuner_status);
  675. if (fe->ops.i2c_gate_ctrl)
  676. fe->ops.i2c_gate_ctrl(fe, 0);
  677. }
  678. if (tuner_status)
  679. *status |= FE_HAS_CARRIER | FE_HAS_SIGNAL;
  680. break;
  681. }
  682. dprintk("%s() status 0x%08x\n", __func__, *status);
  683. return 0;
  684. }
  685. static int s5h1409_qam256_lookup_snr(struct dvb_frontend *fe, u16 *snr, u16 v)
  686. {
  687. int i, ret = -EINVAL;
  688. dprintk("%s()\n", __func__);
  689. for (i = 0; i < ARRAY_SIZE(qam256_snr_tab); i++) {
  690. if (v < qam256_snr_tab[i].val) {
  691. *snr = qam256_snr_tab[i].data;
  692. ret = 0;
  693. break;
  694. }
  695. }
  696. return ret;
  697. }
  698. static int s5h1409_qam64_lookup_snr(struct dvb_frontend *fe, u16 *snr, u16 v)
  699. {
  700. int i, ret = -EINVAL;
  701. dprintk("%s()\n", __func__);
  702. for (i = 0; i < ARRAY_SIZE(qam64_snr_tab); i++) {
  703. if (v < qam64_snr_tab[i].val) {
  704. *snr = qam64_snr_tab[i].data;
  705. ret = 0;
  706. break;
  707. }
  708. }
  709. return ret;
  710. }
  711. static int s5h1409_vsb_lookup_snr(struct dvb_frontend *fe, u16 *snr, u16 v)
  712. {
  713. int i, ret = -EINVAL;
  714. dprintk("%s()\n", __func__);
  715. for (i = 0; i < ARRAY_SIZE(vsb_snr_tab); i++) {
  716. if (v > vsb_snr_tab[i].val) {
  717. *snr = vsb_snr_tab[i].data;
  718. ret = 0;
  719. break;
  720. }
  721. }
  722. dprintk("%s() snr=%d\n", __func__, *snr);
  723. return ret;
  724. }
  725. static int s5h1409_read_snr(struct dvb_frontend *fe, u16 *snr)
  726. {
  727. struct s5h1409_state *state = fe->demodulator_priv;
  728. u16 reg;
  729. dprintk("%s()\n", __func__);
  730. switch (state->current_modulation) {
  731. case QAM_64:
  732. reg = s5h1409_readreg(state, 0xf0) & 0xff;
  733. return s5h1409_qam64_lookup_snr(fe, snr, reg);
  734. case QAM_256:
  735. reg = s5h1409_readreg(state, 0xf0) & 0xff;
  736. return s5h1409_qam256_lookup_snr(fe, snr, reg);
  737. case VSB_8:
  738. reg = s5h1409_readreg(state, 0xf1) & 0x3ff;
  739. return s5h1409_vsb_lookup_snr(fe, snr, reg);
  740. default:
  741. break;
  742. }
  743. return -EINVAL;
  744. }
  745. static int s5h1409_read_signal_strength(struct dvb_frontend *fe,
  746. u16 *signal_strength)
  747. {
  748. /* borrowed from lgdt330x.c
  749. *
  750. * Calculate strength from SNR up to 35dB
  751. * Even though the SNR can go higher than 35dB,
  752. * there is some comfort factor in having a range of
  753. * strong signals that can show at 100%
  754. */
  755. u16 snr;
  756. u32 tmp;
  757. int ret = s5h1409_read_snr(fe, &snr);
  758. *signal_strength = 0;
  759. if (0 == ret) {
  760. /* The following calculation method was chosen
  761. * purely for the sake of code re-use from the
  762. * other demod drivers that use this method */
  763. /* Convert from SNR in dB * 10 to 8.24 fixed-point */
  764. tmp = (snr * ((1 << 24) / 10));
  765. /* Convert from 8.24 fixed-point to
  766. * scale the range 0 - 35*2^24 into 0 - 65535*/
  767. if (tmp >= 8960 * 0x10000)
  768. *signal_strength = 0xffff;
  769. else
  770. *signal_strength = tmp / 8960;
  771. }
  772. return ret;
  773. }
  774. static int s5h1409_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
  775. {
  776. struct s5h1409_state *state = fe->demodulator_priv;
  777. *ucblocks = s5h1409_readreg(state, 0xb5);
  778. return 0;
  779. }
  780. static int s5h1409_read_ber(struct dvb_frontend *fe, u32 *ber)
  781. {
  782. return s5h1409_read_ucblocks(fe, ber);
  783. }
  784. static int s5h1409_get_frontend(struct dvb_frontend *fe,
  785. struct dtv_frontend_properties *p)
  786. {
  787. struct s5h1409_state *state = fe->demodulator_priv;
  788. p->frequency = state->current_frequency;
  789. p->modulation = state->current_modulation;
  790. return 0;
  791. }
  792. static int s5h1409_get_tune_settings(struct dvb_frontend *fe,
  793. struct dvb_frontend_tune_settings *tune)
  794. {
  795. tune->min_delay_ms = 1000;
  796. return 0;
  797. }
  798. static void s5h1409_release(struct dvb_frontend *fe)
  799. {
  800. struct s5h1409_state *state = fe->demodulator_priv;
  801. kfree(state);
  802. }
  803. static const struct dvb_frontend_ops s5h1409_ops;
  804. struct dvb_frontend *s5h1409_attach(const struct s5h1409_config *config,
  805. struct i2c_adapter *i2c)
  806. {
  807. struct s5h1409_state *state = NULL;
  808. u16 reg;
  809. /* allocate memory for the internal state */
  810. state = kzalloc(sizeof(struct s5h1409_state), GFP_KERNEL);
  811. if (state == NULL)
  812. goto error;
  813. /* setup the state */
  814. state->config = config;
  815. state->i2c = i2c;
  816. state->current_modulation = 0;
  817. state->if_freq = S5H1409_VSB_IF_FREQ;
  818. /* check if the demod exists */
  819. reg = s5h1409_readreg(state, 0x04);
  820. if ((reg != 0x0066) && (reg != 0x007f))
  821. goto error;
  822. /* create dvb_frontend */
  823. memcpy(&state->frontend.ops, &s5h1409_ops,
  824. sizeof(struct dvb_frontend_ops));
  825. state->frontend.demodulator_priv = state;
  826. if (s5h1409_init(&state->frontend) != 0) {
  827. printk(KERN_ERR "%s: Failed to initialize correctly\n",
  828. __func__);
  829. goto error;
  830. }
  831. /* Note: Leaving the I2C gate open here. */
  832. s5h1409_i2c_gate_ctrl(&state->frontend, 1);
  833. return &state->frontend;
  834. error:
  835. kfree(state);
  836. return NULL;
  837. }
  838. EXPORT_SYMBOL(s5h1409_attach);
  839. static const struct dvb_frontend_ops s5h1409_ops = {
  840. .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
  841. .info = {
  842. .name = "Samsung S5H1409 QAM/8VSB Frontend",
  843. .frequency_min_hz = 54 * MHz,
  844. .frequency_max_hz = 858 * MHz,
  845. .frequency_stepsize_hz = 62500,
  846. .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
  847. },
  848. .init = s5h1409_init,
  849. .i2c_gate_ctrl = s5h1409_i2c_gate_ctrl,
  850. .set_frontend = s5h1409_set_frontend,
  851. .get_frontend = s5h1409_get_frontend,
  852. .get_tune_settings = s5h1409_get_tune_settings,
  853. .read_status = s5h1409_read_status,
  854. .read_ber = s5h1409_read_ber,
  855. .read_signal_strength = s5h1409_read_signal_strength,
  856. .read_snr = s5h1409_read_snr,
  857. .read_ucblocks = s5h1409_read_ucblocks,
  858. .release = s5h1409_release,
  859. };
  860. MODULE_DESCRIPTION("Samsung S5H1409 QAM-B/ATSC Demodulator driver");
  861. MODULE_AUTHOR("Steven Toth");
  862. MODULE_LICENSE("GPL");