nxt200x.c 29 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Support for NXT2002 and NXT2004 - VSB/QAM
  4. *
  5. * Copyright (C) 2005 Kirk Lapray <kirk.lapray@gmail.com>
  6. * Copyright (C) 2006-2014 Michael Krufky <mkrufky@linuxtv.org>
  7. * based on nxt2002 by Taylor Jacob <rtjacob@earthlink.net>
  8. * and nxt2004 by Jean-Francois Thibert <jeanfrancois@sagetv.com>
  9. */
  10. /*
  11. * NOTES ABOUT THIS DRIVER
  12. *
  13. * This Linux driver supports:
  14. * B2C2/BBTI Technisat Air2PC - ATSC (NXT2002)
  15. * AverTVHD MCE A180 (NXT2004)
  16. * ATI HDTV Wonder (NXT2004)
  17. *
  18. * This driver needs external firmware. Please use the command
  19. * "<kerneldir>/scripts/get_dvb_firmware nxt2002" or
  20. * "<kerneldir>/scripts/get_dvb_firmware nxt2004" to
  21. * download/extract the appropriate firmware, and then copy it to
  22. * /usr/lib/hotplug/firmware/ or /lib/firmware/
  23. * (depending on configuration of firmware hotplug).
  24. */
  25. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  26. /* Max transfer size done by I2C transfer functions */
  27. #define MAX_XFER_SIZE 256
  28. #define NXT2002_DEFAULT_FIRMWARE "dvb-fe-nxt2002.fw"
  29. #define NXT2004_DEFAULT_FIRMWARE "dvb-fe-nxt2004.fw"
  30. #define CRC_CCIT_MASK 0x1021
  31. #include <linux/kernel.h>
  32. #include <linux/init.h>
  33. #include <linux/module.h>
  34. #include <linux/slab.h>
  35. #include <linux/string.h>
  36. #include <media/dvb_frontend.h>
  37. #include "nxt200x.h"
  38. struct nxt200x_state {
  39. struct i2c_adapter* i2c;
  40. const struct nxt200x_config* config;
  41. struct dvb_frontend frontend;
  42. /* demodulator private data */
  43. nxt_chip_type demod_chip;
  44. u8 initialised:1;
  45. };
  46. static int debug;
  47. #define dprintk(args...) do { if (debug) pr_debug(args); } while (0)
  48. static int i2c_writebytes (struct nxt200x_state* state, u8 addr, u8 *buf, u8 len)
  49. {
  50. int err;
  51. struct i2c_msg msg = { .addr = addr, .flags = 0, .buf = buf, .len = len };
  52. if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) {
  53. pr_warn("%s: i2c write error (addr 0x%02x, err == %i)\n",
  54. __func__, addr, err);
  55. return -EREMOTEIO;
  56. }
  57. return 0;
  58. }
  59. static int i2c_readbytes(struct nxt200x_state *state, u8 addr, u8 *buf, u8 len)
  60. {
  61. int err;
  62. struct i2c_msg msg = { .addr = addr, .flags = I2C_M_RD, .buf = buf, .len = len };
  63. if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) {
  64. pr_warn("%s: i2c read error (addr 0x%02x, err == %i)\n",
  65. __func__, addr, err);
  66. return -EREMOTEIO;
  67. }
  68. return 0;
  69. }
  70. static int nxt200x_writebytes (struct nxt200x_state* state, u8 reg,
  71. const u8 *buf, u8 len)
  72. {
  73. u8 buf2[MAX_XFER_SIZE];
  74. int err;
  75. struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf2, .len = len + 1 };
  76. if (1 + len > sizeof(buf2)) {
  77. pr_warn("%s: i2c wr reg=%04x: len=%d is too big!\n",
  78. __func__, reg, len);
  79. return -EINVAL;
  80. }
  81. buf2[0] = reg;
  82. memcpy(&buf2[1], buf, len);
  83. if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) {
  84. pr_warn("%s: i2c write error (addr 0x%02x, err == %i)\n",
  85. __func__, state->config->demod_address, err);
  86. return -EREMOTEIO;
  87. }
  88. return 0;
  89. }
  90. static int nxt200x_readbytes(struct nxt200x_state *state, u8 reg, u8 *buf, u8 len)
  91. {
  92. u8 reg2 [] = { reg };
  93. struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = reg2, .len = 1 },
  94. { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = buf, .len = len } };
  95. int err;
  96. if ((err = i2c_transfer (state->i2c, msg, 2)) != 2) {
  97. pr_warn("%s: i2c read error (addr 0x%02x, err == %i)\n",
  98. __func__, state->config->demod_address, err);
  99. return -EREMOTEIO;
  100. }
  101. return 0;
  102. }
  103. static u16 nxt200x_crc(u16 crc, u8 c)
  104. {
  105. u8 i;
  106. u16 input = (u16) c & 0xFF;
  107. input<<=8;
  108. for(i=0; i<8; i++) {
  109. if((crc^input) & 0x8000)
  110. crc=(crc<<1)^CRC_CCIT_MASK;
  111. else
  112. crc<<=1;
  113. input<<=1;
  114. }
  115. return crc;
  116. }
  117. static int nxt200x_writereg_multibyte (struct nxt200x_state* state, u8 reg, u8* data, u8 len)
  118. {
  119. u8 attr, len2, buf;
  120. dprintk("%s\n", __func__);
  121. /* set multi register register */
  122. nxt200x_writebytes(state, 0x35, &reg, 1);
  123. /* send the actual data */
  124. nxt200x_writebytes(state, 0x36, data, len);
  125. switch (state->demod_chip) {
  126. case NXT2002:
  127. len2 = len;
  128. buf = 0x02;
  129. break;
  130. case NXT2004:
  131. /* probably not right, but gives correct values */
  132. attr = 0x02;
  133. if (reg & 0x80) {
  134. attr = attr << 1;
  135. if (reg & 0x04)
  136. attr = attr >> 1;
  137. }
  138. /* set write bit */
  139. len2 = ((attr << 4) | 0x10) | len;
  140. buf = 0x80;
  141. break;
  142. default:
  143. return -EINVAL;
  144. break;
  145. }
  146. /* set multi register length */
  147. nxt200x_writebytes(state, 0x34, &len2, 1);
  148. /* toggle the multireg write bit */
  149. nxt200x_writebytes(state, 0x21, &buf, 1);
  150. nxt200x_readbytes(state, 0x21, &buf, 1);
  151. switch (state->demod_chip) {
  152. case NXT2002:
  153. if ((buf & 0x02) == 0)
  154. return 0;
  155. break;
  156. case NXT2004:
  157. if (buf == 0)
  158. return 0;
  159. break;
  160. default:
  161. return -EINVAL;
  162. break;
  163. }
  164. pr_warn("Error writing multireg register 0x%02X\n", reg);
  165. return 0;
  166. }
  167. static int nxt200x_readreg_multibyte (struct nxt200x_state* state, u8 reg, u8* data, u8 len)
  168. {
  169. int i;
  170. u8 buf, len2, attr;
  171. dprintk("%s\n", __func__);
  172. /* set multi register register */
  173. nxt200x_writebytes(state, 0x35, &reg, 1);
  174. switch (state->demod_chip) {
  175. case NXT2002:
  176. /* set multi register length */
  177. len2 = len & 0x80;
  178. nxt200x_writebytes(state, 0x34, &len2, 1);
  179. /* read the actual data */
  180. nxt200x_readbytes(state, reg, data, len);
  181. return 0;
  182. break;
  183. case NXT2004:
  184. /* probably not right, but gives correct values */
  185. attr = 0x02;
  186. if (reg & 0x80) {
  187. attr = attr << 1;
  188. if (reg & 0x04)
  189. attr = attr >> 1;
  190. }
  191. /* set multi register length */
  192. len2 = (attr << 4) | len;
  193. nxt200x_writebytes(state, 0x34, &len2, 1);
  194. /* toggle the multireg bit*/
  195. buf = 0x80;
  196. nxt200x_writebytes(state, 0x21, &buf, 1);
  197. /* read the actual data */
  198. for(i = 0; i < len; i++) {
  199. nxt200x_readbytes(state, 0x36 + i, &data[i], 1);
  200. }
  201. return 0;
  202. break;
  203. default:
  204. return -EINVAL;
  205. break;
  206. }
  207. }
  208. static void nxt200x_microcontroller_stop (struct nxt200x_state* state)
  209. {
  210. u8 buf, stopval, counter = 0;
  211. dprintk("%s\n", __func__);
  212. /* set correct stop value */
  213. switch (state->demod_chip) {
  214. case NXT2002:
  215. stopval = 0x40;
  216. break;
  217. case NXT2004:
  218. stopval = 0x10;
  219. break;
  220. default:
  221. stopval = 0;
  222. break;
  223. }
  224. buf = 0x80;
  225. nxt200x_writebytes(state, 0x22, &buf, 1);
  226. while (counter < 20) {
  227. nxt200x_readbytes(state, 0x31, &buf, 1);
  228. if (buf & stopval)
  229. return;
  230. msleep(10);
  231. counter++;
  232. }
  233. pr_warn("Timeout waiting for nxt200x to stop. This is ok after firmware upload.\n");
  234. return;
  235. }
  236. static void nxt200x_microcontroller_start (struct nxt200x_state* state)
  237. {
  238. u8 buf;
  239. dprintk("%s\n", __func__);
  240. buf = 0x00;
  241. nxt200x_writebytes(state, 0x22, &buf, 1);
  242. }
  243. static void nxt2004_microcontroller_init (struct nxt200x_state* state)
  244. {
  245. u8 buf[9];
  246. u8 counter = 0;
  247. dprintk("%s\n", __func__);
  248. buf[0] = 0x00;
  249. nxt200x_writebytes(state, 0x2b, buf, 1);
  250. buf[0] = 0x70;
  251. nxt200x_writebytes(state, 0x34, buf, 1);
  252. buf[0] = 0x04;
  253. nxt200x_writebytes(state, 0x35, buf, 1);
  254. buf[0] = 0x01; buf[1] = 0x23; buf[2] = 0x45; buf[3] = 0x67; buf[4] = 0x89;
  255. buf[5] = 0xAB; buf[6] = 0xCD; buf[7] = 0xEF; buf[8] = 0xC0;
  256. nxt200x_writebytes(state, 0x36, buf, 9);
  257. buf[0] = 0x80;
  258. nxt200x_writebytes(state, 0x21, buf, 1);
  259. while (counter < 20) {
  260. nxt200x_readbytes(state, 0x21, buf, 1);
  261. if (buf[0] == 0)
  262. return;
  263. msleep(10);
  264. counter++;
  265. }
  266. pr_warn("Timeout waiting for nxt2004 to init.\n");
  267. return;
  268. }
  269. static int nxt200x_writetuner (struct nxt200x_state* state, u8* data)
  270. {
  271. u8 buf, count = 0;
  272. dprintk("%s\n", __func__);
  273. dprintk("Tuner Bytes: %*ph\n", 4, data + 1);
  274. /* if NXT2004, write directly to tuner. if NXT2002, write through NXT chip.
  275. * direct write is required for Philips TUV1236D and ALPS TDHU2 */
  276. switch (state->demod_chip) {
  277. case NXT2004:
  278. if (i2c_writebytes(state, data[0], data+1, 4))
  279. pr_warn("error writing to tuner\n");
  280. /* wait until we have a lock */
  281. while (count < 20) {
  282. i2c_readbytes(state, data[0], &buf, 1);
  283. if (buf & 0x40)
  284. return 0;
  285. msleep(100);
  286. count++;
  287. }
  288. pr_warn("timeout waiting for tuner lock\n");
  289. break;
  290. case NXT2002:
  291. /* set the i2c transfer speed to the tuner */
  292. buf = 0x03;
  293. nxt200x_writebytes(state, 0x20, &buf, 1);
  294. /* setup to transfer 4 bytes via i2c */
  295. buf = 0x04;
  296. nxt200x_writebytes(state, 0x34, &buf, 1);
  297. /* write actual tuner bytes */
  298. nxt200x_writebytes(state, 0x36, data+1, 4);
  299. /* set tuner i2c address */
  300. buf = data[0] << 1;
  301. nxt200x_writebytes(state, 0x35, &buf, 1);
  302. /* write UC Opmode to begin transfer */
  303. buf = 0x80;
  304. nxt200x_writebytes(state, 0x21, &buf, 1);
  305. while (count < 20) {
  306. nxt200x_readbytes(state, 0x21, &buf, 1);
  307. if ((buf & 0x80)== 0x00)
  308. return 0;
  309. msleep(100);
  310. count++;
  311. }
  312. pr_warn("timeout error writing to tuner\n");
  313. break;
  314. default:
  315. return -EINVAL;
  316. break;
  317. }
  318. return 0;
  319. }
  320. static void nxt200x_agc_reset(struct nxt200x_state* state)
  321. {
  322. u8 buf;
  323. dprintk("%s\n", __func__);
  324. switch (state->demod_chip) {
  325. case NXT2002:
  326. buf = 0x08;
  327. nxt200x_writebytes(state, 0x08, &buf, 1);
  328. buf = 0x00;
  329. nxt200x_writebytes(state, 0x08, &buf, 1);
  330. break;
  331. case NXT2004:
  332. nxt200x_readreg_multibyte(state, 0x08, &buf, 1);
  333. buf = 0x08;
  334. nxt200x_writereg_multibyte(state, 0x08, &buf, 1);
  335. buf = 0x00;
  336. nxt200x_writereg_multibyte(state, 0x08, &buf, 1);
  337. break;
  338. default:
  339. break;
  340. }
  341. return;
  342. }
  343. static int nxt2002_load_firmware (struct dvb_frontend* fe, const struct firmware *fw)
  344. {
  345. struct nxt200x_state* state = fe->demodulator_priv;
  346. u8 buf[3], written = 0, chunkpos = 0;
  347. u16 rambase, position, crc = 0;
  348. dprintk("%s\n", __func__);
  349. dprintk("Firmware is %zu bytes\n", fw->size);
  350. /* Get the RAM base for this nxt2002 */
  351. nxt200x_readbytes(state, 0x10, buf, 1);
  352. if (buf[0] & 0x10)
  353. rambase = 0x1000;
  354. else
  355. rambase = 0x0000;
  356. dprintk("rambase on this nxt2002 is %04X\n", rambase);
  357. /* Hold the micro in reset while loading firmware */
  358. buf[0] = 0x80;
  359. nxt200x_writebytes(state, 0x2B, buf, 1);
  360. for (position = 0; position < fw->size; position++) {
  361. if (written == 0) {
  362. crc = 0;
  363. chunkpos = 0x28;
  364. buf[0] = ((rambase + position) >> 8);
  365. buf[1] = (rambase + position) & 0xFF;
  366. buf[2] = 0x81;
  367. /* write starting address */
  368. nxt200x_writebytes(state, 0x29, buf, 3);
  369. }
  370. written++;
  371. chunkpos++;
  372. if ((written % 4) == 0)
  373. nxt200x_writebytes(state, chunkpos, &fw->data[position-3], 4);
  374. crc = nxt200x_crc(crc, fw->data[position]);
  375. if ((written == 255) || (position+1 == fw->size)) {
  376. /* write remaining bytes of firmware */
  377. nxt200x_writebytes(state, chunkpos+4-(written %4),
  378. &fw->data[position-(written %4) + 1],
  379. written %4);
  380. buf[0] = crc << 8;
  381. buf[1] = crc & 0xFF;
  382. /* write crc */
  383. nxt200x_writebytes(state, 0x2C, buf, 2);
  384. /* do a read to stop things */
  385. nxt200x_readbytes(state, 0x2A, buf, 1);
  386. /* set transfer mode to complete */
  387. buf[0] = 0x80;
  388. nxt200x_writebytes(state, 0x2B, buf, 1);
  389. written = 0;
  390. }
  391. }
  392. return 0;
  393. };
  394. static int nxt2004_load_firmware (struct dvb_frontend* fe, const struct firmware *fw)
  395. {
  396. struct nxt200x_state* state = fe->demodulator_priv;
  397. u8 buf[3];
  398. u16 rambase, position, crc=0;
  399. dprintk("%s\n", __func__);
  400. dprintk("Firmware is %zu bytes\n", fw->size);
  401. /* set rambase */
  402. rambase = 0x1000;
  403. /* hold the micro in reset while loading firmware */
  404. buf[0] = 0x80;
  405. nxt200x_writebytes(state, 0x2B, buf,1);
  406. /* calculate firmware CRC */
  407. for (position = 0; position < fw->size; position++) {
  408. crc = nxt200x_crc(crc, fw->data[position]);
  409. }
  410. buf[0] = rambase >> 8;
  411. buf[1] = rambase & 0xFF;
  412. buf[2] = 0x81;
  413. /* write starting address */
  414. nxt200x_writebytes(state,0x29,buf,3);
  415. for (position = 0; position < fw->size;) {
  416. nxt200x_writebytes(state, 0x2C, &fw->data[position],
  417. fw->size-position > 255 ? 255 : fw->size-position);
  418. position += (fw->size-position > 255 ? 255 : fw->size-position);
  419. }
  420. buf[0] = crc >> 8;
  421. buf[1] = crc & 0xFF;
  422. dprintk("firmware crc is 0x%02X 0x%02X\n", buf[0], buf[1]);
  423. /* write crc */
  424. nxt200x_writebytes(state, 0x2C, buf,2);
  425. /* do a read to stop things */
  426. nxt200x_readbytes(state, 0x2C, buf, 1);
  427. /* set transfer mode to complete */
  428. buf[0] = 0x80;
  429. nxt200x_writebytes(state, 0x2B, buf,1);
  430. return 0;
  431. };
  432. static int nxt200x_setup_frontend_parameters(struct dvb_frontend *fe)
  433. {
  434. struct dtv_frontend_properties *p = &fe->dtv_property_cache;
  435. struct nxt200x_state* state = fe->demodulator_priv;
  436. u8 buf[5];
  437. /* stop the micro first */
  438. nxt200x_microcontroller_stop(state);
  439. if (state->demod_chip == NXT2004) {
  440. /* make sure demod is set to digital */
  441. buf[0] = 0x04;
  442. nxt200x_writebytes(state, 0x14, buf, 1);
  443. buf[0] = 0x00;
  444. nxt200x_writebytes(state, 0x17, buf, 1);
  445. }
  446. /* set additional params */
  447. switch (p->modulation) {
  448. case QAM_64:
  449. case QAM_256:
  450. /* Set punctured clock for QAM */
  451. /* This is just a guess since I am unable to test it */
  452. if (state->config->set_ts_params)
  453. state->config->set_ts_params(fe, 1);
  454. break;
  455. case VSB_8:
  456. /* Set non-punctured clock for VSB */
  457. if (state->config->set_ts_params)
  458. state->config->set_ts_params(fe, 0);
  459. break;
  460. default:
  461. return -EINVAL;
  462. break;
  463. }
  464. if (fe->ops.tuner_ops.calc_regs) {
  465. /* get tuning information */
  466. fe->ops.tuner_ops.calc_regs(fe, buf, 5);
  467. /* write frequency information */
  468. nxt200x_writetuner(state, buf);
  469. }
  470. /* reset the agc now that tuning has been completed */
  471. nxt200x_agc_reset(state);
  472. /* set target power level */
  473. switch (p->modulation) {
  474. case QAM_64:
  475. case QAM_256:
  476. buf[0] = 0x74;
  477. break;
  478. case VSB_8:
  479. buf[0] = 0x70;
  480. break;
  481. default:
  482. return -EINVAL;
  483. break;
  484. }
  485. nxt200x_writebytes(state, 0x42, buf, 1);
  486. /* configure sdm */
  487. switch (state->demod_chip) {
  488. case NXT2002:
  489. buf[0] = 0x87;
  490. break;
  491. case NXT2004:
  492. buf[0] = 0x07;
  493. break;
  494. default:
  495. return -EINVAL;
  496. break;
  497. }
  498. nxt200x_writebytes(state, 0x57, buf, 1);
  499. /* write sdm1 input */
  500. buf[0] = 0x10;
  501. buf[1] = 0x00;
  502. switch (state->demod_chip) {
  503. case NXT2002:
  504. nxt200x_writereg_multibyte(state, 0x58, buf, 2);
  505. break;
  506. case NXT2004:
  507. nxt200x_writebytes(state, 0x58, buf, 2);
  508. break;
  509. default:
  510. return -EINVAL;
  511. break;
  512. }
  513. /* write sdmx input */
  514. switch (p->modulation) {
  515. case QAM_64:
  516. buf[0] = 0x68;
  517. break;
  518. case QAM_256:
  519. buf[0] = 0x64;
  520. break;
  521. case VSB_8:
  522. buf[0] = 0x60;
  523. break;
  524. default:
  525. return -EINVAL;
  526. break;
  527. }
  528. buf[1] = 0x00;
  529. switch (state->demod_chip) {
  530. case NXT2002:
  531. nxt200x_writereg_multibyte(state, 0x5C, buf, 2);
  532. break;
  533. case NXT2004:
  534. nxt200x_writebytes(state, 0x5C, buf, 2);
  535. break;
  536. default:
  537. return -EINVAL;
  538. break;
  539. }
  540. /* write adc power lpf fc */
  541. buf[0] = 0x05;
  542. nxt200x_writebytes(state, 0x43, buf, 1);
  543. if (state->demod_chip == NXT2004) {
  544. /* write ??? */
  545. buf[0] = 0x00;
  546. buf[1] = 0x00;
  547. nxt200x_writebytes(state, 0x46, buf, 2);
  548. }
  549. /* write accumulator2 input */
  550. buf[0] = 0x80;
  551. buf[1] = 0x00;
  552. switch (state->demod_chip) {
  553. case NXT2002:
  554. nxt200x_writereg_multibyte(state, 0x4B, buf, 2);
  555. break;
  556. case NXT2004:
  557. nxt200x_writebytes(state, 0x4B, buf, 2);
  558. break;
  559. default:
  560. return -EINVAL;
  561. break;
  562. }
  563. /* write kg1 */
  564. buf[0] = 0x00;
  565. nxt200x_writebytes(state, 0x4D, buf, 1);
  566. /* write sdm12 lpf fc */
  567. buf[0] = 0x44;
  568. nxt200x_writebytes(state, 0x55, buf, 1);
  569. /* write agc control reg */
  570. buf[0] = 0x04;
  571. nxt200x_writebytes(state, 0x41, buf, 1);
  572. if (state->demod_chip == NXT2004) {
  573. nxt200x_readreg_multibyte(state, 0x80, buf, 1);
  574. buf[0] = 0x24;
  575. nxt200x_writereg_multibyte(state, 0x80, buf, 1);
  576. /* soft reset? */
  577. nxt200x_readreg_multibyte(state, 0x08, buf, 1);
  578. buf[0] = 0x10;
  579. nxt200x_writereg_multibyte(state, 0x08, buf, 1);
  580. nxt200x_readreg_multibyte(state, 0x08, buf, 1);
  581. buf[0] = 0x00;
  582. nxt200x_writereg_multibyte(state, 0x08, buf, 1);
  583. nxt200x_readreg_multibyte(state, 0x80, buf, 1);
  584. buf[0] = 0x04;
  585. nxt200x_writereg_multibyte(state, 0x80, buf, 1);
  586. buf[0] = 0x00;
  587. nxt200x_writereg_multibyte(state, 0x81, buf, 1);
  588. buf[0] = 0x80; buf[1] = 0x00; buf[2] = 0x00;
  589. nxt200x_writereg_multibyte(state, 0x82, buf, 3);
  590. nxt200x_readreg_multibyte(state, 0x88, buf, 1);
  591. buf[0] = 0x11;
  592. nxt200x_writereg_multibyte(state, 0x88, buf, 1);
  593. nxt200x_readreg_multibyte(state, 0x80, buf, 1);
  594. buf[0] = 0x44;
  595. nxt200x_writereg_multibyte(state, 0x80, buf, 1);
  596. }
  597. /* write agc ucgp0 */
  598. switch (p->modulation) {
  599. case QAM_64:
  600. buf[0] = 0x02;
  601. break;
  602. case QAM_256:
  603. buf[0] = 0x03;
  604. break;
  605. case VSB_8:
  606. buf[0] = 0x00;
  607. break;
  608. default:
  609. return -EINVAL;
  610. break;
  611. }
  612. nxt200x_writebytes(state, 0x30, buf, 1);
  613. /* write agc control reg */
  614. buf[0] = 0x00;
  615. nxt200x_writebytes(state, 0x41, buf, 1);
  616. /* write accumulator2 input */
  617. buf[0] = 0x80;
  618. buf[1] = 0x00;
  619. switch (state->demod_chip) {
  620. case NXT2002:
  621. nxt200x_writereg_multibyte(state, 0x49, buf, 2);
  622. nxt200x_writereg_multibyte(state, 0x4B, buf, 2);
  623. break;
  624. case NXT2004:
  625. nxt200x_writebytes(state, 0x49, buf, 2);
  626. nxt200x_writebytes(state, 0x4B, buf, 2);
  627. break;
  628. default:
  629. return -EINVAL;
  630. break;
  631. }
  632. /* write agc control reg */
  633. buf[0] = 0x04;
  634. nxt200x_writebytes(state, 0x41, buf, 1);
  635. nxt200x_microcontroller_start(state);
  636. if (state->demod_chip == NXT2004) {
  637. nxt2004_microcontroller_init(state);
  638. /* ???? */
  639. buf[0] = 0xF0;
  640. buf[1] = 0x00;
  641. nxt200x_writebytes(state, 0x5C, buf, 2);
  642. }
  643. /* adjacent channel detection should be done here, but I don't
  644. have any stations with this need so I cannot test it */
  645. return 0;
  646. }
  647. static int nxt200x_read_status(struct dvb_frontend *fe, enum fe_status *status)
  648. {
  649. struct nxt200x_state* state = fe->demodulator_priv;
  650. u8 lock;
  651. nxt200x_readbytes(state, 0x31, &lock, 1);
  652. *status = 0;
  653. if (lock & 0x20) {
  654. *status |= FE_HAS_SIGNAL;
  655. *status |= FE_HAS_CARRIER;
  656. *status |= FE_HAS_VITERBI;
  657. *status |= FE_HAS_SYNC;
  658. *status |= FE_HAS_LOCK;
  659. }
  660. return 0;
  661. }
  662. static int nxt200x_read_ber(struct dvb_frontend* fe, u32* ber)
  663. {
  664. struct nxt200x_state* state = fe->demodulator_priv;
  665. u8 b[3];
  666. nxt200x_readreg_multibyte(state, 0xE6, b, 3);
  667. *ber = ((b[0] << 8) + b[1]) * 8;
  668. return 0;
  669. }
  670. static int nxt200x_read_signal_strength(struct dvb_frontend* fe, u16* strength)
  671. {
  672. struct nxt200x_state* state = fe->demodulator_priv;
  673. u8 b[2];
  674. u16 temp = 0;
  675. /* setup to read cluster variance */
  676. b[0] = 0x00;
  677. nxt200x_writebytes(state, 0xA1, b, 1);
  678. /* get multreg val */
  679. nxt200x_readreg_multibyte(state, 0xA6, b, 2);
  680. temp = (b[0] << 8) | b[1];
  681. *strength = ((0x7FFF - temp) & 0x0FFF) * 16;
  682. return 0;
  683. }
  684. static int nxt200x_read_snr(struct dvb_frontend* fe, u16* snr)
  685. {
  686. struct nxt200x_state* state = fe->demodulator_priv;
  687. u8 b[2];
  688. u16 temp = 0, temp2;
  689. u32 snrdb = 0;
  690. /* setup to read cluster variance */
  691. b[0] = 0x00;
  692. nxt200x_writebytes(state, 0xA1, b, 1);
  693. /* get multreg val from 0xA6 */
  694. nxt200x_readreg_multibyte(state, 0xA6, b, 2);
  695. temp = (b[0] << 8) | b[1];
  696. temp2 = 0x7FFF - temp;
  697. /* snr will be in db */
  698. if (temp2 > 0x7F00)
  699. snrdb = 1000*24 + ( 1000*(30-24) * ( temp2 - 0x7F00 ) / ( 0x7FFF - 0x7F00 ) );
  700. else if (temp2 > 0x7EC0)
  701. snrdb = 1000*18 + ( 1000*(24-18) * ( temp2 - 0x7EC0 ) / ( 0x7F00 - 0x7EC0 ) );
  702. else if (temp2 > 0x7C00)
  703. snrdb = 1000*12 + ( 1000*(18-12) * ( temp2 - 0x7C00 ) / ( 0x7EC0 - 0x7C00 ) );
  704. else
  705. snrdb = 1000*0 + ( 1000*(12-0) * ( temp2 - 0 ) / ( 0x7C00 - 0 ) );
  706. /* the value reported back from the frontend will be FFFF=32db 0000=0db */
  707. *snr = snrdb * (0xFFFF/32000);
  708. return 0;
  709. }
  710. static int nxt200x_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
  711. {
  712. struct nxt200x_state* state = fe->demodulator_priv;
  713. u8 b[3];
  714. nxt200x_readreg_multibyte(state, 0xE6, b, 3);
  715. *ucblocks = b[2];
  716. return 0;
  717. }
  718. static int nxt200x_sleep(struct dvb_frontend* fe)
  719. {
  720. return 0;
  721. }
  722. static int nxt2002_init(struct dvb_frontend* fe)
  723. {
  724. struct nxt200x_state* state = fe->demodulator_priv;
  725. const struct firmware *fw;
  726. int ret;
  727. u8 buf[2];
  728. /* request the firmware, this will block until someone uploads it */
  729. pr_debug("%s: Waiting for firmware upload (%s)...\n",
  730. __func__, NXT2002_DEFAULT_FIRMWARE);
  731. ret = request_firmware(&fw, NXT2002_DEFAULT_FIRMWARE,
  732. state->i2c->dev.parent);
  733. pr_debug("%s: Waiting for firmware upload(2)...\n", __func__);
  734. if (ret) {
  735. pr_err("%s: No firmware uploaded (timeout or file not found?)\n",
  736. __func__);
  737. return ret;
  738. }
  739. ret = nxt2002_load_firmware(fe, fw);
  740. release_firmware(fw);
  741. if (ret) {
  742. pr_err("%s: Writing firmware to device failed\n", __func__);
  743. return ret;
  744. }
  745. pr_info("%s: Firmware upload complete\n", __func__);
  746. /* Put the micro into reset */
  747. nxt200x_microcontroller_stop(state);
  748. /* ensure transfer is complete */
  749. buf[0]=0x00;
  750. nxt200x_writebytes(state, 0x2B, buf, 1);
  751. /* Put the micro into reset for real this time */
  752. nxt200x_microcontroller_stop(state);
  753. /* soft reset everything (agc,frontend,eq,fec)*/
  754. buf[0] = 0x0F;
  755. nxt200x_writebytes(state, 0x08, buf, 1);
  756. buf[0] = 0x00;
  757. nxt200x_writebytes(state, 0x08, buf, 1);
  758. /* write agc sdm configure */
  759. buf[0] = 0xF1;
  760. nxt200x_writebytes(state, 0x57, buf, 1);
  761. /* write mod output format */
  762. buf[0] = 0x20;
  763. nxt200x_writebytes(state, 0x09, buf, 1);
  764. /* write fec mpeg mode */
  765. buf[0] = 0x7E;
  766. buf[1] = 0x00;
  767. nxt200x_writebytes(state, 0xE9, buf, 2);
  768. /* write mux selection */
  769. buf[0] = 0x00;
  770. nxt200x_writebytes(state, 0xCC, buf, 1);
  771. return 0;
  772. }
  773. static int nxt2004_init(struct dvb_frontend* fe)
  774. {
  775. struct nxt200x_state* state = fe->demodulator_priv;
  776. const struct firmware *fw;
  777. int ret;
  778. u8 buf[3];
  779. /* ??? */
  780. buf[0]=0x00;
  781. nxt200x_writebytes(state, 0x1E, buf, 1);
  782. /* request the firmware, this will block until someone uploads it */
  783. pr_debug("%s: Waiting for firmware upload (%s)...\n",
  784. __func__, NXT2004_DEFAULT_FIRMWARE);
  785. ret = request_firmware(&fw, NXT2004_DEFAULT_FIRMWARE,
  786. state->i2c->dev.parent);
  787. pr_debug("%s: Waiting for firmware upload(2)...\n", __func__);
  788. if (ret) {
  789. pr_err("%s: No firmware uploaded (timeout or file not found?)\n",
  790. __func__);
  791. return ret;
  792. }
  793. ret = nxt2004_load_firmware(fe, fw);
  794. release_firmware(fw);
  795. if (ret) {
  796. pr_err("%s: Writing firmware to device failed\n", __func__);
  797. return ret;
  798. }
  799. pr_info("%s: Firmware upload complete\n", __func__);
  800. /* ensure transfer is complete */
  801. buf[0] = 0x01;
  802. nxt200x_writebytes(state, 0x19, buf, 1);
  803. nxt2004_microcontroller_init(state);
  804. nxt200x_microcontroller_stop(state);
  805. nxt200x_microcontroller_stop(state);
  806. nxt2004_microcontroller_init(state);
  807. nxt200x_microcontroller_stop(state);
  808. /* soft reset everything (agc,frontend,eq,fec)*/
  809. buf[0] = 0xFF;
  810. nxt200x_writereg_multibyte(state, 0x08, buf, 1);
  811. buf[0] = 0x00;
  812. nxt200x_writereg_multibyte(state, 0x08, buf, 1);
  813. /* write agc sdm configure */
  814. buf[0] = 0xD7;
  815. nxt200x_writebytes(state, 0x57, buf, 1);
  816. /* ???*/
  817. buf[0] = 0x07;
  818. buf[1] = 0xfe;
  819. nxt200x_writebytes(state, 0x35, buf, 2);
  820. buf[0] = 0x12;
  821. nxt200x_writebytes(state, 0x34, buf, 1);
  822. buf[0] = 0x80;
  823. nxt200x_writebytes(state, 0x21, buf, 1);
  824. /* ???*/
  825. buf[0] = 0x21;
  826. nxt200x_writebytes(state, 0x0A, buf, 1);
  827. /* ???*/
  828. buf[0] = 0x01;
  829. nxt200x_writereg_multibyte(state, 0x80, buf, 1);
  830. /* write fec mpeg mode */
  831. buf[0] = 0x7E;
  832. buf[1] = 0x00;
  833. nxt200x_writebytes(state, 0xE9, buf, 2);
  834. /* write mux selection */
  835. buf[0] = 0x00;
  836. nxt200x_writebytes(state, 0xCC, buf, 1);
  837. /* ???*/
  838. nxt200x_readreg_multibyte(state, 0x80, buf, 1);
  839. buf[0] = 0x00;
  840. nxt200x_writereg_multibyte(state, 0x80, buf, 1);
  841. /* soft reset? */
  842. nxt200x_readreg_multibyte(state, 0x08, buf, 1);
  843. buf[0] = 0x10;
  844. nxt200x_writereg_multibyte(state, 0x08, buf, 1);
  845. nxt200x_readreg_multibyte(state, 0x08, buf, 1);
  846. buf[0] = 0x00;
  847. nxt200x_writereg_multibyte(state, 0x08, buf, 1);
  848. /* ???*/
  849. nxt200x_readreg_multibyte(state, 0x80, buf, 1);
  850. buf[0] = 0x01;
  851. nxt200x_writereg_multibyte(state, 0x80, buf, 1);
  852. buf[0] = 0x70;
  853. nxt200x_writereg_multibyte(state, 0x81, buf, 1);
  854. buf[0] = 0x31; buf[1] = 0x5E; buf[2] = 0x66;
  855. nxt200x_writereg_multibyte(state, 0x82, buf, 3);
  856. nxt200x_readreg_multibyte(state, 0x88, buf, 1);
  857. buf[0] = 0x11;
  858. nxt200x_writereg_multibyte(state, 0x88, buf, 1);
  859. nxt200x_readreg_multibyte(state, 0x80, buf, 1);
  860. buf[0] = 0x40;
  861. nxt200x_writereg_multibyte(state, 0x80, buf, 1);
  862. nxt200x_readbytes(state, 0x10, buf, 1);
  863. buf[0] = 0x10;
  864. nxt200x_writebytes(state, 0x10, buf, 1);
  865. nxt200x_readbytes(state, 0x0A, buf, 1);
  866. buf[0] = 0x21;
  867. nxt200x_writebytes(state, 0x0A, buf, 1);
  868. nxt2004_microcontroller_init(state);
  869. buf[0] = 0x21;
  870. nxt200x_writebytes(state, 0x0A, buf, 1);
  871. buf[0] = 0x7E;
  872. nxt200x_writebytes(state, 0xE9, buf, 1);
  873. buf[0] = 0x00;
  874. nxt200x_writebytes(state, 0xEA, buf, 1);
  875. nxt200x_readreg_multibyte(state, 0x80, buf, 1);
  876. buf[0] = 0x00;
  877. nxt200x_writereg_multibyte(state, 0x80, buf, 1);
  878. nxt200x_readreg_multibyte(state, 0x80, buf, 1);
  879. buf[0] = 0x00;
  880. nxt200x_writereg_multibyte(state, 0x80, buf, 1);
  881. /* soft reset? */
  882. nxt200x_readreg_multibyte(state, 0x08, buf, 1);
  883. buf[0] = 0x10;
  884. nxt200x_writereg_multibyte(state, 0x08, buf, 1);
  885. nxt200x_readreg_multibyte(state, 0x08, buf, 1);
  886. buf[0] = 0x00;
  887. nxt200x_writereg_multibyte(state, 0x08, buf, 1);
  888. nxt200x_readreg_multibyte(state, 0x80, buf, 1);
  889. buf[0] = 0x04;
  890. nxt200x_writereg_multibyte(state, 0x80, buf, 1);
  891. buf[0] = 0x00;
  892. nxt200x_writereg_multibyte(state, 0x81, buf, 1);
  893. buf[0] = 0x80; buf[1] = 0x00; buf[2] = 0x00;
  894. nxt200x_writereg_multibyte(state, 0x82, buf, 3);
  895. nxt200x_readreg_multibyte(state, 0x88, buf, 1);
  896. buf[0] = 0x11;
  897. nxt200x_writereg_multibyte(state, 0x88, buf, 1);
  898. nxt200x_readreg_multibyte(state, 0x80, buf, 1);
  899. buf[0] = 0x44;
  900. nxt200x_writereg_multibyte(state, 0x80, buf, 1);
  901. /* initialize tuner */
  902. nxt200x_readbytes(state, 0x10, buf, 1);
  903. buf[0] = 0x12;
  904. nxt200x_writebytes(state, 0x10, buf, 1);
  905. buf[0] = 0x04;
  906. nxt200x_writebytes(state, 0x13, buf, 1);
  907. buf[0] = 0x00;
  908. nxt200x_writebytes(state, 0x16, buf, 1);
  909. buf[0] = 0x04;
  910. nxt200x_writebytes(state, 0x14, buf, 1);
  911. buf[0] = 0x00;
  912. nxt200x_writebytes(state, 0x14, buf, 1);
  913. nxt200x_writebytes(state, 0x17, buf, 1);
  914. nxt200x_writebytes(state, 0x14, buf, 1);
  915. nxt200x_writebytes(state, 0x17, buf, 1);
  916. return 0;
  917. }
  918. static int nxt200x_init(struct dvb_frontend* fe)
  919. {
  920. struct nxt200x_state* state = fe->demodulator_priv;
  921. int ret = 0;
  922. if (!state->initialised) {
  923. switch (state->demod_chip) {
  924. case NXT2002:
  925. ret = nxt2002_init(fe);
  926. break;
  927. case NXT2004:
  928. ret = nxt2004_init(fe);
  929. break;
  930. default:
  931. return -EINVAL;
  932. break;
  933. }
  934. state->initialised = 1;
  935. }
  936. return ret;
  937. }
  938. static int nxt200x_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings)
  939. {
  940. fesettings->min_delay_ms = 500;
  941. fesettings->step_size = 0;
  942. fesettings->max_drift = 0;
  943. return 0;
  944. }
  945. static void nxt200x_release(struct dvb_frontend* fe)
  946. {
  947. struct nxt200x_state* state = fe->demodulator_priv;
  948. kfree(state);
  949. }
  950. static const struct dvb_frontend_ops nxt200x_ops;
  951. struct dvb_frontend* nxt200x_attach(const struct nxt200x_config* config,
  952. struct i2c_adapter* i2c)
  953. {
  954. struct nxt200x_state* state = NULL;
  955. u8 buf [] = {0,0,0,0,0};
  956. /* allocate memory for the internal state */
  957. state = kzalloc(sizeof(struct nxt200x_state), GFP_KERNEL);
  958. if (state == NULL)
  959. goto error;
  960. /* setup the state */
  961. state->config = config;
  962. state->i2c = i2c;
  963. state->initialised = 0;
  964. /* read card id */
  965. nxt200x_readbytes(state, 0x00, buf, 5);
  966. dprintk("NXT info: %*ph\n", 5, buf);
  967. /* set demod chip */
  968. switch (buf[0]) {
  969. case 0x04:
  970. state->demod_chip = NXT2002;
  971. pr_info("NXT2002 Detected\n");
  972. break;
  973. case 0x05:
  974. state->demod_chip = NXT2004;
  975. pr_info("NXT2004 Detected\n");
  976. break;
  977. default:
  978. goto error;
  979. }
  980. /* make sure demod chip is supported */
  981. switch (state->demod_chip) {
  982. case NXT2002:
  983. if (buf[0] != 0x04) goto error; /* device id */
  984. if (buf[1] != 0x02) goto error; /* fab id */
  985. if (buf[2] != 0x11) goto error; /* month */
  986. if (buf[3] != 0x20) goto error; /* year msb */
  987. if (buf[4] != 0x00) goto error; /* year lsb */
  988. break;
  989. case NXT2004:
  990. if (buf[0] != 0x05) goto error; /* device id */
  991. break;
  992. default:
  993. goto error;
  994. }
  995. /* create dvb_frontend */
  996. memcpy(&state->frontend.ops, &nxt200x_ops, sizeof(struct dvb_frontend_ops));
  997. state->frontend.demodulator_priv = state;
  998. return &state->frontend;
  999. error:
  1000. kfree(state);
  1001. pr_err("Unknown/Unsupported NXT chip: %*ph\n", 5, buf);
  1002. return NULL;
  1003. }
  1004. static const struct dvb_frontend_ops nxt200x_ops = {
  1005. .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
  1006. .info = {
  1007. .name = "Nextwave NXT200X VSB/QAM frontend",
  1008. .frequency_min_hz = 54 * MHz,
  1009. .frequency_max_hz = 860 * MHz,
  1010. .frequency_stepsize_hz = 166666, /* stepsize is just a guess */
  1011. .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
  1012. FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
  1013. FE_CAN_8VSB | FE_CAN_QAM_64 | FE_CAN_QAM_256
  1014. },
  1015. .release = nxt200x_release,
  1016. .init = nxt200x_init,
  1017. .sleep = nxt200x_sleep,
  1018. .set_frontend = nxt200x_setup_frontend_parameters,
  1019. .get_tune_settings = nxt200x_get_tune_settings,
  1020. .read_status = nxt200x_read_status,
  1021. .read_ber = nxt200x_read_ber,
  1022. .read_signal_strength = nxt200x_read_signal_strength,
  1023. .read_snr = nxt200x_read_snr,
  1024. .read_ucblocks = nxt200x_read_ucblocks,
  1025. };
  1026. module_param(debug, int, 0644);
  1027. MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
  1028. MODULE_DESCRIPTION("NXT200X (ATSC 8VSB & ITU-T J.83 AnnexB 64/256 QAM) Demodulator Driver");
  1029. MODULE_AUTHOR("Kirk Lapray, Michael Krufky, Jean-Francois Thibert, and Taylor Jacob");
  1030. MODULE_LICENSE("GPL");
  1031. EXPORT_SYMBOL(nxt200x_attach);