mb86a20s.c 52 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Fujitu mb86a20s ISDB-T/ISDB-Tsb Module driver
  4. *
  5. * Copyright (C) 2010-2013 Mauro Carvalho Chehab
  6. * Copyright (C) 2009-2010 Douglas Landgraf <dougsland@redhat.com>
  7. */
  8. #include <linux/kernel.h>
  9. #include <asm/div64.h>
  10. #include <media/dvb_frontend.h>
  11. #include "mb86a20s.h"
  12. #define NUM_LAYERS 3
  13. enum mb86a20s_bandwidth {
  14. MB86A20S_13SEG = 0,
  15. MB86A20S_13SEG_PARTIAL = 1,
  16. MB86A20S_1SEG = 2,
  17. MB86A20S_3SEG = 3,
  18. };
  19. static u8 mb86a20s_subchannel[] = {
  20. 0xb0, 0xc0, 0xd0, 0xe0,
  21. 0xf0, 0x00, 0x10, 0x20,
  22. };
  23. struct mb86a20s_state {
  24. struct i2c_adapter *i2c;
  25. const struct mb86a20s_config *config;
  26. u32 last_frequency;
  27. struct dvb_frontend frontend;
  28. u32 if_freq;
  29. enum mb86a20s_bandwidth bw;
  30. bool inversion;
  31. u32 subchannel;
  32. u32 estimated_rate[NUM_LAYERS];
  33. unsigned long get_strength_time;
  34. bool need_init;
  35. };
  36. struct regdata {
  37. u8 reg;
  38. u8 data;
  39. };
  40. #define BER_SAMPLING_RATE 1 /* Seconds */
  41. /*
  42. * Initialization sequence: Use whatevere default values that PV SBTVD
  43. * does on its initialisation, obtained via USB snoop
  44. */
  45. static struct regdata mb86a20s_init1[] = {
  46. { 0x70, 0x0f },
  47. { 0x70, 0xff },
  48. { 0x08, 0x01 },
  49. { 0x50, 0xd1 }, { 0x51, 0x20 },
  50. };
  51. static struct regdata mb86a20s_init2[] = {
  52. { 0x50, 0xd1 }, { 0x51, 0x22 },
  53. { 0x39, 0x01 },
  54. { 0x71, 0x00 },
  55. { 0x3b, 0x21 },
  56. { 0x3c, 0x3a },
  57. { 0x01, 0x0d },
  58. { 0x04, 0x08 }, { 0x05, 0x05 },
  59. { 0x04, 0x0e }, { 0x05, 0x00 },
  60. { 0x04, 0x0f }, { 0x05, 0x14 },
  61. { 0x04, 0x0b }, { 0x05, 0x8c },
  62. { 0x04, 0x00 }, { 0x05, 0x00 },
  63. { 0x04, 0x01 }, { 0x05, 0x07 },
  64. { 0x04, 0x02 }, { 0x05, 0x0f },
  65. { 0x04, 0x03 }, { 0x05, 0xa0 },
  66. { 0x04, 0x09 }, { 0x05, 0x00 },
  67. { 0x04, 0x0a }, { 0x05, 0xff },
  68. { 0x04, 0x27 }, { 0x05, 0x64 },
  69. { 0x04, 0x28 }, { 0x05, 0x00 },
  70. { 0x04, 0x1e }, { 0x05, 0xff },
  71. { 0x04, 0x29 }, { 0x05, 0x0a },
  72. { 0x04, 0x32 }, { 0x05, 0x0a },
  73. { 0x04, 0x14 }, { 0x05, 0x02 },
  74. { 0x04, 0x04 }, { 0x05, 0x00 },
  75. { 0x04, 0x05 }, { 0x05, 0x22 },
  76. { 0x04, 0x06 }, { 0x05, 0x0e },
  77. { 0x04, 0x07 }, { 0x05, 0xd8 },
  78. { 0x04, 0x12 }, { 0x05, 0x00 },
  79. { 0x04, 0x13 }, { 0x05, 0xff },
  80. /*
  81. * On this demod, when the bit count reaches the count below,
  82. * it collects the bit error count. The bit counters are initialized
  83. * to 65535 here. This warrants that all of them will be quickly
  84. * calculated when device gets locked. As TMCC is parsed, the values
  85. * will be adjusted later in the driver's code.
  86. */
  87. { 0x52, 0x01 }, /* Turn on BER before Viterbi */
  88. { 0x50, 0xa7 }, { 0x51, 0x00 },
  89. { 0x50, 0xa8 }, { 0x51, 0xff },
  90. { 0x50, 0xa9 }, { 0x51, 0xff },
  91. { 0x50, 0xaa }, { 0x51, 0x00 },
  92. { 0x50, 0xab }, { 0x51, 0xff },
  93. { 0x50, 0xac }, { 0x51, 0xff },
  94. { 0x50, 0xad }, { 0x51, 0x00 },
  95. { 0x50, 0xae }, { 0x51, 0xff },
  96. { 0x50, 0xaf }, { 0x51, 0xff },
  97. /*
  98. * On this demod, post BER counts blocks. When the count reaches the
  99. * value below, it collects the block error count. The block counters
  100. * are initialized to 127 here. This warrants that all of them will be
  101. * quickly calculated when device gets locked. As TMCC is parsed, the
  102. * values will be adjusted later in the driver's code.
  103. */
  104. { 0x5e, 0x07 }, /* Turn on BER after Viterbi */
  105. { 0x50, 0xdc }, { 0x51, 0x00 },
  106. { 0x50, 0xdd }, { 0x51, 0x7f },
  107. { 0x50, 0xde }, { 0x51, 0x00 },
  108. { 0x50, 0xdf }, { 0x51, 0x7f },
  109. { 0x50, 0xe0 }, { 0x51, 0x00 },
  110. { 0x50, 0xe1 }, { 0x51, 0x7f },
  111. /*
  112. * On this demod, when the block count reaches the count below,
  113. * it collects the block error count. The block counters are initialized
  114. * to 127 here. This warrants that all of them will be quickly
  115. * calculated when device gets locked. As TMCC is parsed, the values
  116. * will be adjusted later in the driver's code.
  117. */
  118. { 0x50, 0xb0 }, { 0x51, 0x07 }, /* Enable PER */
  119. { 0x50, 0xb2 }, { 0x51, 0x00 },
  120. { 0x50, 0xb3 }, { 0x51, 0x7f },
  121. { 0x50, 0xb4 }, { 0x51, 0x00 },
  122. { 0x50, 0xb5 }, { 0x51, 0x7f },
  123. { 0x50, 0xb6 }, { 0x51, 0x00 },
  124. { 0x50, 0xb7 }, { 0x51, 0x7f },
  125. { 0x50, 0x50 }, { 0x51, 0x02 }, /* MER manual mode */
  126. { 0x50, 0x51 }, { 0x51, 0x04 }, /* MER symbol 4 */
  127. { 0x45, 0x04 }, /* CN symbol 4 */
  128. { 0x48, 0x04 }, /* CN manual mode */
  129. { 0x50, 0xd5 }, { 0x51, 0x01 },
  130. { 0x50, 0xd6 }, { 0x51, 0x1f },
  131. { 0x50, 0xd2 }, { 0x51, 0x03 },
  132. { 0x50, 0xd7 }, { 0x51, 0x3f },
  133. { 0x1c, 0x01 },
  134. { 0x28, 0x06 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x03 },
  135. { 0x28, 0x07 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0d },
  136. { 0x28, 0x08 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x02 },
  137. { 0x28, 0x09 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x01 },
  138. { 0x28, 0x0a }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x21 },
  139. { 0x28, 0x0b }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x29 },
  140. { 0x28, 0x0c }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x16 },
  141. { 0x28, 0x0d }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x31 },
  142. { 0x28, 0x0e }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0e },
  143. { 0x28, 0x0f }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x4e },
  144. { 0x28, 0x10 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x46 },
  145. { 0x28, 0x11 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0f },
  146. { 0x28, 0x12 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x56 },
  147. { 0x28, 0x13 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x35 },
  148. { 0x28, 0x14 }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0xbe },
  149. { 0x28, 0x15 }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0x84 },
  150. { 0x28, 0x16 }, { 0x29, 0x00 }, { 0x2a, 0x03 }, { 0x2b, 0xee },
  151. { 0x28, 0x17 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x98 },
  152. { 0x28, 0x18 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x9f },
  153. { 0x28, 0x19 }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0xb2 },
  154. { 0x28, 0x1a }, { 0x29, 0x00 }, { 0x2a, 0x06 }, { 0x2b, 0xc2 },
  155. { 0x28, 0x1b }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0x4a },
  156. { 0x28, 0x1c }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0xbc },
  157. { 0x28, 0x1d }, { 0x29, 0x00 }, { 0x2a, 0x04 }, { 0x2b, 0xba },
  158. { 0x28, 0x1e }, { 0x29, 0x00 }, { 0x2a, 0x06 }, { 0x2b, 0x14 },
  159. { 0x50, 0x1e }, { 0x51, 0x5d },
  160. { 0x50, 0x22 }, { 0x51, 0x00 },
  161. { 0x50, 0x23 }, { 0x51, 0xc8 },
  162. { 0x50, 0x24 }, { 0x51, 0x00 },
  163. { 0x50, 0x25 }, { 0x51, 0xf0 },
  164. { 0x50, 0x26 }, { 0x51, 0x00 },
  165. { 0x50, 0x27 }, { 0x51, 0xc3 },
  166. { 0x50, 0x39 }, { 0x51, 0x02 },
  167. { 0x50, 0xd5 }, { 0x51, 0x01 },
  168. { 0xd0, 0x00 },
  169. };
  170. static struct regdata mb86a20s_reset_reception[] = {
  171. { 0x70, 0xf0 },
  172. { 0x70, 0xff },
  173. { 0x08, 0x01 },
  174. { 0x08, 0x00 },
  175. };
  176. static struct regdata mb86a20s_per_ber_reset[] = {
  177. { 0x53, 0x00 }, /* pre BER Counter reset */
  178. { 0x53, 0x07 },
  179. { 0x5f, 0x00 }, /* post BER Counter reset */
  180. { 0x5f, 0x07 },
  181. { 0x50, 0xb1 }, /* PER Counter reset */
  182. { 0x51, 0x07 },
  183. { 0x51, 0x00 },
  184. };
  185. /*
  186. * I2C read/write functions and macros
  187. */
  188. static int mb86a20s_i2c_writereg(struct mb86a20s_state *state,
  189. u8 i2c_addr, u8 reg, u8 data)
  190. {
  191. u8 buf[] = { reg, data };
  192. struct i2c_msg msg = {
  193. .addr = i2c_addr, .flags = 0, .buf = buf, .len = 2
  194. };
  195. int rc;
  196. rc = i2c_transfer(state->i2c, &msg, 1);
  197. if (rc != 1) {
  198. dev_err(&state->i2c->dev,
  199. "%s: writereg error (rc == %i, reg == 0x%02x, data == 0x%02x)\n",
  200. __func__, rc, reg, data);
  201. return rc;
  202. }
  203. return 0;
  204. }
  205. static int mb86a20s_i2c_writeregdata(struct mb86a20s_state *state,
  206. u8 i2c_addr, struct regdata *rd, int size)
  207. {
  208. int i, rc;
  209. for (i = 0; i < size; i++) {
  210. rc = mb86a20s_i2c_writereg(state, i2c_addr, rd[i].reg,
  211. rd[i].data);
  212. if (rc < 0)
  213. return rc;
  214. }
  215. return 0;
  216. }
  217. static int mb86a20s_i2c_readreg(struct mb86a20s_state *state,
  218. u8 i2c_addr, u8 reg)
  219. {
  220. u8 val;
  221. int rc;
  222. struct i2c_msg msg[] = {
  223. { .addr = i2c_addr, .flags = 0, .buf = &reg, .len = 1 },
  224. { .addr = i2c_addr, .flags = I2C_M_RD, .buf = &val, .len = 1 }
  225. };
  226. rc = i2c_transfer(state->i2c, msg, 2);
  227. if (rc != 2) {
  228. dev_err(&state->i2c->dev, "%s: reg=0x%x (error=%d)\n",
  229. __func__, reg, rc);
  230. return (rc < 0) ? rc : -EIO;
  231. }
  232. return val;
  233. }
  234. #define mb86a20s_readreg(state, reg) \
  235. mb86a20s_i2c_readreg(state, state->config->demod_address, reg)
  236. #define mb86a20s_writereg(state, reg, val) \
  237. mb86a20s_i2c_writereg(state, state->config->demod_address, reg, val)
  238. #define mb86a20s_writeregdata(state, regdata) \
  239. mb86a20s_i2c_writeregdata(state, state->config->demod_address, \
  240. regdata, ARRAY_SIZE(regdata))
  241. /*
  242. * Ancillary internal routines (likely compiled inlined)
  243. *
  244. * The functions below assume that gateway lock has already obtained
  245. */
  246. static int mb86a20s_read_status(struct dvb_frontend *fe, enum fe_status *status)
  247. {
  248. struct mb86a20s_state *state = fe->demodulator_priv;
  249. int val;
  250. *status = 0;
  251. val = mb86a20s_readreg(state, 0x0a);
  252. if (val < 0)
  253. return val;
  254. val &= 0xf;
  255. if (val >= 2)
  256. *status |= FE_HAS_SIGNAL;
  257. if (val >= 4)
  258. *status |= FE_HAS_CARRIER;
  259. if (val >= 5)
  260. *status |= FE_HAS_VITERBI;
  261. if (val >= 7)
  262. *status |= FE_HAS_SYNC;
  263. /*
  264. * Actually, on state S8, it starts receiving TS, but the TS
  265. * output is only on normal state after the transition to S9.
  266. */
  267. if (val >= 9)
  268. *status |= FE_HAS_LOCK;
  269. dev_dbg(&state->i2c->dev, "%s: Status = 0x%02x (state = %d)\n",
  270. __func__, *status, val);
  271. return val;
  272. }
  273. static int mb86a20s_read_signal_strength(struct dvb_frontend *fe)
  274. {
  275. struct mb86a20s_state *state = fe->demodulator_priv;
  276. struct dtv_frontend_properties *c = &fe->dtv_property_cache;
  277. int rc;
  278. unsigned rf_max, rf_min, rf;
  279. if (state->get_strength_time &&
  280. (!time_after(jiffies, state->get_strength_time)))
  281. return c->strength.stat[0].uvalue;
  282. /* Reset its value if an error happen */
  283. c->strength.stat[0].uvalue = 0;
  284. /* Does a binary search to get RF strength */
  285. rf_max = 0xfff;
  286. rf_min = 0;
  287. do {
  288. rf = (rf_max + rf_min) / 2;
  289. rc = mb86a20s_writereg(state, 0x04, 0x1f);
  290. if (rc < 0)
  291. return rc;
  292. rc = mb86a20s_writereg(state, 0x05, rf >> 8);
  293. if (rc < 0)
  294. return rc;
  295. rc = mb86a20s_writereg(state, 0x04, 0x20);
  296. if (rc < 0)
  297. return rc;
  298. rc = mb86a20s_writereg(state, 0x05, rf);
  299. if (rc < 0)
  300. return rc;
  301. rc = mb86a20s_readreg(state, 0x02);
  302. if (rc < 0)
  303. return rc;
  304. if (rc & 0x08)
  305. rf_min = (rf_max + rf_min) / 2;
  306. else
  307. rf_max = (rf_max + rf_min) / 2;
  308. if (rf_max - rf_min < 4) {
  309. rf = (rf_max + rf_min) / 2;
  310. /* Rescale it from 2^12 (4096) to 2^16 */
  311. rf = rf << (16 - 12);
  312. if (rf)
  313. rf |= (1 << 12) - 1;
  314. dev_dbg(&state->i2c->dev,
  315. "%s: signal strength = %d (%d < RF=%d < %d)\n",
  316. __func__, rf, rf_min, rf >> 4, rf_max);
  317. c->strength.stat[0].uvalue = rf;
  318. state->get_strength_time = jiffies +
  319. msecs_to_jiffies(1000);
  320. return 0;
  321. }
  322. } while (1);
  323. }
  324. static int mb86a20s_get_modulation(struct mb86a20s_state *state,
  325. unsigned layer)
  326. {
  327. int rc;
  328. static unsigned char reg[] = {
  329. [0] = 0x86, /* Layer A */
  330. [1] = 0x8a, /* Layer B */
  331. [2] = 0x8e, /* Layer C */
  332. };
  333. if (layer >= ARRAY_SIZE(reg))
  334. return -EINVAL;
  335. rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
  336. if (rc < 0)
  337. return rc;
  338. rc = mb86a20s_readreg(state, 0x6e);
  339. if (rc < 0)
  340. return rc;
  341. switch ((rc >> 4) & 0x07) {
  342. case 0:
  343. return DQPSK;
  344. case 1:
  345. return QPSK;
  346. case 2:
  347. return QAM_16;
  348. case 3:
  349. return QAM_64;
  350. default:
  351. return QAM_AUTO;
  352. }
  353. }
  354. static int mb86a20s_get_fec(struct mb86a20s_state *state,
  355. unsigned layer)
  356. {
  357. int rc;
  358. static unsigned char reg[] = {
  359. [0] = 0x87, /* Layer A */
  360. [1] = 0x8b, /* Layer B */
  361. [2] = 0x8f, /* Layer C */
  362. };
  363. if (layer >= ARRAY_SIZE(reg))
  364. return -EINVAL;
  365. rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
  366. if (rc < 0)
  367. return rc;
  368. rc = mb86a20s_readreg(state, 0x6e);
  369. if (rc < 0)
  370. return rc;
  371. switch ((rc >> 4) & 0x07) {
  372. case 0:
  373. return FEC_1_2;
  374. case 1:
  375. return FEC_2_3;
  376. case 2:
  377. return FEC_3_4;
  378. case 3:
  379. return FEC_5_6;
  380. case 4:
  381. return FEC_7_8;
  382. default:
  383. return FEC_AUTO;
  384. }
  385. }
  386. static int mb86a20s_get_interleaving(struct mb86a20s_state *state,
  387. unsigned layer)
  388. {
  389. int rc;
  390. int interleaving[] = {
  391. 0, 1, 2, 4, 8
  392. };
  393. static unsigned char reg[] = {
  394. [0] = 0x88, /* Layer A */
  395. [1] = 0x8c, /* Layer B */
  396. [2] = 0x90, /* Layer C */
  397. };
  398. if (layer >= ARRAY_SIZE(reg))
  399. return -EINVAL;
  400. rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
  401. if (rc < 0)
  402. return rc;
  403. rc = mb86a20s_readreg(state, 0x6e);
  404. if (rc < 0)
  405. return rc;
  406. return interleaving[(rc >> 4) & 0x07];
  407. }
  408. static int mb86a20s_get_segment_count(struct mb86a20s_state *state,
  409. unsigned layer)
  410. {
  411. int rc, count;
  412. static unsigned char reg[] = {
  413. [0] = 0x89, /* Layer A */
  414. [1] = 0x8d, /* Layer B */
  415. [2] = 0x91, /* Layer C */
  416. };
  417. dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
  418. if (layer >= ARRAY_SIZE(reg))
  419. return -EINVAL;
  420. rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
  421. if (rc < 0)
  422. return rc;
  423. rc = mb86a20s_readreg(state, 0x6e);
  424. if (rc < 0)
  425. return rc;
  426. count = (rc >> 4) & 0x0f;
  427. dev_dbg(&state->i2c->dev, "%s: segments: %d.\n", __func__, count);
  428. return count;
  429. }
  430. static void mb86a20s_reset_frontend_cache(struct dvb_frontend *fe)
  431. {
  432. struct mb86a20s_state *state = fe->demodulator_priv;
  433. struct dtv_frontend_properties *c = &fe->dtv_property_cache;
  434. dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
  435. /* Fixed parameters */
  436. c->delivery_system = SYS_ISDBT;
  437. c->bandwidth_hz = 6000000;
  438. /* Initialize values that will be later autodetected */
  439. c->isdbt_layer_enabled = 0;
  440. c->transmission_mode = TRANSMISSION_MODE_AUTO;
  441. c->guard_interval = GUARD_INTERVAL_AUTO;
  442. c->isdbt_sb_mode = 0;
  443. c->isdbt_sb_segment_count = 0;
  444. }
  445. /*
  446. * Estimates the bit rate using the per-segment bit rate given by
  447. * ABNT/NBR 15601 spec (table 4).
  448. */
  449. static const u32 isdbt_rate[3][5][4] = {
  450. { /* DQPSK/QPSK */
  451. { 280850, 312060, 330420, 340430 }, /* 1/2 */
  452. { 374470, 416080, 440560, 453910 }, /* 2/3 */
  453. { 421280, 468090, 495630, 510650 }, /* 3/4 */
  454. { 468090, 520100, 550700, 567390 }, /* 5/6 */
  455. { 491500, 546110, 578230, 595760 }, /* 7/8 */
  456. }, { /* QAM16 */
  457. { 561710, 624130, 660840, 680870 }, /* 1/2 */
  458. { 748950, 832170, 881120, 907820 }, /* 2/3 */
  459. { 842570, 936190, 991260, 1021300 }, /* 3/4 */
  460. { 936190, 1040210, 1101400, 1134780 }, /* 5/6 */
  461. { 983000, 1092220, 1156470, 1191520 }, /* 7/8 */
  462. }, { /* QAM64 */
  463. { 842570, 936190, 991260, 1021300 }, /* 1/2 */
  464. { 1123430, 1248260, 1321680, 1361740 }, /* 2/3 */
  465. { 1263860, 1404290, 1486900, 1531950 }, /* 3/4 */
  466. { 1404290, 1560320, 1652110, 1702170 }, /* 5/6 */
  467. { 1474500, 1638340, 1734710, 1787280 }, /* 7/8 */
  468. }
  469. };
  470. static u32 isdbt_layer_min_bitrate(struct dtv_frontend_properties *c,
  471. u32 layer)
  472. {
  473. int mod, fec, guard;
  474. /*
  475. * If modulation/fec/guard is not detected, the default is
  476. * to consider the lowest bit rate, to avoid taking too long time
  477. * to get BER.
  478. */
  479. switch (c->layer[layer].modulation) {
  480. case DQPSK:
  481. case QPSK:
  482. default:
  483. mod = 0;
  484. break;
  485. case QAM_16:
  486. mod = 1;
  487. break;
  488. case QAM_64:
  489. mod = 2;
  490. break;
  491. }
  492. switch (c->layer[layer].fec) {
  493. default:
  494. case FEC_1_2:
  495. case FEC_AUTO:
  496. fec = 0;
  497. break;
  498. case FEC_2_3:
  499. fec = 1;
  500. break;
  501. case FEC_3_4:
  502. fec = 2;
  503. break;
  504. case FEC_5_6:
  505. fec = 3;
  506. break;
  507. case FEC_7_8:
  508. fec = 4;
  509. break;
  510. }
  511. switch (c->guard_interval) {
  512. default:
  513. case GUARD_INTERVAL_1_4:
  514. guard = 0;
  515. break;
  516. case GUARD_INTERVAL_1_8:
  517. guard = 1;
  518. break;
  519. case GUARD_INTERVAL_1_16:
  520. guard = 2;
  521. break;
  522. case GUARD_INTERVAL_1_32:
  523. guard = 3;
  524. break;
  525. }
  526. return isdbt_rate[mod][fec][guard] * c->layer[layer].segment_count;
  527. }
  528. static int mb86a20s_get_frontend(struct dvb_frontend *fe)
  529. {
  530. struct mb86a20s_state *state = fe->demodulator_priv;
  531. struct dtv_frontend_properties *c = &fe->dtv_property_cache;
  532. int layer, rc, rate, counter;
  533. dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
  534. /* Reset frontend cache to default values */
  535. mb86a20s_reset_frontend_cache(fe);
  536. /* Check for partial reception */
  537. rc = mb86a20s_writereg(state, 0x6d, 0x85);
  538. if (rc < 0)
  539. return rc;
  540. rc = mb86a20s_readreg(state, 0x6e);
  541. if (rc < 0)
  542. return rc;
  543. c->isdbt_partial_reception = (rc & 0x10) ? 1 : 0;
  544. /* Get per-layer data */
  545. for (layer = 0; layer < NUM_LAYERS; layer++) {
  546. dev_dbg(&state->i2c->dev, "%s: getting data for layer %c.\n",
  547. __func__, 'A' + layer);
  548. rc = mb86a20s_get_segment_count(state, layer);
  549. if (rc < 0)
  550. goto noperlayer_error;
  551. if (rc >= 0 && rc < 14) {
  552. c->layer[layer].segment_count = rc;
  553. } else {
  554. c->layer[layer].segment_count = 0;
  555. state->estimated_rate[layer] = 0;
  556. continue;
  557. }
  558. c->isdbt_layer_enabled |= 1 << layer;
  559. rc = mb86a20s_get_modulation(state, layer);
  560. if (rc < 0)
  561. goto noperlayer_error;
  562. dev_dbg(&state->i2c->dev, "%s: modulation %d.\n",
  563. __func__, rc);
  564. c->layer[layer].modulation = rc;
  565. rc = mb86a20s_get_fec(state, layer);
  566. if (rc < 0)
  567. goto noperlayer_error;
  568. dev_dbg(&state->i2c->dev, "%s: FEC %d.\n",
  569. __func__, rc);
  570. c->layer[layer].fec = rc;
  571. rc = mb86a20s_get_interleaving(state, layer);
  572. if (rc < 0)
  573. goto noperlayer_error;
  574. dev_dbg(&state->i2c->dev, "%s: interleaving %d.\n",
  575. __func__, rc);
  576. c->layer[layer].interleaving = rc;
  577. rate = isdbt_layer_min_bitrate(c, layer);
  578. counter = rate * BER_SAMPLING_RATE;
  579. /* Avoids sampling too quickly or to overflow the register */
  580. if (counter < 256)
  581. counter = 256;
  582. else if (counter > (1 << 24) - 1)
  583. counter = (1 << 24) - 1;
  584. dev_dbg(&state->i2c->dev,
  585. "%s: layer %c bitrate: %d kbps; counter = %d (0x%06x)\n",
  586. __func__, 'A' + layer, rate / 1000, counter, counter);
  587. state->estimated_rate[layer] = counter;
  588. }
  589. rc = mb86a20s_writereg(state, 0x6d, 0x84);
  590. if (rc < 0)
  591. return rc;
  592. if ((rc & 0x60) == 0x20) {
  593. c->isdbt_sb_mode = 1;
  594. /* At least, one segment should exist */
  595. if (!c->isdbt_sb_segment_count)
  596. c->isdbt_sb_segment_count = 1;
  597. }
  598. /* Get transmission mode and guard interval */
  599. rc = mb86a20s_readreg(state, 0x07);
  600. if (rc < 0)
  601. return rc;
  602. c->transmission_mode = TRANSMISSION_MODE_AUTO;
  603. if ((rc & 0x60) == 0x20) {
  604. /* Only modes 2 and 3 are supported */
  605. switch ((rc >> 2) & 0x03) {
  606. case 1:
  607. c->transmission_mode = TRANSMISSION_MODE_4K;
  608. break;
  609. case 2:
  610. c->transmission_mode = TRANSMISSION_MODE_8K;
  611. break;
  612. }
  613. }
  614. c->guard_interval = GUARD_INTERVAL_AUTO;
  615. if (!(rc & 0x10)) {
  616. /* Guard interval 1/32 is not supported */
  617. switch (rc & 0x3) {
  618. case 0:
  619. c->guard_interval = GUARD_INTERVAL_1_4;
  620. break;
  621. case 1:
  622. c->guard_interval = GUARD_INTERVAL_1_8;
  623. break;
  624. case 2:
  625. c->guard_interval = GUARD_INTERVAL_1_16;
  626. break;
  627. }
  628. }
  629. return 0;
  630. noperlayer_error:
  631. /* per-layer info is incomplete; discard all per-layer */
  632. c->isdbt_layer_enabled = 0;
  633. return rc;
  634. }
  635. static int mb86a20s_reset_counters(struct dvb_frontend *fe)
  636. {
  637. struct mb86a20s_state *state = fe->demodulator_priv;
  638. struct dtv_frontend_properties *c = &fe->dtv_property_cache;
  639. int rc, val;
  640. dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
  641. /* Reset the counters, if the channel changed */
  642. if (state->last_frequency != c->frequency) {
  643. memset(&c->cnr, 0, sizeof(c->cnr));
  644. memset(&c->pre_bit_error, 0, sizeof(c->pre_bit_error));
  645. memset(&c->pre_bit_count, 0, sizeof(c->pre_bit_count));
  646. memset(&c->post_bit_error, 0, sizeof(c->post_bit_error));
  647. memset(&c->post_bit_count, 0, sizeof(c->post_bit_count));
  648. memset(&c->block_error, 0, sizeof(c->block_error));
  649. memset(&c->block_count, 0, sizeof(c->block_count));
  650. state->last_frequency = c->frequency;
  651. }
  652. /* Clear status for most stats */
  653. /* BER/PER counter reset */
  654. rc = mb86a20s_writeregdata(state, mb86a20s_per_ber_reset);
  655. if (rc < 0)
  656. goto err;
  657. /* CNR counter reset */
  658. rc = mb86a20s_readreg(state, 0x45);
  659. if (rc < 0)
  660. goto err;
  661. val = rc;
  662. rc = mb86a20s_writereg(state, 0x45, val | 0x10);
  663. if (rc < 0)
  664. goto err;
  665. rc = mb86a20s_writereg(state, 0x45, val & 0x6f);
  666. if (rc < 0)
  667. goto err;
  668. /* MER counter reset */
  669. rc = mb86a20s_writereg(state, 0x50, 0x50);
  670. if (rc < 0)
  671. goto err;
  672. rc = mb86a20s_readreg(state, 0x51);
  673. if (rc < 0)
  674. goto err;
  675. val = rc;
  676. rc = mb86a20s_writereg(state, 0x51, val | 0x01);
  677. if (rc < 0)
  678. goto err;
  679. rc = mb86a20s_writereg(state, 0x51, val & 0x06);
  680. if (rc < 0)
  681. goto err;
  682. goto ok;
  683. err:
  684. dev_err(&state->i2c->dev,
  685. "%s: Can't reset FE statistics (error %d).\n",
  686. __func__, rc);
  687. ok:
  688. return rc;
  689. }
  690. static int mb86a20s_get_pre_ber(struct dvb_frontend *fe,
  691. unsigned layer,
  692. u32 *error, u32 *count)
  693. {
  694. struct mb86a20s_state *state = fe->demodulator_priv;
  695. int rc, val;
  696. dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
  697. if (layer >= NUM_LAYERS)
  698. return -EINVAL;
  699. /* Check if the BER measures are already available */
  700. rc = mb86a20s_readreg(state, 0x54);
  701. if (rc < 0)
  702. return rc;
  703. /* Check if data is available for that layer */
  704. if (!(rc & (1 << layer))) {
  705. dev_dbg(&state->i2c->dev,
  706. "%s: preBER for layer %c is not available yet.\n",
  707. __func__, 'A' + layer);
  708. return -EBUSY;
  709. }
  710. /* Read Bit Error Count */
  711. rc = mb86a20s_readreg(state, 0x55 + layer * 3);
  712. if (rc < 0)
  713. return rc;
  714. *error = rc << 16;
  715. rc = mb86a20s_readreg(state, 0x56 + layer * 3);
  716. if (rc < 0)
  717. return rc;
  718. *error |= rc << 8;
  719. rc = mb86a20s_readreg(state, 0x57 + layer * 3);
  720. if (rc < 0)
  721. return rc;
  722. *error |= rc;
  723. dev_dbg(&state->i2c->dev,
  724. "%s: bit error before Viterbi for layer %c: %d.\n",
  725. __func__, 'A' + layer, *error);
  726. /* Read Bit Count */
  727. rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3);
  728. if (rc < 0)
  729. return rc;
  730. rc = mb86a20s_readreg(state, 0x51);
  731. if (rc < 0)
  732. return rc;
  733. *count = rc << 16;
  734. rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3);
  735. if (rc < 0)
  736. return rc;
  737. rc = mb86a20s_readreg(state, 0x51);
  738. if (rc < 0)
  739. return rc;
  740. *count |= rc << 8;
  741. rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3);
  742. if (rc < 0)
  743. return rc;
  744. rc = mb86a20s_readreg(state, 0x51);
  745. if (rc < 0)
  746. return rc;
  747. *count |= rc;
  748. dev_dbg(&state->i2c->dev,
  749. "%s: bit count before Viterbi for layer %c: %d.\n",
  750. __func__, 'A' + layer, *count);
  751. /*
  752. * As we get TMCC data from the frontend, we can better estimate the
  753. * BER bit counters, in order to do the BER measure during a longer
  754. * time. Use those data, if available, to update the bit count
  755. * measure.
  756. */
  757. if (state->estimated_rate[layer]
  758. && state->estimated_rate[layer] != *count) {
  759. dev_dbg(&state->i2c->dev,
  760. "%s: updating layer %c preBER counter to %d.\n",
  761. __func__, 'A' + layer, state->estimated_rate[layer]);
  762. /* Turn off BER before Viterbi */
  763. rc = mb86a20s_writereg(state, 0x52, 0x00);
  764. /* Update counter for this layer */
  765. rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3);
  766. if (rc < 0)
  767. return rc;
  768. rc = mb86a20s_writereg(state, 0x51,
  769. state->estimated_rate[layer] >> 16);
  770. if (rc < 0)
  771. return rc;
  772. rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3);
  773. if (rc < 0)
  774. return rc;
  775. rc = mb86a20s_writereg(state, 0x51,
  776. state->estimated_rate[layer] >> 8);
  777. if (rc < 0)
  778. return rc;
  779. rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3);
  780. if (rc < 0)
  781. return rc;
  782. rc = mb86a20s_writereg(state, 0x51,
  783. state->estimated_rate[layer]);
  784. if (rc < 0)
  785. return rc;
  786. /* Turn on BER before Viterbi */
  787. rc = mb86a20s_writereg(state, 0x52, 0x01);
  788. /* Reset all preBER counters */
  789. rc = mb86a20s_writereg(state, 0x53, 0x00);
  790. if (rc < 0)
  791. return rc;
  792. rc = mb86a20s_writereg(state, 0x53, 0x07);
  793. } else {
  794. /* Reset counter to collect new data */
  795. rc = mb86a20s_readreg(state, 0x53);
  796. if (rc < 0)
  797. return rc;
  798. val = rc;
  799. rc = mb86a20s_writereg(state, 0x53, val & ~(1 << layer));
  800. if (rc < 0)
  801. return rc;
  802. rc = mb86a20s_writereg(state, 0x53, val | (1 << layer));
  803. }
  804. return rc;
  805. }
  806. static int mb86a20s_get_post_ber(struct dvb_frontend *fe,
  807. unsigned layer,
  808. u32 *error, u32 *count)
  809. {
  810. struct mb86a20s_state *state = fe->demodulator_priv;
  811. u32 counter, collect_rate;
  812. int rc, val;
  813. dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
  814. if (layer >= NUM_LAYERS)
  815. return -EINVAL;
  816. /* Check if the BER measures are already available */
  817. rc = mb86a20s_readreg(state, 0x60);
  818. if (rc < 0)
  819. return rc;
  820. /* Check if data is available for that layer */
  821. if (!(rc & (1 << layer))) {
  822. dev_dbg(&state->i2c->dev,
  823. "%s: post BER for layer %c is not available yet.\n",
  824. __func__, 'A' + layer);
  825. return -EBUSY;
  826. }
  827. /* Read Bit Error Count */
  828. rc = mb86a20s_readreg(state, 0x64 + layer * 3);
  829. if (rc < 0)
  830. return rc;
  831. *error = rc << 16;
  832. rc = mb86a20s_readreg(state, 0x65 + layer * 3);
  833. if (rc < 0)
  834. return rc;
  835. *error |= rc << 8;
  836. rc = mb86a20s_readreg(state, 0x66 + layer * 3);
  837. if (rc < 0)
  838. return rc;
  839. *error |= rc;
  840. dev_dbg(&state->i2c->dev,
  841. "%s: post bit error for layer %c: %d.\n",
  842. __func__, 'A' + layer, *error);
  843. /* Read Bit Count */
  844. rc = mb86a20s_writereg(state, 0x50, 0xdc + layer * 2);
  845. if (rc < 0)
  846. return rc;
  847. rc = mb86a20s_readreg(state, 0x51);
  848. if (rc < 0)
  849. return rc;
  850. counter = rc << 8;
  851. rc = mb86a20s_writereg(state, 0x50, 0xdd + layer * 2);
  852. if (rc < 0)
  853. return rc;
  854. rc = mb86a20s_readreg(state, 0x51);
  855. if (rc < 0)
  856. return rc;
  857. counter |= rc;
  858. *count = counter * 204 * 8;
  859. dev_dbg(&state->i2c->dev,
  860. "%s: post bit count for layer %c: %d.\n",
  861. __func__, 'A' + layer, *count);
  862. /*
  863. * As we get TMCC data from the frontend, we can better estimate the
  864. * BER bit counters, in order to do the BER measure during a longer
  865. * time. Use those data, if available, to update the bit count
  866. * measure.
  867. */
  868. if (!state->estimated_rate[layer])
  869. goto reset_measurement;
  870. collect_rate = state->estimated_rate[layer] / 204 / 8;
  871. if (collect_rate < 32)
  872. collect_rate = 32;
  873. if (collect_rate > 65535)
  874. collect_rate = 65535;
  875. if (collect_rate != counter) {
  876. dev_dbg(&state->i2c->dev,
  877. "%s: updating postBER counter on layer %c to %d.\n",
  878. __func__, 'A' + layer, collect_rate);
  879. /* Turn off BER after Viterbi */
  880. rc = mb86a20s_writereg(state, 0x5e, 0x00);
  881. /* Update counter for this layer */
  882. rc = mb86a20s_writereg(state, 0x50, 0xdc + layer * 2);
  883. if (rc < 0)
  884. return rc;
  885. rc = mb86a20s_writereg(state, 0x51, collect_rate >> 8);
  886. if (rc < 0)
  887. return rc;
  888. rc = mb86a20s_writereg(state, 0x50, 0xdd + layer * 2);
  889. if (rc < 0)
  890. return rc;
  891. rc = mb86a20s_writereg(state, 0x51, collect_rate & 0xff);
  892. if (rc < 0)
  893. return rc;
  894. /* Turn on BER after Viterbi */
  895. rc = mb86a20s_writereg(state, 0x5e, 0x07);
  896. /* Reset all preBER counters */
  897. rc = mb86a20s_writereg(state, 0x5f, 0x00);
  898. if (rc < 0)
  899. return rc;
  900. rc = mb86a20s_writereg(state, 0x5f, 0x07);
  901. return rc;
  902. }
  903. reset_measurement:
  904. /* Reset counter to collect new data */
  905. rc = mb86a20s_readreg(state, 0x5f);
  906. if (rc < 0)
  907. return rc;
  908. val = rc;
  909. rc = mb86a20s_writereg(state, 0x5f, val & ~(1 << layer));
  910. if (rc < 0)
  911. return rc;
  912. rc = mb86a20s_writereg(state, 0x5f, val | (1 << layer));
  913. return rc;
  914. }
  915. static int mb86a20s_get_blk_error(struct dvb_frontend *fe,
  916. unsigned layer,
  917. u32 *error, u32 *count)
  918. {
  919. struct mb86a20s_state *state = fe->demodulator_priv;
  920. int rc, val;
  921. u32 collect_rate;
  922. dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
  923. if (layer >= NUM_LAYERS)
  924. return -EINVAL;
  925. /* Check if the PER measures are already available */
  926. rc = mb86a20s_writereg(state, 0x50, 0xb8);
  927. if (rc < 0)
  928. return rc;
  929. rc = mb86a20s_readreg(state, 0x51);
  930. if (rc < 0)
  931. return rc;
  932. /* Check if data is available for that layer */
  933. if (!(rc & (1 << layer))) {
  934. dev_dbg(&state->i2c->dev,
  935. "%s: block counts for layer %c aren't available yet.\n",
  936. __func__, 'A' + layer);
  937. return -EBUSY;
  938. }
  939. /* Read Packet error Count */
  940. rc = mb86a20s_writereg(state, 0x50, 0xb9 + layer * 2);
  941. if (rc < 0)
  942. return rc;
  943. rc = mb86a20s_readreg(state, 0x51);
  944. if (rc < 0)
  945. return rc;
  946. *error = rc << 8;
  947. rc = mb86a20s_writereg(state, 0x50, 0xba + layer * 2);
  948. if (rc < 0)
  949. return rc;
  950. rc = mb86a20s_readreg(state, 0x51);
  951. if (rc < 0)
  952. return rc;
  953. *error |= rc;
  954. dev_dbg(&state->i2c->dev, "%s: block error for layer %c: %d.\n",
  955. __func__, 'A' + layer, *error);
  956. /* Read Bit Count */
  957. rc = mb86a20s_writereg(state, 0x50, 0xb2 + layer * 2);
  958. if (rc < 0)
  959. return rc;
  960. rc = mb86a20s_readreg(state, 0x51);
  961. if (rc < 0)
  962. return rc;
  963. *count = rc << 8;
  964. rc = mb86a20s_writereg(state, 0x50, 0xb3 + layer * 2);
  965. if (rc < 0)
  966. return rc;
  967. rc = mb86a20s_readreg(state, 0x51);
  968. if (rc < 0)
  969. return rc;
  970. *count |= rc;
  971. dev_dbg(&state->i2c->dev,
  972. "%s: block count for layer %c: %d.\n",
  973. __func__, 'A' + layer, *count);
  974. /*
  975. * As we get TMCC data from the frontend, we can better estimate the
  976. * BER bit counters, in order to do the BER measure during a longer
  977. * time. Use those data, if available, to update the bit count
  978. * measure.
  979. */
  980. if (!state->estimated_rate[layer])
  981. goto reset_measurement;
  982. collect_rate = state->estimated_rate[layer] / 204 / 8;
  983. if (collect_rate < 32)
  984. collect_rate = 32;
  985. if (collect_rate > 65535)
  986. collect_rate = 65535;
  987. if (collect_rate != *count) {
  988. dev_dbg(&state->i2c->dev,
  989. "%s: updating PER counter on layer %c to %d.\n",
  990. __func__, 'A' + layer, collect_rate);
  991. /* Stop PER measurement */
  992. rc = mb86a20s_writereg(state, 0x50, 0xb0);
  993. if (rc < 0)
  994. return rc;
  995. rc = mb86a20s_writereg(state, 0x51, 0x00);
  996. if (rc < 0)
  997. return rc;
  998. /* Update this layer's counter */
  999. rc = mb86a20s_writereg(state, 0x50, 0xb2 + layer * 2);
  1000. if (rc < 0)
  1001. return rc;
  1002. rc = mb86a20s_writereg(state, 0x51, collect_rate >> 8);
  1003. if (rc < 0)
  1004. return rc;
  1005. rc = mb86a20s_writereg(state, 0x50, 0xb3 + layer * 2);
  1006. if (rc < 0)
  1007. return rc;
  1008. rc = mb86a20s_writereg(state, 0x51, collect_rate & 0xff);
  1009. if (rc < 0)
  1010. return rc;
  1011. /* start PER measurement */
  1012. rc = mb86a20s_writereg(state, 0x50, 0xb0);
  1013. if (rc < 0)
  1014. return rc;
  1015. rc = mb86a20s_writereg(state, 0x51, 0x07);
  1016. if (rc < 0)
  1017. return rc;
  1018. /* Reset all counters to collect new data */
  1019. rc = mb86a20s_writereg(state, 0x50, 0xb1);
  1020. if (rc < 0)
  1021. return rc;
  1022. rc = mb86a20s_writereg(state, 0x51, 0x07);
  1023. if (rc < 0)
  1024. return rc;
  1025. rc = mb86a20s_writereg(state, 0x51, 0x00);
  1026. return rc;
  1027. }
  1028. reset_measurement:
  1029. /* Reset counter to collect new data */
  1030. rc = mb86a20s_writereg(state, 0x50, 0xb1);
  1031. if (rc < 0)
  1032. return rc;
  1033. rc = mb86a20s_readreg(state, 0x51);
  1034. if (rc < 0)
  1035. return rc;
  1036. val = rc;
  1037. rc = mb86a20s_writereg(state, 0x51, val | (1 << layer));
  1038. if (rc < 0)
  1039. return rc;
  1040. rc = mb86a20s_writereg(state, 0x51, val & ~(1 << layer));
  1041. return rc;
  1042. }
  1043. struct linear_segments {
  1044. unsigned x, y;
  1045. };
  1046. /*
  1047. * All tables below return a dB/1000 measurement
  1048. */
  1049. static const struct linear_segments cnr_to_db_table[] = {
  1050. { 19648, 0},
  1051. { 18187, 1000},
  1052. { 16534, 2000},
  1053. { 14823, 3000},
  1054. { 13161, 4000},
  1055. { 11622, 5000},
  1056. { 10279, 6000},
  1057. { 9089, 7000},
  1058. { 8042, 8000},
  1059. { 7137, 9000},
  1060. { 6342, 10000},
  1061. { 5641, 11000},
  1062. { 5030, 12000},
  1063. { 4474, 13000},
  1064. { 3988, 14000},
  1065. { 3556, 15000},
  1066. { 3180, 16000},
  1067. { 2841, 17000},
  1068. { 2541, 18000},
  1069. { 2276, 19000},
  1070. { 2038, 20000},
  1071. { 1800, 21000},
  1072. { 1625, 22000},
  1073. { 1462, 23000},
  1074. { 1324, 24000},
  1075. { 1175, 25000},
  1076. { 1063, 26000},
  1077. { 980, 27000},
  1078. { 907, 28000},
  1079. { 840, 29000},
  1080. { 788, 30000},
  1081. };
  1082. static const struct linear_segments cnr_64qam_table[] = {
  1083. { 3922688, 0},
  1084. { 3920384, 1000},
  1085. { 3902720, 2000},
  1086. { 3894784, 3000},
  1087. { 3882496, 4000},
  1088. { 3872768, 5000},
  1089. { 3858944, 6000},
  1090. { 3851520, 7000},
  1091. { 3838976, 8000},
  1092. { 3829248, 9000},
  1093. { 3818240, 10000},
  1094. { 3806976, 11000},
  1095. { 3791872, 12000},
  1096. { 3767040, 13000},
  1097. { 3720960, 14000},
  1098. { 3637504, 15000},
  1099. { 3498496, 16000},
  1100. { 3296000, 17000},
  1101. { 3031040, 18000},
  1102. { 2715392, 19000},
  1103. { 2362624, 20000},
  1104. { 1963264, 21000},
  1105. { 1649664, 22000},
  1106. { 1366784, 23000},
  1107. { 1120768, 24000},
  1108. { 890880, 25000},
  1109. { 723456, 26000},
  1110. { 612096, 27000},
  1111. { 518912, 28000},
  1112. { 448256, 29000},
  1113. { 388864, 30000},
  1114. };
  1115. static const struct linear_segments cnr_16qam_table[] = {
  1116. { 5314816, 0},
  1117. { 5219072, 1000},
  1118. { 5118720, 2000},
  1119. { 4998912, 3000},
  1120. { 4875520, 4000},
  1121. { 4736000, 5000},
  1122. { 4604160, 6000},
  1123. { 4458752, 7000},
  1124. { 4300288, 8000},
  1125. { 4092928, 9000},
  1126. { 3836160, 10000},
  1127. { 3521024, 11000},
  1128. { 3155968, 12000},
  1129. { 2756864, 13000},
  1130. { 2347008, 14000},
  1131. { 1955072, 15000},
  1132. { 1593600, 16000},
  1133. { 1297920, 17000},
  1134. { 1043968, 18000},
  1135. { 839680, 19000},
  1136. { 672256, 20000},
  1137. { 523008, 21000},
  1138. { 424704, 22000},
  1139. { 345088, 23000},
  1140. { 280064, 24000},
  1141. { 221440, 25000},
  1142. { 179712, 26000},
  1143. { 151040, 27000},
  1144. { 128512, 28000},
  1145. { 110080, 29000},
  1146. { 95744, 30000},
  1147. };
  1148. static const struct linear_segments cnr_qpsk_table[] = {
  1149. { 2834176, 0},
  1150. { 2683648, 1000},
  1151. { 2536960, 2000},
  1152. { 2391808, 3000},
  1153. { 2133248, 4000},
  1154. { 1906176, 5000},
  1155. { 1666560, 6000},
  1156. { 1422080, 7000},
  1157. { 1189632, 8000},
  1158. { 976384, 9000},
  1159. { 790272, 10000},
  1160. { 633344, 11000},
  1161. { 505600, 12000},
  1162. { 402944, 13000},
  1163. { 320768, 14000},
  1164. { 255488, 15000},
  1165. { 204032, 16000},
  1166. { 163072, 17000},
  1167. { 130304, 18000},
  1168. { 105216, 19000},
  1169. { 83456, 20000},
  1170. { 65024, 21000},
  1171. { 52480, 22000},
  1172. { 42752, 23000},
  1173. { 34560, 24000},
  1174. { 27136, 25000},
  1175. { 22016, 26000},
  1176. { 18432, 27000},
  1177. { 15616, 28000},
  1178. { 13312, 29000},
  1179. { 11520, 30000},
  1180. };
  1181. static u32 interpolate_value(u32 value, const struct linear_segments *segments,
  1182. unsigned len)
  1183. {
  1184. u64 tmp64;
  1185. u32 dx, dy;
  1186. int i, ret;
  1187. if (value >= segments[0].x)
  1188. return segments[0].y;
  1189. if (value < segments[len-1].x)
  1190. return segments[len-1].y;
  1191. for (i = 1; i < len - 1; i++) {
  1192. /* If value is identical, no need to interpolate */
  1193. if (value == segments[i].x)
  1194. return segments[i].y;
  1195. if (value > segments[i].x)
  1196. break;
  1197. }
  1198. /* Linear interpolation between the two (x,y) points */
  1199. dy = segments[i].y - segments[i - 1].y;
  1200. dx = segments[i - 1].x - segments[i].x;
  1201. tmp64 = value - segments[i].x;
  1202. tmp64 *= dy;
  1203. do_div(tmp64, dx);
  1204. ret = segments[i].y - tmp64;
  1205. return ret;
  1206. }
  1207. static int mb86a20s_get_main_CNR(struct dvb_frontend *fe)
  1208. {
  1209. struct mb86a20s_state *state = fe->demodulator_priv;
  1210. struct dtv_frontend_properties *c = &fe->dtv_property_cache;
  1211. u32 cnr_linear, cnr;
  1212. int rc, val;
  1213. /* Check if CNR is available */
  1214. rc = mb86a20s_readreg(state, 0x45);
  1215. if (rc < 0)
  1216. return rc;
  1217. if (!(rc & 0x40)) {
  1218. dev_dbg(&state->i2c->dev, "%s: CNR is not available yet.\n",
  1219. __func__);
  1220. return -EBUSY;
  1221. }
  1222. val = rc;
  1223. rc = mb86a20s_readreg(state, 0x46);
  1224. if (rc < 0)
  1225. return rc;
  1226. cnr_linear = rc << 8;
  1227. rc = mb86a20s_readreg(state, 0x46);
  1228. if (rc < 0)
  1229. return rc;
  1230. cnr_linear |= rc;
  1231. cnr = interpolate_value(cnr_linear,
  1232. cnr_to_db_table, ARRAY_SIZE(cnr_to_db_table));
  1233. c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
  1234. c->cnr.stat[0].svalue = cnr;
  1235. dev_dbg(&state->i2c->dev, "%s: CNR is %d.%03d dB (%d)\n",
  1236. __func__, cnr / 1000, cnr % 1000, cnr_linear);
  1237. /* CNR counter reset */
  1238. rc = mb86a20s_writereg(state, 0x45, val | 0x10);
  1239. if (rc < 0)
  1240. return rc;
  1241. rc = mb86a20s_writereg(state, 0x45, val & 0x6f);
  1242. return rc;
  1243. }
  1244. static int mb86a20s_get_blk_error_layer_CNR(struct dvb_frontend *fe)
  1245. {
  1246. struct mb86a20s_state *state = fe->demodulator_priv;
  1247. struct dtv_frontend_properties *c = &fe->dtv_property_cache;
  1248. u32 mer, cnr;
  1249. int rc, val, layer;
  1250. const struct linear_segments *segs;
  1251. unsigned segs_len;
  1252. dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
  1253. /* Check if the measures are already available */
  1254. rc = mb86a20s_writereg(state, 0x50, 0x5b);
  1255. if (rc < 0)
  1256. return rc;
  1257. rc = mb86a20s_readreg(state, 0x51);
  1258. if (rc < 0)
  1259. return rc;
  1260. /* Check if data is available */
  1261. if (!(rc & 0x01)) {
  1262. dev_dbg(&state->i2c->dev,
  1263. "%s: MER measures aren't available yet.\n", __func__);
  1264. return -EBUSY;
  1265. }
  1266. /* Read all layers */
  1267. for (layer = 0; layer < NUM_LAYERS; layer++) {
  1268. if (!(c->isdbt_layer_enabled & (1 << layer))) {
  1269. c->cnr.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
  1270. continue;
  1271. }
  1272. rc = mb86a20s_writereg(state, 0x50, 0x52 + layer * 3);
  1273. if (rc < 0)
  1274. return rc;
  1275. rc = mb86a20s_readreg(state, 0x51);
  1276. if (rc < 0)
  1277. return rc;
  1278. mer = rc << 16;
  1279. rc = mb86a20s_writereg(state, 0x50, 0x53 + layer * 3);
  1280. if (rc < 0)
  1281. return rc;
  1282. rc = mb86a20s_readreg(state, 0x51);
  1283. if (rc < 0)
  1284. return rc;
  1285. mer |= rc << 8;
  1286. rc = mb86a20s_writereg(state, 0x50, 0x54 + layer * 3);
  1287. if (rc < 0)
  1288. return rc;
  1289. rc = mb86a20s_readreg(state, 0x51);
  1290. if (rc < 0)
  1291. return rc;
  1292. mer |= rc;
  1293. switch (c->layer[layer].modulation) {
  1294. case DQPSK:
  1295. case QPSK:
  1296. segs = cnr_qpsk_table;
  1297. segs_len = ARRAY_SIZE(cnr_qpsk_table);
  1298. break;
  1299. case QAM_16:
  1300. segs = cnr_16qam_table;
  1301. segs_len = ARRAY_SIZE(cnr_16qam_table);
  1302. break;
  1303. default:
  1304. case QAM_64:
  1305. segs = cnr_64qam_table;
  1306. segs_len = ARRAY_SIZE(cnr_64qam_table);
  1307. break;
  1308. }
  1309. cnr = interpolate_value(mer, segs, segs_len);
  1310. c->cnr.stat[1 + layer].scale = FE_SCALE_DECIBEL;
  1311. c->cnr.stat[1 + layer].svalue = cnr;
  1312. dev_dbg(&state->i2c->dev,
  1313. "%s: CNR for layer %c is %d.%03d dB (MER = %d).\n",
  1314. __func__, 'A' + layer, cnr / 1000, cnr % 1000, mer);
  1315. }
  1316. /* Start a new MER measurement */
  1317. /* MER counter reset */
  1318. rc = mb86a20s_writereg(state, 0x50, 0x50);
  1319. if (rc < 0)
  1320. return rc;
  1321. rc = mb86a20s_readreg(state, 0x51);
  1322. if (rc < 0)
  1323. return rc;
  1324. val = rc;
  1325. rc = mb86a20s_writereg(state, 0x51, val | 0x01);
  1326. if (rc < 0)
  1327. return rc;
  1328. rc = mb86a20s_writereg(state, 0x51, val & 0x06);
  1329. if (rc < 0)
  1330. return rc;
  1331. return 0;
  1332. }
  1333. static void mb86a20s_stats_not_ready(struct dvb_frontend *fe)
  1334. {
  1335. struct mb86a20s_state *state = fe->demodulator_priv;
  1336. struct dtv_frontend_properties *c = &fe->dtv_property_cache;
  1337. int layer;
  1338. dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
  1339. /* Fill the length of each status counter */
  1340. /* Only global stats */
  1341. c->strength.len = 1;
  1342. /* Per-layer stats - 3 layers + global */
  1343. c->cnr.len = NUM_LAYERS + 1;
  1344. c->pre_bit_error.len = NUM_LAYERS + 1;
  1345. c->pre_bit_count.len = NUM_LAYERS + 1;
  1346. c->post_bit_error.len = NUM_LAYERS + 1;
  1347. c->post_bit_count.len = NUM_LAYERS + 1;
  1348. c->block_error.len = NUM_LAYERS + 1;
  1349. c->block_count.len = NUM_LAYERS + 1;
  1350. /* Signal is always available */
  1351. c->strength.stat[0].scale = FE_SCALE_RELATIVE;
  1352. c->strength.stat[0].uvalue = 0;
  1353. /* Put all of them at FE_SCALE_NOT_AVAILABLE */
  1354. for (layer = 0; layer < NUM_LAYERS + 1; layer++) {
  1355. c->cnr.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
  1356. c->pre_bit_error.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
  1357. c->pre_bit_count.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
  1358. c->post_bit_error.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
  1359. c->post_bit_count.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
  1360. c->block_error.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
  1361. c->block_count.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
  1362. }
  1363. }
  1364. static int mb86a20s_get_stats(struct dvb_frontend *fe, int status_nr)
  1365. {
  1366. struct mb86a20s_state *state = fe->demodulator_priv;
  1367. struct dtv_frontend_properties *c = &fe->dtv_property_cache;
  1368. int rc = 0, layer;
  1369. u32 bit_error = 0, bit_count = 0;
  1370. u32 t_pre_bit_error = 0, t_pre_bit_count = 0;
  1371. u32 t_post_bit_error = 0, t_post_bit_count = 0;
  1372. u32 block_error = 0, block_count = 0;
  1373. u32 t_block_error = 0, t_block_count = 0;
  1374. int active_layers = 0, pre_ber_layers = 0, post_ber_layers = 0;
  1375. int per_layers = 0;
  1376. dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
  1377. mb86a20s_get_main_CNR(fe);
  1378. /* Get per-layer stats */
  1379. mb86a20s_get_blk_error_layer_CNR(fe);
  1380. /*
  1381. * At state 7, only CNR is available
  1382. * For BER measures, state=9 is required
  1383. * FIXME: we may get MER measures with state=8
  1384. */
  1385. if (status_nr < 9)
  1386. return 0;
  1387. for (layer = 0; layer < NUM_LAYERS; layer++) {
  1388. if (c->isdbt_layer_enabled & (1 << layer)) {
  1389. /* Layer is active and has rc segments */
  1390. active_layers++;
  1391. /* Handle BER before vterbi */
  1392. rc = mb86a20s_get_pre_ber(fe, layer,
  1393. &bit_error, &bit_count);
  1394. if (rc >= 0) {
  1395. c->pre_bit_error.stat[1 + layer].scale = FE_SCALE_COUNTER;
  1396. c->pre_bit_error.stat[1 + layer].uvalue += bit_error;
  1397. c->pre_bit_count.stat[1 + layer].scale = FE_SCALE_COUNTER;
  1398. c->pre_bit_count.stat[1 + layer].uvalue += bit_count;
  1399. } else if (rc != -EBUSY) {
  1400. /*
  1401. * If an I/O error happened,
  1402. * measures are now unavailable
  1403. */
  1404. c->pre_bit_error.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
  1405. c->pre_bit_count.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
  1406. dev_err(&state->i2c->dev,
  1407. "%s: Can't get BER for layer %c (error %d).\n",
  1408. __func__, 'A' + layer, rc);
  1409. }
  1410. if (c->block_error.stat[1 + layer].scale != FE_SCALE_NOT_AVAILABLE)
  1411. pre_ber_layers++;
  1412. /* Handle BER post vterbi */
  1413. rc = mb86a20s_get_post_ber(fe, layer,
  1414. &bit_error, &bit_count);
  1415. if (rc >= 0) {
  1416. c->post_bit_error.stat[1 + layer].scale = FE_SCALE_COUNTER;
  1417. c->post_bit_error.stat[1 + layer].uvalue += bit_error;
  1418. c->post_bit_count.stat[1 + layer].scale = FE_SCALE_COUNTER;
  1419. c->post_bit_count.stat[1 + layer].uvalue += bit_count;
  1420. } else if (rc != -EBUSY) {
  1421. /*
  1422. * If an I/O error happened,
  1423. * measures are now unavailable
  1424. */
  1425. c->post_bit_error.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
  1426. c->post_bit_count.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
  1427. dev_err(&state->i2c->dev,
  1428. "%s: Can't get BER for layer %c (error %d).\n",
  1429. __func__, 'A' + layer, rc);
  1430. }
  1431. if (c->block_error.stat[1 + layer].scale != FE_SCALE_NOT_AVAILABLE)
  1432. post_ber_layers++;
  1433. /* Handle Block errors for PER/UCB reports */
  1434. rc = mb86a20s_get_blk_error(fe, layer,
  1435. &block_error,
  1436. &block_count);
  1437. if (rc >= 0) {
  1438. c->block_error.stat[1 + layer].scale = FE_SCALE_COUNTER;
  1439. c->block_error.stat[1 + layer].uvalue += block_error;
  1440. c->block_count.stat[1 + layer].scale = FE_SCALE_COUNTER;
  1441. c->block_count.stat[1 + layer].uvalue += block_count;
  1442. } else if (rc != -EBUSY) {
  1443. /*
  1444. * If an I/O error happened,
  1445. * measures are now unavailable
  1446. */
  1447. c->block_error.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
  1448. c->block_count.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
  1449. dev_err(&state->i2c->dev,
  1450. "%s: Can't get PER for layer %c (error %d).\n",
  1451. __func__, 'A' + layer, rc);
  1452. }
  1453. if (c->block_error.stat[1 + layer].scale != FE_SCALE_NOT_AVAILABLE)
  1454. per_layers++;
  1455. /* Update total preBER */
  1456. t_pre_bit_error += c->pre_bit_error.stat[1 + layer].uvalue;
  1457. t_pre_bit_count += c->pre_bit_count.stat[1 + layer].uvalue;
  1458. /* Update total postBER */
  1459. t_post_bit_error += c->post_bit_error.stat[1 + layer].uvalue;
  1460. t_post_bit_count += c->post_bit_count.stat[1 + layer].uvalue;
  1461. /* Update total PER */
  1462. t_block_error += c->block_error.stat[1 + layer].uvalue;
  1463. t_block_count += c->block_count.stat[1 + layer].uvalue;
  1464. }
  1465. }
  1466. /*
  1467. * Start showing global count if at least one error count is
  1468. * available.
  1469. */
  1470. if (pre_ber_layers) {
  1471. /*
  1472. * At least one per-layer BER measure was read. We can now
  1473. * calculate the total BER
  1474. *
  1475. * Total Bit Error/Count is calculated as the sum of the
  1476. * bit errors on all active layers.
  1477. */
  1478. c->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
  1479. c->pre_bit_error.stat[0].uvalue = t_pre_bit_error;
  1480. c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
  1481. c->pre_bit_count.stat[0].uvalue = t_pre_bit_count;
  1482. } else {
  1483. c->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
  1484. c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
  1485. }
  1486. /*
  1487. * Start showing global count if at least one error count is
  1488. * available.
  1489. */
  1490. if (post_ber_layers) {
  1491. /*
  1492. * At least one per-layer BER measure was read. We can now
  1493. * calculate the total BER
  1494. *
  1495. * Total Bit Error/Count is calculated as the sum of the
  1496. * bit errors on all active layers.
  1497. */
  1498. c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
  1499. c->post_bit_error.stat[0].uvalue = t_post_bit_error;
  1500. c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
  1501. c->post_bit_count.stat[0].uvalue = t_post_bit_count;
  1502. } else {
  1503. c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
  1504. c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
  1505. }
  1506. if (per_layers) {
  1507. /*
  1508. * At least one per-layer UCB measure was read. We can now
  1509. * calculate the total UCB
  1510. *
  1511. * Total block Error/Count is calculated as the sum of the
  1512. * block errors on all active layers.
  1513. */
  1514. c->block_error.stat[0].scale = FE_SCALE_COUNTER;
  1515. c->block_error.stat[0].uvalue = t_block_error;
  1516. c->block_count.stat[0].scale = FE_SCALE_COUNTER;
  1517. c->block_count.stat[0].uvalue = t_block_count;
  1518. } else {
  1519. c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
  1520. c->block_count.stat[0].scale = FE_SCALE_COUNTER;
  1521. }
  1522. return rc;
  1523. }
  1524. /*
  1525. * The functions below are called via DVB callbacks, so they need to
  1526. * properly use the I2C gate control
  1527. */
  1528. static int mb86a20s_initfe(struct dvb_frontend *fe)
  1529. {
  1530. struct mb86a20s_state *state = fe->demodulator_priv;
  1531. u64 pll;
  1532. u32 fclk;
  1533. int rc;
  1534. u8 regD5 = 1, reg71, reg09 = 0x3a;
  1535. dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
  1536. if (fe->ops.i2c_gate_ctrl)
  1537. fe->ops.i2c_gate_ctrl(fe, 0);
  1538. /* Initialize the frontend */
  1539. rc = mb86a20s_writeregdata(state, mb86a20s_init1);
  1540. if (rc < 0)
  1541. goto err;
  1542. if (!state->inversion)
  1543. reg09 |= 0x04;
  1544. rc = mb86a20s_writereg(state, 0x09, reg09);
  1545. if (rc < 0)
  1546. goto err;
  1547. if (!state->bw)
  1548. reg71 = 1;
  1549. else
  1550. reg71 = 0;
  1551. rc = mb86a20s_writereg(state, 0x39, reg71);
  1552. if (rc < 0)
  1553. goto err;
  1554. rc = mb86a20s_writereg(state, 0x71, state->bw);
  1555. if (rc < 0)
  1556. goto err;
  1557. if (state->subchannel) {
  1558. rc = mb86a20s_writereg(state, 0x44, state->subchannel);
  1559. if (rc < 0)
  1560. goto err;
  1561. }
  1562. fclk = state->config->fclk;
  1563. if (!fclk)
  1564. fclk = 32571428;
  1565. /* Adjust IF frequency to match tuner */
  1566. if (fe->ops.tuner_ops.get_if_frequency)
  1567. fe->ops.tuner_ops.get_if_frequency(fe, &state->if_freq);
  1568. if (!state->if_freq)
  1569. state->if_freq = 3300000;
  1570. pll = (((u64)1) << 34) * state->if_freq;
  1571. do_div(pll, 63 * fclk);
  1572. pll = (1 << 25) - pll;
  1573. rc = mb86a20s_writereg(state, 0x28, 0x2a);
  1574. if (rc < 0)
  1575. goto err;
  1576. rc = mb86a20s_writereg(state, 0x29, (pll >> 16) & 0xff);
  1577. if (rc < 0)
  1578. goto err;
  1579. rc = mb86a20s_writereg(state, 0x2a, (pll >> 8) & 0xff);
  1580. if (rc < 0)
  1581. goto err;
  1582. rc = mb86a20s_writereg(state, 0x2b, pll & 0xff);
  1583. if (rc < 0)
  1584. goto err;
  1585. dev_dbg(&state->i2c->dev, "%s: fclk=%d, IF=%d, clock reg=0x%06llx\n",
  1586. __func__, fclk, state->if_freq, (long long)pll);
  1587. /* pll = freq[Hz] * 2^24/10^6 / 16.285714286 */
  1588. pll = state->if_freq * 1677721600L;
  1589. do_div(pll, 1628571429L);
  1590. rc = mb86a20s_writereg(state, 0x28, 0x20);
  1591. if (rc < 0)
  1592. goto err;
  1593. rc = mb86a20s_writereg(state, 0x29, (pll >> 16) & 0xff);
  1594. if (rc < 0)
  1595. goto err;
  1596. rc = mb86a20s_writereg(state, 0x2a, (pll >> 8) & 0xff);
  1597. if (rc < 0)
  1598. goto err;
  1599. rc = mb86a20s_writereg(state, 0x2b, pll & 0xff);
  1600. if (rc < 0)
  1601. goto err;
  1602. dev_dbg(&state->i2c->dev, "%s: IF=%d, IF reg=0x%06llx\n",
  1603. __func__, state->if_freq, (long long)pll);
  1604. if (!state->config->is_serial)
  1605. regD5 &= ~1;
  1606. rc = mb86a20s_writereg(state, 0x50, 0xd5);
  1607. if (rc < 0)
  1608. goto err;
  1609. rc = mb86a20s_writereg(state, 0x51, regD5);
  1610. if (rc < 0)
  1611. goto err;
  1612. rc = mb86a20s_writeregdata(state, mb86a20s_init2);
  1613. if (rc < 0)
  1614. goto err;
  1615. err:
  1616. if (fe->ops.i2c_gate_ctrl)
  1617. fe->ops.i2c_gate_ctrl(fe, 1);
  1618. if (rc < 0) {
  1619. state->need_init = true;
  1620. dev_info(&state->i2c->dev,
  1621. "mb86a20s: Init failed. Will try again later\n");
  1622. } else {
  1623. state->need_init = false;
  1624. dev_dbg(&state->i2c->dev, "Initialization succeeded.\n");
  1625. }
  1626. return rc;
  1627. }
  1628. static int mb86a20s_set_frontend(struct dvb_frontend *fe)
  1629. {
  1630. struct mb86a20s_state *state = fe->demodulator_priv;
  1631. struct dtv_frontend_properties *c = &fe->dtv_property_cache;
  1632. int rc, if_freq;
  1633. dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
  1634. if (!c->isdbt_layer_enabled)
  1635. c->isdbt_layer_enabled = 7;
  1636. if (c->isdbt_layer_enabled == 1)
  1637. state->bw = MB86A20S_1SEG;
  1638. else if (c->isdbt_partial_reception)
  1639. state->bw = MB86A20S_13SEG_PARTIAL;
  1640. else
  1641. state->bw = MB86A20S_13SEG;
  1642. if (c->inversion == INVERSION_ON)
  1643. state->inversion = true;
  1644. else
  1645. state->inversion = false;
  1646. if (!c->isdbt_sb_mode) {
  1647. state->subchannel = 0;
  1648. } else {
  1649. if (c->isdbt_sb_subchannel >= ARRAY_SIZE(mb86a20s_subchannel))
  1650. c->isdbt_sb_subchannel = 0;
  1651. state->subchannel = mb86a20s_subchannel[c->isdbt_sb_subchannel];
  1652. }
  1653. /*
  1654. * Gate should already be opened, but it doesn't hurt to
  1655. * double-check
  1656. */
  1657. if (fe->ops.i2c_gate_ctrl)
  1658. fe->ops.i2c_gate_ctrl(fe, 1);
  1659. fe->ops.tuner_ops.set_params(fe);
  1660. if (fe->ops.tuner_ops.get_if_frequency)
  1661. fe->ops.tuner_ops.get_if_frequency(fe, &if_freq);
  1662. /*
  1663. * Make it more reliable: if, for some reason, the initial
  1664. * device initialization doesn't happen, initialize it when
  1665. * a SBTVD parameters are adjusted.
  1666. *
  1667. * Unfortunately, due to a hard to track bug at tda829x/tda18271,
  1668. * the agc callback logic is not called during DVB attach time,
  1669. * causing mb86a20s to not be initialized with Kworld SBTVD.
  1670. * So, this hack is needed, in order to make Kworld SBTVD to work.
  1671. *
  1672. * It is also needed to change the IF after the initial init.
  1673. *
  1674. * HACK: Always init the frontend when set_frontend is called:
  1675. * it was noticed that, on some devices, it fails to lock on a
  1676. * different channel. So, it is better to reset everything, even
  1677. * wasting some time, than to loose channel lock.
  1678. */
  1679. mb86a20s_initfe(fe);
  1680. if (fe->ops.i2c_gate_ctrl)
  1681. fe->ops.i2c_gate_ctrl(fe, 0);
  1682. rc = mb86a20s_writeregdata(state, mb86a20s_reset_reception);
  1683. mb86a20s_reset_counters(fe);
  1684. mb86a20s_stats_not_ready(fe);
  1685. if (fe->ops.i2c_gate_ctrl)
  1686. fe->ops.i2c_gate_ctrl(fe, 1);
  1687. return rc;
  1688. }
  1689. static int mb86a20s_read_status_and_stats(struct dvb_frontend *fe,
  1690. enum fe_status *status)
  1691. {
  1692. struct mb86a20s_state *state = fe->demodulator_priv;
  1693. int rc, status_nr;
  1694. dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
  1695. if (fe->ops.i2c_gate_ctrl)
  1696. fe->ops.i2c_gate_ctrl(fe, 0);
  1697. /* Get lock */
  1698. status_nr = mb86a20s_read_status(fe, status);
  1699. if (status_nr < 7) {
  1700. mb86a20s_stats_not_ready(fe);
  1701. mb86a20s_reset_frontend_cache(fe);
  1702. }
  1703. if (status_nr < 0) {
  1704. dev_err(&state->i2c->dev,
  1705. "%s: Can't read frontend lock status\n", __func__);
  1706. rc = status_nr;
  1707. goto error;
  1708. }
  1709. /* Get signal strength */
  1710. rc = mb86a20s_read_signal_strength(fe);
  1711. if (rc < 0) {
  1712. dev_err(&state->i2c->dev,
  1713. "%s: Can't reset VBER registers.\n", __func__);
  1714. mb86a20s_stats_not_ready(fe);
  1715. mb86a20s_reset_frontend_cache(fe);
  1716. rc = 0; /* Status is OK */
  1717. goto error;
  1718. }
  1719. if (status_nr >= 7) {
  1720. /* Get TMCC info*/
  1721. rc = mb86a20s_get_frontend(fe);
  1722. if (rc < 0) {
  1723. dev_err(&state->i2c->dev,
  1724. "%s: Can't get FE TMCC data.\n", __func__);
  1725. rc = 0; /* Status is OK */
  1726. goto error;
  1727. }
  1728. /* Get statistics */
  1729. rc = mb86a20s_get_stats(fe, status_nr);
  1730. if (rc < 0 && rc != -EBUSY) {
  1731. dev_err(&state->i2c->dev,
  1732. "%s: Can't get FE statistics.\n", __func__);
  1733. rc = 0;
  1734. goto error;
  1735. }
  1736. rc = 0; /* Don't return EBUSY to userspace */
  1737. }
  1738. goto ok;
  1739. error:
  1740. mb86a20s_stats_not_ready(fe);
  1741. ok:
  1742. if (fe->ops.i2c_gate_ctrl)
  1743. fe->ops.i2c_gate_ctrl(fe, 1);
  1744. return rc;
  1745. }
  1746. static int mb86a20s_read_signal_strength_from_cache(struct dvb_frontend *fe,
  1747. u16 *strength)
  1748. {
  1749. struct dtv_frontend_properties *c = &fe->dtv_property_cache;
  1750. *strength = c->strength.stat[0].uvalue;
  1751. return 0;
  1752. }
  1753. static int mb86a20s_tune(struct dvb_frontend *fe,
  1754. bool re_tune,
  1755. unsigned int mode_flags,
  1756. unsigned int *delay,
  1757. enum fe_status *status)
  1758. {
  1759. struct mb86a20s_state *state = fe->demodulator_priv;
  1760. int rc = 0;
  1761. dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
  1762. if (re_tune)
  1763. rc = mb86a20s_set_frontend(fe);
  1764. if (!(mode_flags & FE_TUNE_MODE_ONESHOT))
  1765. mb86a20s_read_status_and_stats(fe, status);
  1766. return rc;
  1767. }
  1768. static void mb86a20s_release(struct dvb_frontend *fe)
  1769. {
  1770. struct mb86a20s_state *state = fe->demodulator_priv;
  1771. dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
  1772. kfree(state);
  1773. }
  1774. static enum dvbfe_algo mb86a20s_get_frontend_algo(struct dvb_frontend *fe)
  1775. {
  1776. return DVBFE_ALGO_HW;
  1777. }
  1778. static const struct dvb_frontend_ops mb86a20s_ops;
  1779. struct dvb_frontend *mb86a20s_attach(const struct mb86a20s_config *config,
  1780. struct i2c_adapter *i2c)
  1781. {
  1782. struct mb86a20s_state *state;
  1783. u8 rev;
  1784. dev_dbg(&i2c->dev, "%s called.\n", __func__);
  1785. /* allocate memory for the internal state */
  1786. state = kzalloc(sizeof(*state), GFP_KERNEL);
  1787. if (!state)
  1788. return NULL;
  1789. /* setup the state */
  1790. state->config = config;
  1791. state->i2c = i2c;
  1792. /* create dvb_frontend */
  1793. memcpy(&state->frontend.ops, &mb86a20s_ops,
  1794. sizeof(struct dvb_frontend_ops));
  1795. state->frontend.demodulator_priv = state;
  1796. /* Check if it is a mb86a20s frontend */
  1797. rev = mb86a20s_readreg(state, 0);
  1798. if (rev != 0x13) {
  1799. kfree(state);
  1800. dev_dbg(&i2c->dev,
  1801. "Frontend revision %d is unknown - aborting.\n",
  1802. rev);
  1803. return NULL;
  1804. }
  1805. dev_info(&i2c->dev, "Detected a Fujitsu mb86a20s frontend\n");
  1806. return &state->frontend;
  1807. }
  1808. EXPORT_SYMBOL(mb86a20s_attach);
  1809. static const struct dvb_frontend_ops mb86a20s_ops = {
  1810. .delsys = { SYS_ISDBT },
  1811. /* Use dib8000 values per default */
  1812. .info = {
  1813. .name = "Fujitsu mb86A20s",
  1814. .caps = FE_CAN_RECOVER |
  1815. FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
  1816. FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
  1817. FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
  1818. FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_QAM_AUTO |
  1819. FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO,
  1820. /* Actually, those values depend on the used tuner */
  1821. .frequency_min_hz = 45 * MHz,
  1822. .frequency_max_hz = 864 * MHz,
  1823. .frequency_stepsize_hz = 62500,
  1824. },
  1825. .release = mb86a20s_release,
  1826. .init = mb86a20s_initfe,
  1827. .set_frontend = mb86a20s_set_frontend,
  1828. .read_status = mb86a20s_read_status_and_stats,
  1829. .read_signal_strength = mb86a20s_read_signal_strength_from_cache,
  1830. .tune = mb86a20s_tune,
  1831. .get_frontend_algo = mb86a20s_get_frontend_algo,
  1832. };
  1833. MODULE_DESCRIPTION("DVB Frontend module for Fujitsu mb86A20s hardware");
  1834. MODULE_AUTHOR("Mauro Carvalho Chehab");
  1835. MODULE_LICENSE("GPL");