m88rs2000.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. Driver for M88RS2000 demodulator and tuner
  4. Copyright (C) 2012 Malcolm Priestley (tvboxspy@gmail.com)
  5. Beta Driver
  6. Include various calculation code from DS3000 driver.
  7. Copyright (C) 2009 Konstantin Dimitrov.
  8. */
  9. #include <linux/init.h>
  10. #include <linux/module.h>
  11. #include <linux/device.h>
  12. #include <linux/jiffies.h>
  13. #include <linux/string.h>
  14. #include <linux/slab.h>
  15. #include <linux/types.h>
  16. #include <media/dvb_frontend.h>
  17. #include "m88rs2000.h"
  18. struct m88rs2000_state {
  19. struct i2c_adapter *i2c;
  20. const struct m88rs2000_config *config;
  21. struct dvb_frontend frontend;
  22. u8 no_lock_count;
  23. u32 tuner_frequency;
  24. u32 symbol_rate;
  25. enum fe_code_rate fec_inner;
  26. u8 tuner_level;
  27. int errmode;
  28. };
  29. static int m88rs2000_debug;
  30. module_param_named(debug, m88rs2000_debug, int, 0644);
  31. MODULE_PARM_DESC(debug, "set debugging level (1=info (or-able)).");
  32. #define dprintk(level, args...) do { \
  33. if (level & m88rs2000_debug) \
  34. printk(KERN_DEBUG "m88rs2000-fe: " args); \
  35. } while (0)
  36. #define deb_info(args...) dprintk(0x01, args)
  37. #define info(format, arg...) \
  38. printk(KERN_INFO "m88rs2000-fe: " format "\n" , ## arg)
  39. static int m88rs2000_writereg(struct m88rs2000_state *state,
  40. u8 reg, u8 data)
  41. {
  42. int ret;
  43. u8 buf[] = { reg, data };
  44. struct i2c_msg msg = {
  45. .addr = state->config->demod_addr,
  46. .flags = 0,
  47. .buf = buf,
  48. .len = 2
  49. };
  50. ret = i2c_transfer(state->i2c, &msg, 1);
  51. if (ret != 1)
  52. deb_info("%s: writereg error (reg == 0x%02x, val == 0x%02x, ret == %i)\n",
  53. __func__, reg, data, ret);
  54. return (ret != 1) ? -EREMOTEIO : 0;
  55. }
  56. static u8 m88rs2000_readreg(struct m88rs2000_state *state, u8 reg)
  57. {
  58. int ret;
  59. u8 b0[] = { reg };
  60. u8 b1[] = { 0 };
  61. struct i2c_msg msg[] = {
  62. {
  63. .addr = state->config->demod_addr,
  64. .flags = 0,
  65. .buf = b0,
  66. .len = 1
  67. }, {
  68. .addr = state->config->demod_addr,
  69. .flags = I2C_M_RD,
  70. .buf = b1,
  71. .len = 1
  72. }
  73. };
  74. ret = i2c_transfer(state->i2c, msg, 2);
  75. if (ret != 2)
  76. deb_info("%s: readreg error (reg == 0x%02x, ret == %i)\n",
  77. __func__, reg, ret);
  78. return b1[0];
  79. }
  80. static u32 m88rs2000_get_mclk(struct dvb_frontend *fe)
  81. {
  82. struct m88rs2000_state *state = fe->demodulator_priv;
  83. u32 mclk;
  84. u8 reg;
  85. /* Must not be 0x00 or 0xff */
  86. reg = m88rs2000_readreg(state, 0x86);
  87. if (!reg || reg == 0xff)
  88. return 0;
  89. reg /= 2;
  90. reg += 1;
  91. mclk = (u32)(reg * RS2000_FE_CRYSTAL_KHZ + 28 / 2) / 28;
  92. return mclk;
  93. }
  94. static int m88rs2000_set_carrieroffset(struct dvb_frontend *fe, s16 offset)
  95. {
  96. struct m88rs2000_state *state = fe->demodulator_priv;
  97. u32 mclk;
  98. s32 tmp;
  99. u8 reg;
  100. int ret;
  101. mclk = m88rs2000_get_mclk(fe);
  102. if (!mclk)
  103. return -EINVAL;
  104. tmp = (offset * 4096 + (s32)mclk / 2) / (s32)mclk;
  105. if (tmp < 0)
  106. tmp += 4096;
  107. /* Carrier Offset */
  108. ret = m88rs2000_writereg(state, 0x9c, (u8)(tmp >> 4));
  109. reg = m88rs2000_readreg(state, 0x9d);
  110. reg &= 0xf;
  111. reg |= (u8)(tmp & 0xf) << 4;
  112. ret |= m88rs2000_writereg(state, 0x9d, reg);
  113. return ret;
  114. }
  115. static int m88rs2000_set_symbolrate(struct dvb_frontend *fe, u32 srate)
  116. {
  117. struct m88rs2000_state *state = fe->demodulator_priv;
  118. int ret;
  119. u64 temp;
  120. u32 mclk;
  121. u8 b[3];
  122. if ((srate < 1000000) || (srate > 45000000))
  123. return -EINVAL;
  124. mclk = m88rs2000_get_mclk(fe);
  125. if (!mclk)
  126. return -EINVAL;
  127. temp = srate / 1000;
  128. temp *= 1 << 24;
  129. do_div(temp, mclk);
  130. b[0] = (u8) (temp >> 16) & 0xff;
  131. b[1] = (u8) (temp >> 8) & 0xff;
  132. b[2] = (u8) temp & 0xff;
  133. ret = m88rs2000_writereg(state, 0x93, b[2]);
  134. ret |= m88rs2000_writereg(state, 0x94, b[1]);
  135. ret |= m88rs2000_writereg(state, 0x95, b[0]);
  136. if (srate > 10000000)
  137. ret |= m88rs2000_writereg(state, 0xa0, 0x20);
  138. else
  139. ret |= m88rs2000_writereg(state, 0xa0, 0x60);
  140. ret |= m88rs2000_writereg(state, 0xa1, 0xe0);
  141. if (srate > 12000000)
  142. ret |= m88rs2000_writereg(state, 0xa3, 0x20);
  143. else if (srate > 2800000)
  144. ret |= m88rs2000_writereg(state, 0xa3, 0x98);
  145. else
  146. ret |= m88rs2000_writereg(state, 0xa3, 0x90);
  147. deb_info("m88rs2000: m88rs2000_set_symbolrate\n");
  148. return ret;
  149. }
  150. static int m88rs2000_send_diseqc_msg(struct dvb_frontend *fe,
  151. struct dvb_diseqc_master_cmd *m)
  152. {
  153. struct m88rs2000_state *state = fe->demodulator_priv;
  154. int i;
  155. u8 reg;
  156. deb_info("%s\n", __func__);
  157. m88rs2000_writereg(state, 0x9a, 0x30);
  158. reg = m88rs2000_readreg(state, 0xb2);
  159. reg &= 0x3f;
  160. m88rs2000_writereg(state, 0xb2, reg);
  161. for (i = 0; i < m->msg_len; i++)
  162. m88rs2000_writereg(state, 0xb3 + i, m->msg[i]);
  163. reg = m88rs2000_readreg(state, 0xb1);
  164. reg &= 0x87;
  165. reg |= ((m->msg_len - 1) << 3) | 0x07;
  166. reg &= 0x7f;
  167. m88rs2000_writereg(state, 0xb1, reg);
  168. for (i = 0; i < 15; i++) {
  169. if ((m88rs2000_readreg(state, 0xb1) & 0x40) == 0x0)
  170. break;
  171. msleep(20);
  172. }
  173. reg = m88rs2000_readreg(state, 0xb1);
  174. if ((reg & 0x40) > 0x0) {
  175. reg &= 0x7f;
  176. reg |= 0x40;
  177. m88rs2000_writereg(state, 0xb1, reg);
  178. }
  179. reg = m88rs2000_readreg(state, 0xb2);
  180. reg &= 0x3f;
  181. reg |= 0x80;
  182. m88rs2000_writereg(state, 0xb2, reg);
  183. m88rs2000_writereg(state, 0x9a, 0xb0);
  184. return 0;
  185. }
  186. static int m88rs2000_send_diseqc_burst(struct dvb_frontend *fe,
  187. enum fe_sec_mini_cmd burst)
  188. {
  189. struct m88rs2000_state *state = fe->demodulator_priv;
  190. u8 reg0, reg1;
  191. deb_info("%s\n", __func__);
  192. m88rs2000_writereg(state, 0x9a, 0x30);
  193. msleep(50);
  194. reg0 = m88rs2000_readreg(state, 0xb1);
  195. reg1 = m88rs2000_readreg(state, 0xb2);
  196. /* TODO complete this section */
  197. m88rs2000_writereg(state, 0xb2, reg1);
  198. m88rs2000_writereg(state, 0xb1, reg0);
  199. m88rs2000_writereg(state, 0x9a, 0xb0);
  200. return 0;
  201. }
  202. static int m88rs2000_set_tone(struct dvb_frontend *fe,
  203. enum fe_sec_tone_mode tone)
  204. {
  205. struct m88rs2000_state *state = fe->demodulator_priv;
  206. u8 reg0, reg1;
  207. m88rs2000_writereg(state, 0x9a, 0x30);
  208. reg0 = m88rs2000_readreg(state, 0xb1);
  209. reg1 = m88rs2000_readreg(state, 0xb2);
  210. reg1 &= 0x3f;
  211. switch (tone) {
  212. case SEC_TONE_ON:
  213. reg0 |= 0x4;
  214. reg0 &= 0xbc;
  215. break;
  216. case SEC_TONE_OFF:
  217. reg1 |= 0x80;
  218. break;
  219. default:
  220. break;
  221. }
  222. m88rs2000_writereg(state, 0xb2, reg1);
  223. m88rs2000_writereg(state, 0xb1, reg0);
  224. m88rs2000_writereg(state, 0x9a, 0xb0);
  225. return 0;
  226. }
  227. struct inittab {
  228. u8 cmd;
  229. u8 reg;
  230. u8 val;
  231. };
  232. static struct inittab m88rs2000_setup[] = {
  233. {DEMOD_WRITE, 0x9a, 0x30},
  234. {DEMOD_WRITE, 0x00, 0x01},
  235. {WRITE_DELAY, 0x19, 0x00},
  236. {DEMOD_WRITE, 0x00, 0x00},
  237. {DEMOD_WRITE, 0x9a, 0xb0},
  238. {DEMOD_WRITE, 0x81, 0xc1},
  239. {DEMOD_WRITE, 0x81, 0x81},
  240. {DEMOD_WRITE, 0x86, 0xc6},
  241. {DEMOD_WRITE, 0x9a, 0x30},
  242. {DEMOD_WRITE, 0xf0, 0x22},
  243. {DEMOD_WRITE, 0xf1, 0xbf},
  244. {DEMOD_WRITE, 0xb0, 0x45},
  245. {DEMOD_WRITE, 0xb2, 0x01}, /* set voltage pin always set 1*/
  246. {DEMOD_WRITE, 0x9a, 0xb0},
  247. {0xff, 0xaa, 0xff}
  248. };
  249. static struct inittab m88rs2000_shutdown[] = {
  250. {DEMOD_WRITE, 0x9a, 0x30},
  251. {DEMOD_WRITE, 0xb0, 0x00},
  252. {DEMOD_WRITE, 0xf1, 0x89},
  253. {DEMOD_WRITE, 0x00, 0x01},
  254. {DEMOD_WRITE, 0x9a, 0xb0},
  255. {DEMOD_WRITE, 0x81, 0x81},
  256. {0xff, 0xaa, 0xff}
  257. };
  258. static struct inittab fe_reset[] = {
  259. {DEMOD_WRITE, 0x00, 0x01},
  260. {DEMOD_WRITE, 0x20, 0x81},
  261. {DEMOD_WRITE, 0x21, 0x80},
  262. {DEMOD_WRITE, 0x10, 0x33},
  263. {DEMOD_WRITE, 0x11, 0x44},
  264. {DEMOD_WRITE, 0x12, 0x07},
  265. {DEMOD_WRITE, 0x18, 0x20},
  266. {DEMOD_WRITE, 0x28, 0x04},
  267. {DEMOD_WRITE, 0x29, 0x8e},
  268. {DEMOD_WRITE, 0x3b, 0xff},
  269. {DEMOD_WRITE, 0x32, 0x10},
  270. {DEMOD_WRITE, 0x33, 0x02},
  271. {DEMOD_WRITE, 0x34, 0x30},
  272. {DEMOD_WRITE, 0x35, 0xff},
  273. {DEMOD_WRITE, 0x38, 0x50},
  274. {DEMOD_WRITE, 0x39, 0x68},
  275. {DEMOD_WRITE, 0x3c, 0x7f},
  276. {DEMOD_WRITE, 0x3d, 0x0f},
  277. {DEMOD_WRITE, 0x45, 0x20},
  278. {DEMOD_WRITE, 0x46, 0x24},
  279. {DEMOD_WRITE, 0x47, 0x7c},
  280. {DEMOD_WRITE, 0x48, 0x16},
  281. {DEMOD_WRITE, 0x49, 0x04},
  282. {DEMOD_WRITE, 0x4a, 0x01},
  283. {DEMOD_WRITE, 0x4b, 0x78},
  284. {DEMOD_WRITE, 0X4d, 0xd2},
  285. {DEMOD_WRITE, 0x4e, 0x6d},
  286. {DEMOD_WRITE, 0x50, 0x30},
  287. {DEMOD_WRITE, 0x51, 0x30},
  288. {DEMOD_WRITE, 0x54, 0x7b},
  289. {DEMOD_WRITE, 0x56, 0x09},
  290. {DEMOD_WRITE, 0x58, 0x59},
  291. {DEMOD_WRITE, 0x59, 0x37},
  292. {DEMOD_WRITE, 0x63, 0xfa},
  293. {0xff, 0xaa, 0xff}
  294. };
  295. static struct inittab fe_trigger[] = {
  296. {DEMOD_WRITE, 0x97, 0x04},
  297. {DEMOD_WRITE, 0x99, 0x77},
  298. {DEMOD_WRITE, 0x9b, 0x64},
  299. {DEMOD_WRITE, 0x9e, 0x00},
  300. {DEMOD_WRITE, 0x9f, 0xf8},
  301. {DEMOD_WRITE, 0x98, 0xff},
  302. {DEMOD_WRITE, 0xc0, 0x0f},
  303. {DEMOD_WRITE, 0x89, 0x01},
  304. {DEMOD_WRITE, 0x00, 0x00},
  305. {WRITE_DELAY, 0x0a, 0x00},
  306. {DEMOD_WRITE, 0x00, 0x01},
  307. {DEMOD_WRITE, 0x00, 0x00},
  308. {DEMOD_WRITE, 0x9a, 0xb0},
  309. {0xff, 0xaa, 0xff}
  310. };
  311. static int m88rs2000_tab_set(struct m88rs2000_state *state,
  312. struct inittab *tab)
  313. {
  314. int ret = 0;
  315. u8 i;
  316. if (tab == NULL)
  317. return -EINVAL;
  318. for (i = 0; i < 255; i++) {
  319. switch (tab[i].cmd) {
  320. case 0x01:
  321. ret = m88rs2000_writereg(state, tab[i].reg,
  322. tab[i].val);
  323. break;
  324. case 0x10:
  325. if (tab[i].reg > 0)
  326. mdelay(tab[i].reg);
  327. break;
  328. case 0xff:
  329. if (tab[i].reg == 0xaa && tab[i].val == 0xff)
  330. return 0;
  331. case 0x00:
  332. break;
  333. default:
  334. return -EINVAL;
  335. }
  336. if (ret < 0)
  337. return -ENODEV;
  338. }
  339. return 0;
  340. }
  341. static int m88rs2000_set_voltage(struct dvb_frontend *fe,
  342. enum fe_sec_voltage volt)
  343. {
  344. struct m88rs2000_state *state = fe->demodulator_priv;
  345. u8 data;
  346. data = m88rs2000_readreg(state, 0xb2);
  347. data |= 0x03; /* bit0 V/H, bit1 off/on */
  348. switch (volt) {
  349. case SEC_VOLTAGE_18:
  350. data &= ~0x03;
  351. break;
  352. case SEC_VOLTAGE_13:
  353. data &= ~0x03;
  354. data |= 0x01;
  355. break;
  356. case SEC_VOLTAGE_OFF:
  357. break;
  358. }
  359. m88rs2000_writereg(state, 0xb2, data);
  360. return 0;
  361. }
  362. static int m88rs2000_init(struct dvb_frontend *fe)
  363. {
  364. struct m88rs2000_state *state = fe->demodulator_priv;
  365. int ret;
  366. deb_info("m88rs2000: init chip\n");
  367. /* Setup frontend from shutdown/cold */
  368. if (state->config->inittab)
  369. ret = m88rs2000_tab_set(state,
  370. (struct inittab *)state->config->inittab);
  371. else
  372. ret = m88rs2000_tab_set(state, m88rs2000_setup);
  373. return ret;
  374. }
  375. static int m88rs2000_sleep(struct dvb_frontend *fe)
  376. {
  377. struct m88rs2000_state *state = fe->demodulator_priv;
  378. int ret;
  379. /* Shutdown the frondend */
  380. ret = m88rs2000_tab_set(state, m88rs2000_shutdown);
  381. return ret;
  382. }
  383. static int m88rs2000_read_status(struct dvb_frontend *fe,
  384. enum fe_status *status)
  385. {
  386. struct m88rs2000_state *state = fe->demodulator_priv;
  387. u8 reg = m88rs2000_readreg(state, 0x8c);
  388. *status = 0;
  389. if ((reg & 0xee) == 0xee) {
  390. *status = FE_HAS_CARRIER | FE_HAS_SIGNAL | FE_HAS_VITERBI
  391. | FE_HAS_SYNC | FE_HAS_LOCK;
  392. if (state->config->set_ts_params)
  393. state->config->set_ts_params(fe, CALL_IS_READ);
  394. }
  395. return 0;
  396. }
  397. static int m88rs2000_read_ber(struct dvb_frontend *fe, u32 *ber)
  398. {
  399. struct m88rs2000_state *state = fe->demodulator_priv;
  400. u8 tmp0, tmp1;
  401. m88rs2000_writereg(state, 0x9a, 0x30);
  402. tmp0 = m88rs2000_readreg(state, 0xd8);
  403. if ((tmp0 & 0x10) != 0) {
  404. m88rs2000_writereg(state, 0x9a, 0xb0);
  405. *ber = 0xffffffff;
  406. return 0;
  407. }
  408. *ber = (m88rs2000_readreg(state, 0xd7) << 8) |
  409. m88rs2000_readreg(state, 0xd6);
  410. tmp1 = m88rs2000_readreg(state, 0xd9);
  411. m88rs2000_writereg(state, 0xd9, (tmp1 & ~7) | 4);
  412. /* needs twice */
  413. m88rs2000_writereg(state, 0xd8, (tmp0 & ~8) | 0x30);
  414. m88rs2000_writereg(state, 0xd8, (tmp0 & ~8) | 0x30);
  415. m88rs2000_writereg(state, 0x9a, 0xb0);
  416. return 0;
  417. }
  418. static int m88rs2000_read_signal_strength(struct dvb_frontend *fe,
  419. u16 *strength)
  420. {
  421. if (fe->ops.tuner_ops.get_rf_strength)
  422. fe->ops.tuner_ops.get_rf_strength(fe, strength);
  423. return 0;
  424. }
  425. static int m88rs2000_read_snr(struct dvb_frontend *fe, u16 *snr)
  426. {
  427. struct m88rs2000_state *state = fe->demodulator_priv;
  428. *snr = 512 * m88rs2000_readreg(state, 0x65);
  429. return 0;
  430. }
  431. static int m88rs2000_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
  432. {
  433. struct m88rs2000_state *state = fe->demodulator_priv;
  434. u8 tmp;
  435. *ucblocks = (m88rs2000_readreg(state, 0xd5) << 8) |
  436. m88rs2000_readreg(state, 0xd4);
  437. tmp = m88rs2000_readreg(state, 0xd8);
  438. m88rs2000_writereg(state, 0xd8, tmp & ~0x20);
  439. /* needs two times */
  440. m88rs2000_writereg(state, 0xd8, tmp | 0x20);
  441. m88rs2000_writereg(state, 0xd8, tmp | 0x20);
  442. return 0;
  443. }
  444. static int m88rs2000_set_fec(struct m88rs2000_state *state,
  445. enum fe_code_rate fec)
  446. {
  447. u8 fec_set, reg;
  448. int ret;
  449. switch (fec) {
  450. case FEC_1_2:
  451. fec_set = 0x8;
  452. break;
  453. case FEC_2_3:
  454. fec_set = 0x10;
  455. break;
  456. case FEC_3_4:
  457. fec_set = 0x20;
  458. break;
  459. case FEC_5_6:
  460. fec_set = 0x40;
  461. break;
  462. case FEC_7_8:
  463. fec_set = 0x80;
  464. break;
  465. case FEC_AUTO:
  466. default:
  467. fec_set = 0x0;
  468. }
  469. reg = m88rs2000_readreg(state, 0x70);
  470. reg &= 0x7;
  471. ret = m88rs2000_writereg(state, 0x70, reg | fec_set);
  472. ret |= m88rs2000_writereg(state, 0x76, 0x8);
  473. return ret;
  474. }
  475. static enum fe_code_rate m88rs2000_get_fec(struct m88rs2000_state *state)
  476. {
  477. u8 reg;
  478. m88rs2000_writereg(state, 0x9a, 0x30);
  479. reg = m88rs2000_readreg(state, 0x76);
  480. m88rs2000_writereg(state, 0x9a, 0xb0);
  481. reg &= 0xf0;
  482. reg >>= 5;
  483. switch (reg) {
  484. case 0x4:
  485. return FEC_1_2;
  486. case 0x3:
  487. return FEC_2_3;
  488. case 0x2:
  489. return FEC_3_4;
  490. case 0x1:
  491. return FEC_5_6;
  492. case 0x0:
  493. return FEC_7_8;
  494. default:
  495. break;
  496. }
  497. return FEC_AUTO;
  498. }
  499. static int m88rs2000_set_frontend(struct dvb_frontend *fe)
  500. {
  501. struct m88rs2000_state *state = fe->demodulator_priv;
  502. struct dtv_frontend_properties *c = &fe->dtv_property_cache;
  503. enum fe_status status = 0;
  504. int i, ret = 0;
  505. u32 tuner_freq;
  506. s16 offset = 0;
  507. u8 reg;
  508. state->no_lock_count = 0;
  509. if (c->delivery_system != SYS_DVBS) {
  510. deb_info("%s: unsupported delivery system selected (%d)\n",
  511. __func__, c->delivery_system);
  512. return -EOPNOTSUPP;
  513. }
  514. /* Set Tuner */
  515. if (fe->ops.tuner_ops.set_params)
  516. ret = fe->ops.tuner_ops.set_params(fe);
  517. if (ret < 0)
  518. return -ENODEV;
  519. if (fe->ops.tuner_ops.get_frequency) {
  520. ret = fe->ops.tuner_ops.get_frequency(fe, &tuner_freq);
  521. if (ret < 0)
  522. return -ENODEV;
  523. offset = (s16)((s32)tuner_freq - c->frequency);
  524. } else {
  525. offset = 0;
  526. }
  527. /* default mclk value 96.4285 * 2 * 1000 = 192857 */
  528. if (((c->frequency % 192857) >= (192857 - 3000)) ||
  529. (c->frequency % 192857) <= 3000)
  530. ret = m88rs2000_writereg(state, 0x86, 0xc2);
  531. else
  532. ret = m88rs2000_writereg(state, 0x86, 0xc6);
  533. ret |= m88rs2000_set_carrieroffset(fe, offset);
  534. if (ret < 0)
  535. return -ENODEV;
  536. /* Reset demod by symbol rate */
  537. if (c->symbol_rate > 27500000)
  538. ret = m88rs2000_writereg(state, 0xf1, 0xa4);
  539. else
  540. ret = m88rs2000_writereg(state, 0xf1, 0xbf);
  541. ret |= m88rs2000_tab_set(state, fe_reset);
  542. if (ret < 0)
  543. return -ENODEV;
  544. /* Set FEC */
  545. ret = m88rs2000_set_fec(state, c->fec_inner);
  546. ret |= m88rs2000_writereg(state, 0x85, 0x1);
  547. ret |= m88rs2000_writereg(state, 0x8a, 0xbf);
  548. ret |= m88rs2000_writereg(state, 0x8d, 0x1e);
  549. ret |= m88rs2000_writereg(state, 0x90, 0xf1);
  550. ret |= m88rs2000_writereg(state, 0x91, 0x08);
  551. if (ret < 0)
  552. return -ENODEV;
  553. /* Set Symbol Rate */
  554. ret = m88rs2000_set_symbolrate(fe, c->symbol_rate);
  555. if (ret < 0)
  556. return -ENODEV;
  557. /* Set up Demod */
  558. ret = m88rs2000_tab_set(state, fe_trigger);
  559. if (ret < 0)
  560. return -ENODEV;
  561. for (i = 0; i < 25; i++) {
  562. reg = m88rs2000_readreg(state, 0x8c);
  563. if ((reg & 0xee) == 0xee) {
  564. status = FE_HAS_LOCK;
  565. break;
  566. }
  567. state->no_lock_count++;
  568. if (state->no_lock_count == 15) {
  569. reg = m88rs2000_readreg(state, 0x70);
  570. reg ^= 0x4;
  571. m88rs2000_writereg(state, 0x70, reg);
  572. state->no_lock_count = 0;
  573. }
  574. msleep(20);
  575. }
  576. if (status & FE_HAS_LOCK) {
  577. state->fec_inner = m88rs2000_get_fec(state);
  578. /* Unknown suspect SNR level */
  579. reg = m88rs2000_readreg(state, 0x65);
  580. }
  581. state->tuner_frequency = c->frequency;
  582. state->symbol_rate = c->symbol_rate;
  583. return 0;
  584. }
  585. static int m88rs2000_get_frontend(struct dvb_frontend *fe,
  586. struct dtv_frontend_properties *c)
  587. {
  588. struct m88rs2000_state *state = fe->demodulator_priv;
  589. c->fec_inner = state->fec_inner;
  590. c->frequency = state->tuner_frequency;
  591. c->symbol_rate = state->symbol_rate;
  592. return 0;
  593. }
  594. static int m88rs2000_get_tune_settings(struct dvb_frontend *fe,
  595. struct dvb_frontend_tune_settings *tune)
  596. {
  597. struct dtv_frontend_properties *c = &fe->dtv_property_cache;
  598. if (c->symbol_rate > 3000000)
  599. tune->min_delay_ms = 2000;
  600. else
  601. tune->min_delay_ms = 3000;
  602. tune->step_size = c->symbol_rate / 16000;
  603. tune->max_drift = c->symbol_rate / 2000;
  604. return 0;
  605. }
  606. static int m88rs2000_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
  607. {
  608. struct m88rs2000_state *state = fe->demodulator_priv;
  609. if (enable)
  610. m88rs2000_writereg(state, 0x81, 0x84);
  611. else
  612. m88rs2000_writereg(state, 0x81, 0x81);
  613. udelay(10);
  614. return 0;
  615. }
  616. static void m88rs2000_release(struct dvb_frontend *fe)
  617. {
  618. struct m88rs2000_state *state = fe->demodulator_priv;
  619. kfree(state);
  620. }
  621. static const struct dvb_frontend_ops m88rs2000_ops = {
  622. .delsys = { SYS_DVBS },
  623. .info = {
  624. .name = "M88RS2000 DVB-S",
  625. .frequency_min_hz = 950 * MHz,
  626. .frequency_max_hz = 2150 * MHz,
  627. .frequency_stepsize_hz = 1 * MHz,
  628. .frequency_tolerance_hz = 5 * MHz,
  629. .symbol_rate_min = 1000000,
  630. .symbol_rate_max = 45000000,
  631. .symbol_rate_tolerance = 500, /* ppm */
  632. .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
  633. FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
  634. FE_CAN_QPSK | FE_CAN_INVERSION_AUTO |
  635. FE_CAN_FEC_AUTO
  636. },
  637. .release = m88rs2000_release,
  638. .init = m88rs2000_init,
  639. .sleep = m88rs2000_sleep,
  640. .i2c_gate_ctrl = m88rs2000_i2c_gate_ctrl,
  641. .read_status = m88rs2000_read_status,
  642. .read_ber = m88rs2000_read_ber,
  643. .read_signal_strength = m88rs2000_read_signal_strength,
  644. .read_snr = m88rs2000_read_snr,
  645. .read_ucblocks = m88rs2000_read_ucblocks,
  646. .diseqc_send_master_cmd = m88rs2000_send_diseqc_msg,
  647. .diseqc_send_burst = m88rs2000_send_diseqc_burst,
  648. .set_tone = m88rs2000_set_tone,
  649. .set_voltage = m88rs2000_set_voltage,
  650. .set_frontend = m88rs2000_set_frontend,
  651. .get_frontend = m88rs2000_get_frontend,
  652. .get_tune_settings = m88rs2000_get_tune_settings,
  653. };
  654. struct dvb_frontend *m88rs2000_attach(const struct m88rs2000_config *config,
  655. struct i2c_adapter *i2c)
  656. {
  657. struct m88rs2000_state *state = NULL;
  658. /* allocate memory for the internal state */
  659. state = kzalloc(sizeof(struct m88rs2000_state), GFP_KERNEL);
  660. if (state == NULL)
  661. goto error;
  662. /* setup the state */
  663. state->config = config;
  664. state->i2c = i2c;
  665. state->tuner_frequency = 0;
  666. state->symbol_rate = 0;
  667. state->fec_inner = 0;
  668. /* create dvb_frontend */
  669. memcpy(&state->frontend.ops, &m88rs2000_ops,
  670. sizeof(struct dvb_frontend_ops));
  671. state->frontend.demodulator_priv = state;
  672. return &state->frontend;
  673. error:
  674. kfree(state);
  675. return NULL;
  676. }
  677. EXPORT_SYMBOL(m88rs2000_attach);
  678. MODULE_DESCRIPTION("M88RS2000 DVB-S Demodulator driver");
  679. MODULE_AUTHOR("Malcolm Priestley tvboxspy@gmail.com");
  680. MODULE_LICENSE("GPL");
  681. MODULE_VERSION("1.13");