lgs8gl5.c 9.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. Legend Silicon LGS-8GL5 DMB-TH OFDM demodulator driver
  4. Copyright (C) 2008 Sirius International (Hong Kong) Limited
  5. Timothy Lee <timothy.lee@siriushk.com>
  6. */
  7. #include <linux/kernel.h>
  8. #include <linux/init.h>
  9. #include <linux/module.h>
  10. #include <linux/string.h>
  11. #include <linux/slab.h>
  12. #include <media/dvb_frontend.h>
  13. #include "lgs8gl5.h"
  14. #define REG_RESET 0x02
  15. #define REG_RESET_OFF 0x01
  16. #define REG_03 0x03
  17. #define REG_04 0x04
  18. #define REG_07 0x07
  19. #define REG_09 0x09
  20. #define REG_0A 0x0a
  21. #define REG_0B 0x0b
  22. #define REG_0C 0x0c
  23. #define REG_37 0x37
  24. #define REG_STRENGTH 0x4b
  25. #define REG_STRENGTH_MASK 0x7f
  26. #define REG_STRENGTH_CARRIER 0x80
  27. #define REG_INVERSION 0x7c
  28. #define REG_INVERSION_ON 0x80
  29. #define REG_7D 0x7d
  30. #define REG_7E 0x7e
  31. #define REG_A2 0xa2
  32. #define REG_STATUS 0xa4
  33. #define REG_STATUS_SYNC 0x04
  34. #define REG_STATUS_LOCK 0x01
  35. struct lgs8gl5_state {
  36. struct i2c_adapter *i2c;
  37. const struct lgs8gl5_config *config;
  38. struct dvb_frontend frontend;
  39. };
  40. static int debug;
  41. #define dprintk(args...) \
  42. do { \
  43. if (debug) \
  44. printk(KERN_DEBUG "lgs8gl5: " args); \
  45. } while (0)
  46. /* Writes into demod's register */
  47. static int
  48. lgs8gl5_write_reg(struct lgs8gl5_state *state, u8 reg, u8 data)
  49. {
  50. int ret;
  51. u8 buf[] = {reg, data};
  52. struct i2c_msg msg = {
  53. .addr = state->config->demod_address,
  54. .flags = 0,
  55. .buf = buf,
  56. .len = 2
  57. };
  58. ret = i2c_transfer(state->i2c, &msg, 1);
  59. if (ret != 1)
  60. dprintk("%s: error (reg=0x%02x, val=0x%02x, ret=%i)\n",
  61. __func__, reg, data, ret);
  62. return (ret != 1) ? -1 : 0;
  63. }
  64. /* Reads from demod's register */
  65. static int
  66. lgs8gl5_read_reg(struct lgs8gl5_state *state, u8 reg)
  67. {
  68. int ret;
  69. u8 b0[] = {reg};
  70. u8 b1[] = {0};
  71. struct i2c_msg msg[2] = {
  72. {
  73. .addr = state->config->demod_address,
  74. .flags = 0,
  75. .buf = b0,
  76. .len = 1
  77. },
  78. {
  79. .addr = state->config->demod_address,
  80. .flags = I2C_M_RD,
  81. .buf = b1,
  82. .len = 1
  83. }
  84. };
  85. ret = i2c_transfer(state->i2c, msg, 2);
  86. if (ret != 2)
  87. return -EIO;
  88. return b1[0];
  89. }
  90. static int
  91. lgs8gl5_update_reg(struct lgs8gl5_state *state, u8 reg, u8 data)
  92. {
  93. lgs8gl5_read_reg(state, reg);
  94. lgs8gl5_write_reg(state, reg, data);
  95. return 0;
  96. }
  97. /* Writes into alternate device's register */
  98. /* TODO: Find out what that device is for! */
  99. static int
  100. lgs8gl5_update_alt_reg(struct lgs8gl5_state *state, u8 reg, u8 data)
  101. {
  102. int ret;
  103. u8 b0[] = {reg};
  104. u8 b1[] = {0};
  105. u8 b2[] = {reg, data};
  106. struct i2c_msg msg[3] = {
  107. {
  108. .addr = state->config->demod_address + 2,
  109. .flags = 0,
  110. .buf = b0,
  111. .len = 1
  112. },
  113. {
  114. .addr = state->config->demod_address + 2,
  115. .flags = I2C_M_RD,
  116. .buf = b1,
  117. .len = 1
  118. },
  119. {
  120. .addr = state->config->demod_address + 2,
  121. .flags = 0,
  122. .buf = b2,
  123. .len = 2
  124. },
  125. };
  126. ret = i2c_transfer(state->i2c, msg, 3);
  127. return (ret != 3) ? -1 : 0;
  128. }
  129. static void
  130. lgs8gl5_soft_reset(struct lgs8gl5_state *state)
  131. {
  132. u8 val;
  133. dprintk("%s\n", __func__);
  134. val = lgs8gl5_read_reg(state, REG_RESET);
  135. lgs8gl5_write_reg(state, REG_RESET, val & ~REG_RESET_OFF);
  136. lgs8gl5_write_reg(state, REG_RESET, val | REG_RESET_OFF);
  137. msleep(5);
  138. }
  139. /* Starts demodulation */
  140. static void
  141. lgs8gl5_start_demod(struct lgs8gl5_state *state)
  142. {
  143. u8 val;
  144. int n;
  145. dprintk("%s\n", __func__);
  146. lgs8gl5_update_alt_reg(state, 0xc2, 0x28);
  147. lgs8gl5_soft_reset(state);
  148. lgs8gl5_update_reg(state, REG_07, 0x10);
  149. lgs8gl5_update_reg(state, REG_07, 0x10);
  150. lgs8gl5_write_reg(state, REG_09, 0x0e);
  151. lgs8gl5_write_reg(state, REG_0A, 0xe5);
  152. lgs8gl5_write_reg(state, REG_0B, 0x35);
  153. lgs8gl5_write_reg(state, REG_0C, 0x30);
  154. lgs8gl5_update_reg(state, REG_03, 0x00);
  155. lgs8gl5_update_reg(state, REG_7E, 0x01);
  156. lgs8gl5_update_alt_reg(state, 0xc5, 0x00);
  157. lgs8gl5_update_reg(state, REG_04, 0x02);
  158. lgs8gl5_update_reg(state, REG_37, 0x01);
  159. lgs8gl5_soft_reset(state);
  160. /* Wait for carrier */
  161. for (n = 0; n < 10; n++) {
  162. val = lgs8gl5_read_reg(state, REG_STRENGTH);
  163. dprintk("Wait for carrier[%d] 0x%02X\n", n, val);
  164. if (val & REG_STRENGTH_CARRIER)
  165. break;
  166. msleep(4);
  167. }
  168. if (!(val & REG_STRENGTH_CARRIER))
  169. return;
  170. /* Wait for lock */
  171. for (n = 0; n < 20; n++) {
  172. val = lgs8gl5_read_reg(state, REG_STATUS);
  173. dprintk("Wait for lock[%d] 0x%02X\n", n, val);
  174. if (val & REG_STATUS_LOCK)
  175. break;
  176. msleep(12);
  177. }
  178. if (!(val & REG_STATUS_LOCK))
  179. return;
  180. lgs8gl5_write_reg(state, REG_7D, lgs8gl5_read_reg(state, REG_A2));
  181. lgs8gl5_soft_reset(state);
  182. }
  183. static int
  184. lgs8gl5_init(struct dvb_frontend *fe)
  185. {
  186. struct lgs8gl5_state *state = fe->demodulator_priv;
  187. dprintk("%s\n", __func__);
  188. lgs8gl5_update_alt_reg(state, 0xc2, 0x28);
  189. lgs8gl5_soft_reset(state);
  190. lgs8gl5_update_reg(state, REG_07, 0x10);
  191. lgs8gl5_update_reg(state, REG_07, 0x10);
  192. lgs8gl5_write_reg(state, REG_09, 0x0e);
  193. lgs8gl5_write_reg(state, REG_0A, 0xe5);
  194. lgs8gl5_write_reg(state, REG_0B, 0x35);
  195. lgs8gl5_write_reg(state, REG_0C, 0x30);
  196. return 0;
  197. }
  198. static int
  199. lgs8gl5_read_status(struct dvb_frontend *fe, enum fe_status *status)
  200. {
  201. struct lgs8gl5_state *state = fe->demodulator_priv;
  202. u8 level = lgs8gl5_read_reg(state, REG_STRENGTH);
  203. u8 flags = lgs8gl5_read_reg(state, REG_STATUS);
  204. *status = 0;
  205. if ((level & REG_STRENGTH_MASK) > 0)
  206. *status |= FE_HAS_SIGNAL;
  207. if (level & REG_STRENGTH_CARRIER)
  208. *status |= FE_HAS_CARRIER;
  209. if (flags & REG_STATUS_SYNC)
  210. *status |= FE_HAS_SYNC;
  211. if (flags & REG_STATUS_LOCK)
  212. *status |= FE_HAS_LOCK;
  213. return 0;
  214. }
  215. static int
  216. lgs8gl5_read_ber(struct dvb_frontend *fe, u32 *ber)
  217. {
  218. *ber = 0;
  219. return 0;
  220. }
  221. static int
  222. lgs8gl5_read_signal_strength(struct dvb_frontend *fe, u16 *signal_strength)
  223. {
  224. struct lgs8gl5_state *state = fe->demodulator_priv;
  225. u8 level = lgs8gl5_read_reg(state, REG_STRENGTH);
  226. *signal_strength = (level & REG_STRENGTH_MASK) << 8;
  227. return 0;
  228. }
  229. static int
  230. lgs8gl5_read_snr(struct dvb_frontend *fe, u16 *snr)
  231. {
  232. struct lgs8gl5_state *state = fe->demodulator_priv;
  233. u8 level = lgs8gl5_read_reg(state, REG_STRENGTH);
  234. *snr = (level & REG_STRENGTH_MASK) << 8;
  235. return 0;
  236. }
  237. static int
  238. lgs8gl5_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
  239. {
  240. *ucblocks = 0;
  241. return 0;
  242. }
  243. static int
  244. lgs8gl5_set_frontend(struct dvb_frontend *fe)
  245. {
  246. struct dtv_frontend_properties *p = &fe->dtv_property_cache;
  247. struct lgs8gl5_state *state = fe->demodulator_priv;
  248. dprintk("%s\n", __func__);
  249. if (p->bandwidth_hz != 8000000)
  250. return -EINVAL;
  251. if (fe->ops.tuner_ops.set_params) {
  252. fe->ops.tuner_ops.set_params(fe);
  253. if (fe->ops.i2c_gate_ctrl)
  254. fe->ops.i2c_gate_ctrl(fe, 0);
  255. }
  256. /* lgs8gl5_set_inversion(state, p->inversion); */
  257. lgs8gl5_start_demod(state);
  258. return 0;
  259. }
  260. static int
  261. lgs8gl5_get_frontend(struct dvb_frontend *fe,
  262. struct dtv_frontend_properties *p)
  263. {
  264. struct lgs8gl5_state *state = fe->demodulator_priv;
  265. u8 inv = lgs8gl5_read_reg(state, REG_INVERSION);
  266. p->inversion = (inv & REG_INVERSION_ON) ? INVERSION_ON : INVERSION_OFF;
  267. p->code_rate_HP = FEC_1_2;
  268. p->code_rate_LP = FEC_7_8;
  269. p->guard_interval = GUARD_INTERVAL_1_32;
  270. p->transmission_mode = TRANSMISSION_MODE_2K;
  271. p->modulation = QAM_64;
  272. p->hierarchy = HIERARCHY_NONE;
  273. p->bandwidth_hz = 8000000;
  274. return 0;
  275. }
  276. static int
  277. lgs8gl5_get_tune_settings(struct dvb_frontend *fe,
  278. struct dvb_frontend_tune_settings *fesettings)
  279. {
  280. fesettings->min_delay_ms = 240;
  281. fesettings->step_size = 0;
  282. fesettings->max_drift = 0;
  283. return 0;
  284. }
  285. static void
  286. lgs8gl5_release(struct dvb_frontend *fe)
  287. {
  288. struct lgs8gl5_state *state = fe->demodulator_priv;
  289. kfree(state);
  290. }
  291. static const struct dvb_frontend_ops lgs8gl5_ops;
  292. struct dvb_frontend*
  293. lgs8gl5_attach(const struct lgs8gl5_config *config, struct i2c_adapter *i2c)
  294. {
  295. struct lgs8gl5_state *state = NULL;
  296. dprintk("%s\n", __func__);
  297. /* Allocate memory for the internal state */
  298. state = kzalloc(sizeof(struct lgs8gl5_state), GFP_KERNEL);
  299. if (state == NULL)
  300. goto error;
  301. /* Setup the state */
  302. state->config = config;
  303. state->i2c = i2c;
  304. /* Check if the demod is there */
  305. if (lgs8gl5_read_reg(state, REG_RESET) < 0)
  306. goto error;
  307. /* Create dvb_frontend */
  308. memcpy(&state->frontend.ops, &lgs8gl5_ops,
  309. sizeof(struct dvb_frontend_ops));
  310. state->frontend.demodulator_priv = state;
  311. return &state->frontend;
  312. error:
  313. kfree(state);
  314. return NULL;
  315. }
  316. EXPORT_SYMBOL(lgs8gl5_attach);
  317. static const struct dvb_frontend_ops lgs8gl5_ops = {
  318. .delsys = { SYS_DTMB },
  319. .info = {
  320. .name = "Legend Silicon LGS-8GL5 DMB-TH",
  321. .frequency_min_hz = 474 * MHz,
  322. .frequency_max_hz = 858 * MHz,
  323. .frequency_stepsize_hz = 10 * kHz,
  324. .caps = FE_CAN_FEC_AUTO |
  325. FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_32 |
  326. FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
  327. FE_CAN_TRANSMISSION_MODE_AUTO |
  328. FE_CAN_BANDWIDTH_AUTO |
  329. FE_CAN_GUARD_INTERVAL_AUTO |
  330. FE_CAN_HIERARCHY_AUTO |
  331. FE_CAN_RECOVER
  332. },
  333. .release = lgs8gl5_release,
  334. .init = lgs8gl5_init,
  335. .set_frontend = lgs8gl5_set_frontend,
  336. .get_frontend = lgs8gl5_get_frontend,
  337. .get_tune_settings = lgs8gl5_get_tune_settings,
  338. .read_status = lgs8gl5_read_status,
  339. .read_ber = lgs8gl5_read_ber,
  340. .read_signal_strength = lgs8gl5_read_signal_strength,
  341. .read_snr = lgs8gl5_read_snr,
  342. .read_ucblocks = lgs8gl5_read_ucblocks,
  343. };
  344. module_param(debug, int, 0644);
  345. MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
  346. MODULE_DESCRIPTION("Legend Silicon LGS-8GL5 DMB-TH Demodulator driver");
  347. MODULE_AUTHOR("Timothy Lee");
  348. MODULE_LICENSE("GPL");