drxd_hard.c 74 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286228722882289229022912292229322942295229622972298229923002301230223032304230523062307230823092310231123122313231423152316231723182319232023212322232323242325232623272328232923302331233223332334233523362337233823392340234123422343234423452346234723482349235023512352235323542355235623572358235923602361236223632364236523662367236823692370237123722373237423752376237723782379238023812382238323842385238623872388238923902391239223932394239523962397239823992400240124022403240424052406240724082409241024112412241324142415241624172418241924202421242224232424242524262427242824292430243124322433243424352436243724382439244024412442244324442445244624472448244924502451245224532454245524562457245824592460246124622463246424652466246724682469247024712472247324742475247624772478247924802481248224832484248524862487248824892490249124922493249424952496249724982499250025012502250325042505250625072508250925102511251225132514251525162517251825192520252125222523252425252526252725282529253025312532253325342535253625372538253925402541254225432544254525462547254825492550255125522553255425552556255725582559256025612562256325642565256625672568256925702571257225732574257525762577257825792580258125822583258425852586258725882589259025912592259325942595259625972598259926002601260226032604260526062607260826092610261126122613261426152616261726182619262026212622262326242625262626272628262926302631263226332634263526362637263826392640264126422643264426452646264726482649265026512652265326542655265626572658265926602661266226632664266526662667266826692670267126722673267426752676267726782679268026812682268326842685268626872688268926902691269226932694269526962697269826992700270127022703270427052706270727082709271027112712271327142715271627172718271927202721272227232724272527262727272827292730273127322733273427352736273727382739274027412742274327442745274627472748274927502751275227532754275527562757275827592760276127622763276427652766276727682769277027712772277327742775277627772778277927802781278227832784278527862787278827892790279127922793279427952796279727982799280028012802280328042805280628072808280928102811281228132814281528162817281828192820282128222823282428252826282728282829283028312832283328342835283628372838283928402841284228432844284528462847284828492850285128522853285428552856285728582859286028612862286328642865286628672868286928702871287228732874287528762877287828792880288128822883288428852886288728882889289028912892289328942895289628972898289929002901290229032904290529062907290829092910291129122913291429152916291729182919292029212922292329242925292629272928292929302931293229332934293529362937293829392940294129422943294429452946294729482949295029512952295329542955
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * drxd_hard.c: DVB-T Demodulator Micronas DRX3975D-A2,DRX397xD-B1
  4. *
  5. * Copyright (C) 2003-2007 Micronas
  6. */
  7. #include <linux/kernel.h>
  8. #include <linux/module.h>
  9. #include <linux/moduleparam.h>
  10. #include <linux/init.h>
  11. #include <linux/delay.h>
  12. #include <linux/firmware.h>
  13. #include <linux/i2c.h>
  14. #include <asm/div64.h>
  15. #include <media/dvb_frontend.h>
  16. #include "drxd.h"
  17. #include "drxd_firm.h"
  18. #define DRX_FW_FILENAME_A2 "drxd-a2-1.1.fw"
  19. #define DRX_FW_FILENAME_B1 "drxd-b1-1.1.fw"
  20. #define CHUNK_SIZE 48
  21. #define DRX_I2C_RMW 0x10
  22. #define DRX_I2C_BROADCAST 0x20
  23. #define DRX_I2C_CLEARCRC 0x80
  24. #define DRX_I2C_SINGLE_MASTER 0xC0
  25. #define DRX_I2C_MODEFLAGS 0xC0
  26. #define DRX_I2C_FLAGS 0xF0
  27. #define DEFAULT_LOCK_TIMEOUT 1100
  28. #define DRX_CHANNEL_AUTO 0
  29. #define DRX_CHANNEL_HIGH 1
  30. #define DRX_CHANNEL_LOW 2
  31. #define DRX_LOCK_MPEG 1
  32. #define DRX_LOCK_FEC 2
  33. #define DRX_LOCK_DEMOD 4
  34. /****************************************************************************/
  35. enum CSCDState {
  36. CSCD_INIT = 0,
  37. CSCD_SET,
  38. CSCD_SAVED
  39. };
  40. enum CDrxdState {
  41. DRXD_UNINITIALIZED = 0,
  42. DRXD_STOPPED,
  43. DRXD_STARTED
  44. };
  45. enum AGC_CTRL_MODE {
  46. AGC_CTRL_AUTO = 0,
  47. AGC_CTRL_USER,
  48. AGC_CTRL_OFF
  49. };
  50. enum OperationMode {
  51. OM_Default,
  52. OM_DVBT_Diversity_Front,
  53. OM_DVBT_Diversity_End
  54. };
  55. struct SCfgAgc {
  56. enum AGC_CTRL_MODE ctrlMode;
  57. u16 outputLevel; /* range [0, ... , 1023], 1/n of fullscale range */
  58. u16 settleLevel; /* range [0, ... , 1023], 1/n of fullscale range */
  59. u16 minOutputLevel; /* range [0, ... , 1023], 1/n of fullscale range */
  60. u16 maxOutputLevel; /* range [0, ... , 1023], 1/n of fullscale range */
  61. u16 speed; /* range [0, ... , 1023], 1/n of fullscale range */
  62. u16 R1;
  63. u16 R2;
  64. u16 R3;
  65. };
  66. struct SNoiseCal {
  67. int cpOpt;
  68. short cpNexpOfs;
  69. short tdCal2k;
  70. short tdCal8k;
  71. };
  72. enum app_env {
  73. APPENV_STATIC = 0,
  74. APPENV_PORTABLE = 1,
  75. APPENV_MOBILE = 2
  76. };
  77. enum EIFFilter {
  78. IFFILTER_SAW = 0,
  79. IFFILTER_DISCRETE = 1
  80. };
  81. struct drxd_state {
  82. struct dvb_frontend frontend;
  83. struct dvb_frontend_ops ops;
  84. struct dtv_frontend_properties props;
  85. const struct firmware *fw;
  86. struct device *dev;
  87. struct i2c_adapter *i2c;
  88. void *priv;
  89. struct drxd_config config;
  90. int i2c_access;
  91. int init_done;
  92. struct mutex mutex;
  93. u8 chip_adr;
  94. u16 hi_cfg_timing_div;
  95. u16 hi_cfg_bridge_delay;
  96. u16 hi_cfg_wakeup_key;
  97. u16 hi_cfg_ctrl;
  98. u16 intermediate_freq;
  99. u16 osc_clock_freq;
  100. enum CSCDState cscd_state;
  101. enum CDrxdState drxd_state;
  102. u16 sys_clock_freq;
  103. s16 osc_clock_deviation;
  104. u16 expected_sys_clock_freq;
  105. u16 insert_rs_byte;
  106. u16 enable_parallel;
  107. int operation_mode;
  108. struct SCfgAgc if_agc_cfg;
  109. struct SCfgAgc rf_agc_cfg;
  110. struct SNoiseCal noise_cal;
  111. u32 fe_fs_add_incr;
  112. u32 org_fe_fs_add_incr;
  113. u16 current_fe_if_incr;
  114. u16 m_FeAgRegAgPwd;
  115. u16 m_FeAgRegAgAgcSio;
  116. u16 m_EcOcRegOcModeLop;
  117. u16 m_EcOcRegSncSncLvl;
  118. u8 *m_InitAtomicRead;
  119. u8 *m_HiI2cPatch;
  120. u8 *m_ResetCEFR;
  121. u8 *m_InitFE_1;
  122. u8 *m_InitFE_2;
  123. u8 *m_InitCP;
  124. u8 *m_InitCE;
  125. u8 *m_InitEQ;
  126. u8 *m_InitSC;
  127. u8 *m_InitEC;
  128. u8 *m_ResetECRAM;
  129. u8 *m_InitDiversityFront;
  130. u8 *m_InitDiversityEnd;
  131. u8 *m_DisableDiversity;
  132. u8 *m_StartDiversityFront;
  133. u8 *m_StartDiversityEnd;
  134. u8 *m_DiversityDelay8MHZ;
  135. u8 *m_DiversityDelay6MHZ;
  136. u8 *microcode;
  137. u32 microcode_length;
  138. int type_A;
  139. int PGA;
  140. int diversity;
  141. int tuner_mirrors;
  142. enum app_env app_env_default;
  143. enum app_env app_env_diversity;
  144. };
  145. /****************************************************************************/
  146. /* I2C **********************************************************************/
  147. /****************************************************************************/
  148. static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 * data, int len)
  149. {
  150. struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = data, .len = len };
  151. if (i2c_transfer(adap, &msg, 1) != 1)
  152. return -1;
  153. return 0;
  154. }
  155. static int i2c_read(struct i2c_adapter *adap,
  156. u8 adr, u8 *msg, int len, u8 *answ, int alen)
  157. {
  158. struct i2c_msg msgs[2] = {
  159. {
  160. .addr = adr, .flags = 0,
  161. .buf = msg, .len = len
  162. }, {
  163. .addr = adr, .flags = I2C_M_RD,
  164. .buf = answ, .len = alen
  165. }
  166. };
  167. if (i2c_transfer(adap, msgs, 2) != 2)
  168. return -1;
  169. return 0;
  170. }
  171. static inline u32 MulDiv32(u32 a, u32 b, u32 c)
  172. {
  173. u64 tmp64;
  174. tmp64 = (u64)a * (u64)b;
  175. do_div(tmp64, c);
  176. return (u32) tmp64;
  177. }
  178. static int Read16(struct drxd_state *state, u32 reg, u16 *data, u8 flags)
  179. {
  180. u8 adr = state->config.demod_address;
  181. u8 mm1[4] = { reg & 0xff, (reg >> 16) & 0xff,
  182. flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff
  183. };
  184. u8 mm2[2];
  185. if (i2c_read(state->i2c, adr, mm1, 4, mm2, 2) < 0)
  186. return -1;
  187. if (data)
  188. *data = mm2[0] | (mm2[1] << 8);
  189. return mm2[0] | (mm2[1] << 8);
  190. }
  191. static int Read32(struct drxd_state *state, u32 reg, u32 *data, u8 flags)
  192. {
  193. u8 adr = state->config.demod_address;
  194. u8 mm1[4] = { reg & 0xff, (reg >> 16) & 0xff,
  195. flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff
  196. };
  197. u8 mm2[4];
  198. if (i2c_read(state->i2c, adr, mm1, 4, mm2, 4) < 0)
  199. return -1;
  200. if (data)
  201. *data =
  202. mm2[0] | (mm2[1] << 8) | (mm2[2] << 16) | (mm2[3] << 24);
  203. return 0;
  204. }
  205. static int Write16(struct drxd_state *state, u32 reg, u16 data, u8 flags)
  206. {
  207. u8 adr = state->config.demod_address;
  208. u8 mm[6] = { reg & 0xff, (reg >> 16) & 0xff,
  209. flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff,
  210. data & 0xff, (data >> 8) & 0xff
  211. };
  212. if (i2c_write(state->i2c, adr, mm, 6) < 0)
  213. return -1;
  214. return 0;
  215. }
  216. static int Write32(struct drxd_state *state, u32 reg, u32 data, u8 flags)
  217. {
  218. u8 adr = state->config.demod_address;
  219. u8 mm[8] = { reg & 0xff, (reg >> 16) & 0xff,
  220. flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff,
  221. data & 0xff, (data >> 8) & 0xff,
  222. (data >> 16) & 0xff, (data >> 24) & 0xff
  223. };
  224. if (i2c_write(state->i2c, adr, mm, 8) < 0)
  225. return -1;
  226. return 0;
  227. }
  228. static int write_chunk(struct drxd_state *state,
  229. u32 reg, u8 *data, u32 len, u8 flags)
  230. {
  231. u8 adr = state->config.demod_address;
  232. u8 mm[CHUNK_SIZE + 4] = { reg & 0xff, (reg >> 16) & 0xff,
  233. flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff
  234. };
  235. int i;
  236. for (i = 0; i < len; i++)
  237. mm[4 + i] = data[i];
  238. if (i2c_write(state->i2c, adr, mm, 4 + len) < 0) {
  239. printk(KERN_ERR "error in write_chunk\n");
  240. return -1;
  241. }
  242. return 0;
  243. }
  244. static int WriteBlock(struct drxd_state *state,
  245. u32 Address, u16 BlockSize, u8 *pBlock, u8 Flags)
  246. {
  247. while (BlockSize > 0) {
  248. u16 Chunk = BlockSize > CHUNK_SIZE ? CHUNK_SIZE : BlockSize;
  249. if (write_chunk(state, Address, pBlock, Chunk, Flags) < 0)
  250. return -1;
  251. pBlock += Chunk;
  252. Address += (Chunk >> 1);
  253. BlockSize -= Chunk;
  254. }
  255. return 0;
  256. }
  257. static int WriteTable(struct drxd_state *state, u8 * pTable)
  258. {
  259. int status = 0;
  260. if (!pTable)
  261. return 0;
  262. while (!status) {
  263. u16 Length;
  264. u32 Address = pTable[0] | (pTable[1] << 8) |
  265. (pTable[2] << 16) | (pTable[3] << 24);
  266. if (Address == 0xFFFFFFFF)
  267. break;
  268. pTable += sizeof(u32);
  269. Length = pTable[0] | (pTable[1] << 8);
  270. pTable += sizeof(u16);
  271. if (!Length)
  272. break;
  273. status = WriteBlock(state, Address, Length * 2, pTable, 0);
  274. pTable += (Length * 2);
  275. }
  276. return status;
  277. }
  278. /****************************************************************************/
  279. /****************************************************************************/
  280. /****************************************************************************/
  281. static int ResetCEFR(struct drxd_state *state)
  282. {
  283. return WriteTable(state, state->m_ResetCEFR);
  284. }
  285. static int InitCP(struct drxd_state *state)
  286. {
  287. return WriteTable(state, state->m_InitCP);
  288. }
  289. static int InitCE(struct drxd_state *state)
  290. {
  291. int status;
  292. enum app_env AppEnv = state->app_env_default;
  293. do {
  294. status = WriteTable(state, state->m_InitCE);
  295. if (status < 0)
  296. break;
  297. if (state->operation_mode == OM_DVBT_Diversity_Front ||
  298. state->operation_mode == OM_DVBT_Diversity_End) {
  299. AppEnv = state->app_env_diversity;
  300. }
  301. if (AppEnv == APPENV_STATIC) {
  302. status = Write16(state, CE_REG_TAPSET__A, 0x0000, 0);
  303. if (status < 0)
  304. break;
  305. } else if (AppEnv == APPENV_PORTABLE) {
  306. status = Write16(state, CE_REG_TAPSET__A, 0x0001, 0);
  307. if (status < 0)
  308. break;
  309. } else if (AppEnv == APPENV_MOBILE && state->type_A) {
  310. status = Write16(state, CE_REG_TAPSET__A, 0x0002, 0);
  311. if (status < 0)
  312. break;
  313. } else if (AppEnv == APPENV_MOBILE && !state->type_A) {
  314. status = Write16(state, CE_REG_TAPSET__A, 0x0006, 0);
  315. if (status < 0)
  316. break;
  317. }
  318. /* start ce */
  319. status = Write16(state, B_CE_REG_COMM_EXEC__A, 0x0001, 0);
  320. if (status < 0)
  321. break;
  322. } while (0);
  323. return status;
  324. }
  325. static int StopOC(struct drxd_state *state)
  326. {
  327. int status = 0;
  328. u16 ocSyncLvl = 0;
  329. u16 ocModeLop = state->m_EcOcRegOcModeLop;
  330. u16 dtoIncLop = 0;
  331. u16 dtoIncHip = 0;
  332. do {
  333. /* Store output configuration */
  334. status = Read16(state, EC_OC_REG_SNC_ISC_LVL__A, &ocSyncLvl, 0);
  335. if (status < 0)
  336. break;
  337. /* CHK_ERROR(Read16(EC_OC_REG_OC_MODE_LOP__A, &ocModeLop)); */
  338. state->m_EcOcRegSncSncLvl = ocSyncLvl;
  339. /* m_EcOcRegOcModeLop = ocModeLop; */
  340. /* Flush FIFO (byte-boundary) at fixed rate */
  341. status = Read16(state, EC_OC_REG_RCN_MAP_LOP__A, &dtoIncLop, 0);
  342. if (status < 0)
  343. break;
  344. status = Read16(state, EC_OC_REG_RCN_MAP_HIP__A, &dtoIncHip, 0);
  345. if (status < 0)
  346. break;
  347. status = Write16(state, EC_OC_REG_DTO_INC_LOP__A, dtoIncLop, 0);
  348. if (status < 0)
  349. break;
  350. status = Write16(state, EC_OC_REG_DTO_INC_HIP__A, dtoIncHip, 0);
  351. if (status < 0)
  352. break;
  353. ocModeLop &= ~(EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M);
  354. ocModeLop |= EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC;
  355. status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0);
  356. if (status < 0)
  357. break;
  358. status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0);
  359. if (status < 0)
  360. break;
  361. msleep(1);
  362. /* Output pins to '0' */
  363. status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS__M, 0);
  364. if (status < 0)
  365. break;
  366. /* Force the OC out of sync */
  367. ocSyncLvl &= ~(EC_OC_REG_SNC_ISC_LVL_OSC__M);
  368. status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, ocSyncLvl, 0);
  369. if (status < 0)
  370. break;
  371. ocModeLop &= ~(EC_OC_REG_OC_MODE_LOP_PAR_ENA__M);
  372. ocModeLop |= EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE;
  373. ocModeLop |= 0x2; /* Magically-out-of-sync */
  374. status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0);
  375. if (status < 0)
  376. break;
  377. status = Write16(state, EC_OC_REG_COMM_INT_STA__A, 0x0, 0);
  378. if (status < 0)
  379. break;
  380. status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0);
  381. if (status < 0)
  382. break;
  383. } while (0);
  384. return status;
  385. }
  386. static int StartOC(struct drxd_state *state)
  387. {
  388. int status = 0;
  389. do {
  390. /* Stop OC */
  391. status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0);
  392. if (status < 0)
  393. break;
  394. /* Restore output configuration */
  395. status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, state->m_EcOcRegSncSncLvl, 0);
  396. if (status < 0)
  397. break;
  398. status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, state->m_EcOcRegOcModeLop, 0);
  399. if (status < 0)
  400. break;
  401. /* Output pins active again */
  402. status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS_INIT, 0);
  403. if (status < 0)
  404. break;
  405. /* Start OC */
  406. status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0);
  407. if (status < 0)
  408. break;
  409. } while (0);
  410. return status;
  411. }
  412. static int InitEQ(struct drxd_state *state)
  413. {
  414. return WriteTable(state, state->m_InitEQ);
  415. }
  416. static int InitEC(struct drxd_state *state)
  417. {
  418. return WriteTable(state, state->m_InitEC);
  419. }
  420. static int InitSC(struct drxd_state *state)
  421. {
  422. return WriteTable(state, state->m_InitSC);
  423. }
  424. static int InitAtomicRead(struct drxd_state *state)
  425. {
  426. return WriteTable(state, state->m_InitAtomicRead);
  427. }
  428. static int CorrectSysClockDeviation(struct drxd_state *state);
  429. static int DRX_GetLockStatus(struct drxd_state *state, u32 * pLockStatus)
  430. {
  431. u16 ScRaRamLock = 0;
  432. const u16 mpeg_lock_mask = (SC_RA_RAM_LOCK_MPEG__M |
  433. SC_RA_RAM_LOCK_FEC__M |
  434. SC_RA_RAM_LOCK_DEMOD__M);
  435. const u16 fec_lock_mask = (SC_RA_RAM_LOCK_FEC__M |
  436. SC_RA_RAM_LOCK_DEMOD__M);
  437. const u16 demod_lock_mask = SC_RA_RAM_LOCK_DEMOD__M;
  438. int status;
  439. *pLockStatus = 0;
  440. status = Read16(state, SC_RA_RAM_LOCK__A, &ScRaRamLock, 0x0000);
  441. if (status < 0) {
  442. printk(KERN_ERR "Can't read SC_RA_RAM_LOCK__A status = %08x\n", status);
  443. return status;
  444. }
  445. if (state->drxd_state != DRXD_STARTED)
  446. return 0;
  447. if ((ScRaRamLock & mpeg_lock_mask) == mpeg_lock_mask) {
  448. *pLockStatus |= DRX_LOCK_MPEG;
  449. CorrectSysClockDeviation(state);
  450. }
  451. if ((ScRaRamLock & fec_lock_mask) == fec_lock_mask)
  452. *pLockStatus |= DRX_LOCK_FEC;
  453. if ((ScRaRamLock & demod_lock_mask) == demod_lock_mask)
  454. *pLockStatus |= DRX_LOCK_DEMOD;
  455. return 0;
  456. }
  457. /****************************************************************************/
  458. static int SetCfgIfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
  459. {
  460. int status;
  461. if (cfg->outputLevel > DRXD_FE_CTRL_MAX)
  462. return -1;
  463. if (cfg->ctrlMode == AGC_CTRL_USER) {
  464. do {
  465. u16 FeAgRegPm1AgcWri;
  466. u16 FeAgRegAgModeLop;
  467. status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0);
  468. if (status < 0)
  469. break;
  470. FeAgRegAgModeLop &= (~FE_AG_REG_AG_MODE_LOP_MODE_4__M);
  471. FeAgRegAgModeLop |= FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC;
  472. status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0);
  473. if (status < 0)
  474. break;
  475. FeAgRegPm1AgcWri = (u16) (cfg->outputLevel &
  476. FE_AG_REG_PM1_AGC_WRI__M);
  477. status = Write16(state, FE_AG_REG_PM1_AGC_WRI__A, FeAgRegPm1AgcWri, 0);
  478. if (status < 0)
  479. break;
  480. } while (0);
  481. } else if (cfg->ctrlMode == AGC_CTRL_AUTO) {
  482. if (((cfg->maxOutputLevel) < (cfg->minOutputLevel)) ||
  483. ((cfg->maxOutputLevel) > DRXD_FE_CTRL_MAX) ||
  484. ((cfg->speed) > DRXD_FE_CTRL_MAX) ||
  485. ((cfg->settleLevel) > DRXD_FE_CTRL_MAX)
  486. )
  487. return -1;
  488. do {
  489. u16 FeAgRegAgModeLop;
  490. u16 FeAgRegEgcSetLvl;
  491. u16 slope, offset;
  492. /* == Mode == */
  493. status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0);
  494. if (status < 0)
  495. break;
  496. FeAgRegAgModeLop &= (~FE_AG_REG_AG_MODE_LOP_MODE_4__M);
  497. FeAgRegAgModeLop |=
  498. FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC;
  499. status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0);
  500. if (status < 0)
  501. break;
  502. /* == Settle level == */
  503. FeAgRegEgcSetLvl = (u16) ((cfg->settleLevel >> 1) &
  504. FE_AG_REG_EGC_SET_LVL__M);
  505. status = Write16(state, FE_AG_REG_EGC_SET_LVL__A, FeAgRegEgcSetLvl, 0);
  506. if (status < 0)
  507. break;
  508. /* == Min/Max == */
  509. slope = (u16) ((cfg->maxOutputLevel -
  510. cfg->minOutputLevel) / 2);
  511. offset = (u16) ((cfg->maxOutputLevel +
  512. cfg->minOutputLevel) / 2 - 511);
  513. status = Write16(state, FE_AG_REG_GC1_AGC_RIC__A, slope, 0);
  514. if (status < 0)
  515. break;
  516. status = Write16(state, FE_AG_REG_GC1_AGC_OFF__A, offset, 0);
  517. if (status < 0)
  518. break;
  519. /* == Speed == */
  520. {
  521. const u16 maxRur = 8;
  522. static const u16 slowIncrDecLUT[] = {
  523. 3, 4, 4, 5, 6 };
  524. static const u16 fastIncrDecLUT[] = {
  525. 14, 15, 15, 16,
  526. 17, 18, 18, 19,
  527. 20, 21, 22, 23,
  528. 24, 26, 27, 28,
  529. 29, 31
  530. };
  531. u16 fineSteps = (DRXD_FE_CTRL_MAX + 1) /
  532. (maxRur + 1);
  533. u16 fineSpeed = (u16) (cfg->speed -
  534. ((cfg->speed /
  535. fineSteps) *
  536. fineSteps));
  537. u16 invRurCount = (u16) (cfg->speed /
  538. fineSteps);
  539. u16 rurCount;
  540. if (invRurCount > maxRur) {
  541. rurCount = 0;
  542. fineSpeed += fineSteps;
  543. } else {
  544. rurCount = maxRur - invRurCount;
  545. }
  546. /*
  547. fastInc = default *
  548. (2^(fineSpeed/fineSteps))
  549. => range[default...2*default>
  550. slowInc = default *
  551. (2^(fineSpeed/fineSteps))
  552. */
  553. {
  554. u16 fastIncrDec =
  555. fastIncrDecLUT[fineSpeed /
  556. ((fineSteps /
  557. (14 + 1)) + 1)];
  558. u16 slowIncrDec =
  559. slowIncrDecLUT[fineSpeed /
  560. (fineSteps /
  561. (3 + 1))];
  562. status = Write16(state, FE_AG_REG_EGC_RUR_CNT__A, rurCount, 0);
  563. if (status < 0)
  564. break;
  565. status = Write16(state, FE_AG_REG_EGC_FAS_INC__A, fastIncrDec, 0);
  566. if (status < 0)
  567. break;
  568. status = Write16(state, FE_AG_REG_EGC_FAS_DEC__A, fastIncrDec, 0);
  569. if (status < 0)
  570. break;
  571. status = Write16(state, FE_AG_REG_EGC_SLO_INC__A, slowIncrDec, 0);
  572. if (status < 0)
  573. break;
  574. status = Write16(state, FE_AG_REG_EGC_SLO_DEC__A, slowIncrDec, 0);
  575. if (status < 0)
  576. break;
  577. }
  578. }
  579. } while (0);
  580. } else {
  581. /* No OFF mode for IF control */
  582. return -1;
  583. }
  584. return status;
  585. }
  586. static int SetCfgRfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
  587. {
  588. int status = 0;
  589. if (cfg->outputLevel > DRXD_FE_CTRL_MAX)
  590. return -1;
  591. if (cfg->ctrlMode == AGC_CTRL_USER) {
  592. do {
  593. u16 AgModeLop = 0;
  594. u16 level = (cfg->outputLevel);
  595. if (level == DRXD_FE_CTRL_MAX)
  596. level++;
  597. status = Write16(state, FE_AG_REG_PM2_AGC_WRI__A, level, 0x0000);
  598. if (status < 0)
  599. break;
  600. /*==== Mode ====*/
  601. /* Powerdown PD2, WRI source */
  602. state->m_FeAgRegAgPwd &= ~(FE_AG_REG_AG_PWD_PWD_PD2__M);
  603. state->m_FeAgRegAgPwd |=
  604. FE_AG_REG_AG_PWD_PWD_PD2_DISABLE;
  605. status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000);
  606. if (status < 0)
  607. break;
  608. status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
  609. if (status < 0)
  610. break;
  611. AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M |
  612. FE_AG_REG_AG_MODE_LOP_MODE_E__M));
  613. AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC |
  614. FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC);
  615. status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
  616. if (status < 0)
  617. break;
  618. /* enable AGC2 pin */
  619. {
  620. u16 FeAgRegAgAgcSio = 0;
  621. status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
  622. if (status < 0)
  623. break;
  624. FeAgRegAgAgcSio &=
  625. ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M);
  626. FeAgRegAgAgcSio |=
  627. FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT;
  628. status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
  629. if (status < 0)
  630. break;
  631. }
  632. } while (0);
  633. } else if (cfg->ctrlMode == AGC_CTRL_AUTO) {
  634. u16 AgModeLop = 0;
  635. do {
  636. u16 level;
  637. /* Automatic control */
  638. /* Powerup PD2, AGC2 as output, TGC source */
  639. (state->m_FeAgRegAgPwd) &=
  640. ~(FE_AG_REG_AG_PWD_PWD_PD2__M);
  641. (state->m_FeAgRegAgPwd) |=
  642. FE_AG_REG_AG_PWD_PWD_PD2_DISABLE;
  643. status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000);
  644. if (status < 0)
  645. break;
  646. status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
  647. if (status < 0)
  648. break;
  649. AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M |
  650. FE_AG_REG_AG_MODE_LOP_MODE_E__M));
  651. AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC |
  652. FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC);
  653. status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
  654. if (status < 0)
  655. break;
  656. /* Settle level */
  657. level = (((cfg->settleLevel) >> 4) &
  658. FE_AG_REG_TGC_SET_LVL__M);
  659. status = Write16(state, FE_AG_REG_TGC_SET_LVL__A, level, 0x0000);
  660. if (status < 0)
  661. break;
  662. /* Min/max: don't care */
  663. /* Speed: TODO */
  664. /* enable AGC2 pin */
  665. {
  666. u16 FeAgRegAgAgcSio = 0;
  667. status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
  668. if (status < 0)
  669. break;
  670. FeAgRegAgAgcSio &=
  671. ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M);
  672. FeAgRegAgAgcSio |=
  673. FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT;
  674. status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
  675. if (status < 0)
  676. break;
  677. }
  678. } while (0);
  679. } else {
  680. u16 AgModeLop = 0;
  681. do {
  682. /* No RF AGC control */
  683. /* Powerdown PD2, AGC2 as output, WRI source */
  684. (state->m_FeAgRegAgPwd) &=
  685. ~(FE_AG_REG_AG_PWD_PWD_PD2__M);
  686. (state->m_FeAgRegAgPwd) |=
  687. FE_AG_REG_AG_PWD_PWD_PD2_ENABLE;
  688. status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000);
  689. if (status < 0)
  690. break;
  691. status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
  692. if (status < 0)
  693. break;
  694. AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M |
  695. FE_AG_REG_AG_MODE_LOP_MODE_E__M));
  696. AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC |
  697. FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC);
  698. status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
  699. if (status < 0)
  700. break;
  701. /* set FeAgRegAgAgcSio AGC2 (RF) as input */
  702. {
  703. u16 FeAgRegAgAgcSio = 0;
  704. status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
  705. if (status < 0)
  706. break;
  707. FeAgRegAgAgcSio &=
  708. ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M);
  709. FeAgRegAgAgcSio |=
  710. FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT;
  711. status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
  712. if (status < 0)
  713. break;
  714. }
  715. } while (0);
  716. }
  717. return status;
  718. }
  719. static int ReadIFAgc(struct drxd_state *state, u32 * pValue)
  720. {
  721. int status = 0;
  722. *pValue = 0;
  723. if (state->if_agc_cfg.ctrlMode != AGC_CTRL_OFF) {
  724. u16 Value;
  725. status = Read16(state, FE_AG_REG_GC1_AGC_DAT__A, &Value, 0);
  726. Value &= FE_AG_REG_GC1_AGC_DAT__M;
  727. if (status >= 0) {
  728. /* 3.3V
  729. |
  730. R1
  731. |
  732. Vin - R3 - * -- Vout
  733. |
  734. R2
  735. |
  736. GND
  737. */
  738. u32 R1 = state->if_agc_cfg.R1;
  739. u32 R2 = state->if_agc_cfg.R2;
  740. u32 R3 = state->if_agc_cfg.R3;
  741. u32 Vmax, Rpar, Vmin, Vout;
  742. if (R2 == 0 && (R1 == 0 || R3 == 0))
  743. return 0;
  744. Vmax = (3300 * R2) / (R1 + R2);
  745. Rpar = (R2 * R3) / (R3 + R2);
  746. Vmin = (3300 * Rpar) / (R1 + Rpar);
  747. Vout = Vmin + ((Vmax - Vmin) * Value) / 1024;
  748. *pValue = Vout;
  749. }
  750. }
  751. return status;
  752. }
  753. static int load_firmware(struct drxd_state *state, const char *fw_name)
  754. {
  755. const struct firmware *fw;
  756. if (request_firmware(&fw, fw_name, state->dev) < 0) {
  757. printk(KERN_ERR "drxd: firmware load failure [%s]\n", fw_name);
  758. return -EIO;
  759. }
  760. state->microcode = kmemdup(fw->data, fw->size, GFP_KERNEL);
  761. if (!state->microcode) {
  762. release_firmware(fw);
  763. return -ENOMEM;
  764. }
  765. state->microcode_length = fw->size;
  766. release_firmware(fw);
  767. return 0;
  768. }
  769. static int DownloadMicrocode(struct drxd_state *state,
  770. const u8 *pMCImage, u32 Length)
  771. {
  772. u8 *pSrc;
  773. u32 Address;
  774. u16 nBlocks;
  775. u16 BlockSize;
  776. u32 offset = 0;
  777. int i, status = 0;
  778. pSrc = (u8 *) pMCImage;
  779. /* We're not using Flags */
  780. /* Flags = (pSrc[0] << 8) | pSrc[1]; */
  781. pSrc += sizeof(u16);
  782. offset += sizeof(u16);
  783. nBlocks = (pSrc[0] << 8) | pSrc[1];
  784. pSrc += sizeof(u16);
  785. offset += sizeof(u16);
  786. for (i = 0; i < nBlocks; i++) {
  787. Address = (pSrc[0] << 24) | (pSrc[1] << 16) |
  788. (pSrc[2] << 8) | pSrc[3];
  789. pSrc += sizeof(u32);
  790. offset += sizeof(u32);
  791. BlockSize = ((pSrc[0] << 8) | pSrc[1]) * sizeof(u16);
  792. pSrc += sizeof(u16);
  793. offset += sizeof(u16);
  794. /* We're not using Flags */
  795. /* u16 Flags = (pSrc[0] << 8) | pSrc[1]; */
  796. pSrc += sizeof(u16);
  797. offset += sizeof(u16);
  798. /* We're not using BlockCRC */
  799. /* u16 BlockCRC = (pSrc[0] << 8) | pSrc[1]; */
  800. pSrc += sizeof(u16);
  801. offset += sizeof(u16);
  802. status = WriteBlock(state, Address, BlockSize,
  803. pSrc, DRX_I2C_CLEARCRC);
  804. if (status < 0)
  805. break;
  806. pSrc += BlockSize;
  807. offset += BlockSize;
  808. }
  809. return status;
  810. }
  811. static int HI_Command(struct drxd_state *state, u16 cmd, u16 * pResult)
  812. {
  813. u32 nrRetries = 0;
  814. int status;
  815. status = Write16(state, HI_RA_RAM_SRV_CMD__A, cmd, 0);
  816. if (status < 0)
  817. return status;
  818. do {
  819. nrRetries += 1;
  820. if (nrRetries > DRXD_MAX_RETRIES) {
  821. status = -1;
  822. break;
  823. }
  824. status = Read16(state, HI_RA_RAM_SRV_CMD__A, NULL, 0);
  825. } while (status != 0);
  826. if (status >= 0)
  827. status = Read16(state, HI_RA_RAM_SRV_RES__A, pResult, 0);
  828. return status;
  829. }
  830. static int HI_CfgCommand(struct drxd_state *state)
  831. {
  832. int status = 0;
  833. mutex_lock(&state->mutex);
  834. Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, HI_RA_RAM_SRV_RST_KEY_ACT, 0);
  835. Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, state->hi_cfg_timing_div, 0);
  836. Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, state->hi_cfg_bridge_delay, 0);
  837. Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, state->hi_cfg_wakeup_key, 0);
  838. Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, state->hi_cfg_ctrl, 0);
  839. Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, HI_RA_RAM_SRV_RST_KEY_ACT, 0);
  840. if ((state->hi_cfg_ctrl & HI_RA_RAM_SRV_CFG_ACT_PWD_EXE) ==
  841. HI_RA_RAM_SRV_CFG_ACT_PWD_EXE)
  842. status = Write16(state, HI_RA_RAM_SRV_CMD__A,
  843. HI_RA_RAM_SRV_CMD_CONFIG, 0);
  844. else
  845. status = HI_Command(state, HI_RA_RAM_SRV_CMD_CONFIG, NULL);
  846. mutex_unlock(&state->mutex);
  847. return status;
  848. }
  849. static int InitHI(struct drxd_state *state)
  850. {
  851. state->hi_cfg_wakeup_key = (state->chip_adr);
  852. /* port/bridge/power down ctrl */
  853. state->hi_cfg_ctrl = HI_RA_RAM_SRV_CFG_ACT_SLV0_ON;
  854. return HI_CfgCommand(state);
  855. }
  856. static int HI_ResetCommand(struct drxd_state *state)
  857. {
  858. int status;
  859. mutex_lock(&state->mutex);
  860. status = Write16(state, HI_RA_RAM_SRV_RST_KEY__A,
  861. HI_RA_RAM_SRV_RST_KEY_ACT, 0);
  862. if (status == 0)
  863. status = HI_Command(state, HI_RA_RAM_SRV_CMD_RESET, NULL);
  864. mutex_unlock(&state->mutex);
  865. msleep(1);
  866. return status;
  867. }
  868. static int DRX_ConfigureI2CBridge(struct drxd_state *state, int bEnableBridge)
  869. {
  870. state->hi_cfg_ctrl &= (~HI_RA_RAM_SRV_CFG_ACT_BRD__M);
  871. if (bEnableBridge)
  872. state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_ON;
  873. else
  874. state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_OFF;
  875. return HI_CfgCommand(state);
  876. }
  877. #define HI_TR_WRITE 0x9
  878. #define HI_TR_READ 0xA
  879. #define HI_TR_READ_WRITE 0xB
  880. #define HI_TR_BROADCAST 0x4
  881. #if 0
  882. static int AtomicReadBlock(struct drxd_state *state,
  883. u32 Addr, u16 DataSize, u8 *pData, u8 Flags)
  884. {
  885. int status;
  886. int i = 0;
  887. /* Parameter check */
  888. if ((!pData) || ((DataSize & 1) != 0))
  889. return -1;
  890. mutex_lock(&state->mutex);
  891. do {
  892. /* Instruct HI to read n bytes */
  893. /* TODO use proper names forthese egisters */
  894. status = Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, (HI_TR_FUNC_ADDR & 0xFFFF), 0);
  895. if (status < 0)
  896. break;
  897. status = Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, (u16) (Addr >> 16), 0);
  898. if (status < 0)
  899. break;
  900. status = Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, (u16) (Addr & 0xFFFF), 0);
  901. if (status < 0)
  902. break;
  903. status = Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, (u16) ((DataSize / 2) - 1), 0);
  904. if (status < 0)
  905. break;
  906. status = Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, HI_TR_READ, 0);
  907. if (status < 0)
  908. break;
  909. status = HI_Command(state, HI_RA_RAM_SRV_CMD_EXECUTE, 0);
  910. if (status < 0)
  911. break;
  912. } while (0);
  913. if (status >= 0) {
  914. for (i = 0; i < (DataSize / 2); i += 1) {
  915. u16 word;
  916. status = Read16(state, (HI_RA_RAM_USR_BEGIN__A + i),
  917. &word, 0);
  918. if (status < 0)
  919. break;
  920. pData[2 * i] = (u8) (word & 0xFF);
  921. pData[(2 * i) + 1] = (u8) (word >> 8);
  922. }
  923. }
  924. mutex_unlock(&state->mutex);
  925. return status;
  926. }
  927. static int AtomicReadReg32(struct drxd_state *state,
  928. u32 Addr, u32 *pData, u8 Flags)
  929. {
  930. u8 buf[sizeof(u32)];
  931. int status;
  932. if (!pData)
  933. return -1;
  934. status = AtomicReadBlock(state, Addr, sizeof(u32), buf, Flags);
  935. *pData = (((u32) buf[0]) << 0) +
  936. (((u32) buf[1]) << 8) +
  937. (((u32) buf[2]) << 16) + (((u32) buf[3]) << 24);
  938. return status;
  939. }
  940. #endif
  941. static int StopAllProcessors(struct drxd_state *state)
  942. {
  943. return Write16(state, HI_COMM_EXEC__A,
  944. SC_COMM_EXEC_CTL_STOP, DRX_I2C_BROADCAST);
  945. }
  946. static int EnableAndResetMB(struct drxd_state *state)
  947. {
  948. if (state->type_A) {
  949. /* disable? monitor bus observe @ EC_OC */
  950. Write16(state, EC_OC_REG_OC_MON_SIO__A, 0x0000, 0x0000);
  951. }
  952. /* do inverse broadcast, followed by explicit write to HI */
  953. Write16(state, HI_COMM_MB__A, 0x0000, DRX_I2C_BROADCAST);
  954. Write16(state, HI_COMM_MB__A, 0x0000, 0x0000);
  955. return 0;
  956. }
  957. static int InitCC(struct drxd_state *state)
  958. {
  959. int status = 0;
  960. if (state->osc_clock_freq == 0 ||
  961. state->osc_clock_freq > 20000 ||
  962. (state->osc_clock_freq % 4000) != 0) {
  963. printk(KERN_ERR "invalid osc frequency %d\n", state->osc_clock_freq);
  964. return -1;
  965. }
  966. status |= Write16(state, CC_REG_OSC_MODE__A, CC_REG_OSC_MODE_M20, 0);
  967. status |= Write16(state, CC_REG_PLL_MODE__A,
  968. CC_REG_PLL_MODE_BYPASS_PLL |
  969. CC_REG_PLL_MODE_PUMP_CUR_12, 0);
  970. status |= Write16(state, CC_REG_REF_DIVIDE__A,
  971. state->osc_clock_freq / 4000, 0);
  972. status |= Write16(state, CC_REG_PWD_MODE__A, CC_REG_PWD_MODE_DOWN_PLL,
  973. 0);
  974. status |= Write16(state, CC_REG_UPDATE__A, CC_REG_UPDATE_KEY, 0);
  975. return status;
  976. }
  977. static int ResetECOD(struct drxd_state *state)
  978. {
  979. int status = 0;
  980. if (state->type_A)
  981. status = Write16(state, EC_OD_REG_SYNC__A, 0x0664, 0);
  982. else
  983. status = Write16(state, B_EC_OD_REG_SYNC__A, 0x0664, 0);
  984. if (!(status < 0))
  985. status = WriteTable(state, state->m_ResetECRAM);
  986. if (!(status < 0))
  987. status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0001, 0);
  988. return status;
  989. }
  990. /* Configure PGA switch */
  991. static int SetCfgPga(struct drxd_state *state, int pgaSwitch)
  992. {
  993. int status;
  994. u16 AgModeLop = 0;
  995. u16 AgModeHip = 0;
  996. do {
  997. if (pgaSwitch) {
  998. /* PGA on */
  999. /* fine gain */
  1000. status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
  1001. if (status < 0)
  1002. break;
  1003. AgModeLop &= (~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M));
  1004. AgModeLop |= B_FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC;
  1005. status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
  1006. if (status < 0)
  1007. break;
  1008. /* coarse gain */
  1009. status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000);
  1010. if (status < 0)
  1011. break;
  1012. AgModeHip &= (~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M));
  1013. AgModeHip |= B_FE_AG_REG_AG_MODE_HIP_MODE_J_DYNAMIC;
  1014. status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000);
  1015. if (status < 0)
  1016. break;
  1017. /* enable fine and coarse gain, enable AAF,
  1018. no ext resistor */
  1019. status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN, 0x0000);
  1020. if (status < 0)
  1021. break;
  1022. } else {
  1023. /* PGA off, bypass */
  1024. /* fine gain */
  1025. status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
  1026. if (status < 0)
  1027. break;
  1028. AgModeLop &= (~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M));
  1029. AgModeLop |= B_FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC;
  1030. status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
  1031. if (status < 0)
  1032. break;
  1033. /* coarse gain */
  1034. status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000);
  1035. if (status < 0)
  1036. break;
  1037. AgModeHip &= (~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M));
  1038. AgModeHip |= B_FE_AG_REG_AG_MODE_HIP_MODE_J_STATIC;
  1039. status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000);
  1040. if (status < 0)
  1041. break;
  1042. /* disable fine and coarse gain, enable AAF,
  1043. no ext resistor */
  1044. status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0x0000);
  1045. if (status < 0)
  1046. break;
  1047. }
  1048. } while (0);
  1049. return status;
  1050. }
  1051. static int InitFE(struct drxd_state *state)
  1052. {
  1053. int status;
  1054. do {
  1055. status = WriteTable(state, state->m_InitFE_1);
  1056. if (status < 0)
  1057. break;
  1058. if (state->type_A) {
  1059. status = Write16(state, FE_AG_REG_AG_PGA_MODE__A,
  1060. FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN,
  1061. 0);
  1062. } else {
  1063. if (state->PGA)
  1064. status = SetCfgPga(state, 0);
  1065. else
  1066. status =
  1067. Write16(state, B_FE_AG_REG_AG_PGA_MODE__A,
  1068. B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN,
  1069. 0);
  1070. }
  1071. if (status < 0)
  1072. break;
  1073. status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, state->m_FeAgRegAgAgcSio, 0x0000);
  1074. if (status < 0)
  1075. break;
  1076. status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000);
  1077. if (status < 0)
  1078. break;
  1079. status = WriteTable(state, state->m_InitFE_2);
  1080. if (status < 0)
  1081. break;
  1082. } while (0);
  1083. return status;
  1084. }
  1085. static int InitFT(struct drxd_state *state)
  1086. {
  1087. /*
  1088. norm OFFSET, MB says =2 voor 8K en =3 voor 2K waarschijnlijk
  1089. SC stuff
  1090. */
  1091. return Write16(state, FT_REG_COMM_EXEC__A, 0x0001, 0x0000);
  1092. }
  1093. static int SC_WaitForReady(struct drxd_state *state)
  1094. {
  1095. int i;
  1096. for (i = 0; i < DRXD_MAX_RETRIES; i += 1) {
  1097. int status = Read16(state, SC_RA_RAM_CMD__A, NULL, 0);
  1098. if (status == 0)
  1099. return status;
  1100. }
  1101. return -1;
  1102. }
  1103. static int SC_SendCommand(struct drxd_state *state, u16 cmd)
  1104. {
  1105. int status = 0, ret;
  1106. u16 errCode;
  1107. status = Write16(state, SC_RA_RAM_CMD__A, cmd, 0);
  1108. if (status < 0)
  1109. return status;
  1110. SC_WaitForReady(state);
  1111. ret = Read16(state, SC_RA_RAM_CMD_ADDR__A, &errCode, 0);
  1112. if (ret < 0 || errCode == 0xFFFF) {
  1113. printk(KERN_ERR "Command Error\n");
  1114. status = -1;
  1115. }
  1116. return status;
  1117. }
  1118. static int SC_ProcStartCommand(struct drxd_state *state,
  1119. u16 subCmd, u16 param0, u16 param1)
  1120. {
  1121. int ret, status = 0;
  1122. u16 scExec;
  1123. mutex_lock(&state->mutex);
  1124. do {
  1125. ret = Read16(state, SC_COMM_EXEC__A, &scExec, 0);
  1126. if (ret < 0 || scExec != 1) {
  1127. status = -1;
  1128. break;
  1129. }
  1130. SC_WaitForReady(state);
  1131. status |= Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0);
  1132. status |= Write16(state, SC_RA_RAM_PARAM1__A, param1, 0);
  1133. status |= Write16(state, SC_RA_RAM_PARAM0__A, param0, 0);
  1134. SC_SendCommand(state, SC_RA_RAM_CMD_PROC_START);
  1135. } while (0);
  1136. mutex_unlock(&state->mutex);
  1137. return status;
  1138. }
  1139. static int SC_SetPrefParamCommand(struct drxd_state *state,
  1140. u16 subCmd, u16 param0, u16 param1)
  1141. {
  1142. int status;
  1143. mutex_lock(&state->mutex);
  1144. do {
  1145. status = SC_WaitForReady(state);
  1146. if (status < 0)
  1147. break;
  1148. status = Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0);
  1149. if (status < 0)
  1150. break;
  1151. status = Write16(state, SC_RA_RAM_PARAM1__A, param1, 0);
  1152. if (status < 0)
  1153. break;
  1154. status = Write16(state, SC_RA_RAM_PARAM0__A, param0, 0);
  1155. if (status < 0)
  1156. break;
  1157. status = SC_SendCommand(state, SC_RA_RAM_CMD_SET_PREF_PARAM);
  1158. if (status < 0)
  1159. break;
  1160. } while (0);
  1161. mutex_unlock(&state->mutex);
  1162. return status;
  1163. }
  1164. #if 0
  1165. static int SC_GetOpParamCommand(struct drxd_state *state, u16 * result)
  1166. {
  1167. int status = 0;
  1168. mutex_lock(&state->mutex);
  1169. do {
  1170. status = SC_WaitForReady(state);
  1171. if (status < 0)
  1172. break;
  1173. status = SC_SendCommand(state, SC_RA_RAM_CMD_GET_OP_PARAM);
  1174. if (status < 0)
  1175. break;
  1176. status = Read16(state, SC_RA_RAM_PARAM0__A, result, 0);
  1177. if (status < 0)
  1178. break;
  1179. } while (0);
  1180. mutex_unlock(&state->mutex);
  1181. return status;
  1182. }
  1183. #endif
  1184. static int ConfigureMPEGOutput(struct drxd_state *state, int bEnableOutput)
  1185. {
  1186. int status;
  1187. do {
  1188. u16 EcOcRegIprInvMpg = 0;
  1189. u16 EcOcRegOcModeLop = 0;
  1190. u16 EcOcRegOcModeHip = 0;
  1191. u16 EcOcRegOcMpgSio = 0;
  1192. /*CHK_ERROR(Read16(state, EC_OC_REG_OC_MODE_LOP__A, &EcOcRegOcModeLop, 0)); */
  1193. if (state->operation_mode == OM_DVBT_Diversity_Front) {
  1194. if (bEnableOutput) {
  1195. EcOcRegOcModeHip |=
  1196. B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR;
  1197. } else
  1198. EcOcRegOcMpgSio |= EC_OC_REG_OC_MPG_SIO__M;
  1199. EcOcRegOcModeLop |=
  1200. EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE;
  1201. } else {
  1202. EcOcRegOcModeLop = state->m_EcOcRegOcModeLop;
  1203. if (bEnableOutput)
  1204. EcOcRegOcMpgSio &= (~(EC_OC_REG_OC_MPG_SIO__M));
  1205. else
  1206. EcOcRegOcMpgSio |= EC_OC_REG_OC_MPG_SIO__M;
  1207. /* Don't Insert RS Byte */
  1208. if (state->insert_rs_byte) {
  1209. EcOcRegOcModeLop &=
  1210. (~(EC_OC_REG_OC_MODE_LOP_PAR_ENA__M));
  1211. EcOcRegOcModeHip &=
  1212. (~EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M);
  1213. EcOcRegOcModeHip |=
  1214. EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_ENABLE;
  1215. } else {
  1216. EcOcRegOcModeLop |=
  1217. EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE;
  1218. EcOcRegOcModeHip &=
  1219. (~EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M);
  1220. EcOcRegOcModeHip |=
  1221. EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_DISABLE;
  1222. }
  1223. /* Mode = Parallel */
  1224. if (state->enable_parallel)
  1225. EcOcRegOcModeLop &=
  1226. (~(EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__M));
  1227. else
  1228. EcOcRegOcModeLop |=
  1229. EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_SERIAL;
  1230. }
  1231. /* Invert Data */
  1232. /* EcOcRegIprInvMpg |= 0x00FF; */
  1233. EcOcRegIprInvMpg &= (~(0x00FF));
  1234. /* Invert Error ( we don't use the pin ) */
  1235. /* EcOcRegIprInvMpg |= 0x0100; */
  1236. EcOcRegIprInvMpg &= (~(0x0100));
  1237. /* Invert Start ( we don't use the pin ) */
  1238. /* EcOcRegIprInvMpg |= 0x0200; */
  1239. EcOcRegIprInvMpg &= (~(0x0200));
  1240. /* Invert Valid ( we don't use the pin ) */
  1241. /* EcOcRegIprInvMpg |= 0x0400; */
  1242. EcOcRegIprInvMpg &= (~(0x0400));
  1243. /* Invert Clock */
  1244. /* EcOcRegIprInvMpg |= 0x0800; */
  1245. EcOcRegIprInvMpg &= (~(0x0800));
  1246. /* EcOcRegOcModeLop =0x05; */
  1247. status = Write16(state, EC_OC_REG_IPR_INV_MPG__A, EcOcRegIprInvMpg, 0);
  1248. if (status < 0)
  1249. break;
  1250. status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, EcOcRegOcModeLop, 0);
  1251. if (status < 0)
  1252. break;
  1253. status = Write16(state, EC_OC_REG_OC_MODE_HIP__A, EcOcRegOcModeHip, 0x0000);
  1254. if (status < 0)
  1255. break;
  1256. status = Write16(state, EC_OC_REG_OC_MPG_SIO__A, EcOcRegOcMpgSio, 0);
  1257. if (status < 0)
  1258. break;
  1259. } while (0);
  1260. return status;
  1261. }
  1262. static int SetDeviceTypeId(struct drxd_state *state)
  1263. {
  1264. int status = 0;
  1265. u16 deviceId = 0;
  1266. do {
  1267. status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0);
  1268. if (status < 0)
  1269. break;
  1270. /* TODO: why twice? */
  1271. status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0);
  1272. if (status < 0)
  1273. break;
  1274. printk(KERN_INFO "drxd: deviceId = %04x\n", deviceId);
  1275. state->type_A = 0;
  1276. state->PGA = 0;
  1277. state->diversity = 0;
  1278. if (deviceId == 0) { /* on A2 only 3975 available */
  1279. state->type_A = 1;
  1280. printk(KERN_INFO "DRX3975D-A2\n");
  1281. } else {
  1282. deviceId >>= 12;
  1283. printk(KERN_INFO "DRX397%dD-B1\n", deviceId);
  1284. switch (deviceId) {
  1285. case 4:
  1286. state->diversity = 1;
  1287. fallthrough;
  1288. case 3:
  1289. case 7:
  1290. state->PGA = 1;
  1291. break;
  1292. case 6:
  1293. state->diversity = 1;
  1294. fallthrough;
  1295. case 5:
  1296. case 8:
  1297. break;
  1298. default:
  1299. status = -1;
  1300. break;
  1301. }
  1302. }
  1303. } while (0);
  1304. if (status < 0)
  1305. return status;
  1306. /* Init Table selection */
  1307. state->m_InitAtomicRead = DRXD_InitAtomicRead;
  1308. state->m_InitSC = DRXD_InitSC;
  1309. state->m_ResetECRAM = DRXD_ResetECRAM;
  1310. if (state->type_A) {
  1311. state->m_ResetCEFR = DRXD_ResetCEFR;
  1312. state->m_InitFE_1 = DRXD_InitFEA2_1;
  1313. state->m_InitFE_2 = DRXD_InitFEA2_2;
  1314. state->m_InitCP = DRXD_InitCPA2;
  1315. state->m_InitCE = DRXD_InitCEA2;
  1316. state->m_InitEQ = DRXD_InitEQA2;
  1317. state->m_InitEC = DRXD_InitECA2;
  1318. if (load_firmware(state, DRX_FW_FILENAME_A2))
  1319. return -EIO;
  1320. } else {
  1321. state->m_ResetCEFR = NULL;
  1322. state->m_InitFE_1 = DRXD_InitFEB1_1;
  1323. state->m_InitFE_2 = DRXD_InitFEB1_2;
  1324. state->m_InitCP = DRXD_InitCPB1;
  1325. state->m_InitCE = DRXD_InitCEB1;
  1326. state->m_InitEQ = DRXD_InitEQB1;
  1327. state->m_InitEC = DRXD_InitECB1;
  1328. if (load_firmware(state, DRX_FW_FILENAME_B1))
  1329. return -EIO;
  1330. }
  1331. if (state->diversity) {
  1332. state->m_InitDiversityFront = DRXD_InitDiversityFront;
  1333. state->m_InitDiversityEnd = DRXD_InitDiversityEnd;
  1334. state->m_DisableDiversity = DRXD_DisableDiversity;
  1335. state->m_StartDiversityFront = DRXD_StartDiversityFront;
  1336. state->m_StartDiversityEnd = DRXD_StartDiversityEnd;
  1337. state->m_DiversityDelay8MHZ = DRXD_DiversityDelay8MHZ;
  1338. state->m_DiversityDelay6MHZ = DRXD_DiversityDelay6MHZ;
  1339. } else {
  1340. state->m_InitDiversityFront = NULL;
  1341. state->m_InitDiversityEnd = NULL;
  1342. state->m_DisableDiversity = NULL;
  1343. state->m_StartDiversityFront = NULL;
  1344. state->m_StartDiversityEnd = NULL;
  1345. state->m_DiversityDelay8MHZ = NULL;
  1346. state->m_DiversityDelay6MHZ = NULL;
  1347. }
  1348. return status;
  1349. }
  1350. static int CorrectSysClockDeviation(struct drxd_state *state)
  1351. {
  1352. int status;
  1353. s32 incr = 0;
  1354. s32 nomincr = 0;
  1355. u32 bandwidth = 0;
  1356. u32 sysClockInHz = 0;
  1357. u32 sysClockFreq = 0; /* in kHz */
  1358. s16 oscClockDeviation;
  1359. s16 Diff;
  1360. do {
  1361. /* Retrieve bandwidth and incr, sanity check */
  1362. /* These accesses should be AtomicReadReg32, but that
  1363. causes trouble (at least for diversity */
  1364. status = Read32(state, LC_RA_RAM_IFINCR_NOM_L__A, ((u32 *) &nomincr), 0);
  1365. if (status < 0)
  1366. break;
  1367. status = Read32(state, FE_IF_REG_INCR0__A, (u32 *) &incr, 0);
  1368. if (status < 0)
  1369. break;
  1370. if (state->type_A) {
  1371. if ((nomincr - incr < -500) || (nomincr - incr > 500))
  1372. break;
  1373. } else {
  1374. if ((nomincr - incr < -2000) || (nomincr - incr > 2000))
  1375. break;
  1376. }
  1377. switch (state->props.bandwidth_hz) {
  1378. case 8000000:
  1379. bandwidth = DRXD_BANDWIDTH_8MHZ_IN_HZ;
  1380. break;
  1381. case 7000000:
  1382. bandwidth = DRXD_BANDWIDTH_7MHZ_IN_HZ;
  1383. break;
  1384. case 6000000:
  1385. bandwidth = DRXD_BANDWIDTH_6MHZ_IN_HZ;
  1386. break;
  1387. default:
  1388. return -1;
  1389. break;
  1390. }
  1391. /* Compute new sysclock value
  1392. sysClockFreq = (((incr + 2^23)*bandwidth)/2^21)/1000 */
  1393. incr += (1 << 23);
  1394. sysClockInHz = MulDiv32(incr, bandwidth, 1 << 21);
  1395. sysClockFreq = (u32) (sysClockInHz / 1000);
  1396. /* rounding */
  1397. if ((sysClockInHz % 1000) > 500)
  1398. sysClockFreq++;
  1399. /* Compute clock deviation in ppm */
  1400. oscClockDeviation = (u16) ((((s32) (sysClockFreq) -
  1401. (s32)
  1402. (state->expected_sys_clock_freq)) *
  1403. 1000000L) /
  1404. (s32)
  1405. (state->expected_sys_clock_freq));
  1406. Diff = oscClockDeviation - state->osc_clock_deviation;
  1407. /*printk(KERN_INFO "sysclockdiff=%d\n", Diff); */
  1408. if (Diff >= -200 && Diff <= 200) {
  1409. state->sys_clock_freq = (u16) sysClockFreq;
  1410. if (oscClockDeviation != state->osc_clock_deviation) {
  1411. if (state->config.osc_deviation) {
  1412. state->config.osc_deviation(state->priv,
  1413. oscClockDeviation,
  1414. 1);
  1415. state->osc_clock_deviation =
  1416. oscClockDeviation;
  1417. }
  1418. }
  1419. /* switch OFF SRMM scan in SC */
  1420. status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DONT_SCAN, 0);
  1421. if (status < 0)
  1422. break;
  1423. /* overrule FE_IF internal value for
  1424. proper re-locking */
  1425. status = Write16(state, SC_RA_RAM_IF_SAVE__AX, state->current_fe_if_incr, 0);
  1426. if (status < 0)
  1427. break;
  1428. state->cscd_state = CSCD_SAVED;
  1429. }
  1430. } while (0);
  1431. return status;
  1432. }
  1433. static int DRX_Stop(struct drxd_state *state)
  1434. {
  1435. int status;
  1436. if (state->drxd_state != DRXD_STARTED)
  1437. return 0;
  1438. do {
  1439. if (state->cscd_state != CSCD_SAVED) {
  1440. u32 lock;
  1441. status = DRX_GetLockStatus(state, &lock);
  1442. if (status < 0)
  1443. break;
  1444. }
  1445. status = StopOC(state);
  1446. if (status < 0)
  1447. break;
  1448. state->drxd_state = DRXD_STOPPED;
  1449. status = ConfigureMPEGOutput(state, 0);
  1450. if (status < 0)
  1451. break;
  1452. if (state->type_A) {
  1453. /* Stop relevant processors off the device */
  1454. status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0x0000);
  1455. if (status < 0)
  1456. break;
  1457. status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
  1458. if (status < 0)
  1459. break;
  1460. status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
  1461. if (status < 0)
  1462. break;
  1463. } else {
  1464. /* Stop all processors except HI & CC & FE */
  1465. status = Write16(state, B_SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
  1466. if (status < 0)
  1467. break;
  1468. status = Write16(state, B_LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
  1469. if (status < 0)
  1470. break;
  1471. status = Write16(state, B_FT_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
  1472. if (status < 0)
  1473. break;
  1474. status = Write16(state, B_CP_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
  1475. if (status < 0)
  1476. break;
  1477. status = Write16(state, B_CE_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
  1478. if (status < 0)
  1479. break;
  1480. status = Write16(state, B_EQ_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
  1481. if (status < 0)
  1482. break;
  1483. status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0);
  1484. if (status < 0)
  1485. break;
  1486. }
  1487. } while (0);
  1488. return status;
  1489. }
  1490. #if 0 /* Currently unused */
  1491. static int SetOperationMode(struct drxd_state *state, int oMode)
  1492. {
  1493. int status;
  1494. do {
  1495. if (state->drxd_state != DRXD_STOPPED) {
  1496. status = -1;
  1497. break;
  1498. }
  1499. if (oMode == state->operation_mode) {
  1500. status = 0;
  1501. break;
  1502. }
  1503. if (oMode != OM_Default && !state->diversity) {
  1504. status = -1;
  1505. break;
  1506. }
  1507. switch (oMode) {
  1508. case OM_DVBT_Diversity_Front:
  1509. status = WriteTable(state, state->m_InitDiversityFront);
  1510. break;
  1511. case OM_DVBT_Diversity_End:
  1512. status = WriteTable(state, state->m_InitDiversityEnd);
  1513. break;
  1514. case OM_Default:
  1515. /* We need to check how to
  1516. get DRXD out of diversity */
  1517. default:
  1518. status = WriteTable(state, state->m_DisableDiversity);
  1519. break;
  1520. }
  1521. } while (0);
  1522. if (!status)
  1523. state->operation_mode = oMode;
  1524. return status;
  1525. }
  1526. #endif
  1527. static int StartDiversity(struct drxd_state *state)
  1528. {
  1529. int status = 0;
  1530. u16 rcControl;
  1531. do {
  1532. if (state->operation_mode == OM_DVBT_Diversity_Front) {
  1533. status = WriteTable(state, state->m_StartDiversityFront);
  1534. if (status < 0)
  1535. break;
  1536. } else if (state->operation_mode == OM_DVBT_Diversity_End) {
  1537. status = WriteTable(state, state->m_StartDiversityEnd);
  1538. if (status < 0)
  1539. break;
  1540. if (state->props.bandwidth_hz == 8000000) {
  1541. status = WriteTable(state, state->m_DiversityDelay8MHZ);
  1542. if (status < 0)
  1543. break;
  1544. } else {
  1545. status = WriteTable(state, state->m_DiversityDelay6MHZ);
  1546. if (status < 0)
  1547. break;
  1548. }
  1549. status = Read16(state, B_EQ_REG_RC_SEL_CAR__A, &rcControl, 0);
  1550. if (status < 0)
  1551. break;
  1552. rcControl &= ~(B_EQ_REG_RC_SEL_CAR_FFTMODE__M);
  1553. rcControl |= B_EQ_REG_RC_SEL_CAR_DIV_ON |
  1554. /* combining enabled */
  1555. B_EQ_REG_RC_SEL_CAR_MEAS_A_CC |
  1556. B_EQ_REG_RC_SEL_CAR_PASS_A_CC |
  1557. B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC;
  1558. status = Write16(state, B_EQ_REG_RC_SEL_CAR__A, rcControl, 0);
  1559. if (status < 0)
  1560. break;
  1561. }
  1562. } while (0);
  1563. return status;
  1564. }
  1565. static int SetFrequencyShift(struct drxd_state *state,
  1566. u32 offsetFreq, int channelMirrored)
  1567. {
  1568. int negativeShift = (state->tuner_mirrors == channelMirrored);
  1569. /* Handle all mirroring
  1570. *
  1571. * Note: ADC mirroring (aliasing) is implictly handled by limiting
  1572. * feFsRegAddInc to 28 bits below
  1573. * (if the result before masking is more than 28 bits, this means
  1574. * that the ADC is mirroring.
  1575. * The masking is in fact the aliasing of the ADC)
  1576. *
  1577. */
  1578. /* Compute register value, unsigned computation */
  1579. state->fe_fs_add_incr = MulDiv32(state->intermediate_freq +
  1580. offsetFreq,
  1581. 1 << 28, state->sys_clock_freq);
  1582. /* Remove integer part */
  1583. state->fe_fs_add_incr &= 0x0FFFFFFFL;
  1584. if (negativeShift)
  1585. state->fe_fs_add_incr = ((1 << 28) - state->fe_fs_add_incr);
  1586. /* Save the frequency shift without tunerOffset compensation
  1587. for CtrlGetChannel. */
  1588. state->org_fe_fs_add_incr = MulDiv32(state->intermediate_freq,
  1589. 1 << 28, state->sys_clock_freq);
  1590. /* Remove integer part */
  1591. state->org_fe_fs_add_incr &= 0x0FFFFFFFL;
  1592. if (negativeShift)
  1593. state->org_fe_fs_add_incr = ((1L << 28) -
  1594. state->org_fe_fs_add_incr);
  1595. return Write32(state, FE_FS_REG_ADD_INC_LOP__A,
  1596. state->fe_fs_add_incr, 0);
  1597. }
  1598. static int SetCfgNoiseCalibration(struct drxd_state *state,
  1599. struct SNoiseCal *noiseCal)
  1600. {
  1601. u16 beOptEna;
  1602. int status = 0;
  1603. do {
  1604. status = Read16(state, SC_RA_RAM_BE_OPT_ENA__A, &beOptEna, 0);
  1605. if (status < 0)
  1606. break;
  1607. if (noiseCal->cpOpt) {
  1608. beOptEna |= (1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT);
  1609. } else {
  1610. beOptEna &= ~(1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT);
  1611. status = Write16(state, CP_REG_AC_NEXP_OFFS__A, noiseCal->cpNexpOfs, 0);
  1612. if (status < 0)
  1613. break;
  1614. }
  1615. status = Write16(state, SC_RA_RAM_BE_OPT_ENA__A, beOptEna, 0);
  1616. if (status < 0)
  1617. break;
  1618. if (!state->type_A) {
  1619. status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_2K__A, noiseCal->tdCal2k, 0);
  1620. if (status < 0)
  1621. break;
  1622. status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_8K__A, noiseCal->tdCal8k, 0);
  1623. if (status < 0)
  1624. break;
  1625. }
  1626. } while (0);
  1627. return status;
  1628. }
  1629. static int DRX_Start(struct drxd_state *state, s32 off)
  1630. {
  1631. struct dtv_frontend_properties *p = &state->props;
  1632. int status;
  1633. u16 transmissionParams = 0;
  1634. u16 operationMode = 0;
  1635. u16 qpskTdTpsPwr = 0;
  1636. u16 qam16TdTpsPwr = 0;
  1637. u16 qam64TdTpsPwr = 0;
  1638. u32 feIfIncr = 0;
  1639. u32 bandwidth = 0;
  1640. int mirrorFreqSpect;
  1641. u16 qpskSnCeGain = 0;
  1642. u16 qam16SnCeGain = 0;
  1643. u16 qam64SnCeGain = 0;
  1644. u16 qpskIsGainMan = 0;
  1645. u16 qam16IsGainMan = 0;
  1646. u16 qam64IsGainMan = 0;
  1647. u16 qpskIsGainExp = 0;
  1648. u16 qam16IsGainExp = 0;
  1649. u16 qam64IsGainExp = 0;
  1650. u16 bandwidthParam = 0;
  1651. if (off < 0)
  1652. off = (off - 500) / 1000;
  1653. else
  1654. off = (off + 500) / 1000;
  1655. do {
  1656. if (state->drxd_state != DRXD_STOPPED)
  1657. return -1;
  1658. status = ResetECOD(state);
  1659. if (status < 0)
  1660. break;
  1661. if (state->type_A) {
  1662. status = InitSC(state);
  1663. if (status < 0)
  1664. break;
  1665. } else {
  1666. status = InitFT(state);
  1667. if (status < 0)
  1668. break;
  1669. status = InitCP(state);
  1670. if (status < 0)
  1671. break;
  1672. status = InitCE(state);
  1673. if (status < 0)
  1674. break;
  1675. status = InitEQ(state);
  1676. if (status < 0)
  1677. break;
  1678. status = InitSC(state);
  1679. if (status < 0)
  1680. break;
  1681. }
  1682. /* Restore current IF & RF AGC settings */
  1683. status = SetCfgIfAgc(state, &state->if_agc_cfg);
  1684. if (status < 0)
  1685. break;
  1686. status = SetCfgRfAgc(state, &state->rf_agc_cfg);
  1687. if (status < 0)
  1688. break;
  1689. mirrorFreqSpect = (state->props.inversion == INVERSION_ON);
  1690. switch (p->transmission_mode) {
  1691. default: /* Not set, detect it automatically */
  1692. operationMode |= SC_RA_RAM_OP_AUTO_MODE__M;
  1693. fallthrough; /* try first guess DRX_FFTMODE_8K */
  1694. case TRANSMISSION_MODE_8K:
  1695. transmissionParams |= SC_RA_RAM_OP_PARAM_MODE_8K;
  1696. if (state->type_A) {
  1697. status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_8K, 0x0000);
  1698. if (status < 0)
  1699. break;
  1700. qpskSnCeGain = 99;
  1701. qam16SnCeGain = 83;
  1702. qam64SnCeGain = 67;
  1703. }
  1704. break;
  1705. case TRANSMISSION_MODE_2K:
  1706. transmissionParams |= SC_RA_RAM_OP_PARAM_MODE_2K;
  1707. if (state->type_A) {
  1708. status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_2K, 0x0000);
  1709. if (status < 0)
  1710. break;
  1711. qpskSnCeGain = 97;
  1712. qam16SnCeGain = 71;
  1713. qam64SnCeGain = 65;
  1714. }
  1715. break;
  1716. }
  1717. switch (p->guard_interval) {
  1718. case GUARD_INTERVAL_1_4:
  1719. transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_4;
  1720. break;
  1721. case GUARD_INTERVAL_1_8:
  1722. transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_8;
  1723. break;
  1724. case GUARD_INTERVAL_1_16:
  1725. transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_16;
  1726. break;
  1727. case GUARD_INTERVAL_1_32:
  1728. transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_32;
  1729. break;
  1730. default: /* Not set, detect it automatically */
  1731. operationMode |= SC_RA_RAM_OP_AUTO_GUARD__M;
  1732. /* try first guess 1/4 */
  1733. transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_4;
  1734. break;
  1735. }
  1736. switch (p->hierarchy) {
  1737. case HIERARCHY_1:
  1738. transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A1;
  1739. if (state->type_A) {
  1740. status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0001, 0x0000);
  1741. if (status < 0)
  1742. break;
  1743. status = Write16(state, EC_SB_REG_ALPHA__A, 0x0001, 0x0000);
  1744. if (status < 0)
  1745. break;
  1746. qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN;
  1747. qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA1;
  1748. qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA1;
  1749. qpskIsGainMan =
  1750. SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE;
  1751. qam16IsGainMan =
  1752. SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE;
  1753. qam64IsGainMan =
  1754. SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE;
  1755. qpskIsGainExp =
  1756. SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE;
  1757. qam16IsGainExp =
  1758. SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE;
  1759. qam64IsGainExp =
  1760. SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE;
  1761. }
  1762. break;
  1763. case HIERARCHY_2:
  1764. transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A2;
  1765. if (state->type_A) {
  1766. status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0002, 0x0000);
  1767. if (status < 0)
  1768. break;
  1769. status = Write16(state, EC_SB_REG_ALPHA__A, 0x0002, 0x0000);
  1770. if (status < 0)
  1771. break;
  1772. qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN;
  1773. qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA2;
  1774. qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA2;
  1775. qpskIsGainMan =
  1776. SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE;
  1777. qam16IsGainMan =
  1778. SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE;
  1779. qam64IsGainMan =
  1780. SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE;
  1781. qpskIsGainExp =
  1782. SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE;
  1783. qam16IsGainExp =
  1784. SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE;
  1785. qam64IsGainExp =
  1786. SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE;
  1787. }
  1788. break;
  1789. case HIERARCHY_4:
  1790. transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A4;
  1791. if (state->type_A) {
  1792. status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0003, 0x0000);
  1793. if (status < 0)
  1794. break;
  1795. status = Write16(state, EC_SB_REG_ALPHA__A, 0x0003, 0x0000);
  1796. if (status < 0)
  1797. break;
  1798. qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN;
  1799. qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA4;
  1800. qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA4;
  1801. qpskIsGainMan =
  1802. SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE;
  1803. qam16IsGainMan =
  1804. SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE;
  1805. qam64IsGainMan =
  1806. SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE;
  1807. qpskIsGainExp =
  1808. SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE;
  1809. qam16IsGainExp =
  1810. SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE;
  1811. qam64IsGainExp =
  1812. SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE;
  1813. }
  1814. break;
  1815. case HIERARCHY_AUTO:
  1816. default:
  1817. /* Not set, detect it automatically, start with none */
  1818. operationMode |= SC_RA_RAM_OP_AUTO_HIER__M;
  1819. transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_NO;
  1820. if (state->type_A) {
  1821. status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0000, 0x0000);
  1822. if (status < 0)
  1823. break;
  1824. status = Write16(state, EC_SB_REG_ALPHA__A, 0x0000, 0x0000);
  1825. if (status < 0)
  1826. break;
  1827. qpskTdTpsPwr = EQ_TD_TPS_PWR_QPSK;
  1828. qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHAN;
  1829. qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHAN;
  1830. qpskIsGainMan =
  1831. SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE;
  1832. qam16IsGainMan =
  1833. SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE;
  1834. qam64IsGainMan =
  1835. SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE;
  1836. qpskIsGainExp =
  1837. SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE;
  1838. qam16IsGainExp =
  1839. SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE;
  1840. qam64IsGainExp =
  1841. SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE;
  1842. }
  1843. break;
  1844. }
  1845. if (status < 0)
  1846. break;
  1847. switch (p->modulation) {
  1848. default:
  1849. operationMode |= SC_RA_RAM_OP_AUTO_CONST__M;
  1850. fallthrough; /* try first guess DRX_CONSTELLATION_QAM64 */
  1851. case QAM_64:
  1852. transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QAM64;
  1853. if (state->type_A) {
  1854. status = Write16(state, EQ_REG_OT_CONST__A, 0x0002, 0x0000);
  1855. if (status < 0)
  1856. break;
  1857. status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_64QAM, 0x0000);
  1858. if (status < 0)
  1859. break;
  1860. status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0020, 0x0000);
  1861. if (status < 0)
  1862. break;
  1863. status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0008, 0x0000);
  1864. if (status < 0)
  1865. break;
  1866. status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0002, 0x0000);
  1867. if (status < 0)
  1868. break;
  1869. status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam64TdTpsPwr, 0x0000);
  1870. if (status < 0)
  1871. break;
  1872. status = Write16(state, EQ_REG_SN_CEGAIN__A, qam64SnCeGain, 0x0000);
  1873. if (status < 0)
  1874. break;
  1875. status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam64IsGainMan, 0x0000);
  1876. if (status < 0)
  1877. break;
  1878. status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam64IsGainExp, 0x0000);
  1879. if (status < 0)
  1880. break;
  1881. }
  1882. break;
  1883. case QPSK:
  1884. transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QPSK;
  1885. if (state->type_A) {
  1886. status = Write16(state, EQ_REG_OT_CONST__A, 0x0000, 0x0000);
  1887. if (status < 0)
  1888. break;
  1889. status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_QPSK, 0x0000);
  1890. if (status < 0)
  1891. break;
  1892. status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000);
  1893. if (status < 0)
  1894. break;
  1895. status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0000, 0x0000);
  1896. if (status < 0)
  1897. break;
  1898. status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000);
  1899. if (status < 0)
  1900. break;
  1901. status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qpskTdTpsPwr, 0x0000);
  1902. if (status < 0)
  1903. break;
  1904. status = Write16(state, EQ_REG_SN_CEGAIN__A, qpskSnCeGain, 0x0000);
  1905. if (status < 0)
  1906. break;
  1907. status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qpskIsGainMan, 0x0000);
  1908. if (status < 0)
  1909. break;
  1910. status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qpskIsGainExp, 0x0000);
  1911. if (status < 0)
  1912. break;
  1913. }
  1914. break;
  1915. case QAM_16:
  1916. transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QAM16;
  1917. if (state->type_A) {
  1918. status = Write16(state, EQ_REG_OT_CONST__A, 0x0001, 0x0000);
  1919. if (status < 0)
  1920. break;
  1921. status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_16QAM, 0x0000);
  1922. if (status < 0)
  1923. break;
  1924. status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000);
  1925. if (status < 0)
  1926. break;
  1927. status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0004, 0x0000);
  1928. if (status < 0)
  1929. break;
  1930. status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000);
  1931. if (status < 0)
  1932. break;
  1933. status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam16TdTpsPwr, 0x0000);
  1934. if (status < 0)
  1935. break;
  1936. status = Write16(state, EQ_REG_SN_CEGAIN__A, qam16SnCeGain, 0x0000);
  1937. if (status < 0)
  1938. break;
  1939. status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam16IsGainMan, 0x0000);
  1940. if (status < 0)
  1941. break;
  1942. status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam16IsGainExp, 0x0000);
  1943. if (status < 0)
  1944. break;
  1945. }
  1946. break;
  1947. }
  1948. if (status < 0)
  1949. break;
  1950. switch (DRX_CHANNEL_HIGH) {
  1951. default:
  1952. case DRX_CHANNEL_AUTO:
  1953. case DRX_CHANNEL_LOW:
  1954. transmissionParams |= SC_RA_RAM_OP_PARAM_PRIO_LO;
  1955. status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_LO, 0x0000);
  1956. break;
  1957. case DRX_CHANNEL_HIGH:
  1958. transmissionParams |= SC_RA_RAM_OP_PARAM_PRIO_HI;
  1959. status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_HI, 0x0000);
  1960. break;
  1961. }
  1962. switch (p->code_rate_HP) {
  1963. case FEC_1_2:
  1964. transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_1_2;
  1965. if (state->type_A)
  1966. status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C1_2, 0x0000);
  1967. break;
  1968. default:
  1969. operationMode |= SC_RA_RAM_OP_AUTO_RATE__M;
  1970. fallthrough;
  1971. case FEC_2_3:
  1972. transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_2_3;
  1973. if (state->type_A)
  1974. status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C2_3, 0x0000);
  1975. break;
  1976. case FEC_3_4:
  1977. transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_3_4;
  1978. if (state->type_A)
  1979. status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C3_4, 0x0000);
  1980. break;
  1981. case FEC_5_6:
  1982. transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_5_6;
  1983. if (state->type_A)
  1984. status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C5_6, 0x0000);
  1985. break;
  1986. case FEC_7_8:
  1987. transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_7_8;
  1988. if (state->type_A)
  1989. status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C7_8, 0x0000);
  1990. break;
  1991. }
  1992. if (status < 0)
  1993. break;
  1994. /* First determine real bandwidth (Hz) */
  1995. /* Also set delay for impulse noise cruncher (only A2) */
  1996. /* Also set parameters for EC_OC fix, note
  1997. EC_OC_REG_TMD_HIL_MAR is changed
  1998. by SC for fix for some 8K,1/8 guard but is restored by
  1999. InitEC and ResetEC
  2000. functions */
  2001. switch (p->bandwidth_hz) {
  2002. case 0:
  2003. p->bandwidth_hz = 8000000;
  2004. fallthrough;
  2005. case 8000000:
  2006. /* (64/7)*(8/8)*1000000 */
  2007. bandwidth = DRXD_BANDWIDTH_8MHZ_IN_HZ;
  2008. bandwidthParam = 0;
  2009. status = Write16(state,
  2010. FE_AG_REG_IND_DEL__A, 50, 0x0000);
  2011. break;
  2012. case 7000000:
  2013. /* (64/7)*(7/8)*1000000 */
  2014. bandwidth = DRXD_BANDWIDTH_7MHZ_IN_HZ;
  2015. bandwidthParam = 0x4807; /*binary:0100 1000 0000 0111 */
  2016. status = Write16(state,
  2017. FE_AG_REG_IND_DEL__A, 59, 0x0000);
  2018. break;
  2019. case 6000000:
  2020. /* (64/7)*(6/8)*1000000 */
  2021. bandwidth = DRXD_BANDWIDTH_6MHZ_IN_HZ;
  2022. bandwidthParam = 0x0F07; /*binary: 0000 1111 0000 0111 */
  2023. status = Write16(state,
  2024. FE_AG_REG_IND_DEL__A, 71, 0x0000);
  2025. break;
  2026. default:
  2027. status = -EINVAL;
  2028. }
  2029. if (status < 0)
  2030. break;
  2031. status = Write16(state, SC_RA_RAM_BAND__A, bandwidthParam, 0x0000);
  2032. if (status < 0)
  2033. break;
  2034. {
  2035. u16 sc_config;
  2036. status = Read16(state, SC_RA_RAM_CONFIG__A, &sc_config, 0);
  2037. if (status < 0)
  2038. break;
  2039. /* enable SLAVE mode in 2k 1/32 to
  2040. prevent timing change glitches */
  2041. if ((p->transmission_mode == TRANSMISSION_MODE_2K) &&
  2042. (p->guard_interval == GUARD_INTERVAL_1_32)) {
  2043. /* enable slave */
  2044. sc_config |= SC_RA_RAM_CONFIG_SLAVE__M;
  2045. } else {
  2046. /* disable slave */
  2047. sc_config &= ~SC_RA_RAM_CONFIG_SLAVE__M;
  2048. }
  2049. status = Write16(state, SC_RA_RAM_CONFIG__A, sc_config, 0);
  2050. if (status < 0)
  2051. break;
  2052. }
  2053. status = SetCfgNoiseCalibration(state, &state->noise_cal);
  2054. if (status < 0)
  2055. break;
  2056. if (state->cscd_state == CSCD_INIT) {
  2057. /* switch on SRMM scan in SC */
  2058. status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DO_SCAN, 0x0000);
  2059. if (status < 0)
  2060. break;
  2061. /* CHK_ERROR(Write16(SC_RA_RAM_SAMPLE_RATE_STEP__A, DRXD_OSCDEV_STEP, 0x0000));*/
  2062. state->cscd_state = CSCD_SET;
  2063. }
  2064. /* Now compute FE_IF_REG_INCR */
  2065. /*((( SysFreq/BandWidth)/2)/2) -1) * 2^23) =>
  2066. ((SysFreq / BandWidth) * (2^21) ) - (2^23) */
  2067. feIfIncr = MulDiv32(state->sys_clock_freq * 1000,
  2068. (1ULL << 21), bandwidth) - (1 << 23);
  2069. status = Write16(state, FE_IF_REG_INCR0__A, (u16) (feIfIncr & FE_IF_REG_INCR0__M), 0x0000);
  2070. if (status < 0)
  2071. break;
  2072. status = Write16(state, FE_IF_REG_INCR1__A, (u16) ((feIfIncr >> FE_IF_REG_INCR0__W) & FE_IF_REG_INCR1__M), 0x0000);
  2073. if (status < 0)
  2074. break;
  2075. /* Bandwidth setting done */
  2076. /* Mirror & frequency offset */
  2077. SetFrequencyShift(state, off, mirrorFreqSpect);
  2078. /* Start SC, write channel settings to SC */
  2079. /* Enable SC after setting all other parameters */
  2080. status = Write16(state, SC_COMM_STATE__A, 0, 0x0000);
  2081. if (status < 0)
  2082. break;
  2083. status = Write16(state, SC_COMM_EXEC__A, 1, 0x0000);
  2084. if (status < 0)
  2085. break;
  2086. /* Write SC parameter registers, operation mode */
  2087. #if 1
  2088. operationMode = (SC_RA_RAM_OP_AUTO_MODE__M |
  2089. SC_RA_RAM_OP_AUTO_GUARD__M |
  2090. SC_RA_RAM_OP_AUTO_CONST__M |
  2091. SC_RA_RAM_OP_AUTO_HIER__M |
  2092. SC_RA_RAM_OP_AUTO_RATE__M);
  2093. #endif
  2094. status = SC_SetPrefParamCommand(state, 0x0000, transmissionParams, operationMode);
  2095. if (status < 0)
  2096. break;
  2097. /* Start correct processes to get in lock */
  2098. status = SC_ProcStartCommand(state, SC_RA_RAM_PROC_LOCKTRACK, SC_RA_RAM_SW_EVENT_RUN_NMASK__M, SC_RA_RAM_LOCKTRACK_MIN);
  2099. if (status < 0)
  2100. break;
  2101. status = StartOC(state);
  2102. if (status < 0)
  2103. break;
  2104. if (state->operation_mode != OM_Default) {
  2105. status = StartDiversity(state);
  2106. if (status < 0)
  2107. break;
  2108. }
  2109. state->drxd_state = DRXD_STARTED;
  2110. } while (0);
  2111. return status;
  2112. }
  2113. static int CDRXD(struct drxd_state *state, u32 IntermediateFrequency)
  2114. {
  2115. u32 ulRfAgcOutputLevel = 0xffffffff;
  2116. u32 ulRfAgcSettleLevel = 528; /* Optimum value for MT2060 */
  2117. u32 ulRfAgcMinLevel = 0; /* Currently unused */
  2118. u32 ulRfAgcMaxLevel = DRXD_FE_CTRL_MAX; /* Currently unused */
  2119. u32 ulRfAgcSpeed = 0; /* Currently unused */
  2120. u32 ulRfAgcMode = 0; /*2; Off */
  2121. u32 ulRfAgcR1 = 820;
  2122. u32 ulRfAgcR2 = 2200;
  2123. u32 ulRfAgcR3 = 150;
  2124. u32 ulIfAgcMode = 0; /* Auto */
  2125. u32 ulIfAgcOutputLevel = 0xffffffff;
  2126. u32 ulIfAgcSettleLevel = 0xffffffff;
  2127. u32 ulIfAgcMinLevel = 0xffffffff;
  2128. u32 ulIfAgcMaxLevel = 0xffffffff;
  2129. u32 ulIfAgcSpeed = 0xffffffff;
  2130. u32 ulIfAgcR1 = 820;
  2131. u32 ulIfAgcR2 = 2200;
  2132. u32 ulIfAgcR3 = 150;
  2133. u32 ulClock = state->config.clock;
  2134. u32 ulSerialMode = 0;
  2135. u32 ulEcOcRegOcModeLop = 4; /* Dynamic DTO source */
  2136. u32 ulHiI2cDelay = HI_I2C_DELAY;
  2137. u32 ulHiI2cBridgeDelay = HI_I2C_BRIDGE_DELAY;
  2138. u32 ulHiI2cPatch = 0;
  2139. u32 ulEnvironment = APPENV_PORTABLE;
  2140. u32 ulEnvironmentDiversity = APPENV_MOBILE;
  2141. u32 ulIFFilter = IFFILTER_SAW;
  2142. state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
  2143. state->if_agc_cfg.outputLevel = 0;
  2144. state->if_agc_cfg.settleLevel = 140;
  2145. state->if_agc_cfg.minOutputLevel = 0;
  2146. state->if_agc_cfg.maxOutputLevel = 1023;
  2147. state->if_agc_cfg.speed = 904;
  2148. if (ulIfAgcMode == 1 && ulIfAgcOutputLevel <= DRXD_FE_CTRL_MAX) {
  2149. state->if_agc_cfg.ctrlMode = AGC_CTRL_USER;
  2150. state->if_agc_cfg.outputLevel = (u16) (ulIfAgcOutputLevel);
  2151. }
  2152. if (ulIfAgcMode == 0 &&
  2153. ulIfAgcSettleLevel <= DRXD_FE_CTRL_MAX &&
  2154. ulIfAgcMinLevel <= DRXD_FE_CTRL_MAX &&
  2155. ulIfAgcMaxLevel <= DRXD_FE_CTRL_MAX &&
  2156. ulIfAgcSpeed <= DRXD_FE_CTRL_MAX) {
  2157. state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
  2158. state->if_agc_cfg.settleLevel = (u16) (ulIfAgcSettleLevel);
  2159. state->if_agc_cfg.minOutputLevel = (u16) (ulIfAgcMinLevel);
  2160. state->if_agc_cfg.maxOutputLevel = (u16) (ulIfAgcMaxLevel);
  2161. state->if_agc_cfg.speed = (u16) (ulIfAgcSpeed);
  2162. }
  2163. state->if_agc_cfg.R1 = (u16) (ulIfAgcR1);
  2164. state->if_agc_cfg.R2 = (u16) (ulIfAgcR2);
  2165. state->if_agc_cfg.R3 = (u16) (ulIfAgcR3);
  2166. state->rf_agc_cfg.R1 = (u16) (ulRfAgcR1);
  2167. state->rf_agc_cfg.R2 = (u16) (ulRfAgcR2);
  2168. state->rf_agc_cfg.R3 = (u16) (ulRfAgcR3);
  2169. state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
  2170. /* rest of the RFAgcCfg structure currently unused */
  2171. if (ulRfAgcMode == 1 && ulRfAgcOutputLevel <= DRXD_FE_CTRL_MAX) {
  2172. state->rf_agc_cfg.ctrlMode = AGC_CTRL_USER;
  2173. state->rf_agc_cfg.outputLevel = (u16) (ulRfAgcOutputLevel);
  2174. }
  2175. if (ulRfAgcMode == 0 &&
  2176. ulRfAgcSettleLevel <= DRXD_FE_CTRL_MAX &&
  2177. ulRfAgcMinLevel <= DRXD_FE_CTRL_MAX &&
  2178. ulRfAgcMaxLevel <= DRXD_FE_CTRL_MAX &&
  2179. ulRfAgcSpeed <= DRXD_FE_CTRL_MAX) {
  2180. state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
  2181. state->rf_agc_cfg.settleLevel = (u16) (ulRfAgcSettleLevel);
  2182. state->rf_agc_cfg.minOutputLevel = (u16) (ulRfAgcMinLevel);
  2183. state->rf_agc_cfg.maxOutputLevel = (u16) (ulRfAgcMaxLevel);
  2184. state->rf_agc_cfg.speed = (u16) (ulRfAgcSpeed);
  2185. }
  2186. if (ulRfAgcMode == 2)
  2187. state->rf_agc_cfg.ctrlMode = AGC_CTRL_OFF;
  2188. if (ulEnvironment <= 2)
  2189. state->app_env_default = (enum app_env)
  2190. (ulEnvironment);
  2191. if (ulEnvironmentDiversity <= 2)
  2192. state->app_env_diversity = (enum app_env)
  2193. (ulEnvironmentDiversity);
  2194. if (ulIFFilter == IFFILTER_DISCRETE) {
  2195. /* discrete filter */
  2196. state->noise_cal.cpOpt = 0;
  2197. state->noise_cal.cpNexpOfs = 40;
  2198. state->noise_cal.tdCal2k = -40;
  2199. state->noise_cal.tdCal8k = -24;
  2200. } else {
  2201. /* SAW filter */
  2202. state->noise_cal.cpOpt = 1;
  2203. state->noise_cal.cpNexpOfs = 0;
  2204. state->noise_cal.tdCal2k = -21;
  2205. state->noise_cal.tdCal8k = -24;
  2206. }
  2207. state->m_EcOcRegOcModeLop = (u16) (ulEcOcRegOcModeLop);
  2208. state->chip_adr = (state->config.demod_address << 1) | 1;
  2209. switch (ulHiI2cPatch) {
  2210. case 1:
  2211. state->m_HiI2cPatch = DRXD_HiI2cPatch_1;
  2212. break;
  2213. case 3:
  2214. state->m_HiI2cPatch = DRXD_HiI2cPatch_3;
  2215. break;
  2216. default:
  2217. state->m_HiI2cPatch = NULL;
  2218. }
  2219. /* modify tuner and clock attributes */
  2220. state->intermediate_freq = (u16) (IntermediateFrequency / 1000);
  2221. /* expected system clock frequency in kHz */
  2222. state->expected_sys_clock_freq = 48000;
  2223. /* real system clock frequency in kHz */
  2224. state->sys_clock_freq = 48000;
  2225. state->osc_clock_freq = (u16) ulClock;
  2226. state->osc_clock_deviation = 0;
  2227. state->cscd_state = CSCD_INIT;
  2228. state->drxd_state = DRXD_UNINITIALIZED;
  2229. state->PGA = 0;
  2230. state->type_A = 0;
  2231. state->tuner_mirrors = 0;
  2232. /* modify MPEG output attributes */
  2233. state->insert_rs_byte = state->config.insert_rs_byte;
  2234. state->enable_parallel = (ulSerialMode != 1);
  2235. /* Timing div, 250ns/Psys */
  2236. /* Timing div, = ( delay (nano seconds) * sysclk (kHz) )/ 1000 */
  2237. state->hi_cfg_timing_div = (u16) ((state->sys_clock_freq / 1000) *
  2238. ulHiI2cDelay) / 1000;
  2239. /* Bridge delay, uses oscilator clock */
  2240. /* Delay = ( delay (nano seconds) * oscclk (kHz) )/ 1000 */
  2241. state->hi_cfg_bridge_delay = (u16) ((state->osc_clock_freq / 1000) *
  2242. ulHiI2cBridgeDelay) / 1000;
  2243. state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER;
  2244. /* state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO; */
  2245. state->m_FeAgRegAgAgcSio = DRXD_DEF_AG_AGC_SIO;
  2246. return 0;
  2247. }
  2248. static int DRXD_init(struct drxd_state *state, const u8 *fw, u32 fw_size)
  2249. {
  2250. int status = 0;
  2251. u32 driverVersion;
  2252. if (state->init_done)
  2253. return 0;
  2254. CDRXD(state, state->config.IF ? state->config.IF : 36000000);
  2255. do {
  2256. state->operation_mode = OM_Default;
  2257. status = SetDeviceTypeId(state);
  2258. if (status < 0)
  2259. break;
  2260. /* Apply I2c address patch to B1 */
  2261. if (!state->type_A && state->m_HiI2cPatch) {
  2262. status = WriteTable(state, state->m_HiI2cPatch);
  2263. if (status < 0)
  2264. break;
  2265. }
  2266. if (state->type_A) {
  2267. /* HI firmware patch for UIO readout,
  2268. avoid clearing of result register */
  2269. status = Write16(state, 0x43012D, 0x047f, 0);
  2270. if (status < 0)
  2271. break;
  2272. }
  2273. status = HI_ResetCommand(state);
  2274. if (status < 0)
  2275. break;
  2276. status = StopAllProcessors(state);
  2277. if (status < 0)
  2278. break;
  2279. status = InitCC(state);
  2280. if (status < 0)
  2281. break;
  2282. state->osc_clock_deviation = 0;
  2283. if (state->config.osc_deviation)
  2284. state->osc_clock_deviation =
  2285. state->config.osc_deviation(state->priv, 0, 0);
  2286. {
  2287. /* Handle clock deviation */
  2288. s32 devB;
  2289. s32 devA = (s32) (state->osc_clock_deviation) *
  2290. (s32) (state->expected_sys_clock_freq);
  2291. /* deviation in kHz */
  2292. s32 deviation = (devA / (1000000L));
  2293. /* rounding, signed */
  2294. if (devA > 0)
  2295. devB = (2);
  2296. else
  2297. devB = (-2);
  2298. if ((devB * (devA % 1000000L) > 1000000L)) {
  2299. /* add +1 or -1 */
  2300. deviation += (devB / 2);
  2301. }
  2302. state->sys_clock_freq =
  2303. (u16) ((state->expected_sys_clock_freq) +
  2304. deviation);
  2305. }
  2306. status = InitHI(state);
  2307. if (status < 0)
  2308. break;
  2309. status = InitAtomicRead(state);
  2310. if (status < 0)
  2311. break;
  2312. status = EnableAndResetMB(state);
  2313. if (status < 0)
  2314. break;
  2315. if (state->type_A) {
  2316. status = ResetCEFR(state);
  2317. if (status < 0)
  2318. break;
  2319. }
  2320. if (fw) {
  2321. status = DownloadMicrocode(state, fw, fw_size);
  2322. if (status < 0)
  2323. break;
  2324. } else {
  2325. status = DownloadMicrocode(state, state->microcode, state->microcode_length);
  2326. if (status < 0)
  2327. break;
  2328. }
  2329. if (state->PGA) {
  2330. state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO;
  2331. SetCfgPga(state, 0); /* PGA = 0 dB */
  2332. } else {
  2333. state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER;
  2334. }
  2335. state->m_FeAgRegAgAgcSio = DRXD_DEF_AG_AGC_SIO;
  2336. status = InitFE(state);
  2337. if (status < 0)
  2338. break;
  2339. status = InitFT(state);
  2340. if (status < 0)
  2341. break;
  2342. status = InitCP(state);
  2343. if (status < 0)
  2344. break;
  2345. status = InitCE(state);
  2346. if (status < 0)
  2347. break;
  2348. status = InitEQ(state);
  2349. if (status < 0)
  2350. break;
  2351. status = InitEC(state);
  2352. if (status < 0)
  2353. break;
  2354. status = InitSC(state);
  2355. if (status < 0)
  2356. break;
  2357. status = SetCfgIfAgc(state, &state->if_agc_cfg);
  2358. if (status < 0)
  2359. break;
  2360. status = SetCfgRfAgc(state, &state->rf_agc_cfg);
  2361. if (status < 0)
  2362. break;
  2363. state->cscd_state = CSCD_INIT;
  2364. status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
  2365. if (status < 0)
  2366. break;
  2367. status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
  2368. if (status < 0)
  2369. break;
  2370. driverVersion = (((VERSION_MAJOR / 10) << 4) +
  2371. (VERSION_MAJOR % 10)) << 24;
  2372. driverVersion += (((VERSION_MINOR / 10) << 4) +
  2373. (VERSION_MINOR % 10)) << 16;
  2374. driverVersion += ((VERSION_PATCH / 1000) << 12) +
  2375. ((VERSION_PATCH / 100) << 8) +
  2376. ((VERSION_PATCH / 10) << 4) + (VERSION_PATCH % 10);
  2377. status = Write32(state, SC_RA_RAM_DRIVER_VERSION__AX, driverVersion, 0);
  2378. if (status < 0)
  2379. break;
  2380. status = StopOC(state);
  2381. if (status < 0)
  2382. break;
  2383. state->drxd_state = DRXD_STOPPED;
  2384. state->init_done = 1;
  2385. status = 0;
  2386. } while (0);
  2387. return status;
  2388. }
  2389. static int DRXD_status(struct drxd_state *state, u32 *pLockStatus)
  2390. {
  2391. DRX_GetLockStatus(state, pLockStatus);
  2392. /*if (*pLockStatus&DRX_LOCK_MPEG) */
  2393. if (*pLockStatus & DRX_LOCK_FEC) {
  2394. ConfigureMPEGOutput(state, 1);
  2395. /* Get status again, in case we have MPEG lock now */
  2396. /*DRX_GetLockStatus(state, pLockStatus); */
  2397. }
  2398. return 0;
  2399. }
  2400. /****************************************************************************/
  2401. /****************************************************************************/
  2402. /****************************************************************************/
  2403. static int drxd_read_signal_strength(struct dvb_frontend *fe, u16 * strength)
  2404. {
  2405. struct drxd_state *state = fe->demodulator_priv;
  2406. u32 value;
  2407. int res;
  2408. res = ReadIFAgc(state, &value);
  2409. if (res < 0)
  2410. *strength = 0;
  2411. else
  2412. *strength = 0xffff - (value << 4);
  2413. return 0;
  2414. }
  2415. static int drxd_read_status(struct dvb_frontend *fe, enum fe_status *status)
  2416. {
  2417. struct drxd_state *state = fe->demodulator_priv;
  2418. u32 lock;
  2419. DRXD_status(state, &lock);
  2420. *status = 0;
  2421. /* No MPEG lock in V255 firmware, bug ? */
  2422. #if 1
  2423. if (lock & DRX_LOCK_MPEG)
  2424. *status |= FE_HAS_LOCK;
  2425. #else
  2426. if (lock & DRX_LOCK_FEC)
  2427. *status |= FE_HAS_LOCK;
  2428. #endif
  2429. if (lock & DRX_LOCK_FEC)
  2430. *status |= FE_HAS_VITERBI | FE_HAS_SYNC;
  2431. if (lock & DRX_LOCK_DEMOD)
  2432. *status |= FE_HAS_CARRIER | FE_HAS_SIGNAL;
  2433. return 0;
  2434. }
  2435. static int drxd_init(struct dvb_frontend *fe)
  2436. {
  2437. struct drxd_state *state = fe->demodulator_priv;
  2438. return DRXD_init(state, NULL, 0);
  2439. }
  2440. static int drxd_config_i2c(struct dvb_frontend *fe, int onoff)
  2441. {
  2442. struct drxd_state *state = fe->demodulator_priv;
  2443. if (state->config.disable_i2c_gate_ctrl == 1)
  2444. return 0;
  2445. return DRX_ConfigureI2CBridge(state, onoff);
  2446. }
  2447. static int drxd_get_tune_settings(struct dvb_frontend *fe,
  2448. struct dvb_frontend_tune_settings *sets)
  2449. {
  2450. sets->min_delay_ms = 10000;
  2451. sets->max_drift = 0;
  2452. sets->step_size = 0;
  2453. return 0;
  2454. }
  2455. static int drxd_read_ber(struct dvb_frontend *fe, u32 * ber)
  2456. {
  2457. *ber = 0;
  2458. return 0;
  2459. }
  2460. static int drxd_read_snr(struct dvb_frontend *fe, u16 * snr)
  2461. {
  2462. *snr = 0;
  2463. return 0;
  2464. }
  2465. static int drxd_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks)
  2466. {
  2467. *ucblocks = 0;
  2468. return 0;
  2469. }
  2470. static int drxd_sleep(struct dvb_frontend *fe)
  2471. {
  2472. struct drxd_state *state = fe->demodulator_priv;
  2473. ConfigureMPEGOutput(state, 0);
  2474. return 0;
  2475. }
  2476. static int drxd_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
  2477. {
  2478. return drxd_config_i2c(fe, enable);
  2479. }
  2480. static int drxd_set_frontend(struct dvb_frontend *fe)
  2481. {
  2482. struct dtv_frontend_properties *p = &fe->dtv_property_cache;
  2483. struct drxd_state *state = fe->demodulator_priv;
  2484. s32 off = 0;
  2485. state->props = *p;
  2486. DRX_Stop(state);
  2487. if (fe->ops.tuner_ops.set_params) {
  2488. fe->ops.tuner_ops.set_params(fe);
  2489. if (fe->ops.i2c_gate_ctrl)
  2490. fe->ops.i2c_gate_ctrl(fe, 0);
  2491. }
  2492. msleep(200);
  2493. return DRX_Start(state, off);
  2494. }
  2495. static void drxd_release(struct dvb_frontend *fe)
  2496. {
  2497. struct drxd_state *state = fe->demodulator_priv;
  2498. kfree(state);
  2499. }
  2500. static const struct dvb_frontend_ops drxd_ops = {
  2501. .delsys = { SYS_DVBT},
  2502. .info = {
  2503. .name = "Micronas DRXD DVB-T",
  2504. .frequency_min_hz = 47125 * kHz,
  2505. .frequency_max_hz = 855250 * kHz,
  2506. .frequency_stepsize_hz = 166667,
  2507. .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
  2508. FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
  2509. FE_CAN_FEC_AUTO |
  2510. FE_CAN_QAM_16 | FE_CAN_QAM_64 |
  2511. FE_CAN_QAM_AUTO |
  2512. FE_CAN_TRANSMISSION_MODE_AUTO |
  2513. FE_CAN_GUARD_INTERVAL_AUTO |
  2514. FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER | FE_CAN_MUTE_TS},
  2515. .release = drxd_release,
  2516. .init = drxd_init,
  2517. .sleep = drxd_sleep,
  2518. .i2c_gate_ctrl = drxd_i2c_gate_ctrl,
  2519. .set_frontend = drxd_set_frontend,
  2520. .get_tune_settings = drxd_get_tune_settings,
  2521. .read_status = drxd_read_status,
  2522. .read_ber = drxd_read_ber,
  2523. .read_signal_strength = drxd_read_signal_strength,
  2524. .read_snr = drxd_read_snr,
  2525. .read_ucblocks = drxd_read_ucblocks,
  2526. };
  2527. struct dvb_frontend *drxd_attach(const struct drxd_config *config,
  2528. void *priv, struct i2c_adapter *i2c,
  2529. struct device *dev)
  2530. {
  2531. struct drxd_state *state = NULL;
  2532. state = kzalloc(sizeof(*state), GFP_KERNEL);
  2533. if (!state)
  2534. return NULL;
  2535. state->ops = drxd_ops;
  2536. state->dev = dev;
  2537. state->config = *config;
  2538. state->i2c = i2c;
  2539. state->priv = priv;
  2540. mutex_init(&state->mutex);
  2541. if (Read16(state, 0, NULL, 0) < 0)
  2542. goto error;
  2543. state->frontend.ops = drxd_ops;
  2544. state->frontend.demodulator_priv = state;
  2545. ConfigureMPEGOutput(state, 0);
  2546. /* add few initialization to allow gate control */
  2547. CDRXD(state, state->config.IF ? state->config.IF : 36000000);
  2548. InitHI(state);
  2549. return &state->frontend;
  2550. error:
  2551. printk(KERN_ERR "drxd: not found\n");
  2552. kfree(state);
  2553. return NULL;
  2554. }
  2555. EXPORT_SYMBOL(drxd_attach);
  2556. MODULE_DESCRIPTION("DRXD driver");
  2557. MODULE_AUTHOR("Micronas");
  2558. MODULE_LICENSE("GPL");