af9033.c 27 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Afatech AF9033 demodulator driver
  4. *
  5. * Copyright (C) 2009 Antti Palosaari <crope@iki.fi>
  6. * Copyright (C) 2012 Antti Palosaari <crope@iki.fi>
  7. */
  8. #include "af9033_priv.h"
  9. struct af9033_dev {
  10. struct i2c_client *client;
  11. struct regmap *regmap;
  12. struct dvb_frontend fe;
  13. struct af9033_config cfg;
  14. bool is_af9035;
  15. bool is_it9135;
  16. u32 bandwidth_hz;
  17. bool ts_mode_parallel;
  18. bool ts_mode_serial;
  19. enum fe_status fe_status;
  20. u64 post_bit_error_prev; /* for old read_ber we return (curr - prev) */
  21. u64 post_bit_error;
  22. u64 post_bit_count;
  23. u64 error_block_count;
  24. u64 total_block_count;
  25. };
  26. /* Write reg val table using reg addr auto increment */
  27. static int af9033_wr_reg_val_tab(struct af9033_dev *dev,
  28. const struct reg_val *tab, int tab_len)
  29. {
  30. struct i2c_client *client = dev->client;
  31. #define MAX_TAB_LEN 212
  32. int ret, i, j;
  33. u8 buf[1 + MAX_TAB_LEN];
  34. dev_dbg(&client->dev, "tab_len=%d\n", tab_len);
  35. if (tab_len > sizeof(buf)) {
  36. dev_warn(&client->dev, "tab len %d is too big\n", tab_len);
  37. return -EINVAL;
  38. }
  39. for (i = 0, j = 0; i < tab_len; i++) {
  40. buf[j] = tab[i].val;
  41. if (i == tab_len - 1 || tab[i].reg != tab[i + 1].reg - 1) {
  42. ret = regmap_bulk_write(dev->regmap, tab[i].reg - j,
  43. buf, j + 1);
  44. if (ret)
  45. goto err;
  46. j = 0;
  47. } else {
  48. j++;
  49. }
  50. }
  51. return 0;
  52. err:
  53. dev_dbg(&client->dev, "failed=%d\n", ret);
  54. return ret;
  55. }
  56. static int af9033_init(struct dvb_frontend *fe)
  57. {
  58. struct af9033_dev *dev = fe->demodulator_priv;
  59. struct i2c_client *client = dev->client;
  60. struct dtv_frontend_properties *c = &fe->dtv_property_cache;
  61. int ret, i, len;
  62. unsigned int utmp;
  63. const struct reg_val *init;
  64. u8 buf[4];
  65. struct reg_val_mask tab[] = {
  66. { 0x80fb24, 0x00, 0x08 },
  67. { 0x80004c, 0x00, 0xff },
  68. { 0x00f641, dev->cfg.tuner, 0xff },
  69. { 0x80f5ca, 0x01, 0x01 },
  70. { 0x80f715, 0x01, 0x01 },
  71. { 0x00f41f, 0x04, 0x04 },
  72. { 0x00f41a, 0x01, 0x01 },
  73. { 0x80f731, 0x00, 0x01 },
  74. { 0x00d91e, 0x00, 0x01 },
  75. { 0x00d919, 0x00, 0x01 },
  76. { 0x80f732, 0x00, 0x01 },
  77. { 0x00d91f, 0x00, 0x01 },
  78. { 0x00d91a, 0x00, 0x01 },
  79. { 0x80f730, 0x00, 0x01 },
  80. { 0x80f778, 0x00, 0xff },
  81. { 0x80f73c, 0x01, 0x01 },
  82. { 0x80f776, 0x00, 0x01 },
  83. { 0x00d8fd, 0x01, 0xff },
  84. { 0x00d830, 0x01, 0xff },
  85. { 0x00d831, 0x00, 0xff },
  86. { 0x00d832, 0x00, 0xff },
  87. { 0x80f985, dev->ts_mode_serial, 0x01 },
  88. { 0x80f986, dev->ts_mode_parallel, 0x01 },
  89. { 0x00d827, 0x00, 0xff },
  90. { 0x00d829, 0x00, 0xff },
  91. { 0x800045, dev->cfg.adc_multiplier, 0xff },
  92. };
  93. dev_dbg(&client->dev, "\n");
  94. /* Main clk control */
  95. utmp = div_u64((u64)dev->cfg.clock * 0x80000, 1000000);
  96. buf[0] = (utmp >> 0) & 0xff;
  97. buf[1] = (utmp >> 8) & 0xff;
  98. buf[2] = (utmp >> 16) & 0xff;
  99. buf[3] = (utmp >> 24) & 0xff;
  100. ret = regmap_bulk_write(dev->regmap, 0x800025, buf, 4);
  101. if (ret)
  102. goto err;
  103. dev_dbg(&client->dev, "clk=%u clk_cw=%08x\n", dev->cfg.clock, utmp);
  104. /* ADC clk control */
  105. for (i = 0; i < ARRAY_SIZE(clock_adc_lut); i++) {
  106. if (clock_adc_lut[i].clock == dev->cfg.clock)
  107. break;
  108. }
  109. if (i == ARRAY_SIZE(clock_adc_lut)) {
  110. dev_err(&client->dev, "Couldn't find ADC config for clock %d\n",
  111. dev->cfg.clock);
  112. goto err;
  113. }
  114. utmp = div_u64((u64)clock_adc_lut[i].adc * 0x80000, 1000000);
  115. buf[0] = (utmp >> 0) & 0xff;
  116. buf[1] = (utmp >> 8) & 0xff;
  117. buf[2] = (utmp >> 16) & 0xff;
  118. ret = regmap_bulk_write(dev->regmap, 0x80f1cd, buf, 3);
  119. if (ret)
  120. goto err;
  121. dev_dbg(&client->dev, "adc=%u adc_cw=%06x\n",
  122. clock_adc_lut[i].adc, utmp);
  123. /* Config register table */
  124. for (i = 0; i < ARRAY_SIZE(tab); i++) {
  125. ret = regmap_update_bits(dev->regmap, tab[i].reg, tab[i].mask,
  126. tab[i].val);
  127. if (ret)
  128. goto err;
  129. }
  130. /* Demod clk output */
  131. if (dev->cfg.dyn0_clk) {
  132. ret = regmap_write(dev->regmap, 0x80fba8, 0x00);
  133. if (ret)
  134. goto err;
  135. }
  136. /* TS interface */
  137. if (dev->cfg.ts_mode == AF9033_TS_MODE_USB) {
  138. ret = regmap_update_bits(dev->regmap, 0x80f9a5, 0x01, 0x00);
  139. if (ret)
  140. goto err;
  141. ret = regmap_update_bits(dev->regmap, 0x80f9b5, 0x01, 0x01);
  142. if (ret)
  143. goto err;
  144. } else {
  145. ret = regmap_update_bits(dev->regmap, 0x80f990, 0x01, 0x00);
  146. if (ret)
  147. goto err;
  148. ret = regmap_update_bits(dev->regmap, 0x80f9b5, 0x01, 0x00);
  149. if (ret)
  150. goto err;
  151. }
  152. /* Demod core settings */
  153. dev_dbg(&client->dev, "load ofsm settings\n");
  154. switch (dev->cfg.tuner) {
  155. case AF9033_TUNER_IT9135_38:
  156. case AF9033_TUNER_IT9135_51:
  157. case AF9033_TUNER_IT9135_52:
  158. len = ARRAY_SIZE(ofsm_init_it9135_v1);
  159. init = ofsm_init_it9135_v1;
  160. break;
  161. case AF9033_TUNER_IT9135_60:
  162. case AF9033_TUNER_IT9135_61:
  163. case AF9033_TUNER_IT9135_62:
  164. len = ARRAY_SIZE(ofsm_init_it9135_v2);
  165. init = ofsm_init_it9135_v2;
  166. break;
  167. default:
  168. len = ARRAY_SIZE(ofsm_init);
  169. init = ofsm_init;
  170. break;
  171. }
  172. ret = af9033_wr_reg_val_tab(dev, init, len);
  173. if (ret)
  174. goto err;
  175. /* Demod tuner specific settings */
  176. dev_dbg(&client->dev, "load tuner specific settings\n");
  177. switch (dev->cfg.tuner) {
  178. case AF9033_TUNER_TUA9001:
  179. len = ARRAY_SIZE(tuner_init_tua9001);
  180. init = tuner_init_tua9001;
  181. break;
  182. case AF9033_TUNER_FC0011:
  183. len = ARRAY_SIZE(tuner_init_fc0011);
  184. init = tuner_init_fc0011;
  185. break;
  186. case AF9033_TUNER_MXL5007T:
  187. len = ARRAY_SIZE(tuner_init_mxl5007t);
  188. init = tuner_init_mxl5007t;
  189. break;
  190. case AF9033_TUNER_TDA18218:
  191. len = ARRAY_SIZE(tuner_init_tda18218);
  192. init = tuner_init_tda18218;
  193. break;
  194. case AF9033_TUNER_FC2580:
  195. len = ARRAY_SIZE(tuner_init_fc2580);
  196. init = tuner_init_fc2580;
  197. break;
  198. case AF9033_TUNER_FC0012:
  199. len = ARRAY_SIZE(tuner_init_fc0012);
  200. init = tuner_init_fc0012;
  201. break;
  202. case AF9033_TUNER_IT9135_38:
  203. len = ARRAY_SIZE(tuner_init_it9135_38);
  204. init = tuner_init_it9135_38;
  205. break;
  206. case AF9033_TUNER_IT9135_51:
  207. len = ARRAY_SIZE(tuner_init_it9135_51);
  208. init = tuner_init_it9135_51;
  209. break;
  210. case AF9033_TUNER_IT9135_52:
  211. len = ARRAY_SIZE(tuner_init_it9135_52);
  212. init = tuner_init_it9135_52;
  213. break;
  214. case AF9033_TUNER_IT9135_60:
  215. len = ARRAY_SIZE(tuner_init_it9135_60);
  216. init = tuner_init_it9135_60;
  217. break;
  218. case AF9033_TUNER_IT9135_61:
  219. len = ARRAY_SIZE(tuner_init_it9135_61);
  220. init = tuner_init_it9135_61;
  221. break;
  222. case AF9033_TUNER_IT9135_62:
  223. len = ARRAY_SIZE(tuner_init_it9135_62);
  224. init = tuner_init_it9135_62;
  225. break;
  226. default:
  227. dev_dbg(&client->dev, "unsupported tuner ID=%d\n",
  228. dev->cfg.tuner);
  229. ret = -ENODEV;
  230. goto err;
  231. }
  232. ret = af9033_wr_reg_val_tab(dev, init, len);
  233. if (ret)
  234. goto err;
  235. if (dev->cfg.ts_mode == AF9033_TS_MODE_SERIAL) {
  236. ret = regmap_update_bits(dev->regmap, 0x00d91c, 0x01, 0x01);
  237. if (ret)
  238. goto err;
  239. ret = regmap_update_bits(dev->regmap, 0x00d917, 0x01, 0x00);
  240. if (ret)
  241. goto err;
  242. ret = regmap_update_bits(dev->regmap, 0x00d916, 0x01, 0x00);
  243. if (ret)
  244. goto err;
  245. }
  246. switch (dev->cfg.tuner) {
  247. case AF9033_TUNER_IT9135_60:
  248. case AF9033_TUNER_IT9135_61:
  249. case AF9033_TUNER_IT9135_62:
  250. ret = regmap_write(dev->regmap, 0x800000, 0x01);
  251. if (ret)
  252. goto err;
  253. }
  254. dev->bandwidth_hz = 0; /* Force to program all parameters */
  255. /* Init stats here in order signal app which stats are supported */
  256. c->strength.len = 1;
  257. c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
  258. c->cnr.len = 1;
  259. c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
  260. c->block_count.len = 1;
  261. c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
  262. c->block_error.len = 1;
  263. c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
  264. c->post_bit_count.len = 1;
  265. c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
  266. c->post_bit_error.len = 1;
  267. c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
  268. return 0;
  269. err:
  270. dev_dbg(&client->dev, "failed=%d\n", ret);
  271. return ret;
  272. }
  273. static int af9033_sleep(struct dvb_frontend *fe)
  274. {
  275. struct af9033_dev *dev = fe->demodulator_priv;
  276. struct i2c_client *client = dev->client;
  277. int ret;
  278. unsigned int utmp;
  279. dev_dbg(&client->dev, "\n");
  280. ret = regmap_write(dev->regmap, 0x80004c, 0x01);
  281. if (ret)
  282. goto err;
  283. ret = regmap_write(dev->regmap, 0x800000, 0x00);
  284. if (ret)
  285. goto err;
  286. ret = regmap_read_poll_timeout(dev->regmap, 0x80004c, utmp, utmp == 0,
  287. 5000, 1000000);
  288. if (ret)
  289. goto err;
  290. ret = regmap_update_bits(dev->regmap, 0x80fb24, 0x08, 0x08);
  291. if (ret)
  292. goto err;
  293. /* Prevent current leak by setting TS interface to parallel mode */
  294. if (dev->cfg.ts_mode == AF9033_TS_MODE_SERIAL) {
  295. /* Enable parallel TS */
  296. ret = regmap_update_bits(dev->regmap, 0x00d917, 0x01, 0x00);
  297. if (ret)
  298. goto err;
  299. ret = regmap_update_bits(dev->regmap, 0x00d916, 0x01, 0x01);
  300. if (ret)
  301. goto err;
  302. }
  303. return 0;
  304. err:
  305. dev_dbg(&client->dev, "failed=%d\n", ret);
  306. return ret;
  307. }
  308. static int af9033_get_tune_settings(struct dvb_frontend *fe,
  309. struct dvb_frontend_tune_settings *fesettings)
  310. {
  311. /* 800 => 2000 because IT9135 v2 is slow to gain lock */
  312. fesettings->min_delay_ms = 2000;
  313. fesettings->step_size = 0;
  314. fesettings->max_drift = 0;
  315. return 0;
  316. }
  317. static int af9033_set_frontend(struct dvb_frontend *fe)
  318. {
  319. struct af9033_dev *dev = fe->demodulator_priv;
  320. struct i2c_client *client = dev->client;
  321. struct dtv_frontend_properties *c = &fe->dtv_property_cache;
  322. int ret, i;
  323. unsigned int utmp, adc_freq;
  324. u8 tmp, buf[3], bandwidth_reg_val;
  325. u32 if_frequency;
  326. dev_dbg(&client->dev, "frequency=%u bandwidth_hz=%u\n",
  327. c->frequency, c->bandwidth_hz);
  328. /* Check bandwidth */
  329. switch (c->bandwidth_hz) {
  330. case 6000000:
  331. bandwidth_reg_val = 0x00;
  332. break;
  333. case 7000000:
  334. bandwidth_reg_val = 0x01;
  335. break;
  336. case 8000000:
  337. bandwidth_reg_val = 0x02;
  338. break;
  339. default:
  340. dev_dbg(&client->dev, "invalid bandwidth_hz\n");
  341. ret = -EINVAL;
  342. goto err;
  343. }
  344. /* Program tuner */
  345. if (fe->ops.tuner_ops.set_params)
  346. fe->ops.tuner_ops.set_params(fe);
  347. /* Coefficients */
  348. if (c->bandwidth_hz != dev->bandwidth_hz) {
  349. for (i = 0; i < ARRAY_SIZE(coeff_lut); i++) {
  350. if (coeff_lut[i].clock == dev->cfg.clock &&
  351. coeff_lut[i].bandwidth_hz == c->bandwidth_hz) {
  352. break;
  353. }
  354. }
  355. if (i == ARRAY_SIZE(coeff_lut)) {
  356. dev_err(&client->dev,
  357. "Couldn't find config for clock %u\n",
  358. dev->cfg.clock);
  359. ret = -EINVAL;
  360. goto err;
  361. }
  362. ret = regmap_bulk_write(dev->regmap, 0x800001, coeff_lut[i].val,
  363. sizeof(coeff_lut[i].val));
  364. if (ret)
  365. goto err;
  366. }
  367. /* IF frequency control */
  368. if (c->bandwidth_hz != dev->bandwidth_hz) {
  369. for (i = 0; i < ARRAY_SIZE(clock_adc_lut); i++) {
  370. if (clock_adc_lut[i].clock == dev->cfg.clock)
  371. break;
  372. }
  373. if (i == ARRAY_SIZE(clock_adc_lut)) {
  374. dev_err(&client->dev,
  375. "Couldn't find ADC clock for clock %u\n",
  376. dev->cfg.clock);
  377. ret = -EINVAL;
  378. goto err;
  379. }
  380. adc_freq = clock_adc_lut[i].adc;
  381. if (dev->cfg.adc_multiplier == AF9033_ADC_MULTIPLIER_2X)
  382. adc_freq = 2 * adc_freq;
  383. /* Get used IF frequency */
  384. if (fe->ops.tuner_ops.get_if_frequency)
  385. fe->ops.tuner_ops.get_if_frequency(fe, &if_frequency);
  386. else
  387. if_frequency = 0;
  388. utmp = DIV_ROUND_CLOSEST_ULL((u64)if_frequency * 0x800000,
  389. adc_freq);
  390. if (!dev->cfg.spec_inv && if_frequency)
  391. utmp = 0x800000 - utmp;
  392. buf[0] = (utmp >> 0) & 0xff;
  393. buf[1] = (utmp >> 8) & 0xff;
  394. buf[2] = (utmp >> 16) & 0xff;
  395. ret = regmap_bulk_write(dev->regmap, 0x800029, buf, 3);
  396. if (ret)
  397. goto err;
  398. dev_dbg(&client->dev, "if_frequency_cw=%06x\n", utmp);
  399. dev->bandwidth_hz = c->bandwidth_hz;
  400. }
  401. ret = regmap_update_bits(dev->regmap, 0x80f904, 0x03,
  402. bandwidth_reg_val);
  403. if (ret)
  404. goto err;
  405. ret = regmap_write(dev->regmap, 0x800040, 0x00);
  406. if (ret)
  407. goto err;
  408. ret = regmap_write(dev->regmap, 0x800047, 0x00);
  409. if (ret)
  410. goto err;
  411. ret = regmap_update_bits(dev->regmap, 0x80f999, 0x01, 0x00);
  412. if (ret)
  413. goto err;
  414. if (c->frequency <= 230000000)
  415. tmp = 0x00; /* VHF */
  416. else
  417. tmp = 0x01; /* UHF */
  418. ret = regmap_write(dev->regmap, 0x80004b, tmp);
  419. if (ret)
  420. goto err;
  421. /* Reset FSM */
  422. ret = regmap_write(dev->regmap, 0x800000, 0x00);
  423. if (ret)
  424. goto err;
  425. return 0;
  426. err:
  427. dev_dbg(&client->dev, "failed=%d\n", ret);
  428. return ret;
  429. }
  430. static int af9033_get_frontend(struct dvb_frontend *fe,
  431. struct dtv_frontend_properties *c)
  432. {
  433. struct af9033_dev *dev = fe->demodulator_priv;
  434. struct i2c_client *client = dev->client;
  435. int ret;
  436. u8 buf[8];
  437. dev_dbg(&client->dev, "\n");
  438. /* Read all needed TPS registers */
  439. ret = regmap_bulk_read(dev->regmap, 0x80f900, buf, 8);
  440. if (ret)
  441. goto err;
  442. switch ((buf[0] >> 0) & 3) {
  443. case 0:
  444. c->transmission_mode = TRANSMISSION_MODE_2K;
  445. break;
  446. case 1:
  447. c->transmission_mode = TRANSMISSION_MODE_8K;
  448. break;
  449. }
  450. switch ((buf[1] >> 0) & 3) {
  451. case 0:
  452. c->guard_interval = GUARD_INTERVAL_1_32;
  453. break;
  454. case 1:
  455. c->guard_interval = GUARD_INTERVAL_1_16;
  456. break;
  457. case 2:
  458. c->guard_interval = GUARD_INTERVAL_1_8;
  459. break;
  460. case 3:
  461. c->guard_interval = GUARD_INTERVAL_1_4;
  462. break;
  463. }
  464. switch ((buf[2] >> 0) & 7) {
  465. case 0:
  466. c->hierarchy = HIERARCHY_NONE;
  467. break;
  468. case 1:
  469. c->hierarchy = HIERARCHY_1;
  470. break;
  471. case 2:
  472. c->hierarchy = HIERARCHY_2;
  473. break;
  474. case 3:
  475. c->hierarchy = HIERARCHY_4;
  476. break;
  477. }
  478. switch ((buf[3] >> 0) & 3) {
  479. case 0:
  480. c->modulation = QPSK;
  481. break;
  482. case 1:
  483. c->modulation = QAM_16;
  484. break;
  485. case 2:
  486. c->modulation = QAM_64;
  487. break;
  488. }
  489. switch ((buf[4] >> 0) & 3) {
  490. case 0:
  491. c->bandwidth_hz = 6000000;
  492. break;
  493. case 1:
  494. c->bandwidth_hz = 7000000;
  495. break;
  496. case 2:
  497. c->bandwidth_hz = 8000000;
  498. break;
  499. }
  500. switch ((buf[6] >> 0) & 7) {
  501. case 0:
  502. c->code_rate_HP = FEC_1_2;
  503. break;
  504. case 1:
  505. c->code_rate_HP = FEC_2_3;
  506. break;
  507. case 2:
  508. c->code_rate_HP = FEC_3_4;
  509. break;
  510. case 3:
  511. c->code_rate_HP = FEC_5_6;
  512. break;
  513. case 4:
  514. c->code_rate_HP = FEC_7_8;
  515. break;
  516. case 5:
  517. c->code_rate_HP = FEC_NONE;
  518. break;
  519. }
  520. switch ((buf[7] >> 0) & 7) {
  521. case 0:
  522. c->code_rate_LP = FEC_1_2;
  523. break;
  524. case 1:
  525. c->code_rate_LP = FEC_2_3;
  526. break;
  527. case 2:
  528. c->code_rate_LP = FEC_3_4;
  529. break;
  530. case 3:
  531. c->code_rate_LP = FEC_5_6;
  532. break;
  533. case 4:
  534. c->code_rate_LP = FEC_7_8;
  535. break;
  536. case 5:
  537. c->code_rate_LP = FEC_NONE;
  538. break;
  539. }
  540. return 0;
  541. err:
  542. dev_dbg(&client->dev, "failed=%d\n", ret);
  543. return ret;
  544. }
  545. static int af9033_read_status(struct dvb_frontend *fe, enum fe_status *status)
  546. {
  547. struct af9033_dev *dev = fe->demodulator_priv;
  548. struct i2c_client *client = dev->client;
  549. struct dtv_frontend_properties *c = &fe->dtv_property_cache;
  550. int ret, tmp = 0;
  551. u8 buf[7];
  552. unsigned int utmp, utmp1;
  553. dev_dbg(&client->dev, "\n");
  554. *status = 0;
  555. /* Radio channel status: 0=no result, 1=has signal, 2=no signal */
  556. ret = regmap_read(dev->regmap, 0x800047, &utmp);
  557. if (ret)
  558. goto err;
  559. /* Has signal */
  560. if (utmp == 0x01)
  561. *status |= FE_HAS_SIGNAL;
  562. if (utmp != 0x02) {
  563. /* TPS lock */
  564. ret = regmap_read(dev->regmap, 0x80f5a9, &utmp);
  565. if (ret)
  566. goto err;
  567. if ((utmp >> 0) & 0x01)
  568. *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
  569. FE_HAS_VITERBI;
  570. /* Full lock */
  571. ret = regmap_read(dev->regmap, 0x80f999, &utmp);
  572. if (ret)
  573. goto err;
  574. if ((utmp >> 0) & 0x01)
  575. *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
  576. FE_HAS_VITERBI | FE_HAS_SYNC |
  577. FE_HAS_LOCK;
  578. }
  579. dev->fe_status = *status;
  580. /* Signal strength */
  581. if (dev->fe_status & FE_HAS_SIGNAL) {
  582. if (dev->is_af9035) {
  583. ret = regmap_read(dev->regmap, 0x80004a, &utmp);
  584. if (ret)
  585. goto err;
  586. tmp = -utmp * 1000;
  587. } else {
  588. ret = regmap_read(dev->regmap, 0x8000f7, &utmp);
  589. if (ret)
  590. goto err;
  591. tmp = (utmp - 100) * 1000;
  592. }
  593. c->strength.len = 1;
  594. c->strength.stat[0].scale = FE_SCALE_DECIBEL;
  595. c->strength.stat[0].svalue = tmp;
  596. } else {
  597. c->strength.len = 1;
  598. c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
  599. }
  600. /* CNR */
  601. if (dev->fe_status & FE_HAS_VITERBI) {
  602. /* Read raw SNR value */
  603. ret = regmap_bulk_read(dev->regmap, 0x80002c, buf, 3);
  604. if (ret)
  605. goto err;
  606. utmp1 = buf[2] << 16 | buf[1] << 8 | buf[0] << 0;
  607. /* Read superframe number */
  608. ret = regmap_read(dev->regmap, 0x80f78b, &utmp);
  609. if (ret)
  610. goto err;
  611. if (utmp)
  612. utmp1 /= utmp;
  613. /* Read current transmission mode */
  614. ret = regmap_read(dev->regmap, 0x80f900, &utmp);
  615. if (ret)
  616. goto err;
  617. switch ((utmp >> 0) & 3) {
  618. case 0:
  619. /* 2k */
  620. utmp1 *= 4;
  621. break;
  622. case 1:
  623. /* 8k */
  624. utmp1 *= 1;
  625. break;
  626. case 2:
  627. /* 4k */
  628. utmp1 *= 2;
  629. break;
  630. default:
  631. utmp1 *= 0;
  632. break;
  633. }
  634. /* Read current modulation */
  635. ret = regmap_read(dev->regmap, 0x80f903, &utmp);
  636. if (ret)
  637. goto err;
  638. switch ((utmp >> 0) & 3) {
  639. case 0:
  640. /*
  641. * QPSK
  642. * CNR[dB] 13 * -log10((1690000 - value) / value) + 2.6
  643. * value [653799, 1689999], 2.6 / 13 = 3355443
  644. */
  645. utmp1 = clamp(utmp1, 653799U, 1689999U);
  646. utmp1 = ((u64)(intlog10(utmp1)
  647. - intlog10(1690000 - utmp1)
  648. + 3355443) * 13 * 1000) >> 24;
  649. break;
  650. case 1:
  651. /*
  652. * QAM-16
  653. * CNR[dB] 6 * log10((value - 370000) / (828000 - value)) + 15.7
  654. * value [371105, 827999], 15.7 / 6 = 43900382
  655. */
  656. utmp1 = clamp(utmp1, 371105U, 827999U);
  657. utmp1 = ((u64)(intlog10(utmp1 - 370000)
  658. - intlog10(828000 - utmp1)
  659. + 43900382) * 6 * 1000) >> 24;
  660. break;
  661. case 2:
  662. /*
  663. * QAM-64
  664. * CNR[dB] 8 * log10((value - 193000) / (425000 - value)) + 23.8
  665. * value [193246, 424999], 23.8 / 8 = 49912218
  666. */
  667. utmp1 = clamp(utmp1, 193246U, 424999U);
  668. utmp1 = ((u64)(intlog10(utmp1 - 193000)
  669. - intlog10(425000 - utmp1)
  670. + 49912218) * 8 * 1000) >> 24;
  671. break;
  672. default:
  673. utmp1 = 0;
  674. break;
  675. }
  676. dev_dbg(&client->dev, "cnr=%u\n", utmp1);
  677. c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
  678. c->cnr.stat[0].svalue = utmp1;
  679. } else {
  680. c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
  681. }
  682. /* UCB/PER/BER */
  683. if (dev->fe_status & FE_HAS_LOCK) {
  684. /* Outer FEC, 204 byte packets */
  685. u16 abort_packet_count, rsd_packet_count;
  686. /* Inner FEC, bits */
  687. u32 rsd_bit_err_count;
  688. /*
  689. * Packet count used for measurement is 10000
  690. * (rsd_packet_count). Maybe it should be increased?
  691. */
  692. ret = regmap_bulk_read(dev->regmap, 0x800032, buf, 7);
  693. if (ret)
  694. goto err;
  695. abort_packet_count = (buf[1] << 8) | (buf[0] << 0);
  696. rsd_bit_err_count = (buf[4] << 16) | (buf[3] << 8) | buf[2];
  697. rsd_packet_count = (buf[6] << 8) | (buf[5] << 0);
  698. dev->error_block_count += abort_packet_count;
  699. dev->total_block_count += rsd_packet_count;
  700. dev->post_bit_error += rsd_bit_err_count;
  701. dev->post_bit_count += rsd_packet_count * 204 * 8;
  702. c->block_count.len = 1;
  703. c->block_count.stat[0].scale = FE_SCALE_COUNTER;
  704. c->block_count.stat[0].uvalue = dev->total_block_count;
  705. c->block_error.len = 1;
  706. c->block_error.stat[0].scale = FE_SCALE_COUNTER;
  707. c->block_error.stat[0].uvalue = dev->error_block_count;
  708. c->post_bit_count.len = 1;
  709. c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
  710. c->post_bit_count.stat[0].uvalue = dev->post_bit_count;
  711. c->post_bit_error.len = 1;
  712. c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
  713. c->post_bit_error.stat[0].uvalue = dev->post_bit_error;
  714. }
  715. return 0;
  716. err:
  717. dev_dbg(&client->dev, "failed=%d\n", ret);
  718. return ret;
  719. }
  720. static int af9033_read_snr(struct dvb_frontend *fe, u16 *snr)
  721. {
  722. struct af9033_dev *dev = fe->demodulator_priv;
  723. struct i2c_client *client = dev->client;
  724. struct dtv_frontend_properties *c = &dev->fe.dtv_property_cache;
  725. int ret;
  726. unsigned int utmp;
  727. dev_dbg(&client->dev, "\n");
  728. /* Use DVBv5 CNR */
  729. if (c->cnr.stat[0].scale == FE_SCALE_DECIBEL) {
  730. /* Return 0.1 dB for AF9030 and 0-0xffff for IT9130. */
  731. if (dev->is_af9035) {
  732. /* 1000x => 10x (0.1 dB) */
  733. *snr = div_s64(c->cnr.stat[0].svalue, 100);
  734. } else {
  735. /* 1000x => 1x (1 dB) */
  736. *snr = div_s64(c->cnr.stat[0].svalue, 1000);
  737. /* Read current modulation */
  738. ret = regmap_read(dev->regmap, 0x80f903, &utmp);
  739. if (ret)
  740. goto err;
  741. /* scale value to 0x0000-0xffff */
  742. switch ((utmp >> 0) & 3) {
  743. case 0:
  744. *snr = *snr * 0xffff / 23;
  745. break;
  746. case 1:
  747. *snr = *snr * 0xffff / 26;
  748. break;
  749. case 2:
  750. *snr = *snr * 0xffff / 32;
  751. break;
  752. default:
  753. goto err;
  754. }
  755. }
  756. } else {
  757. *snr = 0;
  758. }
  759. return 0;
  760. err:
  761. dev_dbg(&client->dev, "failed=%d\n", ret);
  762. return ret;
  763. }
  764. static int af9033_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
  765. {
  766. struct af9033_dev *dev = fe->demodulator_priv;
  767. struct i2c_client *client = dev->client;
  768. struct dtv_frontend_properties *c = &dev->fe.dtv_property_cache;
  769. int ret, tmp, power_real;
  770. unsigned int utmp;
  771. u8 gain_offset, buf[7];
  772. dev_dbg(&client->dev, "\n");
  773. if (dev->is_af9035) {
  774. /* Read signal strength of 0-100 scale */
  775. ret = regmap_read(dev->regmap, 0x800048, &utmp);
  776. if (ret)
  777. goto err;
  778. /* Scale value to 0x0000-0xffff */
  779. *strength = utmp * 0xffff / 100;
  780. } else {
  781. ret = regmap_read(dev->regmap, 0x8000f7, &utmp);
  782. if (ret)
  783. goto err;
  784. ret = regmap_bulk_read(dev->regmap, 0x80f900, buf, 7);
  785. if (ret)
  786. goto err;
  787. if (c->frequency <= 300000000)
  788. gain_offset = 7; /* VHF */
  789. else
  790. gain_offset = 4; /* UHF */
  791. power_real = (utmp - 100 - gain_offset) -
  792. power_reference[((buf[3] >> 0) & 3)][((buf[6] >> 0) & 7)];
  793. if (power_real < -15)
  794. tmp = 0;
  795. else if ((power_real >= -15) && (power_real < 0))
  796. tmp = (2 * (power_real + 15)) / 3;
  797. else if ((power_real >= 0) && (power_real < 20))
  798. tmp = 4 * power_real + 10;
  799. else if ((power_real >= 20) && (power_real < 35))
  800. tmp = (2 * (power_real - 20)) / 3 + 90;
  801. else
  802. tmp = 100;
  803. /* Scale value to 0x0000-0xffff */
  804. *strength = tmp * 0xffff / 100;
  805. }
  806. return 0;
  807. err:
  808. dev_dbg(&client->dev, "failed=%d\n", ret);
  809. return ret;
  810. }
  811. static int af9033_read_ber(struct dvb_frontend *fe, u32 *ber)
  812. {
  813. struct af9033_dev *dev = fe->demodulator_priv;
  814. *ber = (dev->post_bit_error - dev->post_bit_error_prev);
  815. dev->post_bit_error_prev = dev->post_bit_error;
  816. return 0;
  817. }
  818. static int af9033_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
  819. {
  820. struct af9033_dev *dev = fe->demodulator_priv;
  821. *ucblocks = dev->error_block_count;
  822. return 0;
  823. }
  824. static int af9033_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
  825. {
  826. struct af9033_dev *dev = fe->demodulator_priv;
  827. struct i2c_client *client = dev->client;
  828. int ret;
  829. dev_dbg(&client->dev, "enable=%d\n", enable);
  830. ret = regmap_update_bits(dev->regmap, 0x00fa04, 0x01, enable);
  831. if (ret)
  832. goto err;
  833. return 0;
  834. err:
  835. dev_dbg(&client->dev, "failed=%d\n", ret);
  836. return ret;
  837. }
  838. static int af9033_pid_filter_ctrl(struct dvb_frontend *fe, int onoff)
  839. {
  840. struct af9033_dev *dev = fe->demodulator_priv;
  841. struct i2c_client *client = dev->client;
  842. int ret;
  843. dev_dbg(&client->dev, "onoff=%d\n", onoff);
  844. ret = regmap_update_bits(dev->regmap, 0x80f993, 0x01, onoff);
  845. if (ret)
  846. goto err;
  847. return 0;
  848. err:
  849. dev_dbg(&client->dev, "failed=%d\n", ret);
  850. return ret;
  851. }
  852. static int af9033_pid_filter(struct dvb_frontend *fe, int index, u16 pid,
  853. int onoff)
  854. {
  855. struct af9033_dev *dev = fe->demodulator_priv;
  856. struct i2c_client *client = dev->client;
  857. int ret;
  858. u8 wbuf[2] = {(pid >> 0) & 0xff, (pid >> 8) & 0xff};
  859. dev_dbg(&client->dev, "index=%d pid=%04x onoff=%d\n",
  860. index, pid, onoff);
  861. if (pid > 0x1fff)
  862. return 0;
  863. ret = regmap_bulk_write(dev->regmap, 0x80f996, wbuf, 2);
  864. if (ret)
  865. goto err;
  866. ret = regmap_write(dev->regmap, 0x80f994, onoff);
  867. if (ret)
  868. goto err;
  869. ret = regmap_write(dev->regmap, 0x80f995, index);
  870. if (ret)
  871. goto err;
  872. return 0;
  873. err:
  874. dev_dbg(&client->dev, "failed=%d\n", ret);
  875. return ret;
  876. }
  877. static const struct dvb_frontend_ops af9033_ops = {
  878. .delsys = {SYS_DVBT},
  879. .info = {
  880. .name = "Afatech AF9033 (DVB-T)",
  881. .frequency_min_hz = 174 * MHz,
  882. .frequency_max_hz = 862 * MHz,
  883. .frequency_stepsize_hz = 250 * kHz,
  884. .caps = FE_CAN_FEC_1_2 |
  885. FE_CAN_FEC_2_3 |
  886. FE_CAN_FEC_3_4 |
  887. FE_CAN_FEC_5_6 |
  888. FE_CAN_FEC_7_8 |
  889. FE_CAN_FEC_AUTO |
  890. FE_CAN_QPSK |
  891. FE_CAN_QAM_16 |
  892. FE_CAN_QAM_64 |
  893. FE_CAN_QAM_AUTO |
  894. FE_CAN_TRANSMISSION_MODE_AUTO |
  895. FE_CAN_GUARD_INTERVAL_AUTO |
  896. FE_CAN_HIERARCHY_AUTO |
  897. FE_CAN_RECOVER |
  898. FE_CAN_MUTE_TS
  899. },
  900. .init = af9033_init,
  901. .sleep = af9033_sleep,
  902. .get_tune_settings = af9033_get_tune_settings,
  903. .set_frontend = af9033_set_frontend,
  904. .get_frontend = af9033_get_frontend,
  905. .read_status = af9033_read_status,
  906. .read_snr = af9033_read_snr,
  907. .read_signal_strength = af9033_read_signal_strength,
  908. .read_ber = af9033_read_ber,
  909. .read_ucblocks = af9033_read_ucblocks,
  910. .i2c_gate_ctrl = af9033_i2c_gate_ctrl,
  911. };
  912. static int af9033_probe(struct i2c_client *client,
  913. const struct i2c_device_id *id)
  914. {
  915. struct af9033_config *cfg = client->dev.platform_data;
  916. struct af9033_dev *dev;
  917. int ret;
  918. u8 buf[8];
  919. u32 reg;
  920. static const struct regmap_config regmap_config = {
  921. .reg_bits = 24,
  922. .val_bits = 8,
  923. };
  924. /* Allocate memory for the internal state */
  925. dev = kzalloc(sizeof(*dev), GFP_KERNEL);
  926. if (!dev) {
  927. ret = -ENOMEM;
  928. goto err;
  929. }
  930. /* Setup the state */
  931. dev->client = client;
  932. memcpy(&dev->cfg, cfg, sizeof(dev->cfg));
  933. switch (dev->cfg.ts_mode) {
  934. case AF9033_TS_MODE_PARALLEL:
  935. dev->ts_mode_parallel = true;
  936. break;
  937. case AF9033_TS_MODE_SERIAL:
  938. dev->ts_mode_serial = true;
  939. break;
  940. case AF9033_TS_MODE_USB:
  941. /* USB mode for AF9035 */
  942. default:
  943. break;
  944. }
  945. if (dev->cfg.clock != 12000000) {
  946. ret = -ENODEV;
  947. dev_err(&client->dev,
  948. "Unsupported clock %u Hz. Only 12000000 Hz is supported currently\n",
  949. dev->cfg.clock);
  950. goto err_kfree;
  951. }
  952. /* Create regmap */
  953. dev->regmap = regmap_init_i2c(client, &regmap_config);
  954. if (IS_ERR(dev->regmap)) {
  955. ret = PTR_ERR(dev->regmap);
  956. goto err_kfree;
  957. }
  958. /* Firmware version */
  959. switch (dev->cfg.tuner) {
  960. case AF9033_TUNER_IT9135_38:
  961. case AF9033_TUNER_IT9135_51:
  962. case AF9033_TUNER_IT9135_52:
  963. case AF9033_TUNER_IT9135_60:
  964. case AF9033_TUNER_IT9135_61:
  965. case AF9033_TUNER_IT9135_62:
  966. dev->is_it9135 = true;
  967. reg = 0x004bfc;
  968. break;
  969. default:
  970. dev->is_af9035 = true;
  971. reg = 0x0083e9;
  972. break;
  973. }
  974. ret = regmap_bulk_read(dev->regmap, reg, &buf[0], 4);
  975. if (ret)
  976. goto err_regmap_exit;
  977. ret = regmap_bulk_read(dev->regmap, 0x804191, &buf[4], 4);
  978. if (ret)
  979. goto err_regmap_exit;
  980. dev_info(&client->dev,
  981. "firmware version: LINK %d.%d.%d.%d - OFDM %d.%d.%d.%d\n",
  982. buf[0], buf[1], buf[2], buf[3],
  983. buf[4], buf[5], buf[6], buf[7]);
  984. /* Sleep as chip seems to be partly active by default */
  985. /* IT9135 did not like to sleep at that early */
  986. if (dev->is_af9035) {
  987. ret = regmap_write(dev->regmap, 0x80004c, 0x01);
  988. if (ret)
  989. goto err_regmap_exit;
  990. ret = regmap_write(dev->regmap, 0x800000, 0x00);
  991. if (ret)
  992. goto err_regmap_exit;
  993. }
  994. /* Create dvb frontend */
  995. memcpy(&dev->fe.ops, &af9033_ops, sizeof(dev->fe.ops));
  996. dev->fe.demodulator_priv = dev;
  997. *cfg->fe = &dev->fe;
  998. if (cfg->ops) {
  999. cfg->ops->pid_filter = af9033_pid_filter;
  1000. cfg->ops->pid_filter_ctrl = af9033_pid_filter_ctrl;
  1001. }
  1002. cfg->regmap = dev->regmap;
  1003. i2c_set_clientdata(client, dev);
  1004. dev_info(&client->dev, "Afatech AF9033 successfully attached\n");
  1005. return 0;
  1006. err_regmap_exit:
  1007. regmap_exit(dev->regmap);
  1008. err_kfree:
  1009. kfree(dev);
  1010. err:
  1011. dev_dbg(&client->dev, "failed=%d\n", ret);
  1012. return ret;
  1013. }
  1014. static int af9033_remove(struct i2c_client *client)
  1015. {
  1016. struct af9033_dev *dev = i2c_get_clientdata(client);
  1017. dev_dbg(&client->dev, "\n");
  1018. regmap_exit(dev->regmap);
  1019. kfree(dev);
  1020. return 0;
  1021. }
  1022. static const struct i2c_device_id af9033_id_table[] = {
  1023. {"af9033", 0},
  1024. {}
  1025. };
  1026. MODULE_DEVICE_TABLE(i2c, af9033_id_table);
  1027. static struct i2c_driver af9033_driver = {
  1028. .driver = {
  1029. .name = "af9033",
  1030. .suppress_bind_attrs = true,
  1031. },
  1032. .probe = af9033_probe,
  1033. .remove = af9033_remove,
  1034. .id_table = af9033_id_table,
  1035. };
  1036. module_i2c_driver(af9033_driver);
  1037. MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
  1038. MODULE_DESCRIPTION("Afatech AF9033 DVB-T demodulator driver");
  1039. MODULE_LICENSE("GPL");