mcb-internal.h 3.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. #ifndef __MCB_INTERNAL
  3. #define __MCB_INTERNAL
  4. #include <linux/types.h>
  5. #define PCI_VENDOR_ID_MEN 0x1a88
  6. #define PCI_DEVICE_ID_MEN_CHAMELEON 0x4d45
  7. #define CHAMELEONV2_MAGIC 0xabce
  8. #define CHAM_HEADER_SIZE 0x200
  9. enum chameleon_descriptor_type {
  10. CHAMELEON_DTYPE_GENERAL = 0x0,
  11. CHAMELEON_DTYPE_BRIDGE = 0x1,
  12. CHAMELEON_DTYPE_CPU = 0x2,
  13. CHAMELEON_DTYPE_BAR = 0x3,
  14. CHAMELEON_DTYPE_END = 0xf,
  15. };
  16. enum chameleon_bus_type {
  17. CHAMELEON_BUS_WISHBONE,
  18. CHAMELEON_BUS_AVALON,
  19. CHAMELEON_BUS_LPC,
  20. CHAMELEON_BUS_ISA,
  21. };
  22. /**
  23. * struct chameleon_fpga_header
  24. *
  25. * @revision: Revison of Chameleon table in FPGA
  26. * @model: Chameleon table model ASCII char
  27. * @minor: Revision minor
  28. * @bus_type: Bus type (usually %CHAMELEON_BUS_WISHBONE)
  29. * @magic: Chameleon header magic number (0xabce for version 2)
  30. * @reserved: Reserved
  31. * @filename: Filename of FPGA bitstream
  32. */
  33. struct chameleon_fpga_header {
  34. u8 revision;
  35. char model;
  36. u8 minor;
  37. u8 bus_type;
  38. u16 magic;
  39. u16 reserved;
  40. /* This one has no '\0' at the end!!! */
  41. char filename[CHAMELEON_FILENAME_LEN];
  42. } __packed;
  43. #define HEADER_MAGIC_OFFSET 0x4
  44. /**
  45. * struct chameleon_gdd - Chameleon General Device Descriptor
  46. *
  47. * @irq: the position in the FPGA's IRQ controller vector
  48. * @rev: the revision of the variant's implementation
  49. * @var: the variant of the IP core
  50. * @dev: the device the IP core is
  51. * @dtype: device descriptor type
  52. * @bar: BAR offset that must be added to module offset
  53. * @inst: the instance number of the device, 0 is first instance
  54. * @group: the group the device belongs to (0 = no group)
  55. * @reserved: reserved
  56. * @offset: beginning of the address window of desired module
  57. * @size: size of the module's address window
  58. */
  59. struct chameleon_gdd {
  60. __le32 reg1;
  61. __le32 reg2;
  62. __le32 offset;
  63. __le32 size;
  64. } __packed;
  65. /* GDD Register 1 fields */
  66. #define GDD_IRQ(x) ((x) & 0x1f)
  67. #define GDD_REV(x) (((x) >> 5) & 0x3f)
  68. #define GDD_VAR(x) (((x) >> 11) & 0x3f)
  69. #define GDD_DEV(x) (((x) >> 18) & 0x3ff)
  70. #define GDD_DTY(x) (((x) >> 28) & 0xf)
  71. /* GDD Register 2 fields */
  72. #define GDD_BAR(x) ((x) & 0x7)
  73. #define GDD_INS(x) (((x) >> 3) & 0x3f)
  74. #define GDD_GRP(x) (((x) >> 9) & 0x3f)
  75. /**
  76. * struct chameleon_bdd - Chameleon Bridge Device Descriptor
  77. *
  78. * @irq: the position in the FPGA's IRQ controller vector
  79. * @rev: the revision of the variant's implementation
  80. * @var: the variant of the IP core
  81. * @dev: the device the IP core is
  82. * @dtype: device descriptor type
  83. * @bar: BAR offset that must be added to module offset
  84. * @inst: the instance number of the device, 0 is first instance
  85. * @dbar: destination bar from the bus _behind_ the bridge
  86. * @chamoff: offset within the BAR of the source bus
  87. * @offset:
  88. * @size:
  89. */
  90. struct chameleon_bdd {
  91. unsigned int irq:6;
  92. unsigned int rev:6;
  93. unsigned int var:6;
  94. unsigned int dev:10;
  95. unsigned int dtype:4;
  96. unsigned int bar:3;
  97. unsigned int inst:6;
  98. unsigned int dbar:3;
  99. unsigned int group:6;
  100. unsigned int reserved:14;
  101. u32 chamoff;
  102. u32 offset;
  103. u32 size;
  104. } __packed;
  105. struct chameleon_bar {
  106. u32 addr;
  107. u32 size;
  108. };
  109. #define BAR_CNT(x) ((x) & 0x07)
  110. #define CHAMELEON_BAR_MAX 6
  111. #define BAR_DESC_SIZE(x) ((x) * sizeof(struct chameleon_bar) + sizeof(__le32))
  112. int chameleon_parse_cells(struct mcb_bus *bus, phys_addr_t mapbase,
  113. void __iomem *base);
  114. #endif