ti-msgmgr.c 24 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Texas Instruments' Message Manager Driver
  4. *
  5. * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/
  6. * Nishanth Menon
  7. */
  8. #define pr_fmt(fmt) "%s: " fmt, __func__
  9. #include <linux/device.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/io.h>
  12. #include <linux/kernel.h>
  13. #include <linux/mailbox_controller.h>
  14. #include <linux/module.h>
  15. #include <linux/of_device.h>
  16. #include <linux/of.h>
  17. #include <linux/of_irq.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/soc/ti/ti-msgmgr.h>
  20. #define Q_DATA_OFFSET(proxy, queue, reg) \
  21. ((0x10000 * (proxy)) + (0x80 * (queue)) + ((reg) * 4))
  22. #define Q_STATE_OFFSET(queue) ((queue) * 0x4)
  23. #define Q_STATE_ENTRY_COUNT_MASK (0xFFF000)
  24. #define SPROXY_THREAD_OFFSET(tid) (0x1000 * (tid))
  25. #define SPROXY_THREAD_DATA_OFFSET(tid, reg) \
  26. (SPROXY_THREAD_OFFSET(tid) + ((reg) * 0x4) + 0x4)
  27. #define SPROXY_THREAD_STATUS_OFFSET(tid) (SPROXY_THREAD_OFFSET(tid))
  28. #define SPROXY_THREAD_STATUS_COUNT_MASK (0xFF)
  29. #define SPROXY_THREAD_CTRL_OFFSET(tid) (0x1000 + SPROXY_THREAD_OFFSET(tid))
  30. #define SPROXY_THREAD_CTRL_DIR_MASK (0x1 << 31)
  31. /**
  32. * struct ti_msgmgr_valid_queue_desc - SoC valid queues meant for this processor
  33. * @queue_id: Queue Number for this path
  34. * @proxy_id: Proxy ID representing the processor in SoC
  35. * @is_tx: Is this a receive path?
  36. */
  37. struct ti_msgmgr_valid_queue_desc {
  38. u8 queue_id;
  39. u8 proxy_id;
  40. bool is_tx;
  41. };
  42. /**
  43. * struct ti_msgmgr_desc - Description of message manager integration
  44. * @queue_count: Number of Queues
  45. * @max_message_size: Message size in bytes
  46. * @max_messages: Number of messages
  47. * @data_first_reg: First data register for proxy data region
  48. * @data_last_reg: Last data register for proxy data region
  49. * @status_cnt_mask: Mask for getting the status value
  50. * @status_err_mask: Mask for getting the error value, if applicable
  51. * @tx_polled: Do I need to use polled mechanism for tx
  52. * @tx_poll_timeout_ms: Timeout in ms if polled
  53. * @valid_queues: List of Valid queues that the processor can access
  54. * @data_region_name: Name of the proxy data region
  55. * @status_region_name: Name of the proxy status region
  56. * @ctrl_region_name: Name of the proxy control region
  57. * @num_valid_queues: Number of valid queues
  58. * @is_sproxy: Is this an Secure Proxy instance?
  59. *
  60. * This structure is used in of match data to describe how integration
  61. * for a specific compatible SoC is done.
  62. */
  63. struct ti_msgmgr_desc {
  64. u8 queue_count;
  65. u8 max_message_size;
  66. u8 max_messages;
  67. u8 data_first_reg;
  68. u8 data_last_reg;
  69. u32 status_cnt_mask;
  70. u32 status_err_mask;
  71. bool tx_polled;
  72. int tx_poll_timeout_ms;
  73. const struct ti_msgmgr_valid_queue_desc *valid_queues;
  74. const char *data_region_name;
  75. const char *status_region_name;
  76. const char *ctrl_region_name;
  77. int num_valid_queues;
  78. bool is_sproxy;
  79. };
  80. /**
  81. * struct ti_queue_inst - Description of a queue instance
  82. * @name: Queue Name
  83. * @queue_id: Queue Identifier as mapped on SoC
  84. * @proxy_id: Proxy Identifier as mapped on SoC
  85. * @irq: IRQ for Rx Queue
  86. * @is_tx: 'true' if transmit queue, else, 'false'
  87. * @queue_buff_start: First register of Data Buffer
  88. * @queue_buff_end: Last (or confirmation) register of Data buffer
  89. * @queue_state: Queue status register
  90. * @queue_ctrl: Queue Control register
  91. * @chan: Mailbox channel
  92. * @rx_buff: Receive buffer pointer allocated at probe, max_message_size
  93. */
  94. struct ti_queue_inst {
  95. char name[30];
  96. u8 queue_id;
  97. u8 proxy_id;
  98. int irq;
  99. bool is_tx;
  100. void __iomem *queue_buff_start;
  101. void __iomem *queue_buff_end;
  102. void __iomem *queue_state;
  103. void __iomem *queue_ctrl;
  104. struct mbox_chan *chan;
  105. u32 *rx_buff;
  106. };
  107. /**
  108. * struct ti_msgmgr_inst - Description of a Message Manager Instance
  109. * @dev: device pointer corresponding to the Message Manager instance
  110. * @desc: Description of the SoC integration
  111. * @queue_proxy_region: Queue proxy region where queue buffers are located
  112. * @queue_state_debug_region: Queue status register regions
  113. * @queue_ctrl_region: Queue Control register regions
  114. * @num_valid_queues: Number of valid queues defined for the processor
  115. * Note: other queues are probably reserved for other processors
  116. * in the SoC.
  117. * @qinsts: Array of valid Queue Instances for the Processor
  118. * @mbox: Mailbox Controller
  119. * @chans: Array for channels corresponding to the Queue Instances.
  120. */
  121. struct ti_msgmgr_inst {
  122. struct device *dev;
  123. const struct ti_msgmgr_desc *desc;
  124. void __iomem *queue_proxy_region;
  125. void __iomem *queue_state_debug_region;
  126. void __iomem *queue_ctrl_region;
  127. u8 num_valid_queues;
  128. struct ti_queue_inst *qinsts;
  129. struct mbox_controller mbox;
  130. struct mbox_chan *chans;
  131. };
  132. /**
  133. * ti_msgmgr_queue_get_num_messages() - Get the number of pending messages
  134. * @d: Description of message manager
  135. * @qinst: Queue instance for which we check the number of pending messages
  136. *
  137. * Return: number of messages pending in the queue (0 == no pending messages)
  138. */
  139. static inline int
  140. ti_msgmgr_queue_get_num_messages(const struct ti_msgmgr_desc *d,
  141. struct ti_queue_inst *qinst)
  142. {
  143. u32 val;
  144. u32 status_cnt_mask = d->status_cnt_mask;
  145. /*
  146. * We cannot use relaxed operation here - update may happen
  147. * real-time.
  148. */
  149. val = readl(qinst->queue_state) & status_cnt_mask;
  150. val >>= __ffs(status_cnt_mask);
  151. return val;
  152. }
  153. /**
  154. * ti_msgmgr_queue_is_error() - Check to see if there is queue error
  155. * @d: Description of message manager
  156. * @qinst: Queue instance for which we check the number of pending messages
  157. *
  158. * Return: true if error, else false
  159. */
  160. static inline bool ti_msgmgr_queue_is_error(const struct ti_msgmgr_desc *d,
  161. struct ti_queue_inst *qinst)
  162. {
  163. u32 val;
  164. /* Msgmgr has no error detection */
  165. if (!d->is_sproxy)
  166. return false;
  167. /*
  168. * We cannot use relaxed operation here - update may happen
  169. * real-time.
  170. */
  171. val = readl(qinst->queue_state) & d->status_err_mask;
  172. return val ? true : false;
  173. }
  174. /**
  175. * ti_msgmgr_queue_rx_interrupt() - Interrupt handler for receive Queue
  176. * @irq: Interrupt number
  177. * @p: Channel Pointer
  178. *
  179. * Return: -EINVAL if there is no instance
  180. * IRQ_NONE if the interrupt is not ours.
  181. * IRQ_HANDLED if the rx interrupt was successfully handled.
  182. */
  183. static irqreturn_t ti_msgmgr_queue_rx_interrupt(int irq, void *p)
  184. {
  185. struct mbox_chan *chan = p;
  186. struct device *dev = chan->mbox->dev;
  187. struct ti_msgmgr_inst *inst = dev_get_drvdata(dev);
  188. struct ti_queue_inst *qinst = chan->con_priv;
  189. const struct ti_msgmgr_desc *desc;
  190. int msg_count, num_words;
  191. struct ti_msgmgr_message message;
  192. void __iomem *data_reg;
  193. u32 *word_data;
  194. if (WARN_ON(!inst)) {
  195. dev_err(dev, "no platform drv data??\n");
  196. return -EINVAL;
  197. }
  198. /* Do I have an invalid interrupt source? */
  199. if (qinst->is_tx) {
  200. dev_err(dev, "Cannot handle rx interrupt on tx channel %s\n",
  201. qinst->name);
  202. return IRQ_NONE;
  203. }
  204. desc = inst->desc;
  205. if (ti_msgmgr_queue_is_error(desc, qinst)) {
  206. dev_err(dev, "Error on Rx channel %s\n", qinst->name);
  207. return IRQ_NONE;
  208. }
  209. /* Do I actually have messages to read? */
  210. msg_count = ti_msgmgr_queue_get_num_messages(desc, qinst);
  211. if (!msg_count) {
  212. /* Shared IRQ? */
  213. dev_dbg(dev, "Spurious event - 0 pending data!\n");
  214. return IRQ_NONE;
  215. }
  216. /*
  217. * I have no idea about the protocol being used to communicate with the
  218. * remote producer - 0 could be valid data, so I wont make a judgement
  219. * of how many bytes I should be reading. Let the client figure this
  220. * out.. I just read the full message and pass it on..
  221. */
  222. message.len = desc->max_message_size;
  223. message.buf = (u8 *)qinst->rx_buff;
  224. /*
  225. * NOTE about register access involved here:
  226. * the hardware block is implemented with 32bit access operations and no
  227. * support for data splitting. We don't want the hardware to misbehave
  228. * with sub 32bit access - For example: if the last register read is
  229. * split into byte wise access, it can result in the queue getting
  230. * stuck or indeterminate behavior. An out of order read operation may
  231. * result in weird data results as well.
  232. * Hence, we do not use memcpy_fromio or __ioread32_copy here, instead
  233. * we depend on readl for the purpose.
  234. *
  235. * Also note that the final register read automatically marks the
  236. * queue message as read.
  237. */
  238. for (data_reg = qinst->queue_buff_start, word_data = qinst->rx_buff,
  239. num_words = (desc->max_message_size / sizeof(u32));
  240. num_words; num_words--, data_reg += sizeof(u32), word_data++)
  241. *word_data = readl(data_reg);
  242. /*
  243. * Last register read automatically clears the IRQ if only 1 message
  244. * is pending - so send the data up the stack..
  245. * NOTE: Client is expected to be as optimal as possible, since
  246. * we invoke the handler in IRQ context.
  247. */
  248. mbox_chan_received_data(chan, (void *)&message);
  249. return IRQ_HANDLED;
  250. }
  251. /**
  252. * ti_msgmgr_queue_peek_data() - Peek to see if there are any rx messages.
  253. * @chan: Channel Pointer
  254. *
  255. * Return: 'true' if there is pending rx data, 'false' if there is none.
  256. */
  257. static bool ti_msgmgr_queue_peek_data(struct mbox_chan *chan)
  258. {
  259. struct ti_queue_inst *qinst = chan->con_priv;
  260. struct device *dev = chan->mbox->dev;
  261. struct ti_msgmgr_inst *inst = dev_get_drvdata(dev);
  262. const struct ti_msgmgr_desc *desc = inst->desc;
  263. int msg_count;
  264. if (qinst->is_tx)
  265. return false;
  266. if (ti_msgmgr_queue_is_error(desc, qinst)) {
  267. dev_err(dev, "Error on channel %s\n", qinst->name);
  268. return false;
  269. }
  270. msg_count = ti_msgmgr_queue_get_num_messages(desc, qinst);
  271. return msg_count ? true : false;
  272. }
  273. /**
  274. * ti_msgmgr_last_tx_done() - See if all the tx messages are sent
  275. * @chan: Channel pointer
  276. *
  277. * Return: 'true' is no pending tx data, 'false' if there are any.
  278. */
  279. static bool ti_msgmgr_last_tx_done(struct mbox_chan *chan)
  280. {
  281. struct ti_queue_inst *qinst = chan->con_priv;
  282. struct device *dev = chan->mbox->dev;
  283. struct ti_msgmgr_inst *inst = dev_get_drvdata(dev);
  284. const struct ti_msgmgr_desc *desc = inst->desc;
  285. int msg_count;
  286. if (!qinst->is_tx)
  287. return false;
  288. if (ti_msgmgr_queue_is_error(desc, qinst)) {
  289. dev_err(dev, "Error on channel %s\n", qinst->name);
  290. return false;
  291. }
  292. msg_count = ti_msgmgr_queue_get_num_messages(desc, qinst);
  293. if (desc->is_sproxy) {
  294. /* In secure proxy, msg_count indicates how many we can send */
  295. return msg_count ? true : false;
  296. }
  297. /* if we have any messages pending.. */
  298. return msg_count ? false : true;
  299. }
  300. /**
  301. * ti_msgmgr_send_data() - Send data
  302. * @chan: Channel Pointer
  303. * @data: ti_msgmgr_message * Message Pointer
  304. *
  305. * Return: 0 if all goes good, else appropriate error messages.
  306. */
  307. static int ti_msgmgr_send_data(struct mbox_chan *chan, void *data)
  308. {
  309. struct device *dev = chan->mbox->dev;
  310. struct ti_msgmgr_inst *inst = dev_get_drvdata(dev);
  311. const struct ti_msgmgr_desc *desc;
  312. struct ti_queue_inst *qinst = chan->con_priv;
  313. int num_words, trail_bytes;
  314. struct ti_msgmgr_message *message = data;
  315. void __iomem *data_reg;
  316. u32 *word_data;
  317. if (WARN_ON(!inst)) {
  318. dev_err(dev, "no platform drv data??\n");
  319. return -EINVAL;
  320. }
  321. desc = inst->desc;
  322. if (ti_msgmgr_queue_is_error(desc, qinst)) {
  323. dev_err(dev, "Error on channel %s\n", qinst->name);
  324. return false;
  325. }
  326. if (desc->max_message_size < message->len) {
  327. dev_err(dev, "Queue %s message length %zu > max %d\n",
  328. qinst->name, message->len, desc->max_message_size);
  329. return -EINVAL;
  330. }
  331. /* NOTE: Constraints similar to rx path exists here as well */
  332. for (data_reg = qinst->queue_buff_start,
  333. num_words = message->len / sizeof(u32),
  334. word_data = (u32 *)message->buf;
  335. num_words; num_words--, data_reg += sizeof(u32), word_data++)
  336. writel(*word_data, data_reg);
  337. trail_bytes = message->len % sizeof(u32);
  338. if (trail_bytes) {
  339. u32 data_trail = *word_data;
  340. /* Ensure all unused data is 0 */
  341. data_trail &= 0xFFFFFFFF >> (8 * (sizeof(u32) - trail_bytes));
  342. writel(data_trail, data_reg);
  343. data_reg++;
  344. }
  345. /*
  346. * 'data_reg' indicates next register to write. If we did not already
  347. * write on tx complete reg(last reg), we must do so for transmit
  348. */
  349. if (data_reg <= qinst->queue_buff_end)
  350. writel(0, qinst->queue_buff_end);
  351. return 0;
  352. }
  353. /**
  354. * ti_msgmgr_queue_rx_irq_req() - RX IRQ request
  355. * @dev: device pointer
  356. * @d: descriptor for ti_msgmgr
  357. * @qinst: Queue instance
  358. * @chan: Channel pointer
  359. */
  360. static int ti_msgmgr_queue_rx_irq_req(struct device *dev,
  361. const struct ti_msgmgr_desc *d,
  362. struct ti_queue_inst *qinst,
  363. struct mbox_chan *chan)
  364. {
  365. int ret = 0;
  366. char of_rx_irq_name[7];
  367. struct device_node *np;
  368. snprintf(of_rx_irq_name, sizeof(of_rx_irq_name),
  369. "rx_%03d", d->is_sproxy ? qinst->proxy_id : qinst->queue_id);
  370. /* Get the IRQ if not found */
  371. if (qinst->irq < 0) {
  372. np = of_node_get(dev->of_node);
  373. if (!np)
  374. return -ENODATA;
  375. qinst->irq = of_irq_get_byname(np, of_rx_irq_name);
  376. of_node_put(np);
  377. if (qinst->irq < 0) {
  378. dev_err(dev,
  379. "QID %d PID %d:No IRQ[%s]: %d\n",
  380. qinst->queue_id, qinst->proxy_id,
  381. of_rx_irq_name, qinst->irq);
  382. return qinst->irq;
  383. }
  384. }
  385. /* With the expectation that the IRQ might be shared in SoC */
  386. ret = request_irq(qinst->irq, ti_msgmgr_queue_rx_interrupt,
  387. IRQF_SHARED, qinst->name, chan);
  388. if (ret) {
  389. dev_err(dev, "Unable to get IRQ %d on %s(res=%d)\n",
  390. qinst->irq, qinst->name, ret);
  391. }
  392. return ret;
  393. }
  394. /**
  395. * ti_msgmgr_queue_startup() - Startup queue
  396. * @chan: Channel pointer
  397. *
  398. * Return: 0 if all goes good, else return corresponding error message
  399. */
  400. static int ti_msgmgr_queue_startup(struct mbox_chan *chan)
  401. {
  402. struct device *dev = chan->mbox->dev;
  403. struct ti_msgmgr_inst *inst = dev_get_drvdata(dev);
  404. struct ti_queue_inst *qinst = chan->con_priv;
  405. const struct ti_msgmgr_desc *d = inst->desc;
  406. int ret;
  407. int msg_count;
  408. /*
  409. * If sproxy is starting and can send messages, we are a Tx thread,
  410. * else Rx
  411. */
  412. if (d->is_sproxy) {
  413. qinst->is_tx = (readl(qinst->queue_ctrl) &
  414. SPROXY_THREAD_CTRL_DIR_MASK) ? false : true;
  415. msg_count = ti_msgmgr_queue_get_num_messages(d, qinst);
  416. if (!msg_count && qinst->is_tx) {
  417. dev_err(dev, "%s: Cannot transmit with 0 credits!\n",
  418. qinst->name);
  419. return -EINVAL;
  420. }
  421. }
  422. if (!qinst->is_tx) {
  423. /* Allocate usage buffer for rx */
  424. qinst->rx_buff = kzalloc(d->max_message_size, GFP_KERNEL);
  425. if (!qinst->rx_buff)
  426. return -ENOMEM;
  427. /* Request IRQ */
  428. ret = ti_msgmgr_queue_rx_irq_req(dev, d, qinst, chan);
  429. if (ret) {
  430. kfree(qinst->rx_buff);
  431. return ret;
  432. }
  433. }
  434. return 0;
  435. }
  436. /**
  437. * ti_msgmgr_queue_shutdown() - Shutdown the queue
  438. * @chan: Channel pointer
  439. */
  440. static void ti_msgmgr_queue_shutdown(struct mbox_chan *chan)
  441. {
  442. struct ti_queue_inst *qinst = chan->con_priv;
  443. if (!qinst->is_tx) {
  444. free_irq(qinst->irq, chan);
  445. kfree(qinst->rx_buff);
  446. }
  447. }
  448. /**
  449. * ti_msgmgr_of_xlate() - Translation of phandle to queue
  450. * @mbox: Mailbox controller
  451. * @p: phandle pointer
  452. *
  453. * Return: Mailbox channel corresponding to the queue, else return error
  454. * pointer.
  455. */
  456. static struct mbox_chan *ti_msgmgr_of_xlate(struct mbox_controller *mbox,
  457. const struct of_phandle_args *p)
  458. {
  459. struct ti_msgmgr_inst *inst;
  460. int req_qid, req_pid;
  461. struct ti_queue_inst *qinst;
  462. const struct ti_msgmgr_desc *d;
  463. int i, ncells;
  464. inst = container_of(mbox, struct ti_msgmgr_inst, mbox);
  465. if (WARN_ON(!inst))
  466. return ERR_PTR(-EINVAL);
  467. d = inst->desc;
  468. if (d->is_sproxy)
  469. ncells = 1;
  470. else
  471. ncells = 2;
  472. if (p->args_count != ncells) {
  473. dev_err(inst->dev, "Invalid arguments in dt[%d]. Must be %d\n",
  474. p->args_count, ncells);
  475. return ERR_PTR(-EINVAL);
  476. }
  477. if (ncells == 1) {
  478. req_qid = 0;
  479. req_pid = p->args[0];
  480. } else {
  481. req_qid = p->args[0];
  482. req_pid = p->args[1];
  483. }
  484. if (d->is_sproxy) {
  485. if (req_pid >= d->num_valid_queues)
  486. goto err;
  487. qinst = &inst->qinsts[req_pid];
  488. return qinst->chan;
  489. }
  490. for (qinst = inst->qinsts, i = 0; i < inst->num_valid_queues;
  491. i++, qinst++) {
  492. if (req_qid == qinst->queue_id && req_pid == qinst->proxy_id)
  493. return qinst->chan;
  494. }
  495. err:
  496. dev_err(inst->dev, "Queue ID %d, Proxy ID %d is wrong on %pOFn\n",
  497. req_qid, req_pid, p->np);
  498. return ERR_PTR(-ENOENT);
  499. }
  500. /**
  501. * ti_msgmgr_queue_setup() - Setup data structures for each queue instance
  502. * @idx: index of the queue
  503. * @dev: pointer to the message manager device
  504. * @np: pointer to the of node
  505. * @inst: Queue instance pointer
  506. * @d: Message Manager instance description data
  507. * @qd: Queue description data
  508. * @qinst: Queue instance pointer
  509. * @chan: pointer to mailbox channel
  510. *
  511. * Return: 0 if all went well, else return corresponding error
  512. */
  513. static int ti_msgmgr_queue_setup(int idx, struct device *dev,
  514. struct device_node *np,
  515. struct ti_msgmgr_inst *inst,
  516. const struct ti_msgmgr_desc *d,
  517. const struct ti_msgmgr_valid_queue_desc *qd,
  518. struct ti_queue_inst *qinst,
  519. struct mbox_chan *chan)
  520. {
  521. char *dir;
  522. qinst->proxy_id = qd->proxy_id;
  523. qinst->queue_id = qd->queue_id;
  524. if (qinst->queue_id > d->queue_count) {
  525. dev_err(dev, "Queue Data [idx=%d] queuid %d > %d\n",
  526. idx, qinst->queue_id, d->queue_count);
  527. return -ERANGE;
  528. }
  529. if (d->is_sproxy) {
  530. qinst->queue_buff_start = inst->queue_proxy_region +
  531. SPROXY_THREAD_DATA_OFFSET(qinst->proxy_id,
  532. d->data_first_reg);
  533. qinst->queue_buff_end = inst->queue_proxy_region +
  534. SPROXY_THREAD_DATA_OFFSET(qinst->proxy_id,
  535. d->data_last_reg);
  536. qinst->queue_state = inst->queue_state_debug_region +
  537. SPROXY_THREAD_STATUS_OFFSET(qinst->proxy_id);
  538. qinst->queue_ctrl = inst->queue_ctrl_region +
  539. SPROXY_THREAD_CTRL_OFFSET(qinst->proxy_id);
  540. /* XXX: DONOT read registers here!.. Some may be unusable */
  541. dir = "thr";
  542. snprintf(qinst->name, sizeof(qinst->name), "%s %s_%03d",
  543. dev_name(dev), dir, qinst->proxy_id);
  544. } else {
  545. qinst->queue_buff_start = inst->queue_proxy_region +
  546. Q_DATA_OFFSET(qinst->proxy_id, qinst->queue_id,
  547. d->data_first_reg);
  548. qinst->queue_buff_end = inst->queue_proxy_region +
  549. Q_DATA_OFFSET(qinst->proxy_id, qinst->queue_id,
  550. d->data_last_reg);
  551. qinst->queue_state =
  552. inst->queue_state_debug_region +
  553. Q_STATE_OFFSET(qinst->queue_id);
  554. qinst->is_tx = qd->is_tx;
  555. dir = qinst->is_tx ? "tx" : "rx";
  556. snprintf(qinst->name, sizeof(qinst->name), "%s %s_%03d_%03d",
  557. dev_name(dev), dir, qinst->queue_id, qinst->proxy_id);
  558. }
  559. qinst->chan = chan;
  560. /* Setup an error value for IRQ - Lazy allocation */
  561. qinst->irq = -EINVAL;
  562. chan->con_priv = qinst;
  563. dev_dbg(dev, "[%d] qidx=%d pidx=%d irq=%d q_s=%p q_e = %p\n",
  564. idx, qinst->queue_id, qinst->proxy_id, qinst->irq,
  565. qinst->queue_buff_start, qinst->queue_buff_end);
  566. return 0;
  567. }
  568. /* Queue operations */
  569. static const struct mbox_chan_ops ti_msgmgr_chan_ops = {
  570. .startup = ti_msgmgr_queue_startup,
  571. .shutdown = ti_msgmgr_queue_shutdown,
  572. .peek_data = ti_msgmgr_queue_peek_data,
  573. .last_tx_done = ti_msgmgr_last_tx_done,
  574. .send_data = ti_msgmgr_send_data,
  575. };
  576. /* Keystone K2G SoC integration details */
  577. static const struct ti_msgmgr_valid_queue_desc k2g_valid_queues[] = {
  578. {.queue_id = 0, .proxy_id = 0, .is_tx = true,},
  579. {.queue_id = 1, .proxy_id = 0, .is_tx = true,},
  580. {.queue_id = 2, .proxy_id = 0, .is_tx = true,},
  581. {.queue_id = 3, .proxy_id = 0, .is_tx = true,},
  582. {.queue_id = 5, .proxy_id = 2, .is_tx = false,},
  583. {.queue_id = 56, .proxy_id = 1, .is_tx = true,},
  584. {.queue_id = 57, .proxy_id = 2, .is_tx = false,},
  585. {.queue_id = 58, .proxy_id = 3, .is_tx = true,},
  586. {.queue_id = 59, .proxy_id = 4, .is_tx = true,},
  587. {.queue_id = 60, .proxy_id = 5, .is_tx = true,},
  588. {.queue_id = 61, .proxy_id = 6, .is_tx = true,},
  589. };
  590. static const struct ti_msgmgr_desc k2g_desc = {
  591. .queue_count = 64,
  592. .max_message_size = 64,
  593. .max_messages = 128,
  594. .data_region_name = "queue_proxy_region",
  595. .status_region_name = "queue_state_debug_region",
  596. .data_first_reg = 16,
  597. .data_last_reg = 31,
  598. .status_cnt_mask = Q_STATE_ENTRY_COUNT_MASK,
  599. .tx_polled = false,
  600. .valid_queues = k2g_valid_queues,
  601. .num_valid_queues = ARRAY_SIZE(k2g_valid_queues),
  602. .is_sproxy = false,
  603. };
  604. static const struct ti_msgmgr_desc am654_desc = {
  605. .queue_count = 190,
  606. .num_valid_queues = 190,
  607. .max_message_size = 60,
  608. .data_region_name = "target_data",
  609. .status_region_name = "rt",
  610. .ctrl_region_name = "scfg",
  611. .data_first_reg = 0,
  612. .data_last_reg = 14,
  613. .status_cnt_mask = SPROXY_THREAD_STATUS_COUNT_MASK,
  614. .tx_polled = false,
  615. .is_sproxy = true,
  616. };
  617. static const struct of_device_id ti_msgmgr_of_match[] = {
  618. {.compatible = "ti,k2g-message-manager", .data = &k2g_desc},
  619. {.compatible = "ti,am654-secure-proxy", .data = &am654_desc},
  620. { /* Sentinel */ }
  621. };
  622. MODULE_DEVICE_TABLE(of, ti_msgmgr_of_match);
  623. static int ti_msgmgr_probe(struct platform_device *pdev)
  624. {
  625. struct device *dev = &pdev->dev;
  626. const struct of_device_id *of_id;
  627. struct device_node *np;
  628. struct resource *res;
  629. const struct ti_msgmgr_desc *desc;
  630. struct ti_msgmgr_inst *inst;
  631. struct ti_queue_inst *qinst;
  632. struct mbox_controller *mbox;
  633. struct mbox_chan *chans;
  634. int queue_count;
  635. int i;
  636. int ret = -EINVAL;
  637. const struct ti_msgmgr_valid_queue_desc *queue_desc;
  638. if (!dev->of_node) {
  639. dev_err(dev, "no OF information\n");
  640. return -EINVAL;
  641. }
  642. np = dev->of_node;
  643. of_id = of_match_device(ti_msgmgr_of_match, dev);
  644. if (!of_id) {
  645. dev_err(dev, "OF data missing\n");
  646. return -EINVAL;
  647. }
  648. desc = of_id->data;
  649. inst = devm_kzalloc(dev, sizeof(*inst), GFP_KERNEL);
  650. if (!inst)
  651. return -ENOMEM;
  652. inst->dev = dev;
  653. inst->desc = desc;
  654. res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  655. desc->data_region_name);
  656. inst->queue_proxy_region = devm_ioremap_resource(dev, res);
  657. if (IS_ERR(inst->queue_proxy_region))
  658. return PTR_ERR(inst->queue_proxy_region);
  659. res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  660. desc->status_region_name);
  661. inst->queue_state_debug_region = devm_ioremap_resource(dev, res);
  662. if (IS_ERR(inst->queue_state_debug_region))
  663. return PTR_ERR(inst->queue_state_debug_region);
  664. if (desc->is_sproxy) {
  665. res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  666. desc->ctrl_region_name);
  667. inst->queue_ctrl_region = devm_ioremap_resource(dev, res);
  668. if (IS_ERR(inst->queue_ctrl_region))
  669. return PTR_ERR(inst->queue_ctrl_region);
  670. }
  671. dev_dbg(dev, "proxy region=%p, queue_state=%p\n",
  672. inst->queue_proxy_region, inst->queue_state_debug_region);
  673. queue_count = desc->num_valid_queues;
  674. if (!queue_count || queue_count > desc->queue_count) {
  675. dev_crit(dev, "Invalid Number of queues %d. Max %d\n",
  676. queue_count, desc->queue_count);
  677. return -ERANGE;
  678. }
  679. inst->num_valid_queues = queue_count;
  680. qinst = devm_kcalloc(dev, queue_count, sizeof(*qinst), GFP_KERNEL);
  681. if (!qinst)
  682. return -ENOMEM;
  683. inst->qinsts = qinst;
  684. chans = devm_kcalloc(dev, queue_count, sizeof(*chans), GFP_KERNEL);
  685. if (!chans)
  686. return -ENOMEM;
  687. inst->chans = chans;
  688. if (desc->is_sproxy) {
  689. struct ti_msgmgr_valid_queue_desc sproxy_desc;
  690. /* All proxies may be valid in Secure Proxy instance */
  691. for (i = 0; i < queue_count; i++, qinst++, chans++) {
  692. sproxy_desc.queue_id = 0;
  693. sproxy_desc.proxy_id = i;
  694. ret = ti_msgmgr_queue_setup(i, dev, np, inst,
  695. desc, &sproxy_desc, qinst,
  696. chans);
  697. if (ret)
  698. return ret;
  699. }
  700. } else {
  701. /* Only Some proxies are valid in Message Manager */
  702. for (i = 0, queue_desc = desc->valid_queues;
  703. i < queue_count; i++, qinst++, chans++, queue_desc++) {
  704. ret = ti_msgmgr_queue_setup(i, dev, np, inst,
  705. desc, queue_desc, qinst,
  706. chans);
  707. if (ret)
  708. return ret;
  709. }
  710. }
  711. mbox = &inst->mbox;
  712. mbox->dev = dev;
  713. mbox->ops = &ti_msgmgr_chan_ops;
  714. mbox->chans = inst->chans;
  715. mbox->num_chans = inst->num_valid_queues;
  716. mbox->txdone_irq = false;
  717. mbox->txdone_poll = desc->tx_polled;
  718. if (desc->tx_polled)
  719. mbox->txpoll_period = desc->tx_poll_timeout_ms;
  720. mbox->of_xlate = ti_msgmgr_of_xlate;
  721. platform_set_drvdata(pdev, inst);
  722. ret = devm_mbox_controller_register(dev, mbox);
  723. if (ret)
  724. dev_err(dev, "Failed to register mbox_controller(%d)\n", ret);
  725. return ret;
  726. }
  727. static struct platform_driver ti_msgmgr_driver = {
  728. .probe = ti_msgmgr_probe,
  729. .driver = {
  730. .name = "ti-msgmgr",
  731. .of_match_table = of_match_ptr(ti_msgmgr_of_match),
  732. },
  733. };
  734. module_platform_driver(ti_msgmgr_driver);
  735. MODULE_LICENSE("GPL v2");
  736. MODULE_DESCRIPTION("TI message manager driver");
  737. MODULE_AUTHOR("Nishanth Menon");
  738. MODULE_ALIAS("platform:ti-msgmgr");